drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.h

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
   2 /* Copyright(c) 2014 - 2020 Intel Corporation */
   3 #ifndef ADF_C62X_HW_DATA_H_
   4 #define ADF_C62X_HW_DATA_H_
   5
   6 /* PCIe configuration space */
   7 #define ADF_C62X_SRAM_BAR 0
   8 #define ADF_C62X_PMISC_BAR 1
   9 #define ADF_C62X_ETR_BAR 2
  10 #define ADF_C62X_RX_RINGS_OFFSET 8
  11 #define ADF_C62X_TX_RINGS_MASK 0xFF
  12 #define ADF_C62X_MAX_ACCELERATORS 5
  13 #define ADF_C62X_MAX_ACCELENGINES 10
  14 #define ADF_C62X_ACCELERATORS_REG_OFFSET 16
  15 #define ADF_C62X_ACCELERATORS_MASK 0x1F
  16 #define ADF_C62X_ACCELENGINES_MASK 0x3FF
  17 #define ADF_C62X_ETR_MAX_BANKS 16
  18 #define ADF_C62X_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
  19 #define ADF_C62X_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
  20 #define ADF_C62X_SMIA0_MASK 0xFFFF
  21 #define ADF_C62X_SMIA1_MASK 0x1
  22 #define ADF_C62X_SOFTSTRAP_CSR_OFFSET 0x2EC
  23 /* Error detection and correction */
  24 #define ADF_C62X_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
  25 #define ADF_C62X_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960)
  26 #define ADF_C62X_ENABLE_AE_ECC_ERR BIT(28)
  27 #define ADF_C62X_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
  28 #define ADF_C62X_UERRSSMSH(i) (i * 0x4000 + 0x18)
  29 #define ADF_C62X_CERRSSMSH(i) (i * 0x4000 + 0x10)
  30 #define ADF_C62X_ERRSSMSH_EN BIT(3)
  31
  32 #define ADF_C62X_PF2VF_OFFSET(i)        (0x3A000 + 0x280 + ((i) * 0x04))
  33 #define ADF_C62X_VINTMSK_OFFSET(i)      (0x3A000 + 0x200 + ((i) * 0x04))
  34
  35 /* AE to function mapping */
  36 #define ADF_C62X_AE2FUNC_MAP_GRP_A_NUM_REGS 80
  37 #define ADF_C62X_AE2FUNC_MAP_GRP_B_NUM_REGS 10
  38
  39 /* Firmware Binary */
  40 #define ADF_C62X_FW "qat_c62x.bin"
  41 #define ADF_C62X_MMP "qat_c62x_mmp.bin"
  42
  43 void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data);
  44 void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data);
  45 #endif