drivers/crypto/qat/qat_common/adf_accel_devices.h

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
   2 /* Copyright(c) 2014 - 2020 Intel Corporation */
   3 #ifndef ADF_ACCEL_DEVICES_H_
   4 #define ADF_ACCEL_DEVICES_H_
   5 #include <linux/interrupt.h>
   6 #include <linux/module.h>
   7 #include <linux/list.h>
   8 #include <linux/io.h>
   9 #include <linux/ratelimit.h>
  10 #include "adf_cfg_common.h"
  11
  12 #define ADF_DH895XCC_DEVICE_NAME "dh895xcc"
  13 #define ADF_DH895XCCVF_DEVICE_NAME "dh895xccvf"
  14 #define ADF_C62X_DEVICE_NAME "c6xx"
  15 #define ADF_C62XVF_DEVICE_NAME "c6xxvf"
  16 #define ADF_C3XXX_DEVICE_NAME "c3xxx"
  17 #define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"
  18 #define ADF_4XXX_DEVICE_NAME "4xxx"
  19 #define ADF_4XXX_PCI_DEVICE_ID 0x4940
  20 #define ADF_4XXXIOV_PCI_DEVICE_ID 0x4941
  21 #define ADF_ERRSOU3 (0x3A000 + 0x0C)
  22 #define ADF_ERRSOU5 (0x3A000 + 0xD8)
  23 #define ADF_DEVICE_FUSECTL_OFFSET 0x40
  24 #define ADF_DEVICE_LEGFUSE_OFFSET 0x4C
  25 #define ADF_DEVICE_FUSECTL_MASK 0x80000000
  26 #define ADF_PCI_MAX_BARS 3
  27 #define ADF_DEVICE_NAME_LENGTH 32
  28 #define ADF_ETR_MAX_RINGS_PER_BANK 16
  29 #define ADF_MAX_MSIX_VECTOR_NAME 16
  30 #define ADF_DEVICE_NAME_PREFIX "qat_"
  31
  32 enum adf_accel_capabilities {
  33         ADF_ACCEL_CAPABILITIES_NULL = 0,
  34         ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1,
  35         ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 2,
  36         ADF_ACCEL_CAPABILITIES_CIPHER = 4,
  37         ADF_ACCEL_CAPABILITIES_AUTHENTICATION = 8,
  38         ADF_ACCEL_CAPABILITIES_COMPRESSION = 32,
  39         ADF_ACCEL_CAPABILITIES_LZS_COMPRESSION = 64,
  40         ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128
  41 };
  42
  43 struct adf_bar {
  44         resource_size_t base_addr;
  45         void __iomem *virt_addr;
  46         resource_size_t size;
  47 } __packed;
  48
  49 struct adf_accel_msix {
  50         struct msix_entry *entries;
  51         char **names;
  52         u32 num_entries;
  53 } __packed;
  54
  55 struct adf_accel_pci {
  56         struct pci_dev *pci_dev;
  57         struct adf_accel_msix msix_entries;
  58         struct adf_bar pci_bars[ADF_PCI_MAX_BARS];
  59         u8 revid;
  60         u8 sku;
  61 } __packed;
  62
  63 enum dev_state {
  64         DEV_DOWN = 0,
  65         DEV_UP
  66 };
  67
  68 enum dev_sku_info {
  69         DEV_SKU_1 = 0,
  70         DEV_SKU_2,
  71         DEV_SKU_3,
  72         DEV_SKU_4,
  73         DEV_SKU_VF,
  74         DEV_SKU_UNKNOWN,
  75 };
  76
  77 static inline const char *get_sku_info(enum dev_sku_info info)
  78 {
  79         switch (info) {
  80         case DEV_SKU_1:
  81                 return "SKU1";
  82         case DEV_SKU_2:
  83                 return "SKU2";
  84         case DEV_SKU_3:
  85                 return "SKU3";
  86         case DEV_SKU_4:
  87                 return "SKU4";
  88         case DEV_SKU_VF:
  89                 return "SKUVF";
  90         case DEV_SKU_UNKNOWN:
  91         default:
  92                 break;
  93         }
  94         return "Unknown SKU";
  95 }
  96
  97 struct adf_hw_device_class {
  98         const char *name;
  99         const enum adf_device_type type;
 100         u32 instances;
 101 } __packed;
 102
 103 struct arb_info {
 104         u32 arb_cfg;
 105         u32 arb_offset;
 106         u32 wt2sam_offset;
 107 };
 108
 109 struct admin_info {
 110         u32 admin_msg_ur;
 111         u32 admin_msg_lr;
 112         u32 mailbox_offset;
 113 };
 114
 115 struct adf_hw_csr_ops {
 116         u64 (*build_csr_ring_base_addr)(dma_addr_t addr, u32 size);
 117         u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
 118                                   u32 ring);
 119         void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
 120                                     u32 ring, u32 value);
 121         u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
 122                                   u32 ring);
 123         void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
 124                                     u32 ring, u32 value);
 125         u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
 126         void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
 127                                       u32 ring, u32 value);
 128         void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
 129                                     u32 ring, dma_addr_t addr);
 130         void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,
 131                                    u32 value);
 132         void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
 133         void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,
 134                                      u32 value);
 135         void (*write_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank,
 136                                       u32 value);
 137         void (*write_csr_int_flag_and_col)(void __iomem *csr_base_addr,
 138                                            u32 bank, u32 value);
 139         void (*write_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank,
 140                                           u32 value);
 141 };
 142
 143 struct adf_cfg_device_data;
 144 struct adf_accel_dev;
 145 struct adf_etr_data;
 146 struct adf_etr_ring_data;
 147
 148 struct adf_hw_device_data {
 149         struct adf_hw_device_class *dev_class;
 150         u32 (*get_accel_mask)(struct adf_hw_device_data *self);
 151         u32 (*get_ae_mask)(struct adf_hw_device_data *self);
 152         u32 (*get_accel_cap)(struct adf_accel_dev *accel_dev);
 153         u32 (*get_sram_bar_id)(struct adf_hw_device_data *self);
 154         u32 (*get_misc_bar_id)(struct adf_hw_device_data *self);
 155         u32 (*get_etr_bar_id)(struct adf_hw_device_data *self);
 156         u32 (*get_num_aes)(struct adf_hw_device_data *self);
 157         u32 (*get_num_accels)(struct adf_hw_device_data *self);
 158         u32 (*get_pf2vf_offset)(u32 i);
 159         u32 (*get_vintmsk_offset)(u32 i);
 160         void (*get_arb_info)(struct arb_info *arb_csrs_info);
 161         void (*get_admin_info)(struct admin_info *admin_csrs_info);
 162         enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
 163         int (*alloc_irq)(struct adf_accel_dev *accel_dev);
 164         void (*free_irq)(struct adf_accel_dev *accel_dev);
 165         void (*enable_error_correction)(struct adf_accel_dev *accel_dev);
 166         int (*init_admin_comms)(struct adf_accel_dev *accel_dev);
 167         void (*exit_admin_comms)(struct adf_accel_dev *accel_dev);
 168         int (*send_admin_init)(struct adf_accel_dev *accel_dev);
 169         int (*init_arb)(struct adf_accel_dev *accel_dev);
 170         void (*exit_arb)(struct adf_accel_dev *accel_dev);
 171         void (*get_arb_mapping)(struct adf_accel_dev *accel_dev,
 172                                 const u32 **cfg);
 173         void (*disable_iov)(struct adf_accel_dev *accel_dev);
 174         void (*configure_iov_threads)(struct adf_accel_dev *accel_dev,
 175                                       bool enable);
 176         void (*enable_ints)(struct adf_accel_dev *accel_dev);
 177         int (*enable_vf2pf_comms)(struct adf_accel_dev *accel_dev);
 178         void (*reset_device)(struct adf_accel_dev *accel_dev);
 179         void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);
 180         char *(*uof_get_name)(u32 obj_num);
 181         u32 (*uof_get_num_objs)(void);
 182         u32 (*uof_get_ae_mask)(u32 obj_num);
 183         struct adf_hw_csr_ops csr_ops;
 184         const char *fw_name;
 185         const char *fw_mmp_name;
 186         u32 fuses;
 187         u32 straps;
 188         u32 accel_capabilities_mask;
 189         u32 instance_id;
 190         u16 accel_mask;
 191         u32 ae_mask;
 192         u32 admin_ae_mask;
 193         u16 tx_rings_mask;
 194         u8 tx_rx_gap;
 195         u8 num_banks;
 196         u8 num_rings_per_bank;
 197         u8 num_accel;
 198         u8 num_logical_accel;
 199         u8 num_engines;
 200         u8 min_iov_compat_ver;
 201 } __packed;
 202
 203 /* CSR write macro */
 204 #define ADF_CSR_WR(csr_base, csr_offset, val) \
 205         __raw_writel(val, csr_base + csr_offset)
 206
 207 /* CSR read macro */
 208 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)
 209
 210 #define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev)
 211 #define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars)
 212 #define GET_HW_DATA(accel_dev) (accel_dev->hw_device)
 213 #define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks)
 214 #define GET_NUM_RINGS_PER_BANK(accel_dev) \
 215         GET_HW_DATA(accel_dev)->num_rings_per_bank
 216 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
 217 #define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops)
 218 #define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev
 219
 220 struct adf_admin_comms;
 221 struct icp_qat_fw_loader_handle;
 222 struct adf_fw_loader_data {
 223         struct icp_qat_fw_loader_handle *fw_loader;
 224         const struct firmware *uof_fw;
 225         const struct firmware *mmp_fw;
 226 };
 227
 228 struct adf_accel_vf_info {
 229         struct adf_accel_dev *accel_dev;
 230         struct tasklet_struct vf2pf_bh_tasklet;
 231         struct mutex pf2vf_lock; /* protect CSR access for PF2VF messages */
 232         struct ratelimit_state vf2pf_ratelimit;
 233         u32 vf_nr;
 234         bool init;
 235 };
 236
 237 struct adf_accel_dev {
 238         struct adf_etr_data *transport;
 239         struct adf_hw_device_data *hw_device;
 240         struct adf_cfg_device_data *cfg;
 241         struct adf_fw_loader_data *fw_loader;
 242         struct adf_admin_comms *admin;
 243         struct list_head crypto_list;
 244         unsigned long status;
 245         atomic_t ref_count;
 246         struct dentry *debugfs_dir;
 247         struct list_head list;
 248         struct module *owner;
 249         struct adf_accel_pci accel_pci_dev;
 250         union {
 251                 struct {
 252                         /* vf_info is non-zero when SR-IOV is init'ed */
 253                         struct adf_accel_vf_info *vf_info;
 254                 } pf;
 255                 struct {
 256                         char *irq_name;
 257                         struct tasklet_struct pf2vf_bh_tasklet;
 258                         struct mutex vf2pf_lock; /* protect CSR access */
 259                         struct completion iov_msg_completion;
 260                         u8 compatible;
 261                         u8 pf_version;
 262                 } vf;
 263         };
 264         bool is_vf;
 265         u32 accel_id;
 266 } __packed;
 267 #endif