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Merge tag 'regmap-fix-v5.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / dma / mxs-dma.c
blob994fc4d2aca42e6a6a0c34995877a3f97137a948
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 //
5 // Refer to drivers/dma/imx-sdma.c
6
7 #include <linux/init.h>
8 #include <linux/types.h>
9 #include <linux/mm.h>
10 #include <linux/interrupt.h>
11 #include <linux/clk.h>
12 #include <linux/wait.h>
13 #include <linux/sched.h>
14 #include <linux/semaphore.h>
15 #include <linux/device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/slab.h>
18 #include <linux/platform_device.h>
19 #include <linux/dmaengine.h>
20 #include <linux/delay.h>
21 #include <linux/module.h>
22 #include <linux/stmp_device.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/of_dma.h>
26 #include <linux/list.h>
27 #include <linux/dma/mxs-dma.h>
28
29 #include <asm/irq.h>
30
31 #include "dmaengine.h"
32
33 /*
34 * NOTE: The term "PIO" throughout the mxs-dma implementation means
35 * PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
36 * dma can program the controller registers of peripheral devices.
37 */
38
39 #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH)
40 #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA)
41
42 #define HW_APBHX_CTRL0 0x000
43 #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
44 #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
45 #define BP_APBH_CTRL0_RESET_CHANNEL 16
46 #define HW_APBHX_CTRL1 0x010
47 #define HW_APBHX_CTRL2 0x020
48 #define HW_APBHX_CHANNEL_CTRL 0x030
49 #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
50 /*
51 * The offset of NXTCMDAR register is different per both dma type and version,
52 * while stride for each channel is all the same 0x70.
53 */
54 #define HW_APBHX_CHn_NXTCMDAR(d, n) \
55 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70)
56 #define HW_APBHX_CHn_SEMA(d, n) \
57 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70)
58 #define HW_APBHX_CHn_BAR(d, n) \
59 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x070 : 0x130) + (n) * 0x70)
60 #define HW_APBX_CHn_DEBUG1(d, n) (0x150 + (n) * 0x70)
61
62 /*
63 * ccw bits definitions
64 *
65 * COMMAND: 0..1 (2)
66 * CHAIN: 2 (1)
67 * IRQ: 3 (1)
68 * NAND_LOCK: 4 (1) - not implemented
69 * NAND_WAIT4READY: 5 (1) - not implemented
70 * DEC_SEM: 6 (1)
71 * WAIT4END: 7 (1)
72 * HALT_ON_TERMINATE: 8 (1)
73 * TERMINATE_FLUSH: 9 (1)
74 * RESERVED: 10..11 (2)
75 * PIO_NUM: 12..15 (4)
76 */
77 #define BP_CCW_COMMAND 0
78 #define BM_CCW_COMMAND (3 << 0)
79 #define CCW_CHAIN (1 << 2)
80 #define CCW_IRQ (1 << 3)
81 #define CCW_WAIT4RDY (1 << 5)
82 #define CCW_DEC_SEM (1 << 6)
83 #define CCW_WAIT4END (1 << 7)
84 #define CCW_HALT_ON_TERM (1 << 8)
85 #define CCW_TERM_FLUSH (1 << 9)
86 #define BP_CCW_PIO_NUM 12
87 #define BM_CCW_PIO_NUM (0xf << 12)
88
89 #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
90
91 #define MXS_DMA_CMD_NO_XFER 0
92 #define MXS_DMA_CMD_WRITE 1
93 #define MXS_DMA_CMD_READ 2
94 #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
95
96 struct mxs_dma_ccw {
97 u32 next;
98 u16 bits;
99 u16 xfer_bytes;
100 #define MAX_XFER_BYTES 0xff00
101 u32 bufaddr;
102 #define MXS_PIO_WORDS 16
103 u32 pio_words[MXS_PIO_WORDS];
104 };
105
106 #define CCW_BLOCK_SIZE (4 * PAGE_SIZE)
107 #define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw))
108
109 struct mxs_dma_chan {
110 struct mxs_dma_engine *mxs_dma;
111 struct dma_chan chan;
112 struct dma_async_tx_descriptor desc;
113 struct tasklet_struct tasklet;
114 unsigned int chan_irq;
115 struct mxs_dma_ccw *ccw;
116 dma_addr_t ccw_phys;
117 int desc_count;
118 enum dma_status status;
119 unsigned int flags;
120 bool reset;
121 #define MXS_DMA_SG_LOOP (1 << 0)
122 #define MXS_DMA_USE_SEMAPHORE (1 << 1)
123 };
124
125 #define MXS_DMA_CHANNELS 16
126 #define MXS_DMA_CHANNELS_MASK 0xffff
127
128 enum mxs_dma_devtype {
129 MXS_DMA_APBH,
130 MXS_DMA_APBX,
131 };
132
133 enum mxs_dma_id {
134 IMX23_DMA,
135 IMX28_DMA,
136 };
137
138 struct mxs_dma_engine {
139 enum mxs_dma_id dev_id;
140 enum mxs_dma_devtype type;
141 void __iomem *base;
142 struct clk *clk;
143 struct dma_device dma_device;
144 struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
145 struct platform_device *pdev;
146 unsigned int nr_channels;
147 };
148
149 struct mxs_dma_type {
150 enum mxs_dma_id id;
151 enum mxs_dma_devtype type;
152 };
153
154 static struct mxs_dma_type mxs_dma_types[] = {
155 {
156 .id = IMX23_DMA,
157 .type = MXS_DMA_APBH,
158 }, {
159 .id = IMX23_DMA,
160 .type = MXS_DMA_APBX,
161 }, {
162 .id = IMX28_DMA,
163 .type = MXS_DMA_APBH,
164 }, {
165 .id = IMX28_DMA,
166 .type = MXS_DMA_APBX,
167 }
168 };
169
170 static const struct of_device_id mxs_dma_dt_ids[] = {
171 { .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_types[0], },
172 { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_types[1], },
173 { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_types[2], },
174 { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_types[3], },
175 { /* sentinel */ }
176 };
177 MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids);
178
179 static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
180 {
181 return container_of(chan, struct mxs_dma_chan, chan);
182 }
183
184 static void mxs_dma_reset_chan(struct dma_chan *chan)
185 {
186 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
187 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
188 int chan_id = mxs_chan->chan.chan_id;
189
190 /*
191 * mxs dma channel resets can cause a channel stall. To recover from a
192 * channel stall, we have to reset the whole DMA engine. To avoid this,
193 * we use cyclic DMA with semaphores, that are enhanced in
194 * mxs_dma_int_handler. To reset the channel, we can simply stop writing
195 * into the semaphore counter.
196 */
197 if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE &&
198 mxs_chan->flags & MXS_DMA_SG_LOOP) {
199 mxs_chan->reset = true;
200 } else if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) {
201 writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
202 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
203 } else {
204 unsigned long elapsed = 0;
205 const unsigned long max_wait = 50000; /* 50ms */
206 void __iomem *reg_dbg1 = mxs_dma->base +
207 HW_APBX_CHn_DEBUG1(mxs_dma, chan_id);
208
209 /*
210 * On i.MX28 APBX, the DMA channel can stop working if we reset
211 * the channel while it is in READ_FLUSH (0x08) state.
212 * We wait here until we leave the state. Then we trigger the
213 * reset. Waiting a maximum of 50ms, the kernel shouldn't crash
214 * because of this.
215 */
216 while ((readl(reg_dbg1) & 0xf) == 0x8 && elapsed < max_wait) {
217 udelay(100);
218 elapsed += 100;
219 }
220
221 if (elapsed >= max_wait)
222 dev_err(&mxs_chan->mxs_dma->pdev->dev,
223 "Failed waiting for the DMA channel %d to leave state READ_FLUSH, trying to reset channel in READ_FLUSH state now\n",
224 chan_id);
225
226 writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
227 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
228 }
229
230 mxs_chan->status = DMA_COMPLETE;
231 }
232
233 static void mxs_dma_enable_chan(struct dma_chan *chan)
234 {
235 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
236 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
237 int chan_id = mxs_chan->chan.chan_id;
238
239 /* set cmd_addr up */
240 writel(mxs_chan->ccw_phys,
241 mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id));
242
243 /* write 1 to SEMA to kick off the channel */
244 if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE &&
245 mxs_chan->flags & MXS_DMA_SG_LOOP) {
246 /* A cyclic DMA consists of at least 2 segments, so initialize
247 * the semaphore with 2 so we have enough time to add 1 to the
248 * semaphore if we need to */
249 writel(2, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
250 } else {
251 writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
252 }
253 mxs_chan->reset = false;
254 }
255
256 static void mxs_dma_disable_chan(struct dma_chan *chan)
257 {
258 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
259
260 mxs_chan->status = DMA_COMPLETE;
261 }
262
263 static int mxs_dma_pause_chan(struct dma_chan *chan)
264 {
265 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
266 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
267 int chan_id = mxs_chan->chan.chan_id;
268
269 /* freeze the channel */
270 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
271 writel(1 << chan_id,
272 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
273 else
274 writel(1 << chan_id,
275 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
276
277 mxs_chan->status = DMA_PAUSED;
278 return 0;
279 }
280
281 static int mxs_dma_resume_chan(struct dma_chan *chan)
282 {
283 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
284 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
285 int chan_id = mxs_chan->chan.chan_id;
286
287 /* unfreeze the channel */
288 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
289 writel(1 << chan_id,
290 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
291 else
292 writel(1 << chan_id,
293 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR);
294
295 mxs_chan->status = DMA_IN_PROGRESS;
296 return 0;
297 }
298
299 static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
300 {
301 return dma_cookie_assign(tx);
302 }
303
304 static void mxs_dma_tasklet(struct tasklet_struct *t)
305 {
306 struct mxs_dma_chan *mxs_chan = from_tasklet(mxs_chan, t, tasklet);
307
308 dmaengine_desc_get_callback_invoke(&mxs_chan->desc, NULL);
309 }
310
311 static int mxs_dma_irq_to_chan(struct mxs_dma_engine *mxs_dma, int irq)
312 {
313 int i;
314
315 for (i = 0; i != mxs_dma->nr_channels; ++i)
316 if (mxs_dma->mxs_chans[i].chan_irq == irq)
317 return i;
318
319 return -EINVAL;
320 }
321
322 static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
323 {
324 struct mxs_dma_engine *mxs_dma = dev_id;
325 struct mxs_dma_chan *mxs_chan;
326 u32 completed;
327 u32 err;
328 int chan = mxs_dma_irq_to_chan(mxs_dma, irq);
329
330 if (chan < 0)
331 return IRQ_NONE;
332
333 /* completion status */
334 completed = readl(mxs_dma->base + HW_APBHX_CTRL1);
335 completed = (completed >> chan) & 0x1;
336
337 /* Clear interrupt */
338 writel((1 << chan),
339 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
340
341 /* error status */
342 err = readl(mxs_dma->base + HW_APBHX_CTRL2);
343 err &= (1 << (MXS_DMA_CHANNELS + chan)) | (1 << chan);
344
345 /*
346 * error status bit is in the upper 16 bits, error irq bit in the lower
347 * 16 bits. We transform it into a simpler error code:
348 * err: 0x00 = no error, 0x01 = TERMINATION, 0x02 = BUS_ERROR
349 */
350 err = (err >> (MXS_DMA_CHANNELS + chan)) + (err >> chan);
351
352 /* Clear error irq */
353 writel((1 << chan),
354 mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
355
356 /*
357 * When both completion and error of termination bits set at the
358 * same time, we do not take it as an error. IOW, it only becomes
359 * an error we need to handle here in case of either it's a bus
360 * error or a termination error with no completion. 0x01 is termination
361 * error, so we can subtract err & completed to get the real error case.
362 */
363 err -= err & completed;
364
365 mxs_chan = &mxs_dma->mxs_chans[chan];
366
367 if (err) {
368 dev_dbg(mxs_dma->dma_device.dev,
369 "%s: error in channel %d\n", __func__,
370 chan);
371 mxs_chan->status = DMA_ERROR;
372 mxs_dma_reset_chan(&mxs_chan->chan);
373 } else if (mxs_chan->status != DMA_COMPLETE) {
374 if (mxs_chan->flags & MXS_DMA_SG_LOOP) {
375 mxs_chan->status = DMA_IN_PROGRESS;
376 if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE)
377 writel(1, mxs_dma->base +
378 HW_APBHX_CHn_SEMA(mxs_dma, chan));
379 } else {
380 mxs_chan->status = DMA_COMPLETE;
381 }
382 }
383
384 if (mxs_chan->status == DMA_COMPLETE) {
385 if (mxs_chan->reset)
386 return IRQ_HANDLED;
387 dma_cookie_complete(&mxs_chan->desc);
388 }
389
390 /* schedule tasklet on this channel */
391 tasklet_schedule(&mxs_chan->tasklet);
392
393 return IRQ_HANDLED;
394 }
395
396 static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
397 {
398 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
399 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
400 int ret;
401
402 mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev,
403 CCW_BLOCK_SIZE,
404 &mxs_chan->ccw_phys, GFP_KERNEL);
405 if (!mxs_chan->ccw) {
406 ret = -ENOMEM;
407 goto err_alloc;
408 }
409
410 ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
411 0, "mxs-dma", mxs_dma);
412 if (ret)
413 goto err_irq;
414
415 ret = clk_prepare_enable(mxs_dma->clk);
416 if (ret)
417 goto err_clk;
418
419 mxs_dma_reset_chan(chan);
420
421 dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
422 mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
423
424 /* the descriptor is ready */
425 async_tx_ack(&mxs_chan->desc);
426
427 return 0;
428
429 err_clk:
430 free_irq(mxs_chan->chan_irq, mxs_dma);
431 err_irq:
432 dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
433 mxs_chan->ccw, mxs_chan->ccw_phys);
434 err_alloc:
435 return ret;
436 }
437
438 static void mxs_dma_free_chan_resources(struct dma_chan *chan)
439 {
440 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
441 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
442
443 mxs_dma_disable_chan(chan);
444
445 free_irq(mxs_chan->chan_irq, mxs_dma);
446
447 dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
448 mxs_chan->ccw, mxs_chan->ccw_phys);
449
450 clk_disable_unprepare(mxs_dma->clk);
451 }
452
453 /*
454 * How to use the flags for ->device_prep_slave_sg() :
455 * [1] If there is only one DMA command in the DMA chain, the code should be:
456 * ......
457 * ->device_prep_slave_sg(DMA_CTRL_ACK);
458 * ......
459 * [2] If there are two DMA commands in the DMA chain, the code should be
460 * ......
461 * ->device_prep_slave_sg(0);
462 * ......
463 * ->device_prep_slave_sg(DMA_CTRL_ACK);
464 * ......
465 * [3] If there are more than two DMA commands in the DMA chain, the code
466 * should be:
467 * ......
468 * ->device_prep_slave_sg(0); // First
469 * ......
470 * ->device_prep_slave_sg(DMA_CTRL_ACK]);
471 * ......
472 * ->device_prep_slave_sg(DMA_CTRL_ACK); // Last
473 * ......
474 */
475 static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
476 struct dma_chan *chan, struct scatterlist *sgl,
477 unsigned int sg_len, enum dma_transfer_direction direction,
478 unsigned long flags, void *context)
479 {
480 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
481 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
482 struct mxs_dma_ccw *ccw;
483 struct scatterlist *sg;
484 u32 i, j;
485 u32 *pio;
486 int idx = 0;
487
488 if (mxs_chan->status == DMA_IN_PROGRESS)
489 idx = mxs_chan->desc_count;
490
491 if (sg_len + idx > NUM_CCW) {
492 dev_err(mxs_dma->dma_device.dev,
493 "maximum number of sg exceeded: %d > %d\n",
494 sg_len, NUM_CCW);
495 goto err_out;
496 }
497
498 mxs_chan->status = DMA_IN_PROGRESS;
499 mxs_chan->flags = 0;
500
501 /*
502 * If the sg is prepared with append flag set, the sg
503 * will be appended to the last prepared sg.
504 */
505 if (idx) {
506 BUG_ON(idx < 1);
507 ccw = &mxs_chan->ccw[idx - 1];
508 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
509 ccw->bits |= CCW_CHAIN;
510 ccw->bits &= ~CCW_IRQ;
511 ccw->bits &= ~CCW_DEC_SEM;
512 } else {
513 idx = 0;
514 }
515
516 if (direction == DMA_TRANS_NONE) {
517 ccw = &mxs_chan->ccw[idx++];
518 pio = (u32 *) sgl;
519
520 for (j = 0; j < sg_len;)
521 ccw->pio_words[j++] = *pio++;
522
523 ccw->bits = 0;
524 ccw->bits |= CCW_IRQ;
525 ccw->bits |= CCW_DEC_SEM;
526 if (flags & MXS_DMA_CTRL_WAIT4END)
527 ccw->bits |= CCW_WAIT4END;
528 ccw->bits |= CCW_HALT_ON_TERM;
529 ccw->bits |= CCW_TERM_FLUSH;
530 ccw->bits |= BF_CCW(sg_len, PIO_NUM);
531 ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
532 if (flags & MXS_DMA_CTRL_WAIT4RDY)
533 ccw->bits |= CCW_WAIT4RDY;
534 } else {
535 for_each_sg(sgl, sg, sg_len, i) {
536 if (sg_dma_len(sg) > MAX_XFER_BYTES) {
537 dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
538 sg_dma_len(sg), MAX_XFER_BYTES);
539 goto err_out;
540 }
541
542 ccw = &mxs_chan->ccw[idx++];
543
544 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
545 ccw->bufaddr = sg->dma_address;
546 ccw->xfer_bytes = sg_dma_len(sg);
547
548 ccw->bits = 0;
549 ccw->bits |= CCW_CHAIN;
550 ccw->bits |= CCW_HALT_ON_TERM;
551 ccw->bits |= CCW_TERM_FLUSH;
552 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
553 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
554 COMMAND);
555
556 if (i + 1 == sg_len) {
557 ccw->bits &= ~CCW_CHAIN;
558 ccw->bits |= CCW_IRQ;
559 ccw->bits |= CCW_DEC_SEM;
560 if (flags & MXS_DMA_CTRL_WAIT4END)
561 ccw->bits |= CCW_WAIT4END;
562 }
563 }
564 }
565 mxs_chan->desc_count = idx;
566
567 return &mxs_chan->desc;
568
569 err_out:
570 mxs_chan->status = DMA_ERROR;
571 return NULL;
572 }
573
574 static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
575 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
576 size_t period_len, enum dma_transfer_direction direction,
577 unsigned long flags)
578 {
579 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
580 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
581 u32 num_periods = buf_len / period_len;
582 u32 i = 0, buf = 0;
583
584 if (mxs_chan->status == DMA_IN_PROGRESS)
585 return NULL;
586
587 mxs_chan->status = DMA_IN_PROGRESS;
588 mxs_chan->flags |= MXS_DMA_SG_LOOP;
589 mxs_chan->flags |= MXS_DMA_USE_SEMAPHORE;
590
591 if (num_periods > NUM_CCW) {
592 dev_err(mxs_dma->dma_device.dev,
593 "maximum number of sg exceeded: %d > %d\n",
594 num_periods, NUM_CCW);
595 goto err_out;
596 }
597
598 if (period_len > MAX_XFER_BYTES) {
599 dev_err(mxs_dma->dma_device.dev,
600 "maximum period size exceeded: %zu > %d\n",
601 period_len, MAX_XFER_BYTES);
602 goto err_out;
603 }
604
605 while (buf < buf_len) {
606 struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
607
608 if (i + 1 == num_periods)
609 ccw->next = mxs_chan->ccw_phys;
610 else
611 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);
612
613 ccw->bufaddr = dma_addr;
614 ccw->xfer_bytes = period_len;
615
616 ccw->bits = 0;
617 ccw->bits |= CCW_CHAIN;
618 ccw->bits |= CCW_IRQ;
619 ccw->bits |= CCW_HALT_ON_TERM;
620 ccw->bits |= CCW_TERM_FLUSH;
621 ccw->bits |= CCW_DEC_SEM;
622 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
623 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
624
625 dma_addr += period_len;
626 buf += period_len;
627
628 i++;
629 }
630 mxs_chan->desc_count = i;
631
632 return &mxs_chan->desc;
633
634 err_out:
635 mxs_chan->status = DMA_ERROR;
636 return NULL;
637 }
638
639 static int mxs_dma_terminate_all(struct dma_chan *chan)
640 {
641 mxs_dma_reset_chan(chan);
642 mxs_dma_disable_chan(chan);
643
644 return 0;
645 }
646
647 static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
648 dma_cookie_t cookie, struct dma_tx_state *txstate)
649 {
650 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
651 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
652 u32 residue = 0;
653
654 if (mxs_chan->status == DMA_IN_PROGRESS &&
655 mxs_chan->flags & MXS_DMA_SG_LOOP) {
656 struct mxs_dma_ccw *last_ccw;
657 u32 bar;
658
659 last_ccw = &mxs_chan->ccw[mxs_chan->desc_count - 1];
660 residue = last_ccw->xfer_bytes + last_ccw->bufaddr;
661
662 bar = readl(mxs_dma->base +
663 HW_APBHX_CHn_BAR(mxs_dma, chan->chan_id));
664 residue -= bar;
665 }
666
667 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
668 residue);
669
670 return mxs_chan->status;
671 }
672
673 static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
674 {
675 int ret;
676
677 ret = clk_prepare_enable(mxs_dma->clk);
678 if (ret)
679 return ret;
680
681 ret = stmp_reset_block(mxs_dma->base);
682 if (ret)
683 goto err_out;
684
685 /* enable apbh burst */
686 if (dma_is_apbh(mxs_dma)) {
687 writel(BM_APBH_CTRL0_APB_BURST_EN,
688 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
689 writel(BM_APBH_CTRL0_APB_BURST8_EN,
690 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
691 }
692
693 /* enable irq for all the channels */
694 writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
695 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
696
697 err_out:
698 clk_disable_unprepare(mxs_dma->clk);
699 return ret;
700 }
701
702 struct mxs_dma_filter_param {
703 unsigned int chan_id;
704 };
705
706 static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param)
707 {
708 struct mxs_dma_filter_param *param = fn_param;
709 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
710 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
711 int chan_irq;
712
713 if (chan->chan_id != param->chan_id)
714 return false;
715
716 chan_irq = platform_get_irq(mxs_dma->pdev, param->chan_id);
717 if (chan_irq < 0)
718 return false;
719
720 mxs_chan->chan_irq = chan_irq;
721
722 return true;
723 }
724
725 static struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec,
726 struct of_dma *ofdma)
727 {
728 struct mxs_dma_engine *mxs_dma = ofdma->of_dma_data;
729 dma_cap_mask_t mask = mxs_dma->dma_device.cap_mask;
730 struct mxs_dma_filter_param param;
731
732 if (dma_spec->args_count != 1)
733 return NULL;
734
735 param.chan_id = dma_spec->args[0];
736
737 if (param.chan_id >= mxs_dma->nr_channels)
738 return NULL;
739
740 return __dma_request_channel(&mask, mxs_dma_filter_fn, &param,
741 ofdma->of_node);
742 }
743
744 static int __init mxs_dma_probe(struct platform_device *pdev)
745 {
746 struct device_node *np = pdev->dev.of_node;
747 const struct mxs_dma_type *dma_type;
748 struct mxs_dma_engine *mxs_dma;
749 struct resource *iores;
750 int ret, i;
751
752 mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL);
753 if (!mxs_dma)
754 return -ENOMEM;
755
756 ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels);
757 if (ret) {
758 dev_err(&pdev->dev, "failed to read dma-channels\n");
759 return ret;
760 }
761
762 dma_type = (struct mxs_dma_type *)of_device_get_match_data(&pdev->dev);
763 mxs_dma->type = dma_type->type;
764 mxs_dma->dev_id = dma_type->id;
765
766 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
767 mxs_dma->base = devm_ioremap_resource(&pdev->dev, iores);
768 if (IS_ERR(mxs_dma->base))
769 return PTR_ERR(mxs_dma->base);
770
771 mxs_dma->clk = devm_clk_get(&pdev->dev, NULL);
772 if (IS_ERR(mxs_dma->clk))
773 return PTR_ERR(mxs_dma->clk);
774
775 dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
776 dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
777
778 INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
779
780 /* Initialize channel parameters */
781 for (i = 0; i < MXS_DMA_CHANNELS; i++) {
782 struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
783
784 mxs_chan->mxs_dma = mxs_dma;
785 mxs_chan->chan.device = &mxs_dma->dma_device;
786 dma_cookie_init(&mxs_chan->chan);
787
788 tasklet_setup(&mxs_chan->tasklet, mxs_dma_tasklet);
789
790
791 /* Add the channel to mxs_chan list */
792 list_add_tail(&mxs_chan->chan.device_node,
793 &mxs_dma->dma_device.channels);
794 }
795
796 ret = mxs_dma_init(mxs_dma);
797 if (ret)
798 return ret;
799
800 mxs_dma->pdev = pdev;
801 mxs_dma->dma_device.dev = &pdev->dev;
802
803 /* mxs_dma gets 65535 bytes maximum sg size */
804 dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
805
806 mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
807 mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
808 mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
809 mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
810 mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
811 mxs_dma->dma_device.device_pause = mxs_dma_pause_chan;
812 mxs_dma->dma_device.device_resume = mxs_dma_resume_chan;
813 mxs_dma->dma_device.device_terminate_all = mxs_dma_terminate_all;
814 mxs_dma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
815 mxs_dma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
816 mxs_dma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
817 mxs_dma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
818 mxs_dma->dma_device.device_issue_pending = mxs_dma_enable_chan;
819
820 ret = dmaenginem_async_device_register(&mxs_dma->dma_device);
821 if (ret) {
822 dev_err(mxs_dma->dma_device.dev, "unable to register\n");
823 return ret;
824 }
825
826 ret = of_dma_controller_register(np, mxs_dma_xlate, mxs_dma);
827 if (ret) {
828 dev_err(mxs_dma->dma_device.dev,
829 "failed to register controller\n");
830 }
831
832 dev_info(mxs_dma->dma_device.dev, "initialized\n");
833
834 return 0;
835 }
836
837 static struct platform_driver mxs_dma_driver = {
838 .driver = {
839 .name = "mxs-dma",
840 .of_match_table = mxs_dma_dt_ids,
841 },
842 };
843
844 static int __init mxs_dma_module_init(void)
845 {
846 return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
847 }
848 subsys_initcall(mxs_dma_module_init);
Linux with added FPC-III support