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Merge tag 'regmap-fix-v5.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / dma / ti / k3-udma.c
blob87157cbae1b8e782b414fd768f330b878b5b016d
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/dmapool.h>
12 #include <linux/err.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/list.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18 #include <linux/spinlock.h>
19 #include <linux/sys_soc.h>
20 #include <linux/of.h>
21 #include <linux/of_dma.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/workqueue.h>
25 #include <linux/completion.h>
26 #include <linux/soc/ti/k3-ringacc.h>
27 #include <linux/soc/ti/ti_sci_protocol.h>
28 #include <linux/soc/ti/ti_sci_inta_msi.h>
29 #include <linux/dma/k3-event-router.h>
30 #include <linux/dma/ti-cppi5.h>
31
32 #include "../virt-dma.h"
33 #include "k3-udma.h"
34 #include "k3-psil-priv.h"
35
36 struct udma_static_tr {
37 u8 elsize; /* RPSTR0 */
38 u16 elcnt; /* RPSTR0 */
39 u16 bstcnt; /* RPSTR1 */
40 };
41
42 #define K3_UDMA_MAX_RFLOWS 1024
43 #define K3_UDMA_DEFAULT_RING_SIZE 16
44
45 /* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */
46 #define UDMA_RFLOW_SRCTAG_NONE 0
47 #define UDMA_RFLOW_SRCTAG_CFG_TAG 1
48 #define UDMA_RFLOW_SRCTAG_FLOW_ID 2
49 #define UDMA_RFLOW_SRCTAG_SRC_TAG 4
50
51 #define UDMA_RFLOW_DSTTAG_NONE 0
52 #define UDMA_RFLOW_DSTTAG_CFG_TAG 1
53 #define UDMA_RFLOW_DSTTAG_FLOW_ID 2
54 #define UDMA_RFLOW_DSTTAG_DST_TAG_LO 4
55 #define UDMA_RFLOW_DSTTAG_DST_TAG_HI 5
56
57 struct udma_chan;
58
59 enum k3_dma_type {
60 DMA_TYPE_UDMA = 0,
61 DMA_TYPE_BCDMA,
62 DMA_TYPE_PKTDMA,
63 };
64
65 enum udma_mmr {
66 MMR_GCFG = 0,
67 MMR_BCHANRT,
68 MMR_RCHANRT,
69 MMR_TCHANRT,
70 MMR_LAST,
71 };
72
73 static const char * const mmr_names[] = {
74 [MMR_GCFG] = "gcfg",
75 [MMR_BCHANRT] = "bchanrt",
76 [MMR_RCHANRT] = "rchanrt",
77 [MMR_TCHANRT] = "tchanrt",
78 };
79
80 struct udma_tchan {
81 void __iomem *reg_rt;
82
83 int id;
84 struct k3_ring *t_ring; /* Transmit ring */
85 struct k3_ring *tc_ring; /* Transmit Completion ring */
86 int tflow_id; /* applicable only for PKTDMA */
87
88 };
89
90 #define udma_bchan udma_tchan
91
92 struct udma_rflow {
93 int id;
94 struct k3_ring *fd_ring; /* Free Descriptor ring */
95 struct k3_ring *r_ring; /* Receive ring */
96 };
97
98 struct udma_rchan {
99 void __iomem *reg_rt;
100
101 int id;
102 };
103
104 struct udma_oes_offsets {
105 /* K3 UDMA Output Event Offset */
106 u32 udma_rchan;
107
108 /* BCDMA Output Event Offsets */
109 u32 bcdma_bchan_data;
110 u32 bcdma_bchan_ring;
111 u32 bcdma_tchan_data;
112 u32 bcdma_tchan_ring;
113 u32 bcdma_rchan_data;
114 u32 bcdma_rchan_ring;
115
116 /* PKTDMA Output Event Offsets */
117 u32 pktdma_tchan_flow;
118 u32 pktdma_rchan_flow;
119 };
120
121 #define UDMA_FLAG_PDMA_ACC32 BIT(0)
122 #define UDMA_FLAG_PDMA_BURST BIT(1)
123 #define UDMA_FLAG_TDTYPE BIT(2)
124
125 struct udma_match_data {
126 enum k3_dma_type type;
127 u32 psil_base;
128 bool enable_memcpy_support;
129 u32 flags;
130 u32 statictr_z_mask;
131 };
132
133 struct udma_soc_data {
134 struct udma_oes_offsets oes;
135 u32 bcdma_trigger_event_offset;
136 };
137
138 struct udma_hwdesc {
139 size_t cppi5_desc_size;
140 void *cppi5_desc_vaddr;
141 dma_addr_t cppi5_desc_paddr;
142
143 /* TR descriptor internal pointers */
144 void *tr_req_base;
145 struct cppi5_tr_resp_t *tr_resp_base;
146 };
147
148 struct udma_rx_flush {
149 struct udma_hwdesc hwdescs[2];
150
151 size_t buffer_size;
152 void *buffer_vaddr;
153 dma_addr_t buffer_paddr;
154 };
155
156 struct udma_tpl {
157 u8 levels;
158 u32 start_idx[3];
159 };
160
161 struct udma_dev {
162 struct dma_device ddev;
163 struct device *dev;
164 void __iomem *mmrs[MMR_LAST];
165 const struct udma_match_data *match_data;
166 const struct udma_soc_data *soc_data;
167
168 struct udma_tpl bchan_tpl;
169 struct udma_tpl tchan_tpl;
170 struct udma_tpl rchan_tpl;
171
172 size_t desc_align; /* alignment to use for descriptors */
173
174 struct udma_tisci_rm tisci_rm;
175
176 struct k3_ringacc *ringacc;
177
178 struct work_struct purge_work;
179 struct list_head desc_to_purge;
180 spinlock_t lock;
181
182 struct udma_rx_flush rx_flush;
183
184 int bchan_cnt;
185 int tchan_cnt;
186 int echan_cnt;
187 int rchan_cnt;
188 int rflow_cnt;
189 int tflow_cnt;
190 unsigned long *bchan_map;
191 unsigned long *tchan_map;
192 unsigned long *rchan_map;
193 unsigned long *rflow_gp_map;
194 unsigned long *rflow_gp_map_allocated;
195 unsigned long *rflow_in_use;
196 unsigned long *tflow_map;
197
198 struct udma_bchan *bchans;
199 struct udma_tchan *tchans;
200 struct udma_rchan *rchans;
201 struct udma_rflow *rflows;
202
203 struct udma_chan *channels;
204 u32 psil_base;
205 u32 atype;
206 u32 asel;
207 };
208
209 struct udma_desc {
210 struct virt_dma_desc vd;
211
212 bool terminated;
213
214 enum dma_transfer_direction dir;
215
216 struct udma_static_tr static_tr;
217 u32 residue;
218
219 unsigned int sglen;
220 unsigned int desc_idx; /* Only used for cyclic in packet mode */
221 unsigned int tr_idx;
222
223 u32 metadata_size;
224 void *metadata; /* pointer to provided metadata buffer (EPIP, PSdata) */
225
226 unsigned int hwdesc_count;
227 struct udma_hwdesc hwdesc[];
228 };
229
230 enum udma_chan_state {
231 UDMA_CHAN_IS_IDLE = 0, /* not active, no teardown is in progress */
232 UDMA_CHAN_IS_ACTIVE, /* Normal operation */
233 UDMA_CHAN_IS_TERMINATING, /* channel is being terminated */
234 };
235
236 struct udma_tx_drain {
237 struct delayed_work work;
238 ktime_t tstamp;
239 u32 residue;
240 };
241
242 struct udma_chan_config {
243 bool pkt_mode; /* TR or packet */
244 bool needs_epib; /* EPIB is needed for the communication or not */
245 u32 psd_size; /* size of Protocol Specific Data */
246 u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */
247 u32 hdesc_size; /* Size of a packet descriptor in packet mode */
248 bool notdpkt; /* Suppress sending TDC packet */
249 int remote_thread_id;
250 u32 atype;
251 u32 asel;
252 u32 src_thread;
253 u32 dst_thread;
254 enum psil_endpoint_type ep_type;
255 bool enable_acc32;
256 bool enable_burst;
257 enum udma_tp_level channel_tpl; /* Channel Throughput Level */
258
259 u32 tr_trigger_type;
260
261 /* PKDMA mapped channel */
262 int mapped_channel_id;
263 /* PKTDMA default tflow or rflow for mapped channel */
264 int default_flow_id;
265
266 enum dma_transfer_direction dir;
267 };
268
269 struct udma_chan {
270 struct virt_dma_chan vc;
271 struct dma_slave_config cfg;
272 struct udma_dev *ud;
273 struct device *dma_dev;
274 struct udma_desc *desc;
275 struct udma_desc *terminated_desc;
276 struct udma_static_tr static_tr;
277 char *name;
278
279 struct udma_bchan *bchan;
280 struct udma_tchan *tchan;
281 struct udma_rchan *rchan;
282 struct udma_rflow *rflow;
283
284 bool psil_paired;
285
286 int irq_num_ring;
287 int irq_num_udma;
288
289 bool cyclic;
290 bool paused;
291
292 enum udma_chan_state state;
293 struct completion teardown_completed;
294
295 struct udma_tx_drain tx_drain;
296
297 u32 bcnt; /* number of bytes completed since the start of the channel */
298
299 /* Channel configuration parameters */
300 struct udma_chan_config config;
301
302 /* dmapool for packet mode descriptors */
303 bool use_dma_pool;
304 struct dma_pool *hdesc_pool;
305
306 u32 id;
307 };
308
309 static inline struct udma_dev *to_udma_dev(struct dma_device *d)
310 {
311 return container_of(d, struct udma_dev, ddev);
312 }
313
314 static inline struct udma_chan *to_udma_chan(struct dma_chan *c)
315 {
316 return container_of(c, struct udma_chan, vc.chan);
317 }
318
319 static inline struct udma_desc *to_udma_desc(struct dma_async_tx_descriptor *t)
320 {
321 return container_of(t, struct udma_desc, vd.tx);
322 }
323
324 /* Generic register access functions */
325 static inline u32 udma_read(void __iomem *base, int reg)
326 {
327 return readl(base + reg);
328 }
329
330 static inline void udma_write(void __iomem *base, int reg, u32 val)
331 {
332 writel(val, base + reg);
333 }
334
335 static inline void udma_update_bits(void __iomem *base, int reg,
336 u32 mask, u32 val)
337 {
338 u32 tmp, orig;
339
340 orig = readl(base + reg);
341 tmp = orig & ~mask;
342 tmp |= (val & mask);
343
344 if (tmp != orig)
345 writel(tmp, base + reg);
346 }
347
348 /* TCHANRT */
349 static inline u32 udma_tchanrt_read(struct udma_chan *uc, int reg)
350 {
351 if (!uc->tchan)
352 return 0;
353 return udma_read(uc->tchan->reg_rt, reg);
354 }
355
356 static inline void udma_tchanrt_write(struct udma_chan *uc, int reg, u32 val)
357 {
358 if (!uc->tchan)
359 return;
360 udma_write(uc->tchan->reg_rt, reg, val);
361 }
362
363 static inline void udma_tchanrt_update_bits(struct udma_chan *uc, int reg,
364 u32 mask, u32 val)
365 {
366 if (!uc->tchan)
367 return;
368 udma_update_bits(uc->tchan->reg_rt, reg, mask, val);
369 }
370
371 /* RCHANRT */
372 static inline u32 udma_rchanrt_read(struct udma_chan *uc, int reg)
373 {
374 if (!uc->rchan)
375 return 0;
376 return udma_read(uc->rchan->reg_rt, reg);
377 }
378
379 static inline void udma_rchanrt_write(struct udma_chan *uc, int reg, u32 val)
380 {
381 if (!uc->rchan)
382 return;
383 udma_write(uc->rchan->reg_rt, reg, val);
384 }
385
386 static inline void udma_rchanrt_update_bits(struct udma_chan *uc, int reg,
387 u32 mask, u32 val)
388 {
389 if (!uc->rchan)
390 return;
391 udma_update_bits(uc->rchan->reg_rt, reg, mask, val);
392 }
393
394 static int navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread)
395 {
396 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
397
398 dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
399 return tisci_rm->tisci_psil_ops->pair(tisci_rm->tisci,
400 tisci_rm->tisci_navss_dev_id,
401 src_thread, dst_thread);
402 }
403
404 static int navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
405 u32 dst_thread)
406 {
407 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
408
409 dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
410 return tisci_rm->tisci_psil_ops->unpair(tisci_rm->tisci,
411 tisci_rm->tisci_navss_dev_id,
412 src_thread, dst_thread);
413 }
414
415 static void k3_configure_chan_coherency(struct dma_chan *chan, u32 asel)
416 {
417 struct device *chan_dev = &chan->dev->device;
418
419 if (asel == 0) {
420 /* No special handling for the channel */
421 chan->dev->chan_dma_dev = false;
422
423 chan_dev->dma_coherent = false;
424 chan_dev->dma_parms = NULL;
425 } else if (asel == 14 || asel == 15) {
426 chan->dev->chan_dma_dev = true;
427
428 chan_dev->dma_coherent = true;
429 dma_coerce_mask_and_coherent(chan_dev, DMA_BIT_MASK(48));
430 chan_dev->dma_parms = chan_dev->parent->dma_parms;
431 } else {
432 dev_warn(chan->device->dev, "Invalid ASEL value: %u\n", asel);
433
434 chan_dev->dma_coherent = false;
435 chan_dev->dma_parms = NULL;
436 }
437 }
438
439 static void udma_reset_uchan(struct udma_chan *uc)
440 {
441 memset(&uc->config, 0, sizeof(uc->config));
442 uc->config.remote_thread_id = -1;
443 uc->config.mapped_channel_id = -1;
444 uc->config.default_flow_id = -1;
445 uc->state = UDMA_CHAN_IS_IDLE;
446 }
447
448 static void udma_dump_chan_stdata(struct udma_chan *uc)
449 {
450 struct device *dev = uc->ud->dev;
451 u32 offset;
452 int i;
453
454 if (uc->config.dir == DMA_MEM_TO_DEV || uc->config.dir == DMA_MEM_TO_MEM) {
455 dev_dbg(dev, "TCHAN State data:\n");
456 for (i = 0; i < 32; i++) {
457 offset = UDMA_CHAN_RT_STDATA_REG + i * 4;
458 dev_dbg(dev, "TRT_STDATA[%02d]: 0x%08x\n", i,
459 udma_tchanrt_read(uc, offset));
460 }
461 }
462
463 if (uc->config.dir == DMA_DEV_TO_MEM || uc->config.dir == DMA_MEM_TO_MEM) {
464 dev_dbg(dev, "RCHAN State data:\n");
465 for (i = 0; i < 32; i++) {
466 offset = UDMA_CHAN_RT_STDATA_REG + i * 4;
467 dev_dbg(dev, "RRT_STDATA[%02d]: 0x%08x\n", i,
468 udma_rchanrt_read(uc, offset));
469 }
470 }
471 }
472
473 static inline dma_addr_t udma_curr_cppi5_desc_paddr(struct udma_desc *d,
474 int idx)
475 {
476 return d->hwdesc[idx].cppi5_desc_paddr;
477 }
478
479 static inline void *udma_curr_cppi5_desc_vaddr(struct udma_desc *d, int idx)
480 {
481 return d->hwdesc[idx].cppi5_desc_vaddr;
482 }
483
484 static struct udma_desc *udma_udma_desc_from_paddr(struct udma_chan *uc,
485 dma_addr_t paddr)
486 {
487 struct udma_desc *d = uc->terminated_desc;
488
489 if (d) {
490 dma_addr_t desc_paddr = udma_curr_cppi5_desc_paddr(d,
491 d->desc_idx);
492
493 if (desc_paddr != paddr)
494 d = NULL;
495 }
496
497 if (!d) {
498 d = uc->desc;
499 if (d) {
500 dma_addr_t desc_paddr = udma_curr_cppi5_desc_paddr(d,
501 d->desc_idx);
502
503 if (desc_paddr != paddr)
504 d = NULL;
505 }
506 }
507
508 return d;
509 }
510
511 static void udma_free_hwdesc(struct udma_chan *uc, struct udma_desc *d)
512 {
513 if (uc->use_dma_pool) {
514 int i;
515
516 for (i = 0; i < d->hwdesc_count; i++) {
517 if (!d->hwdesc[i].cppi5_desc_vaddr)
518 continue;
519
520 dma_pool_free(uc->hdesc_pool,
521 d->hwdesc[i].cppi5_desc_vaddr,
522 d->hwdesc[i].cppi5_desc_paddr);
523
524 d->hwdesc[i].cppi5_desc_vaddr = NULL;
525 }
526 } else if (d->hwdesc[0].cppi5_desc_vaddr) {
527 dma_free_coherent(uc->dma_dev, d->hwdesc[0].cppi5_desc_size,
528 d->hwdesc[0].cppi5_desc_vaddr,
529 d->hwdesc[0].cppi5_desc_paddr);
530
531 d->hwdesc[0].cppi5_desc_vaddr = NULL;
532 }
533 }
534
535 static void udma_purge_desc_work(struct work_struct *work)
536 {
537 struct udma_dev *ud = container_of(work, typeof(*ud), purge_work);
538 struct virt_dma_desc *vd, *_vd;
539 unsigned long flags;
540 LIST_HEAD(head);
541
542 spin_lock_irqsave(&ud->lock, flags);
543 list_splice_tail_init(&ud->desc_to_purge, &head);
544 spin_unlock_irqrestore(&ud->lock, flags);
545
546 list_for_each_entry_safe(vd, _vd, &head, node) {
547 struct udma_chan *uc = to_udma_chan(vd->tx.chan);
548 struct udma_desc *d = to_udma_desc(&vd->tx);
549
550 udma_free_hwdesc(uc, d);
551 list_del(&vd->node);
552 kfree(d);
553 }
554
555 /* If more to purge, schedule the work again */
556 if (!list_empty(&ud->desc_to_purge))
557 schedule_work(&ud->purge_work);
558 }
559
560 static void udma_desc_free(struct virt_dma_desc *vd)
561 {
562 struct udma_dev *ud = to_udma_dev(vd->tx.chan->device);
563 struct udma_chan *uc = to_udma_chan(vd->tx.chan);
564 struct udma_desc *d = to_udma_desc(&vd->tx);
565 unsigned long flags;
566
567 if (uc->terminated_desc == d)
568 uc->terminated_desc = NULL;
569
570 if (uc->use_dma_pool) {
571 udma_free_hwdesc(uc, d);
572 kfree(d);
573 return;
574 }
575
576 spin_lock_irqsave(&ud->lock, flags);
577 list_add_tail(&vd->node, &ud->desc_to_purge);
578 spin_unlock_irqrestore(&ud->lock, flags);
579
580 schedule_work(&ud->purge_work);
581 }
582
583 static bool udma_is_chan_running(struct udma_chan *uc)
584 {
585 u32 trt_ctl = 0;
586 u32 rrt_ctl = 0;
587
588 if (uc->tchan)
589 trt_ctl = udma_tchanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
590 if (uc->rchan)
591 rrt_ctl = udma_rchanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
592
593 if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN)
594 return true;
595
596 return false;
597 }
598
599 static bool udma_is_chan_paused(struct udma_chan *uc)
600 {
601 u32 val, pause_mask;
602
603 switch (uc->config.dir) {
604 case DMA_DEV_TO_MEM:
605 val = udma_rchanrt_read(uc, UDMA_CHAN_RT_PEER_RT_EN_REG);
606 pause_mask = UDMA_PEER_RT_EN_PAUSE;
607 break;
608 case DMA_MEM_TO_DEV:
609 val = udma_tchanrt_read(uc, UDMA_CHAN_RT_PEER_RT_EN_REG);
610 pause_mask = UDMA_PEER_RT_EN_PAUSE;
611 break;
612 case DMA_MEM_TO_MEM:
613 val = udma_tchanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
614 pause_mask = UDMA_CHAN_RT_CTL_PAUSE;
615 break;
616 default:
617 return false;
618 }
619
620 if (val & pause_mask)
621 return true;
622
623 return false;
624 }
625
626 static inline dma_addr_t udma_get_rx_flush_hwdesc_paddr(struct udma_chan *uc)
627 {
628 return uc->ud->rx_flush.hwdescs[uc->config.pkt_mode].cppi5_desc_paddr;
629 }
630
631 static int udma_push_to_ring(struct udma_chan *uc, int idx)
632 {
633 struct udma_desc *d = uc->desc;
634 struct k3_ring *ring = NULL;
635 dma_addr_t paddr;
636
637 switch (uc->config.dir) {
638 case DMA_DEV_TO_MEM:
639 ring = uc->rflow->fd_ring;
640 break;
641 case DMA_MEM_TO_DEV:
642 case DMA_MEM_TO_MEM:
643 ring = uc->tchan->t_ring;
644 break;
645 default:
646 return -EINVAL;
647 }
648
649 /* RX flush packet: idx == -1 is only passed in case of DEV_TO_MEM */
650 if (idx == -1) {
651 paddr = udma_get_rx_flush_hwdesc_paddr(uc);
652 } else {
653 paddr = udma_curr_cppi5_desc_paddr(d, idx);
654
655 wmb(); /* Ensure that writes are not moved over this point */
656 }
657
658 return k3_ringacc_ring_push(ring, &paddr);
659 }
660
661 static bool udma_desc_is_rx_flush(struct udma_chan *uc, dma_addr_t addr)
662 {
663 if (uc->config.dir != DMA_DEV_TO_MEM)
664 return false;
665
666 if (addr == udma_get_rx_flush_hwdesc_paddr(uc))
667 return true;
668
669 return false;
670 }
671
672 static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr)
673 {
674 struct k3_ring *ring = NULL;
675 int ret;
676
677 switch (uc->config.dir) {
678 case DMA_DEV_TO_MEM:
679 ring = uc->rflow->r_ring;
680 break;
681 case DMA_MEM_TO_DEV:
682 case DMA_MEM_TO_MEM:
683 ring = uc->tchan->tc_ring;
684 break;
685 default:
686 return -ENOENT;
687 }
688
689 ret = k3_ringacc_ring_pop(ring, addr);
690 if (ret)
691 return ret;
692
693 rmb(); /* Ensure that reads are not moved before this point */
694
695 /* Teardown completion */
696 if (cppi5_desc_is_tdcm(*addr))
697 return 0;
698
699 /* Check for flush descriptor */
700 if (udma_desc_is_rx_flush(uc, *addr))
701 return -ENOENT;
702
703 return 0;
704 }
705
706 static void udma_reset_rings(struct udma_chan *uc)
707 {
708 struct k3_ring *ring1 = NULL;
709 struct k3_ring *ring2 = NULL;
710
711 switch (uc->config.dir) {
712 case DMA_DEV_TO_MEM:
713 if (uc->rchan) {
714 ring1 = uc->rflow->fd_ring;
715 ring2 = uc->rflow->r_ring;
716 }
717 break;
718 case DMA_MEM_TO_DEV:
719 case DMA_MEM_TO_MEM:
720 if (uc->tchan) {
721 ring1 = uc->tchan->t_ring;
722 ring2 = uc->tchan->tc_ring;
723 }
724 break;
725 default:
726 break;
727 }
728
729 if (ring1)
730 k3_ringacc_ring_reset_dma(ring1,
731 k3_ringacc_ring_get_occ(ring1));
732 if (ring2)
733 k3_ringacc_ring_reset(ring2);
734
735 /* make sure we are not leaking memory by stalled descriptor */
736 if (uc->terminated_desc) {
737 udma_desc_free(&uc->terminated_desc->vd);
738 uc->terminated_desc = NULL;
739 }
740 }
741
742 static void udma_reset_counters(struct udma_chan *uc)
743 {
744 u32 val;
745
746 if (uc->tchan) {
747 val = udma_tchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
748 udma_tchanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
749
750 val = udma_tchanrt_read(uc, UDMA_CHAN_RT_SBCNT_REG);
751 udma_tchanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
752
753 val = udma_tchanrt_read(uc, UDMA_CHAN_RT_PCNT_REG);
754 udma_tchanrt_write(uc, UDMA_CHAN_RT_PCNT_REG, val);
755
756 if (!uc->bchan) {
757 val = udma_tchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG);
758 udma_tchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val);
759 }
760 }
761
762 if (uc->rchan) {
763 val = udma_rchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
764 udma_rchanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
765
766 val = udma_rchanrt_read(uc, UDMA_CHAN_RT_SBCNT_REG);
767 udma_rchanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
768
769 val = udma_rchanrt_read(uc, UDMA_CHAN_RT_PCNT_REG);
770 udma_rchanrt_write(uc, UDMA_CHAN_RT_PCNT_REG, val);
771
772 val = udma_rchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG);
773 udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val);
774 }
775
776 uc->bcnt = 0;
777 }
778
779 static int udma_reset_chan(struct udma_chan *uc, bool hard)
780 {
781 switch (uc->config.dir) {
782 case DMA_DEV_TO_MEM:
783 udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_RT_EN_REG, 0);
784 udma_rchanrt_write(uc, UDMA_CHAN_RT_CTL_REG, 0);
785 break;
786 case DMA_MEM_TO_DEV:
787 udma_tchanrt_write(uc, UDMA_CHAN_RT_CTL_REG, 0);
788 udma_tchanrt_write(uc, UDMA_CHAN_RT_PEER_RT_EN_REG, 0);
789 break;
790 case DMA_MEM_TO_MEM:
791 udma_rchanrt_write(uc, UDMA_CHAN_RT_CTL_REG, 0);
792 udma_tchanrt_write(uc, UDMA_CHAN_RT_CTL_REG, 0);
793 break;
794 default:
795 return -EINVAL;
796 }
797
798 /* Reset all counters */
799 udma_reset_counters(uc);
800
801 /* Hard reset: re-initialize the channel to reset */
802 if (hard) {
803 struct udma_chan_config ucc_backup;
804 int ret;
805
806 memcpy(&ucc_backup, &uc->config, sizeof(uc->config));
807 uc->ud->ddev.device_free_chan_resources(&uc->vc.chan);
808
809 /* restore the channel configuration */
810 memcpy(&uc->config, &ucc_backup, sizeof(uc->config));
811 ret = uc->ud->ddev.device_alloc_chan_resources(&uc->vc.chan);
812 if (ret)
813 return ret;
814
815 /*
816 * Setting forced teardown after forced reset helps recovering
817 * the rchan.
818 */
819 if (uc->config.dir == DMA_DEV_TO_MEM)
820 udma_rchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
821 UDMA_CHAN_RT_CTL_EN |
822 UDMA_CHAN_RT_CTL_TDOWN |
823 UDMA_CHAN_RT_CTL_FTDOWN);
824 }
825 uc->state = UDMA_CHAN_IS_IDLE;
826
827 return 0;
828 }
829
830 static void udma_start_desc(struct udma_chan *uc)
831 {
832 struct udma_chan_config *ucc = &uc->config;
833
834 if (uc->ud->match_data->type == DMA_TYPE_UDMA && ucc->pkt_mode &&
835 (uc->cyclic || ucc->dir == DMA_DEV_TO_MEM)) {
836 int i;
837
838 /*
839 * UDMA only: Push all descriptors to ring for packet mode
840 * cyclic or RX
841 * PKTDMA supports pre-linked descriptor and cyclic is not
842 * supported
843 */
844 for (i = 0; i < uc->desc->sglen; i++)
845 udma_push_to_ring(uc, i);
846 } else {
847 udma_push_to_ring(uc, 0);
848 }
849 }
850
851 static bool udma_chan_needs_reconfiguration(struct udma_chan *uc)
852 {
853 /* Only PDMAs have staticTR */
854 if (uc->config.ep_type == PSIL_EP_NATIVE)
855 return false;
856
857 /* Check if the staticTR configuration has changed for TX */
858 if (memcmp(&uc->static_tr, &uc->desc->static_tr, sizeof(uc->static_tr)))
859 return true;
860
861 return false;
862 }
863
864 static int udma_start(struct udma_chan *uc)
865 {
866 struct virt_dma_desc *vd = vchan_next_desc(&uc->vc);
867
868 if (!vd) {
869 uc->desc = NULL;
870 return -ENOENT;
871 }
872
873 list_del(&vd->node);
874
875 uc->desc = to_udma_desc(&vd->tx);
876
877 /* Channel is already running and does not need reconfiguration */
878 if (udma_is_chan_running(uc) && !udma_chan_needs_reconfiguration(uc)) {
879 udma_start_desc(uc);
880 goto out;
881 }
882
883 /* Make sure that we clear the teardown bit, if it is set */
884 udma_reset_chan(uc, false);
885
886 /* Push descriptors before we start the channel */
887 udma_start_desc(uc);
888
889 switch (uc->desc->dir) {
890 case DMA_DEV_TO_MEM:
891 /* Config remote TR */
892 if (uc->config.ep_type == PSIL_EP_PDMA_XY) {
893 u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) |
894 PDMA_STATIC_TR_X(uc->desc->static_tr.elsize);
895 const struct udma_match_data *match_data =
896 uc->ud->match_data;
897
898 if (uc->config.enable_acc32)
899 val |= PDMA_STATIC_TR_XY_ACC32;
900 if (uc->config.enable_burst)
901 val |= PDMA_STATIC_TR_XY_BURST;
902
903 udma_rchanrt_write(uc,
904 UDMA_CHAN_RT_PEER_STATIC_TR_XY_REG,
905 val);
906
907 udma_rchanrt_write(uc,
908 UDMA_CHAN_RT_PEER_STATIC_TR_Z_REG,
909 PDMA_STATIC_TR_Z(uc->desc->static_tr.bstcnt,
910 match_data->statictr_z_mask));
911
912 /* save the current staticTR configuration */
913 memcpy(&uc->static_tr, &uc->desc->static_tr,
914 sizeof(uc->static_tr));
915 }
916
917 udma_rchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
918 UDMA_CHAN_RT_CTL_EN);
919
920 /* Enable remote */
921 udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_RT_EN_REG,
922 UDMA_PEER_RT_EN_ENABLE);
923
924 break;
925 case DMA_MEM_TO_DEV:
926 /* Config remote TR */
927 if (uc->config.ep_type == PSIL_EP_PDMA_XY) {
928 u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) |
929 PDMA_STATIC_TR_X(uc->desc->static_tr.elsize);
930
931 if (uc->config.enable_acc32)
932 val |= PDMA_STATIC_TR_XY_ACC32;
933 if (uc->config.enable_burst)
934 val |= PDMA_STATIC_TR_XY_BURST;
935
936 udma_tchanrt_write(uc,
937 UDMA_CHAN_RT_PEER_STATIC_TR_XY_REG,
938 val);
939
940 /* save the current staticTR configuration */
941 memcpy(&uc->static_tr, &uc->desc->static_tr,
942 sizeof(uc->static_tr));
943 }
944
945 /* Enable remote */
946 udma_tchanrt_write(uc, UDMA_CHAN_RT_PEER_RT_EN_REG,
947 UDMA_PEER_RT_EN_ENABLE);
948
949 udma_tchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
950 UDMA_CHAN_RT_CTL_EN);
951
952 break;
953 case DMA_MEM_TO_MEM:
954 udma_rchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
955 UDMA_CHAN_RT_CTL_EN);
956 udma_tchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
957 UDMA_CHAN_RT_CTL_EN);
958
959 break;
960 default:
961 return -EINVAL;
962 }
963
964 uc->state = UDMA_CHAN_IS_ACTIVE;
965 out:
966
967 return 0;
968 }
969
970 static int udma_stop(struct udma_chan *uc)
971 {
972 enum udma_chan_state old_state = uc->state;
973
974 uc->state = UDMA_CHAN_IS_TERMINATING;
975 reinit_completion(&uc->teardown_completed);
976
977 switch (uc->config.dir) {
978 case DMA_DEV_TO_MEM:
979 if (!uc->cyclic && !uc->desc)
980 udma_push_to_ring(uc, -1);
981
982 udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_RT_EN_REG,
983 UDMA_PEER_RT_EN_ENABLE |
984 UDMA_PEER_RT_EN_TEARDOWN);
985 break;
986 case DMA_MEM_TO_DEV:
987 udma_tchanrt_write(uc, UDMA_CHAN_RT_PEER_RT_EN_REG,
988 UDMA_PEER_RT_EN_ENABLE |
989 UDMA_PEER_RT_EN_FLUSH);
990 udma_tchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
991 UDMA_CHAN_RT_CTL_EN |
992 UDMA_CHAN_RT_CTL_TDOWN);
993 break;
994 case DMA_MEM_TO_MEM:
995 udma_tchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
996 UDMA_CHAN_RT_CTL_EN |
997 UDMA_CHAN_RT_CTL_TDOWN);
998 break;
999 default:
1000 uc->state = old_state;
1001 complete_all(&uc->teardown_completed);
1002 return -EINVAL;
1003 }
1004
1005 return 0;
1006 }
1007
1008 static void udma_cyclic_packet_elapsed(struct udma_chan *uc)
1009 {
1010 struct udma_desc *d = uc->desc;
1011 struct cppi5_host_desc_t *h_desc;
1012
1013 h_desc = d->hwdesc[d->desc_idx].cppi5_desc_vaddr;
1014 cppi5_hdesc_reset_to_original(h_desc);
1015 udma_push_to_ring(uc, d->desc_idx);
1016 d->desc_idx = (d->desc_idx + 1) % d->sglen;
1017 }
1018
1019 static inline void udma_fetch_epib(struct udma_chan *uc, struct udma_desc *d)
1020 {
1021 struct cppi5_host_desc_t *h_desc = d->hwdesc[0].cppi5_desc_vaddr;
1022
1023 memcpy(d->metadata, h_desc->epib, d->metadata_size);
1024 }
1025
1026 static bool udma_is_desc_really_done(struct udma_chan *uc, struct udma_desc *d)
1027 {
1028 u32 peer_bcnt, bcnt;
1029
1030 /* Only TX towards PDMA is affected */
1031 if (uc->config.ep_type == PSIL_EP_NATIVE ||
1032 uc->config.dir != DMA_MEM_TO_DEV)
1033 return true;
1034
1035 peer_bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG);
1036 bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
1037
1038 /* Transfer is incomplete, store current residue and time stamp */
1039 if (peer_bcnt < bcnt) {
1040 uc->tx_drain.residue = bcnt - peer_bcnt;
1041 uc->tx_drain.tstamp = ktime_get();
1042 return false;
1043 }
1044
1045 return true;
1046 }
1047
1048 static void udma_check_tx_completion(struct work_struct *work)
1049 {
1050 struct udma_chan *uc = container_of(work, typeof(*uc),
1051 tx_drain.work.work);
1052 bool desc_done = true;
1053 u32 residue_diff;
1054 ktime_t time_diff;
1055 unsigned long delay;
1056
1057 while (1) {
1058 if (uc->desc) {
1059 /* Get previous residue and time stamp */
1060 residue_diff = uc->tx_drain.residue;
1061 time_diff = uc->tx_drain.tstamp;
1062 /*
1063 * Get current residue and time stamp or see if
1064 * transfer is complete
1065 */
1066 desc_done = udma_is_desc_really_done(uc, uc->desc);
1067 }
1068
1069 if (!desc_done) {
1070 /*
1071 * Find the time delta and residue delta w.r.t
1072 * previous poll
1073 */
1074 time_diff = ktime_sub(uc->tx_drain.tstamp,
1075 time_diff) + 1;
1076 residue_diff -= uc->tx_drain.residue;
1077 if (residue_diff) {
1078 /*
1079 * Try to guess when we should check
1080 * next time by calculating rate at
1081 * which data is being drained at the
1082 * peer device
1083 */
1084 delay = (time_diff / residue_diff) *
1085 uc->tx_drain.residue;
1086 } else {
1087 /* No progress, check again in 1 second */
1088 schedule_delayed_work(&uc->tx_drain.work, HZ);
1089 break;
1090 }
1091
1092 usleep_range(ktime_to_us(delay),
1093 ktime_to_us(delay) + 10);
1094 continue;
1095 }
1096
1097 if (uc->desc) {
1098 struct udma_desc *d = uc->desc;
1099
1100 uc->bcnt += d->residue;
1101 udma_start(uc);
1102 vchan_cookie_complete(&d->vd);
1103 break;
1104 }
1105
1106 break;
1107 }
1108 }
1109
1110 static irqreturn_t udma_ring_irq_handler(int irq, void *data)
1111 {
1112 struct udma_chan *uc = data;
1113 struct udma_desc *d;
1114 dma_addr_t paddr = 0;
1115
1116 if (udma_pop_from_ring(uc, &paddr) || !paddr)
1117 return IRQ_HANDLED;
1118
1119 spin_lock(&uc->vc.lock);
1120
1121 /* Teardown completion message */
1122 if (cppi5_desc_is_tdcm(paddr)) {
1123 complete_all(&uc->teardown_completed);
1124
1125 if (uc->terminated_desc) {
1126 udma_desc_free(&uc->terminated_desc->vd);
1127 uc->terminated_desc = NULL;
1128 }
1129
1130 if (!uc->desc)
1131 udma_start(uc);
1132
1133 goto out;
1134 }
1135
1136 d = udma_udma_desc_from_paddr(uc, paddr);
1137
1138 if (d) {
1139 dma_addr_t desc_paddr = udma_curr_cppi5_desc_paddr(d,
1140 d->desc_idx);
1141 if (desc_paddr != paddr) {
1142 dev_err(uc->ud->dev, "not matching descriptors!\n");
1143 goto out;
1144 }
1145
1146 if (d == uc->desc) {
1147 /* active descriptor */
1148 if (uc->cyclic) {
1149 udma_cyclic_packet_elapsed(uc);
1150 vchan_cyclic_callback(&d->vd);
1151 } else {
1152 if (udma_is_desc_really_done(uc, d)) {
1153 uc->bcnt += d->residue;
1154 udma_start(uc);
1155 vchan_cookie_complete(&d->vd);
1156 } else {
1157 schedule_delayed_work(&uc->tx_drain.work,
1158 0);
1159 }
1160 }
1161 } else {
1162 /*
1163 * terminated descriptor, mark the descriptor as
1164 * completed to update the channel's cookie marker
1165 */
1166 dma_cookie_complete(&d->vd.tx);
1167 }
1168 }
1169 out:
1170 spin_unlock(&uc->vc.lock);
1171
1172 return IRQ_HANDLED;
1173 }
1174
1175 static irqreturn_t udma_udma_irq_handler(int irq, void *data)
1176 {
1177 struct udma_chan *uc = data;
1178 struct udma_desc *d;
1179
1180 spin_lock(&uc->vc.lock);
1181 d = uc->desc;
1182 if (d) {
1183 d->tr_idx = (d->tr_idx + 1) % d->sglen;
1184
1185 if (uc->cyclic) {
1186 vchan_cyclic_callback(&d->vd);
1187 } else {
1188 /* TODO: figure out the real amount of data */
1189 uc->bcnt += d->residue;
1190 udma_start(uc);
1191 vchan_cookie_complete(&d->vd);
1192 }
1193 }
1194
1195 spin_unlock(&uc->vc.lock);
1196
1197 return IRQ_HANDLED;
1198 }
1199
1200 /**
1201 * __udma_alloc_gp_rflow_range - alloc range of GP RX flows
1202 * @ud: UDMA device
1203 * @from: Start the search from this flow id number
1204 * @cnt: Number of consecutive flow ids to allocate
1205 *
1206 * Allocate range of RX flow ids for future use, those flows can be requested
1207 * only using explicit flow id number. if @from is set to -1 it will try to find
1208 * first free range. if @from is positive value it will force allocation only
1209 * of the specified range of flows.
1210 *
1211 * Returns -ENOMEM if can't find free range.
1212 * -EEXIST if requested range is busy.
1213 * -EINVAL if wrong input values passed.
1214 * Returns flow id on success.
1215 */
1216 static int __udma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt)
1217 {
1218 int start, tmp_from;
1219 DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS);
1220
1221 tmp_from = from;
1222 if (tmp_from < 0)
1223 tmp_from = ud->rchan_cnt;
1224 /* default flows can't be allocated and accessible only by id */
1225 if (tmp_from < ud->rchan_cnt)
1226 return -EINVAL;
1227
1228 if (tmp_from + cnt > ud->rflow_cnt)
1229 return -EINVAL;
1230
1231 bitmap_or(tmp, ud->rflow_gp_map, ud->rflow_gp_map_allocated,
1232 ud->rflow_cnt);
1233
1234 start = bitmap_find_next_zero_area(tmp,
1235 ud->rflow_cnt,
1236 tmp_from, cnt, 0);
1237 if (start >= ud->rflow_cnt)
1238 return -ENOMEM;
1239
1240 if (from >= 0 && start != from)
1241 return -EEXIST;
1242
1243 bitmap_set(ud->rflow_gp_map_allocated, start, cnt);
1244 return start;
1245 }
1246
1247 static int __udma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt)
1248 {
1249 if (from < ud->rchan_cnt)
1250 return -EINVAL;
1251 if (from + cnt > ud->rflow_cnt)
1252 return -EINVAL;
1253
1254 bitmap_clear(ud->rflow_gp_map_allocated, from, cnt);
1255 return 0;
1256 }
1257
1258 static struct udma_rflow *__udma_get_rflow(struct udma_dev *ud, int id)
1259 {
1260 /*
1261 * Attempt to request rflow by ID can be made for any rflow
1262 * if not in use with assumption that caller knows what's doing.
1263 * TI-SCI FW will perform additional permission check ant way, it's
1264 * safe
1265 */
1266
1267 if (id < 0 || id >= ud->rflow_cnt)
1268 return ERR_PTR(-ENOENT);
1269
1270 if (test_bit(id, ud->rflow_in_use))
1271 return ERR_PTR(-ENOENT);
1272
1273 if (ud->rflow_gp_map) {
1274 /* GP rflow has to be allocated first */
1275 if (!test_bit(id, ud->rflow_gp_map) &&
1276 !test_bit(id, ud->rflow_gp_map_allocated))
1277 return ERR_PTR(-EINVAL);
1278 }
1279
1280 dev_dbg(ud->dev, "get rflow%d\n", id);
1281 set_bit(id, ud->rflow_in_use);
1282 return &ud->rflows[id];
1283 }
1284
1285 static void __udma_put_rflow(struct udma_dev *ud, struct udma_rflow *rflow)
1286 {
1287 if (!test_bit(rflow->id, ud->rflow_in_use)) {
1288 dev_err(ud->dev, "attempt to put unused rflow%d\n", rflow->id);
1289 return;
1290 }
1291
1292 dev_dbg(ud->dev, "put rflow%d\n", rflow->id);
1293 clear_bit(rflow->id, ud->rflow_in_use);
1294 }
1295
1296 #define UDMA_RESERVE_RESOURCE(res) \
1297 static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \
1298 enum udma_tp_level tpl, \
1299 int id) \
1300 { \
1301 if (id >= 0) { \
1302 if (test_bit(id, ud->res##_map)) { \
1303 dev_err(ud->dev, "res##%d is in use\n", id); \
1304 return ERR_PTR(-ENOENT); \
1305 } \
1306 } else { \
1307 int start; \
1308 \
1309 if (tpl >= ud->res##_tpl.levels) \
1310 tpl = ud->res##_tpl.levels - 1; \
1311 \
1312 start = ud->res##_tpl.start_idx[tpl]; \
1313 \
1314 id = find_next_zero_bit(ud->res##_map, ud->res##_cnt, \
1315 start); \
1316 if (id == ud->res##_cnt) { \
1317 return ERR_PTR(-ENOENT); \
1318 } \
1319 } \
1320 \
1321 set_bit(id, ud->res##_map); \
1322 return &ud->res##s[id]; \
1323 }
1324
1325 UDMA_RESERVE_RESOURCE(bchan);
1326 UDMA_RESERVE_RESOURCE(tchan);
1327 UDMA_RESERVE_RESOURCE(rchan);
1328
1329 static int bcdma_get_bchan(struct udma_chan *uc)
1330 {
1331 struct udma_dev *ud = uc->ud;
1332 enum udma_tp_level tpl;
1333
1334 if (uc->bchan) {
1335 dev_dbg(ud->dev, "chan%d: already have bchan%d allocated\n",
1336 uc->id, uc->bchan->id);
1337 return 0;
1338 }
1339
1340 /*
1341 * Use normal channels for peripherals, and highest TPL channel for
1342 * mem2mem
1343 */
1344 if (uc->config.tr_trigger_type)
1345 tpl = 0;
1346 else
1347 tpl = ud->bchan_tpl.levels - 1;
1348
1349 uc->bchan = __udma_reserve_bchan(ud, tpl, -1);
1350 if (IS_ERR(uc->bchan))
1351 return PTR_ERR(uc->bchan);
1352
1353 uc->tchan = uc->bchan;
1354
1355 return 0;
1356 }
1357
1358 static int udma_get_tchan(struct udma_chan *uc)
1359 {
1360 struct udma_dev *ud = uc->ud;
1361
1362 if (uc->tchan) {
1363 dev_dbg(ud->dev, "chan%d: already have tchan%d allocated\n",
1364 uc->id, uc->tchan->id);
1365 return 0;
1366 }
1367
1368 /*
1369 * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels.
1370 * For PKTDMA mapped channels it is configured to a channel which must
1371 * be used to service the peripheral.
1372 */
1373 uc->tchan = __udma_reserve_tchan(ud, uc->config.channel_tpl,
1374 uc->config.mapped_channel_id);
1375 if (IS_ERR(uc->tchan))
1376 return PTR_ERR(uc->tchan);
1377
1378 if (ud->tflow_cnt) {
1379 int tflow_id;
1380
1381 /* Only PKTDMA have support for tx flows */
1382 if (uc->config.default_flow_id >= 0)
1383 tflow_id = uc->config.default_flow_id;
1384 else
1385 tflow_id = uc->tchan->id;
1386
1387 if (test_bit(tflow_id, ud->tflow_map)) {
1388 dev_err(ud->dev, "tflow%d is in use\n", tflow_id);
1389 clear_bit(uc->tchan->id, ud->tchan_map);
1390 uc->tchan = NULL;
1391 return -ENOENT;
1392 }
1393
1394 uc->tchan->tflow_id = tflow_id;
1395 set_bit(tflow_id, ud->tflow_map);
1396 } else {
1397 uc->tchan->tflow_id = -1;
1398 }
1399
1400 return 0;
1401 }
1402
1403 static int udma_get_rchan(struct udma_chan *uc)
1404 {
1405 struct udma_dev *ud = uc->ud;
1406
1407 if (uc->rchan) {
1408 dev_dbg(ud->dev, "chan%d: already have rchan%d allocated\n",
1409 uc->id, uc->rchan->id);
1410 return 0;
1411 }
1412
1413 /*
1414 * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels.
1415 * For PKTDMA mapped channels it is configured to a channel which must
1416 * be used to service the peripheral.
1417 */
1418 uc->rchan = __udma_reserve_rchan(ud, uc->config.channel_tpl,
1419 uc->config.mapped_channel_id);
1420
1421 return PTR_ERR_OR_ZERO(uc->rchan);
1422 }
1423
1424 static int udma_get_chan_pair(struct udma_chan *uc)
1425 {
1426 struct udma_dev *ud = uc->ud;
1427 int chan_id, end;
1428
1429 if ((uc->tchan && uc->rchan) && uc->tchan->id == uc->rchan->id) {
1430 dev_info(ud->dev, "chan%d: already have %d pair allocated\n",
1431 uc->id, uc->tchan->id);
1432 return 0;
1433 }
1434
1435 if (uc->tchan) {
1436 dev_err(ud->dev, "chan%d: already have tchan%d allocated\n",
1437 uc->id, uc->tchan->id);
1438 return -EBUSY;
1439 } else if (uc->rchan) {
1440 dev_err(ud->dev, "chan%d: already have rchan%d allocated\n",
1441 uc->id, uc->rchan->id);
1442 return -EBUSY;
1443 }
1444
1445 /* Can be optimized, but let's have it like this for now */
1446 end = min(ud->tchan_cnt, ud->rchan_cnt);
1447 /*
1448 * Try to use the highest TPL channel pair for MEM_TO_MEM channels
1449 * Note: in UDMAP the channel TPL is symmetric between tchan and rchan
1450 */
1451 chan_id = ud->tchan_tpl.start_idx[ud->tchan_tpl.levels - 1];
1452 for (; chan_id < end; chan_id++) {
1453 if (!test_bit(chan_id, ud->tchan_map) &&
1454 !test_bit(chan_id, ud->rchan_map))
1455 break;
1456 }
1457
1458 if (chan_id == end)
1459 return -ENOENT;
1460
1461 set_bit(chan_id, ud->tchan_map);
1462 set_bit(chan_id, ud->rchan_map);
1463 uc->tchan = &ud->tchans[chan_id];
1464 uc->rchan = &ud->rchans[chan_id];
1465
1466 /* UDMA does not use tx flows */
1467 uc->tchan->tflow_id = -1;
1468
1469 return 0;
1470 }
1471
1472 static int udma_get_rflow(struct udma_chan *uc, int flow_id)
1473 {
1474 struct udma_dev *ud = uc->ud;
1475
1476 if (!uc->rchan) {
1477 dev_err(ud->dev, "chan%d: does not have rchan??\n", uc->id);
1478 return -EINVAL;
1479 }
1480
1481 if (uc->rflow) {
1482 dev_dbg(ud->dev, "chan%d: already have rflow%d allocated\n",
1483 uc->id, uc->rflow->id);
1484 return 0;
1485 }
1486
1487 uc->rflow = __udma_get_rflow(ud, flow_id);
1488
1489 return PTR_ERR_OR_ZERO(uc->rflow);
1490 }
1491
1492 static void bcdma_put_bchan(struct udma_chan *uc)
1493 {
1494 struct udma_dev *ud = uc->ud;
1495
1496 if (uc->bchan) {
1497 dev_dbg(ud->dev, "chan%d: put bchan%d\n", uc->id,
1498 uc->bchan->id);
1499 clear_bit(uc->bchan->id, ud->bchan_map);
1500 uc->bchan = NULL;
1501 uc->tchan = NULL;
1502 }
1503 }
1504
1505 static void udma_put_rchan(struct udma_chan *uc)
1506 {
1507 struct udma_dev *ud = uc->ud;
1508
1509 if (uc->rchan) {
1510 dev_dbg(ud->dev, "chan%d: put rchan%d\n", uc->id,
1511 uc->rchan->id);
1512 clear_bit(uc->rchan->id, ud->rchan_map);
1513 uc->rchan = NULL;
1514 }
1515 }
1516
1517 static void udma_put_tchan(struct udma_chan *uc)
1518 {
1519 struct udma_dev *ud = uc->ud;
1520
1521 if (uc->tchan) {
1522 dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id,
1523 uc->tchan->id);
1524 clear_bit(uc->tchan->id, ud->tchan_map);
1525
1526 if (uc->tchan->tflow_id >= 0)
1527 clear_bit(uc->tchan->tflow_id, ud->tflow_map);
1528
1529 uc->tchan = NULL;
1530 }
1531 }
1532
1533 static void udma_put_rflow(struct udma_chan *uc)
1534 {
1535 struct udma_dev *ud = uc->ud;
1536
1537 if (uc->rflow) {
1538 dev_dbg(ud->dev, "chan%d: put rflow%d\n", uc->id,
1539 uc->rflow->id);
1540 __udma_put_rflow(ud, uc->rflow);
1541 uc->rflow = NULL;
1542 }
1543 }
1544
1545 static void bcdma_free_bchan_resources(struct udma_chan *uc)
1546 {
1547 if (!uc->bchan)
1548 return;
1549
1550 k3_ringacc_ring_free(uc->bchan->tc_ring);
1551 k3_ringacc_ring_free(uc->bchan->t_ring);
1552 uc->bchan->tc_ring = NULL;
1553 uc->bchan->t_ring = NULL;
1554 k3_configure_chan_coherency(&uc->vc.chan, 0);
1555
1556 bcdma_put_bchan(uc);
1557 }
1558
1559 static int bcdma_alloc_bchan_resources(struct udma_chan *uc)
1560 {
1561 struct k3_ring_cfg ring_cfg;
1562 struct udma_dev *ud = uc->ud;
1563 int ret;
1564
1565 ret = bcdma_get_bchan(uc);
1566 if (ret)
1567 return ret;
1568
1569 ret = k3_ringacc_request_rings_pair(ud->ringacc, uc->bchan->id, -1,
1570 &uc->bchan->t_ring,
1571 &uc->bchan->tc_ring);
1572 if (ret) {
1573 ret = -EBUSY;
1574 goto err_ring;
1575 }
1576
1577 memset(&ring_cfg, 0, sizeof(ring_cfg));
1578 ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
1579 ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
1580 ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
1581
1582 k3_configure_chan_coherency(&uc->vc.chan, ud->asel);
1583 ring_cfg.asel = ud->asel;
1584 ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan);
1585
1586 ret = k3_ringacc_ring_cfg(uc->bchan->t_ring, &ring_cfg);
1587 if (ret)
1588 goto err_ringcfg;
1589
1590 return 0;
1591
1592 err_ringcfg:
1593 k3_ringacc_ring_free(uc->bchan->tc_ring);
1594 uc->bchan->tc_ring = NULL;
1595 k3_ringacc_ring_free(uc->bchan->t_ring);
1596 uc->bchan->t_ring = NULL;
1597 k3_configure_chan_coherency(&uc->vc.chan, 0);
1598 err_ring:
1599 bcdma_put_bchan(uc);
1600
1601 return ret;
1602 }
1603
1604 static void udma_free_tx_resources(struct udma_chan *uc)
1605 {
1606 if (!uc->tchan)
1607 return;
1608
1609 k3_ringacc_ring_free(uc->tchan->t_ring);
1610 k3_ringacc_ring_free(uc->tchan->tc_ring);
1611 uc->tchan->t_ring = NULL;
1612 uc->tchan->tc_ring = NULL;
1613
1614 udma_put_tchan(uc);
1615 }
1616
1617 static int udma_alloc_tx_resources(struct udma_chan *uc)
1618 {
1619 struct k3_ring_cfg ring_cfg;
1620 struct udma_dev *ud = uc->ud;
1621 struct udma_tchan *tchan;
1622 int ring_idx, ret;
1623
1624 ret = udma_get_tchan(uc);
1625 if (ret)
1626 return ret;
1627
1628 tchan = uc->tchan;
1629 if (tchan->tflow_id >= 0)
1630 ring_idx = tchan->tflow_id;
1631 else
1632 ring_idx = ud->bchan_cnt + tchan->id;
1633
1634 ret = k3_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1,
1635 &tchan->t_ring,
1636 &tchan->tc_ring);
1637 if (ret) {
1638 ret = -EBUSY;
1639 goto err_ring;
1640 }
1641
1642 memset(&ring_cfg, 0, sizeof(ring_cfg));
1643 ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
1644 ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
1645 if (ud->match_data->type == DMA_TYPE_UDMA) {
1646 ring_cfg.mode = K3_RINGACC_RING_MODE_MESSAGE;
1647 } else {
1648 ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
1649
1650 k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel);
1651 ring_cfg.asel = uc->config.asel;
1652 ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan);
1653 }
1654
1655 ret = k3_ringacc_ring_cfg(tchan->t_ring, &ring_cfg);
1656 ret |= k3_ringacc_ring_cfg(tchan->tc_ring, &ring_cfg);
1657
1658 if (ret)
1659 goto err_ringcfg;
1660
1661 return 0;
1662
1663 err_ringcfg:
1664 k3_ringacc_ring_free(uc->tchan->tc_ring);
1665 uc->tchan->tc_ring = NULL;
1666 k3_ringacc_ring_free(uc->tchan->t_ring);
1667 uc->tchan->t_ring = NULL;
1668 err_ring:
1669 udma_put_tchan(uc);
1670
1671 return ret;
1672 }
1673
1674 static void udma_free_rx_resources(struct udma_chan *uc)
1675 {
1676 if (!uc->rchan)
1677 return;
1678
1679 if (uc->rflow) {
1680 struct udma_rflow *rflow = uc->rflow;
1681
1682 k3_ringacc_ring_free(rflow->fd_ring);
1683 k3_ringacc_ring_free(rflow->r_ring);
1684 rflow->fd_ring = NULL;
1685 rflow->r_ring = NULL;
1686
1687 udma_put_rflow(uc);
1688 }
1689
1690 udma_put_rchan(uc);
1691 }
1692
1693 static int udma_alloc_rx_resources(struct udma_chan *uc)
1694 {
1695 struct udma_dev *ud = uc->ud;
1696 struct k3_ring_cfg ring_cfg;
1697 struct udma_rflow *rflow;
1698 int fd_ring_id;
1699 int ret;
1700
1701 ret = udma_get_rchan(uc);
1702 if (ret)
1703 return ret;
1704
1705 /* For MEM_TO_MEM we don't need rflow or rings */
1706 if (uc->config.dir == DMA_MEM_TO_MEM)
1707 return 0;
1708
1709 if (uc->config.default_flow_id >= 0)
1710 ret = udma_get_rflow(uc, uc->config.default_flow_id);
1711 else
1712 ret = udma_get_rflow(uc, uc->rchan->id);
1713
1714 if (ret) {
1715 ret = -EBUSY;
1716 goto err_rflow;
1717 }
1718
1719 rflow = uc->rflow;
1720 if (ud->tflow_cnt)
1721 fd_ring_id = ud->tflow_cnt + rflow->id;
1722 else
1723 fd_ring_id = ud->bchan_cnt + ud->tchan_cnt + ud->echan_cnt +
1724 uc->rchan->id;
1725
1726 ret = k3_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1,
1727 &rflow->fd_ring, &rflow->r_ring);
1728 if (ret) {
1729 ret = -EBUSY;
1730 goto err_ring;
1731 }
1732
1733 memset(&ring_cfg, 0, sizeof(ring_cfg));
1734
1735 ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
1736 if (ud->match_data->type == DMA_TYPE_UDMA) {
1737 if (uc->config.pkt_mode)
1738 ring_cfg.size = SG_MAX_SEGMENTS;
1739 else
1740 ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
1741
1742 ring_cfg.mode = K3_RINGACC_RING_MODE_MESSAGE;
1743 } else {
1744 ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
1745 ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
1746
1747 k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel);
1748 ring_cfg.asel = uc->config.asel;
1749 ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan);
1750 }
1751
1752 ret = k3_ringacc_ring_cfg(rflow->fd_ring, &ring_cfg);
1753
1754 ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
1755 ret |= k3_ringacc_ring_cfg(rflow->r_ring, &ring_cfg);
1756
1757 if (ret)
1758 goto err_ringcfg;
1759
1760 return 0;
1761
1762 err_ringcfg:
1763 k3_ringacc_ring_free(rflow->r_ring);
1764 rflow->r_ring = NULL;
1765 k3_ringacc_ring_free(rflow->fd_ring);
1766 rflow->fd_ring = NULL;
1767 err_ring:
1768 udma_put_rflow(uc);
1769 err_rflow:
1770 udma_put_rchan(uc);
1771
1772 return ret;
1773 }
1774
1775 #define TISCI_BCDMA_BCHAN_VALID_PARAMS ( \
1776 TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
1777 TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID)
1778
1779 #define TISCI_BCDMA_TCHAN_VALID_PARAMS ( \
1780 TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
1781 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID)
1782
1783 #define TISCI_BCDMA_RCHAN_VALID_PARAMS ( \
1784 TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID)
1785
1786 #define TISCI_UDMA_TCHAN_VALID_PARAMS ( \
1787 TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
1788 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID | \
1789 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID | \
1790 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \
1791 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID | \
1792 TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \
1793 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \
1794 TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID)
1795
1796 #define TISCI_UDMA_RCHAN_VALID_PARAMS ( \
1797 TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
1798 TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \
1799 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \
1800 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \
1801 TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID | \
1802 TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID | \
1803 TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID | \
1804 TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID | \
1805 TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID)
1806
1807 static int udma_tisci_m2m_channel_config(struct udma_chan *uc)
1808 {
1809 struct udma_dev *ud = uc->ud;
1810 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
1811 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
1812 struct udma_tchan *tchan = uc->tchan;
1813 struct udma_rchan *rchan = uc->rchan;
1814 int ret = 0;
1815
1816 /* Non synchronized - mem to mem type of transfer */
1817 int tc_ring = k3_ringacc_get_ring_id(tchan->tc_ring);
1818 struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx = { 0 };
1819 struct ti_sci_msg_rm_udmap_rx_ch_cfg req_rx = { 0 };
1820
1821 req_tx.valid_params = TISCI_UDMA_TCHAN_VALID_PARAMS;
1822 req_tx.nav_id = tisci_rm->tisci_dev_id;
1823 req_tx.index = tchan->id;
1824 req_tx.tx_chan_type = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR;
1825 req_tx.tx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
1826 req_tx.txcq_qnum = tc_ring;
1827 req_tx.tx_atype = ud->atype;
1828
1829 ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx);
1830 if (ret) {
1831 dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret);
1832 return ret;
1833 }
1834
1835 req_rx.valid_params = TISCI_UDMA_RCHAN_VALID_PARAMS;
1836 req_rx.nav_id = tisci_rm->tisci_dev_id;
1837 req_rx.index = rchan->id;
1838 req_rx.rx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
1839 req_rx.rxcq_qnum = tc_ring;
1840 req_rx.rx_chan_type = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR;
1841 req_rx.rx_atype = ud->atype;
1842
1843 ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx);
1844 if (ret)
1845 dev_err(ud->dev, "rchan%d alloc failed %d\n", rchan->id, ret);
1846
1847 return ret;
1848 }
1849
1850 static int bcdma_tisci_m2m_channel_config(struct udma_chan *uc)
1851 {
1852 struct udma_dev *ud = uc->ud;
1853 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
1854 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
1855 struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx = { 0 };
1856 struct udma_bchan *bchan = uc->bchan;
1857 int ret = 0;
1858
1859 req_tx.valid_params = TISCI_BCDMA_BCHAN_VALID_PARAMS;
1860 req_tx.nav_id = tisci_rm->tisci_dev_id;
1861 req_tx.extended_ch_type = TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN;
1862 req_tx.index = bchan->id;
1863
1864 ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx);
1865 if (ret)
1866 dev_err(ud->dev, "bchan%d cfg failed %d\n", bchan->id, ret);
1867
1868 return ret;
1869 }
1870
1871 static int udma_tisci_tx_channel_config(struct udma_chan *uc)
1872 {
1873 struct udma_dev *ud = uc->ud;
1874 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
1875 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
1876 struct udma_tchan *tchan = uc->tchan;
1877 int tc_ring = k3_ringacc_get_ring_id(tchan->tc_ring);
1878 struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx = { 0 };
1879 u32 mode, fetch_size;
1880 int ret = 0;
1881
1882 if (uc->config.pkt_mode) {
1883 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
1884 fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
1885 uc->config.psd_size, 0);
1886 } else {
1887 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR;
1888 fetch_size = sizeof(struct cppi5_desc_hdr_t);
1889 }
1890
1891 req_tx.valid_params = TISCI_UDMA_TCHAN_VALID_PARAMS;
1892 req_tx.nav_id = tisci_rm->tisci_dev_id;
1893 req_tx.index = tchan->id;
1894 req_tx.tx_chan_type = mode;
1895 req_tx.tx_supr_tdpkt = uc->config.notdpkt;
1896 req_tx.tx_fetch_size = fetch_size >> 2;
1897 req_tx.txcq_qnum = tc_ring;
1898 req_tx.tx_atype = uc->config.atype;
1899 if (uc->config.ep_type == PSIL_EP_PDMA_XY &&
1900 ud->match_data->flags & UDMA_FLAG_TDTYPE) {
1901 /* wait for peer to complete the teardown for PDMAs */
1902 req_tx.valid_params |=
1903 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID;
1904 req_tx.tx_tdtype = 1;
1905 }
1906
1907 ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx);
1908 if (ret)
1909 dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret);
1910
1911 return ret;
1912 }
1913
1914 static int bcdma_tisci_tx_channel_config(struct udma_chan *uc)
1915 {
1916 struct udma_dev *ud = uc->ud;
1917 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
1918 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
1919 struct udma_tchan *tchan = uc->tchan;
1920 struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx = { 0 };
1921 int ret = 0;
1922
1923 req_tx.valid_params = TISCI_BCDMA_TCHAN_VALID_PARAMS;
1924 req_tx.nav_id = tisci_rm->tisci_dev_id;
1925 req_tx.index = tchan->id;
1926 req_tx.tx_supr_tdpkt = uc->config.notdpkt;
1927 if (ud->match_data->flags & UDMA_FLAG_TDTYPE) {
1928 /* wait for peer to complete the teardown for PDMAs */
1929 req_tx.valid_params |=
1930 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID;
1931 req_tx.tx_tdtype = 1;
1932 }
1933
1934 ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx);
1935 if (ret)
1936 dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret);
1937
1938 return ret;
1939 }
1940
1941 #define pktdma_tisci_tx_channel_config bcdma_tisci_tx_channel_config
1942
1943 static int udma_tisci_rx_channel_config(struct udma_chan *uc)
1944 {
1945 struct udma_dev *ud = uc->ud;
1946 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
1947 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
1948 struct udma_rchan *rchan = uc->rchan;
1949 int fd_ring = k3_ringacc_get_ring_id(uc->rflow->fd_ring);
1950 int rx_ring = k3_ringacc_get_ring_id(uc->rflow->r_ring);
1951 struct ti_sci_msg_rm_udmap_rx_ch_cfg req_rx = { 0 };
1952 struct ti_sci_msg_rm_udmap_flow_cfg flow_req = { 0 };
1953 u32 mode, fetch_size;
1954 int ret = 0;
1955
1956 if (uc->config.pkt_mode) {
1957 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
1958 fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
1959 uc->config.psd_size, 0);
1960 } else {
1961 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR;
1962 fetch_size = sizeof(struct cppi5_desc_hdr_t);
1963 }
1964
1965 req_rx.valid_params = TISCI_UDMA_RCHAN_VALID_PARAMS;
1966 req_rx.nav_id = tisci_rm->tisci_dev_id;
1967 req_rx.index = rchan->id;
1968 req_rx.rx_fetch_size = fetch_size >> 2;
1969 req_rx.rxcq_qnum = rx_ring;
1970 req_rx.rx_chan_type = mode;
1971 req_rx.rx_atype = uc->config.atype;
1972
1973 ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx);
1974 if (ret) {
1975 dev_err(ud->dev, "rchan%d cfg failed %d\n", rchan->id, ret);
1976 return ret;
1977 }
1978
1979 flow_req.valid_params =
1980 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID |
1981 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID |
1982 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID |
1983 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID |
1984 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID |
1985 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID |
1986 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID |
1987 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID |
1988 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID |
1989 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID |
1990 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID |
1991 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID |
1992 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID;
1993
1994 flow_req.nav_id = tisci_rm->tisci_dev_id;
1995 flow_req.flow_index = rchan->id;
1996
1997 if (uc->config.needs_epib)
1998 flow_req.rx_einfo_present = 1;
1999 else
2000 flow_req.rx_einfo_present = 0;
2001 if (uc->config.psd_size)
2002 flow_req.rx_psinfo_present = 1;
2003 else
2004 flow_req.rx_psinfo_present = 0;
2005 flow_req.rx_error_handling = 1;
2006 flow_req.rx_dest_qnum = rx_ring;
2007 flow_req.rx_src_tag_hi_sel = UDMA_RFLOW_SRCTAG_NONE;
2008 flow_req.rx_src_tag_lo_sel = UDMA_RFLOW_SRCTAG_SRC_TAG;
2009 flow_req.rx_dest_tag_hi_sel = UDMA_RFLOW_DSTTAG_DST_TAG_HI;
2010 flow_req.rx_dest_tag_lo_sel = UDMA_RFLOW_DSTTAG_DST_TAG_LO;
2011 flow_req.rx_fdq0_sz0_qnum = fd_ring;
2012 flow_req.rx_fdq1_qnum = fd_ring;
2013 flow_req.rx_fdq2_qnum = fd_ring;
2014 flow_req.rx_fdq3_qnum = fd_ring;
2015
2016 ret = tisci_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req);
2017
2018 if (ret)
2019 dev_err(ud->dev, "flow%d config failed: %d\n", rchan->id, ret);
2020
2021 return 0;
2022 }
2023
2024 static int bcdma_tisci_rx_channel_config(struct udma_chan *uc)
2025 {
2026 struct udma_dev *ud = uc->ud;
2027 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
2028 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
2029 struct udma_rchan *rchan = uc->rchan;
2030 struct ti_sci_msg_rm_udmap_rx_ch_cfg req_rx = { 0 };
2031 int ret = 0;
2032
2033 req_rx.valid_params = TISCI_BCDMA_RCHAN_VALID_PARAMS;
2034 req_rx.nav_id = tisci_rm->tisci_dev_id;
2035 req_rx.index = rchan->id;
2036
2037 ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx);
2038 if (ret)
2039 dev_err(ud->dev, "rchan%d cfg failed %d\n", rchan->id, ret);
2040
2041 return ret;
2042 }
2043
2044 static int pktdma_tisci_rx_channel_config(struct udma_chan *uc)
2045 {
2046 struct udma_dev *ud = uc->ud;
2047 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
2048 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
2049 struct ti_sci_msg_rm_udmap_rx_ch_cfg req_rx = { 0 };
2050 struct ti_sci_msg_rm_udmap_flow_cfg flow_req = { 0 };
2051 int ret = 0;
2052
2053 req_rx.valid_params = TISCI_BCDMA_RCHAN_VALID_PARAMS;
2054 req_rx.nav_id = tisci_rm->tisci_dev_id;
2055 req_rx.index = uc->rchan->id;
2056
2057 ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx);
2058 if (ret) {
2059 dev_err(ud->dev, "rchan%d cfg failed %d\n", uc->rchan->id, ret);
2060 return ret;
2061 }
2062
2063 flow_req.valid_params =
2064 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID |
2065 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID |
2066 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID;
2067
2068 flow_req.nav_id = tisci_rm->tisci_dev_id;
2069 flow_req.flow_index = uc->rflow->id;
2070
2071 if (uc->config.needs_epib)
2072 flow_req.rx_einfo_present = 1;
2073 else
2074 flow_req.rx_einfo_present = 0;
2075 if (uc->config.psd_size)
2076 flow_req.rx_psinfo_present = 1;
2077 else
2078 flow_req.rx_psinfo_present = 0;
2079 flow_req.rx_error_handling = 1;
2080
2081 ret = tisci_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req);
2082
2083 if (ret)
2084 dev_err(ud->dev, "flow%d config failed: %d\n", uc->rflow->id,
2085 ret);
2086
2087 return ret;
2088 }
2089
2090 static int udma_alloc_chan_resources(struct dma_chan *chan)
2091 {
2092 struct udma_chan *uc = to_udma_chan(chan);
2093 struct udma_dev *ud = to_udma_dev(chan->device);
2094 const struct udma_soc_data *soc_data = ud->soc_data;
2095 struct k3_ring *irq_ring;
2096 u32 irq_udma_idx;
2097 int ret;
2098
2099 uc->dma_dev = ud->dev;
2100
2101 if (uc->config.pkt_mode || uc->config.dir == DMA_MEM_TO_MEM) {
2102 uc->use_dma_pool = true;
2103 /* in case of MEM_TO_MEM we have maximum of two TRs */
2104 if (uc->config.dir == DMA_MEM_TO_MEM) {
2105 uc->config.hdesc_size = cppi5_trdesc_calc_size(
2106 sizeof(struct cppi5_tr_type15_t), 2);
2107 uc->config.pkt_mode = false;
2108 }
2109 }
2110
2111 if (uc->use_dma_pool) {
2112 uc->hdesc_pool = dma_pool_create(uc->name, ud->ddev.dev,
2113 uc->config.hdesc_size,
2114 ud->desc_align,
2115 0);
2116 if (!uc->hdesc_pool) {
2117 dev_err(ud->ddev.dev,
2118 "Descriptor pool allocation failed\n");
2119 uc->use_dma_pool = false;
2120 ret = -ENOMEM;
2121 goto err_cleanup;
2122 }
2123 }
2124
2125 /*
2126 * Make sure that the completion is in a known state:
2127 * No teardown, the channel is idle
2128 */
2129 reinit_completion(&uc->teardown_completed);
2130 complete_all(&uc->teardown_completed);
2131 uc->state = UDMA_CHAN_IS_IDLE;
2132
2133 switch (uc->config.dir) {
2134 case DMA_MEM_TO_MEM:
2135 /* Non synchronized - mem to mem type of transfer */
2136 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__,
2137 uc->id);
2138
2139 ret = udma_get_chan_pair(uc);
2140 if (ret)
2141 goto err_cleanup;
2142
2143 ret = udma_alloc_tx_resources(uc);
2144 if (ret) {
2145 udma_put_rchan(uc);
2146 goto err_cleanup;
2147 }
2148
2149 ret = udma_alloc_rx_resources(uc);
2150 if (ret) {
2151 udma_free_tx_resources(uc);
2152 goto err_cleanup;
2153 }
2154
2155 uc->config.src_thread = ud->psil_base + uc->tchan->id;
2156 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
2157 K3_PSIL_DST_THREAD_ID_OFFSET;
2158
2159 irq_ring = uc->tchan->tc_ring;
2160 irq_udma_idx = uc->tchan->id;
2161
2162 ret = udma_tisci_m2m_channel_config(uc);
2163 break;
2164 case DMA_MEM_TO_DEV:
2165 /* Slave transfer synchronized - mem to dev (TX) trasnfer */
2166 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__,
2167 uc->id);
2168
2169 ret = udma_alloc_tx_resources(uc);
2170 if (ret)
2171 goto err_cleanup;
2172
2173 uc->config.src_thread = ud->psil_base + uc->tchan->id;
2174 uc->config.dst_thread = uc->config.remote_thread_id;
2175 uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
2176
2177 irq_ring = uc->tchan->tc_ring;
2178 irq_udma_idx = uc->tchan->id;
2179
2180 ret = udma_tisci_tx_channel_config(uc);
2181 break;
2182 case DMA_DEV_TO_MEM:
2183 /* Slave transfer synchronized - dev to mem (RX) trasnfer */
2184 dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__,
2185 uc->id);
2186
2187 ret = udma_alloc_rx_resources(uc);
2188 if (ret)
2189 goto err_cleanup;
2190
2191 uc->config.src_thread = uc->config.remote_thread_id;
2192 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
2193 K3_PSIL_DST_THREAD_ID_OFFSET;
2194
2195 irq_ring = uc->rflow->r_ring;
2196 irq_udma_idx = soc_data->oes.udma_rchan + uc->rchan->id;
2197
2198 ret = udma_tisci_rx_channel_config(uc);
2199 break;
2200 default:
2201 /* Can not happen */
2202 dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
2203 __func__, uc->id, uc->config.dir);
2204 ret = -EINVAL;
2205 goto err_cleanup;
2206
2207 }
2208
2209 /* check if the channel configuration was successful */
2210 if (ret)
2211 goto err_res_free;
2212
2213 if (udma_is_chan_running(uc)) {
2214 dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
2215 udma_reset_chan(uc, false);
2216 if (udma_is_chan_running(uc)) {
2217 dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
2218 ret = -EBUSY;
2219 goto err_res_free;
2220 }
2221 }
2222
2223 /* PSI-L pairing */
2224 ret = navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread);
2225 if (ret) {
2226 dev_err(ud->dev, "PSI-L pairing failed: 0x%04x -> 0x%04x\n",
2227 uc->config.src_thread, uc->config.dst_thread);
2228 goto err_res_free;
2229 }
2230
2231 uc->psil_paired = true;
2232
2233 uc->irq_num_ring = k3_ringacc_get_ring_irq_num(irq_ring);
2234 if (uc->irq_num_ring <= 0) {
2235 dev_err(ud->dev, "Failed to get ring irq (index: %u)\n",
2236 k3_ringacc_get_ring_id(irq_ring));
2237 ret = -EINVAL;
2238 goto err_psi_free;
2239 }
2240
2241 ret = request_irq(uc->irq_num_ring, udma_ring_irq_handler,
2242 IRQF_TRIGGER_HIGH, uc->name, uc);
2243 if (ret) {
2244 dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id);
2245 goto err_irq_free;
2246 }
2247
2248 /* Event from UDMA (TR events) only needed for slave TR mode channels */
2249 if (is_slave_direction(uc->config.dir) && !uc->config.pkt_mode) {
2250 uc->irq_num_udma = ti_sci_inta_msi_get_virq(ud->dev,
2251 irq_udma_idx);
2252 if (uc->irq_num_udma <= 0) {
2253 dev_err(ud->dev, "Failed to get udma irq (index: %u)\n",
2254 irq_udma_idx);
2255 free_irq(uc->irq_num_ring, uc);
2256 ret = -EINVAL;
2257 goto err_irq_free;
2258 }
2259
2260 ret = request_irq(uc->irq_num_udma, udma_udma_irq_handler, 0,
2261 uc->name, uc);
2262 if (ret) {
2263 dev_err(ud->dev, "chan%d: UDMA irq request failed\n",
2264 uc->id);
2265 free_irq(uc->irq_num_ring, uc);
2266 goto err_irq_free;
2267 }
2268 } else {
2269 uc->irq_num_udma = 0;
2270 }
2271
2272 udma_reset_rings(uc);
2273
2274 return 0;
2275
2276 err_irq_free:
2277 uc->irq_num_ring = 0;
2278 uc->irq_num_udma = 0;
2279 err_psi_free:
2280 navss_psil_unpair(ud, uc->config.src_thread, uc->config.dst_thread);
2281 uc->psil_paired = false;
2282 err_res_free:
2283 udma_free_tx_resources(uc);
2284 udma_free_rx_resources(uc);
2285 err_cleanup:
2286 udma_reset_uchan(uc);
2287
2288 if (uc->use_dma_pool) {
2289 dma_pool_destroy(uc->hdesc_pool);
2290 uc->use_dma_pool = false;
2291 }
2292
2293 return ret;
2294 }
2295
2296 static int bcdma_alloc_chan_resources(struct dma_chan *chan)
2297 {
2298 struct udma_chan *uc = to_udma_chan(chan);
2299 struct udma_dev *ud = to_udma_dev(chan->device);
2300 const struct udma_oes_offsets *oes = &ud->soc_data->oes;
2301 u32 irq_udma_idx, irq_ring_idx;
2302 int ret;
2303
2304 /* Only TR mode is supported */
2305 uc->config.pkt_mode = false;
2306
2307 /*
2308 * Make sure that the completion is in a known state:
2309 * No teardown, the channel is idle
2310 */
2311 reinit_completion(&uc->teardown_completed);
2312 complete_all(&uc->teardown_completed);
2313 uc->state = UDMA_CHAN_IS_IDLE;
2314
2315 switch (uc->config.dir) {
2316 case DMA_MEM_TO_MEM:
2317 /* Non synchronized - mem to mem type of transfer */
2318 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__,
2319 uc->id);
2320
2321 ret = bcdma_alloc_bchan_resources(uc);
2322 if (ret)
2323 return ret;
2324
2325 irq_ring_idx = uc->bchan->id + oes->bcdma_bchan_ring;
2326 irq_udma_idx = uc->bchan->id + oes->bcdma_bchan_data;
2327
2328 ret = bcdma_tisci_m2m_channel_config(uc);
2329 break;
2330 case DMA_MEM_TO_DEV:
2331 /* Slave transfer synchronized - mem to dev (TX) trasnfer */
2332 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__,
2333 uc->id);
2334
2335 ret = udma_alloc_tx_resources(uc);
2336 if (ret) {
2337 uc->config.remote_thread_id = -1;
2338 return ret;
2339 }
2340
2341 uc->config.src_thread = ud->psil_base + uc->tchan->id;
2342 uc->config.dst_thread = uc->config.remote_thread_id;
2343 uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
2344
2345 irq_ring_idx = uc->tchan->id + oes->bcdma_tchan_ring;
2346 irq_udma_idx = uc->tchan->id + oes->bcdma_tchan_data;
2347
2348 ret = bcdma_tisci_tx_channel_config(uc);
2349 break;
2350 case DMA_DEV_TO_MEM:
2351 /* Slave transfer synchronized - dev to mem (RX) trasnfer */
2352 dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__,
2353 uc->id);
2354
2355 ret = udma_alloc_rx_resources(uc);
2356 if (ret) {
2357 uc->config.remote_thread_id = -1;
2358 return ret;
2359 }
2360
2361 uc->config.src_thread = uc->config.remote_thread_id;
2362 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
2363 K3_PSIL_DST_THREAD_ID_OFFSET;
2364
2365 irq_ring_idx = uc->rchan->id + oes->bcdma_rchan_ring;
2366 irq_udma_idx = uc->rchan->id + oes->bcdma_rchan_data;
2367
2368 ret = bcdma_tisci_rx_channel_config(uc);
2369 break;
2370 default:
2371 /* Can not happen */
2372 dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
2373 __func__, uc->id, uc->config.dir);
2374 return -EINVAL;
2375 }
2376
2377 /* check if the channel configuration was successful */
2378 if (ret)
2379 goto err_res_free;
2380
2381 if (udma_is_chan_running(uc)) {
2382 dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
2383 udma_reset_chan(uc, false);
2384 if (udma_is_chan_running(uc)) {
2385 dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
2386 ret = -EBUSY;
2387 goto err_res_free;
2388 }
2389 }
2390
2391 uc->dma_dev = dmaengine_get_dma_device(chan);
2392 if (uc->config.dir == DMA_MEM_TO_MEM && !uc->config.tr_trigger_type) {
2393 uc->config.hdesc_size = cppi5_trdesc_calc_size(
2394 sizeof(struct cppi5_tr_type15_t), 2);
2395
2396 uc->hdesc_pool = dma_pool_create(uc->name, ud->ddev.dev,
2397 uc->config.hdesc_size,
2398 ud->desc_align,
2399 0);
2400 if (!uc->hdesc_pool) {
2401 dev_err(ud->ddev.dev,
2402 "Descriptor pool allocation failed\n");
2403 uc->use_dma_pool = false;
2404 return -ENOMEM;
2405 }
2406
2407 uc->use_dma_pool = true;
2408 } else if (uc->config.dir != DMA_MEM_TO_MEM) {
2409 /* PSI-L pairing */
2410 ret = navss_psil_pair(ud, uc->config.src_thread,
2411 uc->config.dst_thread);
2412 if (ret) {
2413 dev_err(ud->dev,
2414 "PSI-L pairing failed: 0x%04x -> 0x%04x\n",
2415 uc->config.src_thread, uc->config.dst_thread);
2416 goto err_res_free;
2417 }
2418
2419 uc->psil_paired = true;
2420 }
2421
2422 uc->irq_num_ring = ti_sci_inta_msi_get_virq(ud->dev, irq_ring_idx);
2423 if (uc->irq_num_ring <= 0) {
2424 dev_err(ud->dev, "Failed to get ring irq (index: %u)\n",
2425 irq_ring_idx);
2426 ret = -EINVAL;
2427 goto err_psi_free;
2428 }
2429
2430 ret = request_irq(uc->irq_num_ring, udma_ring_irq_handler,
2431 IRQF_TRIGGER_HIGH, uc->name, uc);
2432 if (ret) {
2433 dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id);
2434 goto err_irq_free;
2435 }
2436
2437 /* Event from BCDMA (TR events) only needed for slave channels */
2438 if (is_slave_direction(uc->config.dir)) {
2439 uc->irq_num_udma = ti_sci_inta_msi_get_virq(ud->dev,
2440 irq_udma_idx);
2441 if (uc->irq_num_udma <= 0) {
2442 dev_err(ud->dev, "Failed to get bcdma irq (index: %u)\n",
2443 irq_udma_idx);
2444 free_irq(uc->irq_num_ring, uc);
2445 ret = -EINVAL;
2446 goto err_irq_free;
2447 }
2448
2449 ret = request_irq(uc->irq_num_udma, udma_udma_irq_handler, 0,
2450 uc->name, uc);
2451 if (ret) {
2452 dev_err(ud->dev, "chan%d: BCDMA irq request failed\n",
2453 uc->id);
2454 free_irq(uc->irq_num_ring, uc);
2455 goto err_irq_free;
2456 }
2457 } else {
2458 uc->irq_num_udma = 0;
2459 }
2460
2461 udma_reset_rings(uc);
2462
2463 INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work,
2464 udma_check_tx_completion);
2465 return 0;
2466
2467 err_irq_free:
2468 uc->irq_num_ring = 0;
2469 uc->irq_num_udma = 0;
2470 err_psi_free:
2471 if (uc->psil_paired)
2472 navss_psil_unpair(ud, uc->config.src_thread,
2473 uc->config.dst_thread);
2474 uc->psil_paired = false;
2475 err_res_free:
2476 bcdma_free_bchan_resources(uc);
2477 udma_free_tx_resources(uc);
2478 udma_free_rx_resources(uc);
2479
2480 udma_reset_uchan(uc);
2481
2482 if (uc->use_dma_pool) {
2483 dma_pool_destroy(uc->hdesc_pool);
2484 uc->use_dma_pool = false;
2485 }
2486
2487 return ret;
2488 }
2489
2490 static int bcdma_router_config(struct dma_chan *chan)
2491 {
2492 struct k3_event_route_data *router_data = chan->route_data;
2493 struct udma_chan *uc = to_udma_chan(chan);
2494 u32 trigger_event;
2495
2496 if (!uc->bchan)
2497 return -EINVAL;
2498
2499 if (uc->config.tr_trigger_type != 1 && uc->config.tr_trigger_type != 2)
2500 return -EINVAL;
2501
2502 trigger_event = uc->ud->soc_data->bcdma_trigger_event_offset;
2503 trigger_event += (uc->bchan->id * 2) + uc->config.tr_trigger_type - 1;
2504
2505 return router_data->set_event(router_data->priv, trigger_event);
2506 }
2507
2508 static int pktdma_alloc_chan_resources(struct dma_chan *chan)
2509 {
2510 struct udma_chan *uc = to_udma_chan(chan);
2511 struct udma_dev *ud = to_udma_dev(chan->device);
2512 const struct udma_oes_offsets *oes = &ud->soc_data->oes;
2513 u32 irq_ring_idx;
2514 int ret;
2515
2516 /*
2517 * Make sure that the completion is in a known state:
2518 * No teardown, the channel is idle
2519 */
2520 reinit_completion(&uc->teardown_completed);
2521 complete_all(&uc->teardown_completed);
2522 uc->state = UDMA_CHAN_IS_IDLE;
2523
2524 switch (uc->config.dir) {
2525 case DMA_MEM_TO_DEV:
2526 /* Slave transfer synchronized - mem to dev (TX) trasnfer */
2527 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__,
2528 uc->id);
2529
2530 ret = udma_alloc_tx_resources(uc);
2531 if (ret) {
2532 uc->config.remote_thread_id = -1;
2533 return ret;
2534 }
2535
2536 uc->config.src_thread = ud->psil_base + uc->tchan->id;
2537 uc->config.dst_thread = uc->config.remote_thread_id;
2538 uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
2539
2540 irq_ring_idx = uc->tchan->tflow_id + oes->pktdma_tchan_flow;
2541
2542 ret = pktdma_tisci_tx_channel_config(uc);
2543 break;
2544 case DMA_DEV_TO_MEM:
2545 /* Slave transfer synchronized - dev to mem (RX) trasnfer */
2546 dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__,
2547 uc->id);
2548
2549 ret = udma_alloc_rx_resources(uc);
2550 if (ret) {
2551 uc->config.remote_thread_id = -1;
2552 return ret;
2553 }
2554
2555 uc->config.src_thread = uc->config.remote_thread_id;
2556 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
2557 K3_PSIL_DST_THREAD_ID_OFFSET;
2558
2559 irq_ring_idx = uc->rflow->id + oes->pktdma_rchan_flow;
2560
2561 ret = pktdma_tisci_rx_channel_config(uc);
2562 break;
2563 default:
2564 /* Can not happen */
2565 dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
2566 __func__, uc->id, uc->config.dir);
2567 return -EINVAL;
2568 }
2569
2570 /* check if the channel configuration was successful */
2571 if (ret)
2572 goto err_res_free;
2573
2574 if (udma_is_chan_running(uc)) {
2575 dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
2576 udma_reset_chan(uc, false);
2577 if (udma_is_chan_running(uc)) {
2578 dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
2579 ret = -EBUSY;
2580 goto err_res_free;
2581 }
2582 }
2583
2584 uc->dma_dev = dmaengine_get_dma_device(chan);
2585 uc->hdesc_pool = dma_pool_create(uc->name, uc->dma_dev,
2586 uc->config.hdesc_size, ud->desc_align,
2587 0);
2588 if (!uc->hdesc_pool) {
2589 dev_err(ud->ddev.dev,
2590 "Descriptor pool allocation failed\n");
2591 uc->use_dma_pool = false;
2592 ret = -ENOMEM;
2593 goto err_res_free;
2594 }
2595
2596 uc->use_dma_pool = true;
2597
2598 /* PSI-L pairing */
2599 ret = navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread);
2600 if (ret) {
2601 dev_err(ud->dev, "PSI-L pairing failed: 0x%04x -> 0x%04x\n",
2602 uc->config.src_thread, uc->config.dst_thread);
2603 goto err_res_free;
2604 }
2605
2606 uc->psil_paired = true;
2607
2608 uc->irq_num_ring = ti_sci_inta_msi_get_virq(ud->dev, irq_ring_idx);
2609 if (uc->irq_num_ring <= 0) {
2610 dev_err(ud->dev, "Failed to get ring irq (index: %u)\n",
2611 irq_ring_idx);
2612 ret = -EINVAL;
2613 goto err_psi_free;
2614 }
2615
2616 ret = request_irq(uc->irq_num_ring, udma_ring_irq_handler,
2617 IRQF_TRIGGER_HIGH, uc->name, uc);
2618 if (ret) {
2619 dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id);
2620 goto err_irq_free;
2621 }
2622
2623 uc->irq_num_udma = 0;
2624
2625 udma_reset_rings(uc);
2626
2627 INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work,
2628 udma_check_tx_completion);
2629
2630 if (uc->tchan)
2631 dev_dbg(ud->dev,
2632 "chan%d: tchan%d, tflow%d, Remote thread: 0x%04x\n",
2633 uc->id, uc->tchan->id, uc->tchan->tflow_id,
2634 uc->config.remote_thread_id);
2635 else if (uc->rchan)
2636 dev_dbg(ud->dev,
2637 "chan%d: rchan%d, rflow%d, Remote thread: 0x%04x\n",
2638 uc->id, uc->rchan->id, uc->rflow->id,
2639 uc->config.remote_thread_id);
2640 return 0;
2641
2642 err_irq_free:
2643 uc->irq_num_ring = 0;
2644 err_psi_free:
2645 navss_psil_unpair(ud, uc->config.src_thread, uc->config.dst_thread);
2646 uc->psil_paired = false;
2647 err_res_free:
2648 udma_free_tx_resources(uc);
2649 udma_free_rx_resources(uc);
2650
2651 udma_reset_uchan(uc);
2652
2653 dma_pool_destroy(uc->hdesc_pool);
2654 uc->use_dma_pool = false;
2655
2656 return ret;
2657 }
2658
2659 static int udma_slave_config(struct dma_chan *chan,
2660 struct dma_slave_config *cfg)
2661 {
2662 struct udma_chan *uc = to_udma_chan(chan);
2663
2664 memcpy(&uc->cfg, cfg, sizeof(uc->cfg));
2665
2666 return 0;
2667 }
2668
2669 static struct udma_desc *udma_alloc_tr_desc(struct udma_chan *uc,
2670 size_t tr_size, int tr_count,
2671 enum dma_transfer_direction dir)
2672 {
2673 struct udma_hwdesc *hwdesc;
2674 struct cppi5_desc_hdr_t *tr_desc;
2675 struct udma_desc *d;
2676 u32 reload_count = 0;
2677 u32 ring_id;
2678
2679 switch (tr_size) {
2680 case 16:
2681 case 32:
2682 case 64:
2683 case 128:
2684 break;
2685 default:
2686 dev_err(uc->ud->dev, "Unsupported TR size of %zu\n", tr_size);
2687 return NULL;
2688 }
2689
2690 /* We have only one descriptor containing multiple TRs */
2691 d = kzalloc(sizeof(*d) + sizeof(d->hwdesc[0]), GFP_NOWAIT);
2692 if (!d)
2693 return NULL;
2694
2695 d->sglen = tr_count;
2696
2697 d->hwdesc_count = 1;
2698 hwdesc = &d->hwdesc[0];
2699
2700 /* Allocate memory for DMA ring descriptor */
2701 if (uc->use_dma_pool) {
2702 hwdesc->cppi5_desc_size = uc->config.hdesc_size;
2703 hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool,
2704 GFP_NOWAIT,
2705 &hwdesc->cppi5_desc_paddr);
2706 } else {
2707 hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size,
2708 tr_count);
2709 hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size,
2710 uc->ud->desc_align);
2711 hwdesc->cppi5_desc_vaddr = dma_alloc_coherent(uc->ud->dev,
2712 hwdesc->cppi5_desc_size,
2713 &hwdesc->cppi5_desc_paddr,
2714 GFP_NOWAIT);
2715 }
2716
2717 if (!hwdesc->cppi5_desc_vaddr) {
2718 kfree(d);
2719 return NULL;
2720 }
2721
2722 /* Start of the TR req records */
2723 hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size;
2724 /* Start address of the TR response array */
2725 hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size * tr_count;
2726
2727 tr_desc = hwdesc->cppi5_desc_vaddr;
2728
2729 if (uc->cyclic)
2730 reload_count = CPPI5_INFO0_TRDESC_RLDCNT_INFINITE;
2731
2732 if (dir == DMA_DEV_TO_MEM)
2733 ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring);
2734 else
2735 ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring);
2736
2737 cppi5_trdesc_init(tr_desc, tr_count, tr_size, 0, reload_count);
2738 cppi5_desc_set_pktids(tr_desc, uc->id,
2739 CPPI5_INFO1_DESC_FLOWID_DEFAULT);
2740 cppi5_desc_set_retpolicy(tr_desc, 0, ring_id);
2741
2742 return d;
2743 }
2744
2745 /**
2746 * udma_get_tr_counters - calculate TR counters for a given length
2747 * @len: Length of the trasnfer
2748 * @align_to: Preferred alignment
2749 * @tr0_cnt0: First TR icnt0
2750 * @tr0_cnt1: First TR icnt1
2751 * @tr1_cnt0: Second (if used) TR icnt0
2752 *
2753 * For len < SZ_64K only one TR is enough, tr1_cnt0 is not updated
2754 * For len >= SZ_64K two TRs are used in a simple way:
2755 * First TR: SZ_64K-alignment blocks (tr0_cnt0, tr0_cnt1)
2756 * Second TR: the remaining length (tr1_cnt0)
2757 *
2758 * Returns the number of TRs the length needs (1 or 2)
2759 * -EINVAL if the length can not be supported
2760 */
2761 static int udma_get_tr_counters(size_t len, unsigned long align_to,
2762 u16 *tr0_cnt0, u16 *tr0_cnt1, u16 *tr1_cnt0)
2763 {
2764 if (len < SZ_64K) {
2765 *tr0_cnt0 = len;
2766 *tr0_cnt1 = 1;
2767
2768 return 1;
2769 }
2770
2771 if (align_to > 3)
2772 align_to = 3;
2773
2774 realign:
2775 *tr0_cnt0 = SZ_64K - BIT(align_to);
2776 if (len / *tr0_cnt0 >= SZ_64K) {
2777 if (align_to) {
2778 align_to--;
2779 goto realign;
2780 }
2781 return -EINVAL;
2782 }
2783
2784 *tr0_cnt1 = len / *tr0_cnt0;
2785 *tr1_cnt0 = len % *tr0_cnt0;
2786
2787 return 2;
2788 }
2789
2790 static struct udma_desc *
2791 udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl,
2792 unsigned int sglen, enum dma_transfer_direction dir,
2793 unsigned long tx_flags, void *context)
2794 {
2795 struct scatterlist *sgent;
2796 struct udma_desc *d;
2797 struct cppi5_tr_type1_t *tr_req = NULL;
2798 u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
2799 unsigned int i;
2800 size_t tr_size;
2801 int num_tr = 0;
2802 int tr_idx = 0;
2803 u64 asel;
2804
2805 /* estimate the number of TRs we will need */
2806 for_each_sg(sgl, sgent, sglen, i) {
2807 if (sg_dma_len(sgent) < SZ_64K)
2808 num_tr++;
2809 else
2810 num_tr += 2;
2811 }
2812
2813 /* Now allocate and setup the descriptor. */
2814 tr_size = sizeof(struct cppi5_tr_type1_t);
2815 d = udma_alloc_tr_desc(uc, tr_size, num_tr, dir);
2816 if (!d)
2817 return NULL;
2818
2819 d->sglen = sglen;
2820
2821 if (uc->ud->match_data->type == DMA_TYPE_UDMA)
2822 asel = 0;
2823 else
2824 asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT;
2825
2826 tr_req = d->hwdesc[0].tr_req_base;
2827 for_each_sg(sgl, sgent, sglen, i) {
2828 dma_addr_t sg_addr = sg_dma_address(sgent);
2829
2830 num_tr = udma_get_tr_counters(sg_dma_len(sgent), __ffs(sg_addr),
2831 &tr0_cnt0, &tr0_cnt1, &tr1_cnt0);
2832 if (num_tr < 0) {
2833 dev_err(uc->ud->dev, "size %u is not supported\n",
2834 sg_dma_len(sgent));
2835 udma_free_hwdesc(uc, d);
2836 kfree(d);
2837 return NULL;
2838 }
2839
2840 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false,
2841 false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
2842 cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT);
2843
2844 sg_addr |= asel;
2845 tr_req[tr_idx].addr = sg_addr;
2846 tr_req[tr_idx].icnt0 = tr0_cnt0;
2847 tr_req[tr_idx].icnt1 = tr0_cnt1;
2848 tr_req[tr_idx].dim1 = tr0_cnt0;
2849 tr_idx++;
2850
2851 if (num_tr == 2) {
2852 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1,
2853 false, false,
2854 CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
2855 cppi5_tr_csf_set(&tr_req[tr_idx].flags,
2856 CPPI5_TR_CSF_SUPR_EVT);
2857
2858 tr_req[tr_idx].addr = sg_addr + tr0_cnt1 * tr0_cnt0;
2859 tr_req[tr_idx].icnt0 = tr1_cnt0;
2860 tr_req[tr_idx].icnt1 = 1;
2861 tr_req[tr_idx].dim1 = tr1_cnt0;
2862 tr_idx++;
2863 }
2864
2865 d->residue += sg_dma_len(sgent);
2866 }
2867
2868 cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags,
2869 CPPI5_TR_CSF_SUPR_EVT | CPPI5_TR_CSF_EOP);
2870
2871 return d;
2872 }
2873
2874 static struct udma_desc *
2875 udma_prep_slave_sg_triggered_tr(struct udma_chan *uc, struct scatterlist *sgl,
2876 unsigned int sglen,
2877 enum dma_transfer_direction dir,
2878 unsigned long tx_flags, void *context)
2879 {
2880 struct scatterlist *sgent;
2881 struct cppi5_tr_type15_t *tr_req = NULL;
2882 enum dma_slave_buswidth dev_width;
2883 u16 tr_cnt0, tr_cnt1;
2884 dma_addr_t dev_addr;
2885 struct udma_desc *d;
2886 unsigned int i;
2887 size_t tr_size, sg_len;
2888 int num_tr = 0;
2889 int tr_idx = 0;
2890 u32 burst, trigger_size, port_window;
2891 u64 asel;
2892
2893 if (dir == DMA_DEV_TO_MEM) {
2894 dev_addr = uc->cfg.src_addr;
2895 dev_width = uc->cfg.src_addr_width;
2896 burst = uc->cfg.src_maxburst;
2897 port_window = uc->cfg.src_port_window_size;
2898 } else if (dir == DMA_MEM_TO_DEV) {
2899 dev_addr = uc->cfg.dst_addr;
2900 dev_width = uc->cfg.dst_addr_width;
2901 burst = uc->cfg.dst_maxburst;
2902 port_window = uc->cfg.dst_port_window_size;
2903 } else {
2904 dev_err(uc->ud->dev, "%s: bad direction?\n", __func__);
2905 return NULL;
2906 }
2907
2908 if (!burst)
2909 burst = 1;
2910
2911 if (port_window) {
2912 if (port_window != burst) {
2913 dev_err(uc->ud->dev,
2914 "The burst must be equal to port_window\n");
2915 return NULL;
2916 }
2917
2918 tr_cnt0 = dev_width * port_window;
2919 tr_cnt1 = 1;
2920 } else {
2921 tr_cnt0 = dev_width;
2922 tr_cnt1 = burst;
2923 }
2924 trigger_size = tr_cnt0 * tr_cnt1;
2925
2926 /* estimate the number of TRs we will need */
2927 for_each_sg(sgl, sgent, sglen, i) {
2928 sg_len = sg_dma_len(sgent);
2929
2930 if (sg_len % trigger_size) {
2931 dev_err(uc->ud->dev,
2932 "Not aligned SG entry (%zu for %u)\n", sg_len,
2933 trigger_size);
2934 return NULL;
2935 }
2936
2937 if (sg_len / trigger_size < SZ_64K)
2938 num_tr++;
2939 else
2940 num_tr += 2;
2941 }
2942
2943 /* Now allocate and setup the descriptor. */
2944 tr_size = sizeof(struct cppi5_tr_type15_t);
2945 d = udma_alloc_tr_desc(uc, tr_size, num_tr, dir);
2946 if (!d)
2947 return NULL;
2948
2949 d->sglen = sglen;
2950
2951 if (uc->ud->match_data->type == DMA_TYPE_UDMA) {
2952 asel = 0;
2953 } else {
2954 asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT;
2955 dev_addr |= asel;
2956 }
2957
2958 tr_req = d->hwdesc[0].tr_req_base;
2959 for_each_sg(sgl, sgent, sglen, i) {
2960 u16 tr0_cnt2, tr0_cnt3, tr1_cnt2;
2961 dma_addr_t sg_addr = sg_dma_address(sgent);
2962
2963 sg_len = sg_dma_len(sgent);
2964 num_tr = udma_get_tr_counters(sg_len / trigger_size, 0,
2965 &tr0_cnt2, &tr0_cnt3, &tr1_cnt2);
2966 if (num_tr < 0) {
2967 dev_err(uc->ud->dev, "size %zu is not supported\n",
2968 sg_len);
2969 udma_free_hwdesc(uc, d);
2970 kfree(d);
2971 return NULL;
2972 }
2973
2974 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, false,
2975 true, CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
2976 cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT);
2977 cppi5_tr_set_trigger(&tr_req[tr_idx].flags,
2978 uc->config.tr_trigger_type,
2979 CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC, 0, 0);
2980
2981 sg_addr |= asel;
2982 if (dir == DMA_DEV_TO_MEM) {
2983 tr_req[tr_idx].addr = dev_addr;
2984 tr_req[tr_idx].icnt0 = tr_cnt0;
2985 tr_req[tr_idx].icnt1 = tr_cnt1;
2986 tr_req[tr_idx].icnt2 = tr0_cnt2;
2987 tr_req[tr_idx].icnt3 = tr0_cnt3;
2988 tr_req[tr_idx].dim1 = (-1) * tr_cnt0;
2989
2990 tr_req[tr_idx].daddr = sg_addr;
2991 tr_req[tr_idx].dicnt0 = tr_cnt0;
2992 tr_req[tr_idx].dicnt1 = tr_cnt1;
2993 tr_req[tr_idx].dicnt2 = tr0_cnt2;
2994 tr_req[tr_idx].dicnt3 = tr0_cnt3;
2995 tr_req[tr_idx].ddim1 = tr_cnt0;
2996 tr_req[tr_idx].ddim2 = trigger_size;
2997 tr_req[tr_idx].ddim3 = trigger_size * tr0_cnt2;
2998 } else {
2999 tr_req[tr_idx].addr = sg_addr;
3000 tr_req[tr_idx].icnt0 = tr_cnt0;
3001 tr_req[tr_idx].icnt1 = tr_cnt1;
3002 tr_req[tr_idx].icnt2 = tr0_cnt2;
3003 tr_req[tr_idx].icnt3 = tr0_cnt3;
3004 tr_req[tr_idx].dim1 = tr_cnt0;
3005 tr_req[tr_idx].dim2 = trigger_size;
3006 tr_req[tr_idx].dim3 = trigger_size * tr0_cnt2;
3007
3008 tr_req[tr_idx].daddr = dev_addr;
3009 tr_req[tr_idx].dicnt0 = tr_cnt0;
3010 tr_req[tr_idx].dicnt1 = tr_cnt1;
3011 tr_req[tr_idx].dicnt2 = tr0_cnt2;
3012 tr_req[tr_idx].dicnt3 = tr0_cnt3;
3013 tr_req[tr_idx].ddim1 = (-1) * tr_cnt0;
3014 }
3015
3016 tr_idx++;
3017
3018 if (num_tr == 2) {
3019 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15,
3020 false, true,
3021 CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
3022 cppi5_tr_csf_set(&tr_req[tr_idx].flags,
3023 CPPI5_TR_CSF_SUPR_EVT);
3024 cppi5_tr_set_trigger(&tr_req[tr_idx].flags,
3025 uc->config.tr_trigger_type,
3026 CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC,
3027 0, 0);
3028
3029 sg_addr += trigger_size * tr0_cnt2 * tr0_cnt3;
3030 if (dir == DMA_DEV_TO_MEM) {
3031 tr_req[tr_idx].addr = dev_addr;
3032 tr_req[tr_idx].icnt0 = tr_cnt0;
3033 tr_req[tr_idx].icnt1 = tr_cnt1;
3034 tr_req[tr_idx].icnt2 = tr1_cnt2;
3035 tr_req[tr_idx].icnt3 = 1;
3036 tr_req[tr_idx].dim1 = (-1) * tr_cnt0;
3037
3038 tr_req[tr_idx].daddr = sg_addr;
3039 tr_req[tr_idx].dicnt0 = tr_cnt0;
3040 tr_req[tr_idx].dicnt1 = tr_cnt1;
3041 tr_req[tr_idx].dicnt2 = tr1_cnt2;
3042 tr_req[tr_idx].dicnt3 = 1;
3043 tr_req[tr_idx].ddim1 = tr_cnt0;
3044 tr_req[tr_idx].ddim2 = trigger_size;
3045 } else {
3046 tr_req[tr_idx].addr = sg_addr;
3047 tr_req[tr_idx].icnt0 = tr_cnt0;
3048 tr_req[tr_idx].icnt1 = tr_cnt1;
3049 tr_req[tr_idx].icnt2 = tr1_cnt2;
3050 tr_req[tr_idx].icnt3 = 1;
3051 tr_req[tr_idx].dim1 = tr_cnt0;
3052 tr_req[tr_idx].dim2 = trigger_size;
3053
3054 tr_req[tr_idx].daddr = dev_addr;
3055 tr_req[tr_idx].dicnt0 = tr_cnt0;
3056 tr_req[tr_idx].dicnt1 = tr_cnt1;
3057 tr_req[tr_idx].dicnt2 = tr1_cnt2;
3058 tr_req[tr_idx].dicnt3 = 1;
3059 tr_req[tr_idx].ddim1 = (-1) * tr_cnt0;
3060 }
3061 tr_idx++;
3062 }
3063
3064 d->residue += sg_len;
3065 }
3066
3067 cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags,
3068 CPPI5_TR_CSF_SUPR_EVT | CPPI5_TR_CSF_EOP);
3069
3070 return d;
3071 }
3072
3073 static int udma_configure_statictr(struct udma_chan *uc, struct udma_desc *d,
3074 enum dma_slave_buswidth dev_width,
3075 u16 elcnt)
3076 {
3077 if (uc->config.ep_type != PSIL_EP_PDMA_XY)
3078 return 0;
3079
3080 /* Bus width translates to the element size (ES) */
3081 switch (dev_width) {
3082 case DMA_SLAVE_BUSWIDTH_1_BYTE:
3083 d->static_tr.elsize = 0;
3084 break;
3085 case DMA_SLAVE_BUSWIDTH_2_BYTES:
3086 d->static_tr.elsize = 1;
3087 break;
3088 case DMA_SLAVE_BUSWIDTH_3_BYTES:
3089 d->static_tr.elsize = 2;
3090 break;
3091 case DMA_SLAVE_BUSWIDTH_4_BYTES:
3092 d->static_tr.elsize = 3;
3093 break;
3094 case DMA_SLAVE_BUSWIDTH_8_BYTES:
3095 d->static_tr.elsize = 4;
3096 break;
3097 default: /* not reached */
3098 return -EINVAL;
3099 }
3100
3101 d->static_tr.elcnt = elcnt;
3102
3103 /*
3104 * PDMA must to close the packet when the channel is in packet mode.
3105 * For TR mode when the channel is not cyclic we also need PDMA to close
3106 * the packet otherwise the transfer will stall because PDMA holds on
3107 * the data it has received from the peripheral.
3108 */
3109 if (uc->config.pkt_mode || !uc->cyclic) {
3110 unsigned int div = dev_width * elcnt;
3111
3112 if (uc->cyclic)
3113 d->static_tr.bstcnt = d->residue / d->sglen / div;
3114 else
3115 d->static_tr.bstcnt = d->residue / div;
3116
3117 if (uc->config.dir == DMA_DEV_TO_MEM &&
3118 d->static_tr.bstcnt > uc->ud->match_data->statictr_z_mask)
3119 return -EINVAL;
3120 } else {
3121 d->static_tr.bstcnt = 0;
3122 }
3123
3124 return 0;
3125 }
3126
3127 static struct udma_desc *
3128 udma_prep_slave_sg_pkt(struct udma_chan *uc, struct scatterlist *sgl,
3129 unsigned int sglen, enum dma_transfer_direction dir,
3130 unsigned long tx_flags, void *context)
3131 {
3132 struct scatterlist *sgent;
3133 struct cppi5_host_desc_t *h_desc = NULL;
3134 struct udma_desc *d;
3135 u32 ring_id;
3136 unsigned int i;
3137 u64 asel;
3138
3139 d = kzalloc(struct_size(d, hwdesc, sglen), GFP_NOWAIT);
3140 if (!d)
3141 return NULL;
3142
3143 d->sglen = sglen;
3144 d->hwdesc_count = sglen;
3145
3146 if (dir == DMA_DEV_TO_MEM)
3147 ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring);
3148 else
3149 ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring);
3150
3151 if (uc->ud->match_data->type == DMA_TYPE_UDMA)
3152 asel = 0;
3153 else
3154 asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT;
3155
3156 for_each_sg(sgl, sgent, sglen, i) {
3157 struct udma_hwdesc *hwdesc = &d->hwdesc[i];
3158 dma_addr_t sg_addr = sg_dma_address(sgent);
3159 struct cppi5_host_desc_t *desc;
3160 size_t sg_len = sg_dma_len(sgent);
3161
3162 hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool,
3163 GFP_NOWAIT,
3164 &hwdesc->cppi5_desc_paddr);
3165 if (!hwdesc->cppi5_desc_vaddr) {
3166 dev_err(uc->ud->dev,
3167 "descriptor%d allocation failed\n", i);
3168
3169 udma_free_hwdesc(uc, d);
3170 kfree(d);
3171 return NULL;
3172 }
3173
3174 d->residue += sg_len;
3175 hwdesc->cppi5_desc_size = uc->config.hdesc_size;
3176 desc = hwdesc->cppi5_desc_vaddr;
3177
3178 if (i == 0) {
3179 cppi5_hdesc_init(desc, 0, 0);
3180 /* Flow and Packed ID */
3181 cppi5_desc_set_pktids(&desc->hdr, uc->id,
3182 CPPI5_INFO1_DESC_FLOWID_DEFAULT);
3183 cppi5_desc_set_retpolicy(&desc->hdr, 0, ring_id);
3184 } else {
3185 cppi5_hdesc_reset_hbdesc(desc);
3186 cppi5_desc_set_retpolicy(&desc->hdr, 0, 0xffff);
3187 }
3188
3189 /* attach the sg buffer to the descriptor */
3190 sg_addr |= asel;
3191 cppi5_hdesc_attach_buf(desc, sg_addr, sg_len, sg_addr, sg_len);
3192
3193 /* Attach link as host buffer descriptor */
3194 if (h_desc)
3195 cppi5_hdesc_link_hbdesc(h_desc,
3196 hwdesc->cppi5_desc_paddr | asel);
3197
3198 if (uc->ud->match_data->type == DMA_TYPE_PKTDMA ||
3199 dir == DMA_MEM_TO_DEV)
3200 h_desc = desc;
3201 }
3202
3203 if (d->residue >= SZ_4M) {
3204 dev_err(uc->ud->dev,
3205 "%s: Transfer size %u is over the supported 4M range\n",
3206 __func__, d->residue);
3207 udma_free_hwdesc(uc, d);
3208 kfree(d);
3209 return NULL;
3210 }
3211
3212 h_desc = d->hwdesc[0].cppi5_desc_vaddr;
3213 cppi5_hdesc_set_pktlen(h_desc, d->residue);
3214
3215 return d;
3216 }
3217
3218 static int udma_attach_metadata(struct dma_async_tx_descriptor *desc,
3219 void *data, size_t len)
3220 {
3221 struct udma_desc *d = to_udma_desc(desc);
3222 struct udma_chan *uc = to_udma_chan(desc->chan);
3223 struct cppi5_host_desc_t *h_desc;
3224 u32 psd_size = len;
3225 u32 flags = 0;
3226
3227 if (!uc->config.pkt_mode || !uc->config.metadata_size)
3228 return -ENOTSUPP;
3229
3230 if (!data || len > uc->config.metadata_size)
3231 return -EINVAL;
3232
3233 if (uc->config.needs_epib && len < CPPI5_INFO0_HDESC_EPIB_SIZE)
3234 return -EINVAL;
3235
3236 h_desc = d->hwdesc[0].cppi5_desc_vaddr;
3237 if (d->dir == DMA_MEM_TO_DEV)
3238 memcpy(h_desc->epib, data, len);
3239
3240 if (uc->config.needs_epib)
3241 psd_size -= CPPI5_INFO0_HDESC_EPIB_SIZE;
3242
3243 d->metadata = data;
3244 d->metadata_size = len;
3245 if (uc->config.needs_epib)
3246 flags |= CPPI5_INFO0_HDESC_EPIB_PRESENT;
3247
3248 cppi5_hdesc_update_flags(h_desc, flags);
3249 cppi5_hdesc_update_psdata_size(h_desc, psd_size);
3250
3251 return 0;
3252 }
3253
3254 static void *udma_get_metadata_ptr(struct dma_async_tx_descriptor *desc,
3255 size_t *payload_len, size_t *max_len)
3256 {
3257 struct udma_desc *d = to_udma_desc(desc);
3258 struct udma_chan *uc = to_udma_chan(desc->chan);
3259 struct cppi5_host_desc_t *h_desc;
3260
3261 if (!uc->config.pkt_mode || !uc->config.metadata_size)
3262 return ERR_PTR(-ENOTSUPP);
3263
3264 h_desc = d->hwdesc[0].cppi5_desc_vaddr;
3265
3266 *max_len = uc->config.metadata_size;
3267
3268 *payload_len = cppi5_hdesc_epib_present(&h_desc->hdr) ?
3269 CPPI5_INFO0_HDESC_EPIB_SIZE : 0;
3270 *payload_len += cppi5_hdesc_get_psdata_size(h_desc);
3271
3272 return h_desc->epib;
3273 }
3274
3275 static int udma_set_metadata_len(struct dma_async_tx_descriptor *desc,
3276 size_t payload_len)
3277 {
3278 struct udma_desc *d = to_udma_desc(desc);
3279 struct udma_chan *uc = to_udma_chan(desc->chan);
3280 struct cppi5_host_desc_t *h_desc;
3281 u32 psd_size = payload_len;
3282 u32 flags = 0;
3283
3284 if (!uc->config.pkt_mode || !uc->config.metadata_size)
3285 return -ENOTSUPP;
3286
3287 if (payload_len > uc->config.metadata_size)
3288 return -EINVAL;
3289
3290 if (uc->config.needs_epib && payload_len < CPPI5_INFO0_HDESC_EPIB_SIZE)
3291 return -EINVAL;
3292
3293 h_desc = d->hwdesc[0].cppi5_desc_vaddr;
3294
3295 if (uc->config.needs_epib) {
3296 psd_size -= CPPI5_INFO0_HDESC_EPIB_SIZE;
3297 flags |= CPPI5_INFO0_HDESC_EPIB_PRESENT;
3298 }
3299
3300 cppi5_hdesc_update_flags(h_desc, flags);
3301 cppi5_hdesc_update_psdata_size(h_desc, psd_size);
3302
3303 return 0;
3304 }
3305
3306 static struct dma_descriptor_metadata_ops metadata_ops = {
3307 .attach = udma_attach_metadata,
3308 .get_ptr = udma_get_metadata_ptr,
3309 .set_len = udma_set_metadata_len,
3310 };
3311
3312 static struct dma_async_tx_descriptor *
3313 udma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
3314 unsigned int sglen, enum dma_transfer_direction dir,
3315 unsigned long tx_flags, void *context)
3316 {
3317 struct udma_chan *uc = to_udma_chan(chan);
3318 enum dma_slave_buswidth dev_width;
3319 struct udma_desc *d;
3320 u32 burst;
3321
3322 if (dir != uc->config.dir &&
3323 (uc->config.dir == DMA_MEM_TO_MEM && !uc->config.tr_trigger_type)) {
3324 dev_err(chan->device->dev,
3325 "%s: chan%d is for %s, not supporting %s\n",
3326 __func__, uc->id,
3327 dmaengine_get_direction_text(uc->config.dir),
3328 dmaengine_get_direction_text(dir));
3329 return NULL;
3330 }
3331
3332 if (dir == DMA_DEV_TO_MEM) {
3333 dev_width = uc->cfg.src_addr_width;
3334 burst = uc->cfg.src_maxburst;
3335 } else if (dir == DMA_MEM_TO_DEV) {
3336 dev_width = uc->cfg.dst_addr_width;
3337 burst = uc->cfg.dst_maxburst;
3338 } else {
3339 dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
3340 return NULL;
3341 }
3342
3343 if (!burst)
3344 burst = 1;
3345
3346 if (uc->config.pkt_mode)
3347 d = udma_prep_slave_sg_pkt(uc, sgl, sglen, dir, tx_flags,
3348 context);
3349 else if (is_slave_direction(uc->config.dir))
3350 d = udma_prep_slave_sg_tr(uc, sgl, sglen, dir, tx_flags,
3351 context);
3352 else
3353 d = udma_prep_slave_sg_triggered_tr(uc, sgl, sglen, dir,
3354 tx_flags, context);
3355
3356 if (!d)
3357 return NULL;
3358
3359 d->dir = dir;
3360 d->desc_idx = 0;
3361 d->tr_idx = 0;
3362
3363 /* static TR for remote PDMA */
3364 if (udma_configure_statictr(uc, d, dev_width, burst)) {
3365 dev_err(uc->ud->dev,
3366 "%s: StaticTR Z is limited to maximum 4095 (%u)\n",
3367 __func__, d->static_tr.bstcnt);
3368
3369 udma_free_hwdesc(uc, d);
3370 kfree(d);
3371 return NULL;
3372 }
3373
3374 if (uc->config.metadata_size)
3375 d->vd.tx.metadata_ops = &metadata_ops;
3376
3377 return vchan_tx_prep(&uc->vc, &d->vd, tx_flags);
3378 }
3379
3380 static struct udma_desc *
3381 udma_prep_dma_cyclic_tr(struct udma_chan *uc, dma_addr_t buf_addr,
3382 size_t buf_len, size_t period_len,
3383 enum dma_transfer_direction dir, unsigned long flags)
3384 {
3385 struct udma_desc *d;
3386 size_t tr_size, period_addr;
3387 struct cppi5_tr_type1_t *tr_req;
3388 unsigned int periods = buf_len / period_len;
3389 u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
3390 unsigned int i;
3391 int num_tr;
3392
3393 num_tr = udma_get_tr_counters(period_len, __ffs(buf_addr), &tr0_cnt0,
3394 &tr0_cnt1, &tr1_cnt0);
3395 if (num_tr < 0) {
3396 dev_err(uc->ud->dev, "size %zu is not supported\n",
3397 period_len);
3398 return NULL;
3399 }
3400
3401 /* Now allocate and setup the descriptor. */
3402 tr_size = sizeof(struct cppi5_tr_type1_t);
3403 d = udma_alloc_tr_desc(uc, tr_size, periods * num_tr, dir);
3404 if (!d)
3405 return NULL;
3406
3407 tr_req = d->hwdesc[0].tr_req_base;
3408 if (uc->ud->match_data->type == DMA_TYPE_UDMA)
3409 period_addr = buf_addr;
3410 else
3411 period_addr = buf_addr |
3412 ((u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT);
3413
3414 for (i = 0; i < periods; i++) {
3415 int tr_idx = i * num_tr;
3416
3417 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false,
3418 false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
3419
3420 tr_req[tr_idx].addr = period_addr;
3421 tr_req[tr_idx].icnt0 = tr0_cnt0;
3422 tr_req[tr_idx].icnt1 = tr0_cnt1;
3423 tr_req[tr_idx].dim1 = tr0_cnt0;
3424
3425 if (num_tr == 2) {
3426 cppi5_tr_csf_set(&tr_req[tr_idx].flags,
3427 CPPI5_TR_CSF_SUPR_EVT);
3428 tr_idx++;
3429
3430 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1,
3431 false, false,
3432 CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
3433
3434 tr_req[tr_idx].addr = period_addr + tr0_cnt1 * tr0_cnt0;
3435 tr_req[tr_idx].icnt0 = tr1_cnt0;
3436 tr_req[tr_idx].icnt1 = 1;
3437 tr_req[tr_idx].dim1 = tr1_cnt0;
3438 }
3439
3440 if (!(flags & DMA_PREP_INTERRUPT))
3441 cppi5_tr_csf_set(&tr_req[tr_idx].flags,
3442 CPPI5_TR_CSF_SUPR_EVT);
3443
3444 period_addr += period_len;
3445 }
3446
3447 return d;
3448 }
3449
3450 static struct udma_desc *
3451 udma_prep_dma_cyclic_pkt(struct udma_chan *uc, dma_addr_t buf_addr,
3452 size_t buf_len, size_t period_len,
3453 enum dma_transfer_direction dir, unsigned long flags)
3454 {
3455 struct udma_desc *d;
3456 u32 ring_id;
3457 int i;
3458 int periods = buf_len / period_len;
3459
3460 if (periods > (K3_UDMA_DEFAULT_RING_SIZE - 1))
3461 return NULL;
3462
3463 if (period_len >= SZ_4M)
3464 return NULL;
3465
3466 d = kzalloc(struct_size(d, hwdesc, periods), GFP_NOWAIT);
3467 if (!d)
3468 return NULL;
3469
3470 d->hwdesc_count = periods;
3471
3472 /* TODO: re-check this... */
3473 if (dir == DMA_DEV_TO_MEM)
3474 ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring);
3475 else
3476 ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring);
3477
3478 if (uc->ud->match_data->type != DMA_TYPE_UDMA)
3479 buf_addr |= (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT;
3480
3481 for (i = 0; i < periods; i++) {
3482 struct udma_hwdesc *hwdesc = &d->hwdesc[i];
3483 dma_addr_t period_addr = buf_addr + (period_len * i);
3484 struct cppi5_host_desc_t *h_desc;
3485
3486 hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool,
3487 GFP_NOWAIT,
3488 &hwdesc->cppi5_desc_paddr);
3489 if (!hwdesc->cppi5_desc_vaddr) {
3490 dev_err(uc->ud->dev,
3491 "descriptor%d allocation failed\n", i);
3492
3493 udma_free_hwdesc(uc, d);
3494 kfree(d);
3495 return NULL;
3496 }
3497
3498 hwdesc->cppi5_desc_size = uc->config.hdesc_size;
3499 h_desc = hwdesc->cppi5_desc_vaddr;
3500
3501 cppi5_hdesc_init(h_desc, 0, 0);
3502 cppi5_hdesc_set_pktlen(h_desc, period_len);
3503
3504 /* Flow and Packed ID */
3505 cppi5_desc_set_pktids(&h_desc->hdr, uc->id,
3506 CPPI5_INFO1_DESC_FLOWID_DEFAULT);
3507 cppi5_desc_set_retpolicy(&h_desc->hdr, 0, ring_id);
3508
3509 /* attach each period to a new descriptor */
3510 cppi5_hdesc_attach_buf(h_desc,
3511 period_addr, period_len,
3512 period_addr, period_len);
3513 }
3514
3515 return d;
3516 }
3517
3518 static struct dma_async_tx_descriptor *
3519 udma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
3520 size_t period_len, enum dma_transfer_direction dir,
3521 unsigned long flags)
3522 {
3523 struct udma_chan *uc = to_udma_chan(chan);
3524 enum dma_slave_buswidth dev_width;
3525 struct udma_desc *d;
3526 u32 burst;
3527
3528 if (dir != uc->config.dir) {
3529 dev_err(chan->device->dev,
3530 "%s: chan%d is for %s, not supporting %s\n",
3531 __func__, uc->id,
3532 dmaengine_get_direction_text(uc->config.dir),
3533 dmaengine_get_direction_text(dir));
3534 return NULL;
3535 }
3536
3537 uc->cyclic = true;
3538
3539 if (dir == DMA_DEV_TO_MEM) {
3540 dev_width = uc->cfg.src_addr_width;
3541 burst = uc->cfg.src_maxburst;
3542 } else if (dir == DMA_MEM_TO_DEV) {
3543 dev_width = uc->cfg.dst_addr_width;
3544 burst = uc->cfg.dst_maxburst;
3545 } else {
3546 dev_err(uc->ud->dev, "%s: bad direction?\n", __func__);
3547 return NULL;
3548 }
3549
3550 if (!burst)
3551 burst = 1;
3552
3553 if (uc->config.pkt_mode)
3554 d = udma_prep_dma_cyclic_pkt(uc, buf_addr, buf_len, period_len,
3555 dir, flags);
3556 else
3557 d = udma_prep_dma_cyclic_tr(uc, buf_addr, buf_len, period_len,
3558 dir, flags);
3559
3560 if (!d)
3561 return NULL;
3562
3563 d->sglen = buf_len / period_len;
3564
3565 d->dir = dir;
3566 d->residue = buf_len;
3567
3568 /* static TR for remote PDMA */
3569 if (udma_configure_statictr(uc, d, dev_width, burst)) {
3570 dev_err(uc->ud->dev,
3571 "%s: StaticTR Z is limited to maximum 4095 (%u)\n",
3572 __func__, d->static_tr.bstcnt);
3573
3574 udma_free_hwdesc(uc, d);
3575 kfree(d);
3576 return NULL;
3577 }
3578
3579 if (uc->config.metadata_size)
3580 d->vd.tx.metadata_ops = &metadata_ops;
3581
3582 return vchan_tx_prep(&uc->vc, &d->vd, flags);
3583 }
3584
3585 static struct dma_async_tx_descriptor *
3586 udma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
3587 size_t len, unsigned long tx_flags)
3588 {
3589 struct udma_chan *uc = to_udma_chan(chan);
3590 struct udma_desc *d;
3591 struct cppi5_tr_type15_t *tr_req;
3592 int num_tr;
3593 size_t tr_size = sizeof(struct cppi5_tr_type15_t);
3594 u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
3595
3596 if (uc->config.dir != DMA_MEM_TO_MEM) {
3597 dev_err(chan->device->dev,
3598 "%s: chan%d is for %s, not supporting %s\n",
3599 __func__, uc->id,
3600 dmaengine_get_direction_text(uc->config.dir),
3601 dmaengine_get_direction_text(DMA_MEM_TO_MEM));
3602 return NULL;
3603 }
3604
3605 num_tr = udma_get_tr_counters(len, __ffs(src | dest), &tr0_cnt0,
3606 &tr0_cnt1, &tr1_cnt0);
3607 if (num_tr < 0) {
3608 dev_err(uc->ud->dev, "size %zu is not supported\n",
3609 len);
3610 return NULL;
3611 }
3612
3613 d = udma_alloc_tr_desc(uc, tr_size, num_tr, DMA_MEM_TO_MEM);
3614 if (!d)
3615 return NULL;
3616
3617 d->dir = DMA_MEM_TO_MEM;
3618 d->desc_idx = 0;
3619 d->tr_idx = 0;
3620 d->residue = len;
3621
3622 if (uc->ud->match_data->type != DMA_TYPE_UDMA) {
3623 src |= (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT;
3624 dest |= (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT;
3625 }
3626
3627 tr_req = d->hwdesc[0].tr_req_base;
3628
3629 cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true,
3630 CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
3631 cppi5_tr_csf_set(&tr_req[0].flags, CPPI5_TR_CSF_SUPR_EVT);
3632
3633 tr_req[0].addr = src;
3634 tr_req[0].icnt0 = tr0_cnt0;
3635 tr_req[0].icnt1 = tr0_cnt1;
3636 tr_req[0].icnt2 = 1;
3637 tr_req[0].icnt3 = 1;
3638 tr_req[0].dim1 = tr0_cnt0;
3639
3640 tr_req[0].daddr = dest;
3641 tr_req[0].dicnt0 = tr0_cnt0;
3642 tr_req[0].dicnt1 = tr0_cnt1;
3643 tr_req[0].dicnt2 = 1;
3644 tr_req[0].dicnt3 = 1;
3645 tr_req[0].ddim1 = tr0_cnt0;
3646
3647 if (num_tr == 2) {
3648 cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true,
3649 CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
3650 cppi5_tr_csf_set(&tr_req[1].flags, CPPI5_TR_CSF_SUPR_EVT);
3651
3652 tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0;
3653 tr_req[1].icnt0 = tr1_cnt0;
3654 tr_req[1].icnt1 = 1;
3655 tr_req[1].icnt2 = 1;
3656 tr_req[1].icnt3 = 1;
3657
3658 tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0;
3659 tr_req[1].dicnt0 = tr1_cnt0;
3660 tr_req[1].dicnt1 = 1;
3661 tr_req[1].dicnt2 = 1;
3662 tr_req[1].dicnt3 = 1;
3663 }
3664
3665 cppi5_tr_csf_set(&tr_req[num_tr - 1].flags,
3666 CPPI5_TR_CSF_SUPR_EVT | CPPI5_TR_CSF_EOP);
3667
3668 if (uc->config.metadata_size)
3669 d->vd.tx.metadata_ops = &metadata_ops;
3670
3671 return vchan_tx_prep(&uc->vc, &d->vd, tx_flags);
3672 }
3673
3674 static void udma_issue_pending(struct dma_chan *chan)
3675 {
3676 struct udma_chan *uc = to_udma_chan(chan);
3677 unsigned long flags;
3678
3679 spin_lock_irqsave(&uc->vc.lock, flags);
3680
3681 /* If we have something pending and no active descriptor, then */
3682 if (vchan_issue_pending(&uc->vc) && !uc->desc) {
3683 /*
3684 * start a descriptor if the channel is NOT [marked as
3685 * terminating _and_ it is still running (teardown has not
3686 * completed yet)].
3687 */
3688 if (!(uc->state == UDMA_CHAN_IS_TERMINATING &&
3689 udma_is_chan_running(uc)))
3690 udma_start(uc);
3691 }
3692
3693 spin_unlock_irqrestore(&uc->vc.lock, flags);
3694 }
3695
3696 static enum dma_status udma_tx_status(struct dma_chan *chan,
3697 dma_cookie_t cookie,
3698 struct dma_tx_state *txstate)
3699 {
3700 struct udma_chan *uc = to_udma_chan(chan);
3701 enum dma_status ret;
3702 unsigned long flags;
3703
3704 spin_lock_irqsave(&uc->vc.lock, flags);
3705
3706 ret = dma_cookie_status(chan, cookie, txstate);
3707
3708 if (!udma_is_chan_running(uc))
3709 ret = DMA_COMPLETE;
3710
3711 if (ret == DMA_IN_PROGRESS && udma_is_chan_paused(uc))
3712 ret = DMA_PAUSED;
3713
3714 if (ret == DMA_COMPLETE || !txstate)
3715 goto out;
3716
3717 if (uc->desc && uc->desc->vd.tx.cookie == cookie) {
3718 u32 peer_bcnt = 0;
3719 u32 bcnt = 0;
3720 u32 residue = uc->desc->residue;
3721 u32 delay = 0;
3722
3723 if (uc->desc->dir == DMA_MEM_TO_DEV) {
3724 bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_SBCNT_REG);
3725
3726 if (uc->config.ep_type != PSIL_EP_NATIVE) {
3727 peer_bcnt = udma_tchanrt_read(uc,
3728 UDMA_CHAN_RT_PEER_BCNT_REG);
3729
3730 if (bcnt > peer_bcnt)
3731 delay = bcnt - peer_bcnt;
3732 }
3733 } else if (uc->desc->dir == DMA_DEV_TO_MEM) {
3734 bcnt = udma_rchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
3735
3736 if (uc->config.ep_type != PSIL_EP_NATIVE) {
3737 peer_bcnt = udma_rchanrt_read(uc,
3738 UDMA_CHAN_RT_PEER_BCNT_REG);
3739
3740 if (peer_bcnt > bcnt)
3741 delay = peer_bcnt - bcnt;
3742 }
3743 } else {
3744 bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
3745 }
3746
3747 bcnt -= uc->bcnt;
3748 if (bcnt && !(bcnt % uc->desc->residue))
3749 residue = 0;
3750 else
3751 residue -= bcnt % uc->desc->residue;
3752
3753 if (!residue && (uc->config.dir == DMA_DEV_TO_MEM || !delay)) {
3754 ret = DMA_COMPLETE;
3755 delay = 0;
3756 }
3757
3758 dma_set_residue(txstate, residue);
3759 dma_set_in_flight_bytes(txstate, delay);
3760
3761 } else {
3762 ret = DMA_COMPLETE;
3763 }
3764
3765 out:
3766 spin_unlock_irqrestore(&uc->vc.lock, flags);
3767 return ret;
3768 }
3769
3770 static int udma_pause(struct dma_chan *chan)
3771 {
3772 struct udma_chan *uc = to_udma_chan(chan);
3773
3774 /* pause the channel */
3775 switch (uc->config.dir) {
3776 case DMA_DEV_TO_MEM:
3777 udma_rchanrt_update_bits(uc, UDMA_CHAN_RT_PEER_RT_EN_REG,
3778 UDMA_PEER_RT_EN_PAUSE,
3779 UDMA_PEER_RT_EN_PAUSE);
3780 break;
3781 case DMA_MEM_TO_DEV:
3782 udma_tchanrt_update_bits(uc, UDMA_CHAN_RT_PEER_RT_EN_REG,
3783 UDMA_PEER_RT_EN_PAUSE,
3784 UDMA_PEER_RT_EN_PAUSE);
3785 break;
3786 case DMA_MEM_TO_MEM:
3787 udma_tchanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG,
3788 UDMA_CHAN_RT_CTL_PAUSE,
3789 UDMA_CHAN_RT_CTL_PAUSE);
3790 break;
3791 default:
3792 return -EINVAL;
3793 }
3794
3795 return 0;
3796 }
3797
3798 static int udma_resume(struct dma_chan *chan)
3799 {
3800 struct udma_chan *uc = to_udma_chan(chan);
3801
3802 /* resume the channel */
3803 switch (uc->config.dir) {
3804 case DMA_DEV_TO_MEM:
3805 udma_rchanrt_update_bits(uc, UDMA_CHAN_RT_PEER_RT_EN_REG,
3806 UDMA_PEER_RT_EN_PAUSE, 0);
3807
3808 break;
3809 case DMA_MEM_TO_DEV:
3810 udma_tchanrt_update_bits(uc, UDMA_CHAN_RT_PEER_RT_EN_REG,
3811 UDMA_PEER_RT_EN_PAUSE, 0);
3812 break;
3813 case DMA_MEM_TO_MEM:
3814 udma_tchanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG,
3815 UDMA_CHAN_RT_CTL_PAUSE, 0);
3816 break;
3817 default:
3818 return -EINVAL;
3819 }
3820
3821 return 0;
3822 }
3823
3824 static int udma_terminate_all(struct dma_chan *chan)
3825 {
3826 struct udma_chan *uc = to_udma_chan(chan);
3827 unsigned long flags;
3828 LIST_HEAD(head);
3829
3830 spin_lock_irqsave(&uc->vc.lock, flags);
3831
3832 if (udma_is_chan_running(uc))
3833 udma_stop(uc);
3834
3835 if (uc->desc) {
3836 uc->terminated_desc = uc->desc;
3837 uc->desc = NULL;
3838 uc->terminated_desc->terminated = true;
3839 cancel_delayed_work(&uc->tx_drain.work);
3840 }
3841
3842 uc->paused = false;
3843
3844 vchan_get_all_descriptors(&uc->vc, &head);
3845 spin_unlock_irqrestore(&uc->vc.lock, flags);
3846 vchan_dma_desc_free_list(&uc->vc, &head);
3847
3848 return 0;
3849 }
3850
3851 static void udma_synchronize(struct dma_chan *chan)
3852 {
3853 struct udma_chan *uc = to_udma_chan(chan);
3854 unsigned long timeout = msecs_to_jiffies(1000);
3855
3856 vchan_synchronize(&uc->vc);
3857
3858 if (uc->state == UDMA_CHAN_IS_TERMINATING) {
3859 timeout = wait_for_completion_timeout(&uc->teardown_completed,
3860 timeout);
3861 if (!timeout) {
3862 dev_warn(uc->ud->dev, "chan%d teardown timeout!\n",
3863 uc->id);
3864 udma_dump_chan_stdata(uc);
3865 udma_reset_chan(uc, true);
3866 }
3867 }
3868
3869 udma_reset_chan(uc, false);
3870 if (udma_is_chan_running(uc))
3871 dev_warn(uc->ud->dev, "chan%d refused to stop!\n", uc->id);
3872
3873 cancel_delayed_work_sync(&uc->tx_drain.work);
3874 udma_reset_rings(uc);
3875 }
3876
3877 static void udma_desc_pre_callback(struct virt_dma_chan *vc,
3878 struct virt_dma_desc *vd,
3879 struct dmaengine_result *result)
3880 {
3881 struct udma_chan *uc = to_udma_chan(&vc->chan);
3882 struct udma_desc *d;
3883
3884 if (!vd)
3885 return;
3886
3887 d = to_udma_desc(&vd->tx);
3888
3889 if (d->metadata_size)
3890 udma_fetch_epib(uc, d);
3891
3892 /* Provide residue information for the client */
3893 if (result) {
3894 void *desc_vaddr = udma_curr_cppi5_desc_vaddr(d, d->desc_idx);
3895
3896 if (cppi5_desc_get_type(desc_vaddr) ==
3897 CPPI5_INFO0_DESC_TYPE_VAL_HOST) {
3898 result->residue = d->residue -
3899 cppi5_hdesc_get_pktlen(desc_vaddr);
3900 if (result->residue)
3901 result->result = DMA_TRANS_ABORTED;
3902 else
3903 result->result = DMA_TRANS_NOERROR;
3904 } else {
3905 result->residue = 0;
3906 result->result = DMA_TRANS_NOERROR;
3907 }
3908 }
3909 }
3910
3911 /*
3912 * This tasklet handles the completion of a DMA descriptor by
3913 * calling its callback and freeing it.
3914 */
3915 static void udma_vchan_complete(struct tasklet_struct *t)
3916 {
3917 struct virt_dma_chan *vc = from_tasklet(vc, t, task);
3918 struct virt_dma_desc *vd, *_vd;
3919 struct dmaengine_desc_callback cb;
3920 LIST_HEAD(head);
3921
3922 spin_lock_irq(&vc->lock);
3923 list_splice_tail_init(&vc->desc_completed, &head);
3924 vd = vc->cyclic;
3925 if (vd) {
3926 vc->cyclic = NULL;
3927 dmaengine_desc_get_callback(&vd->tx, &cb);
3928 } else {
3929 memset(&cb, 0, sizeof(cb));
3930 }
3931 spin_unlock_irq(&vc->lock);
3932
3933 udma_desc_pre_callback(vc, vd, NULL);
3934 dmaengine_desc_callback_invoke(&cb, NULL);
3935
3936 list_for_each_entry_safe(vd, _vd, &head, node) {
3937 struct dmaengine_result result;
3938
3939 dmaengine_desc_get_callback(&vd->tx, &cb);
3940
3941 list_del(&vd->node);
3942
3943 udma_desc_pre_callback(vc, vd, &result);
3944 dmaengine_desc_callback_invoke(&cb, &result);
3945
3946 vchan_vdesc_fini(vd);
3947 }
3948 }
3949
3950 static void udma_free_chan_resources(struct dma_chan *chan)
3951 {
3952 struct udma_chan *uc = to_udma_chan(chan);
3953 struct udma_dev *ud = to_udma_dev(chan->device);
3954
3955 udma_terminate_all(chan);
3956 if (uc->terminated_desc) {
3957 udma_reset_chan(uc, false);
3958 udma_reset_rings(uc);
3959 }
3960
3961 cancel_delayed_work_sync(&uc->tx_drain.work);
3962
3963 if (uc->irq_num_ring > 0) {
3964 free_irq(uc->irq_num_ring, uc);
3965
3966 uc->irq_num_ring = 0;
3967 }
3968 if (uc->irq_num_udma > 0) {
3969 free_irq(uc->irq_num_udma, uc);
3970
3971 uc->irq_num_udma = 0;
3972 }
3973
3974 /* Release PSI-L pairing */
3975 if (uc->psil_paired) {
3976 navss_psil_unpair(ud, uc->config.src_thread,
3977 uc->config.dst_thread);
3978 uc->psil_paired = false;
3979 }
3980
3981 vchan_free_chan_resources(&uc->vc);
3982 tasklet_kill(&uc->vc.task);
3983
3984 bcdma_free_bchan_resources(uc);
3985 udma_free_tx_resources(uc);
3986 udma_free_rx_resources(uc);
3987 udma_reset_uchan(uc);
3988
3989 if (uc->use_dma_pool) {
3990 dma_pool_destroy(uc->hdesc_pool);
3991 uc->use_dma_pool = false;
3992 }
3993 }
3994
3995 static struct platform_driver udma_driver;
3996 static struct platform_driver bcdma_driver;
3997 static struct platform_driver pktdma_driver;
3998
3999 struct udma_filter_param {
4000 int remote_thread_id;
4001 u32 atype;
4002 u32 asel;
4003 u32 tr_trigger_type;
4004 };
4005
4006 static bool udma_dma_filter_fn(struct dma_chan *chan, void *param)
4007 {
4008 struct udma_chan_config *ucc;
4009 struct psil_endpoint_config *ep_config;
4010 struct udma_filter_param *filter_param;
4011 struct udma_chan *uc;
4012 struct udma_dev *ud;
4013
4014 if (chan->device->dev->driver != &udma_driver.driver &&
4015 chan->device->dev->driver != &bcdma_driver.driver &&
4016 chan->device->dev->driver != &pktdma_driver.driver)
4017 return false;
4018
4019 uc = to_udma_chan(chan);
4020 ucc = &uc->config;
4021 ud = uc->ud;
4022 filter_param = param;
4023
4024 if (filter_param->atype > 2) {
4025 dev_err(ud->dev, "Invalid channel atype: %u\n",
4026 filter_param->atype);
4027 return false;
4028 }
4029
4030 if (filter_param->asel > 15) {
4031 dev_err(ud->dev, "Invalid channel asel: %u\n",
4032 filter_param->asel);
4033 return false;
4034 }
4035
4036 ucc->remote_thread_id = filter_param->remote_thread_id;
4037 ucc->atype = filter_param->atype;
4038 ucc->asel = filter_param->asel;
4039 ucc->tr_trigger_type = filter_param->tr_trigger_type;
4040
4041 if (ucc->tr_trigger_type) {
4042 ucc->dir = DMA_MEM_TO_MEM;
4043 goto triggered_bchan;
4044 } else if (ucc->remote_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET) {
4045 ucc->dir = DMA_MEM_TO_DEV;
4046 } else {
4047 ucc->dir = DMA_DEV_TO_MEM;
4048 }
4049
4050 ep_config = psil_get_ep_config(ucc->remote_thread_id);
4051 if (IS_ERR(ep_config)) {
4052 dev_err(ud->dev, "No configuration for psi-l thread 0x%04x\n",
4053 ucc->remote_thread_id);
4054 ucc->dir = DMA_MEM_TO_MEM;
4055 ucc->remote_thread_id = -1;
4056 ucc->atype = 0;
4057 ucc->asel = 0;
4058 return false;
4059 }
4060
4061 if (ud->match_data->type == DMA_TYPE_BCDMA &&
4062 ep_config->pkt_mode) {
4063 dev_err(ud->dev,
4064 "Only TR mode is supported (psi-l thread 0x%04x)\n",
4065 ucc->remote_thread_id);
4066 ucc->dir = DMA_MEM_TO_MEM;
4067 ucc->remote_thread_id = -1;
4068 ucc->atype = 0;
4069 ucc->asel = 0;
4070 return false;
4071 }
4072
4073 ucc->pkt_mode = ep_config->pkt_mode;
4074 ucc->channel_tpl = ep_config->channel_tpl;
4075 ucc->notdpkt = ep_config->notdpkt;
4076 ucc->ep_type = ep_config->ep_type;
4077
4078 if (ud->match_data->type == DMA_TYPE_PKTDMA &&
4079 ep_config->mapped_channel_id >= 0) {
4080 ucc->mapped_channel_id = ep_config->mapped_channel_id;
4081 ucc->default_flow_id = ep_config->default_flow_id;
4082 } else {
4083 ucc->mapped_channel_id = -1;
4084 ucc->default_flow_id = -1;
4085 }
4086
4087 if (ucc->ep_type != PSIL_EP_NATIVE) {
4088 const struct udma_match_data *match_data = ud->match_data;
4089
4090 if (match_data->flags & UDMA_FLAG_PDMA_ACC32)
4091 ucc->enable_acc32 = ep_config->pdma_acc32;
4092 if (match_data->flags & UDMA_FLAG_PDMA_BURST)
4093 ucc->enable_burst = ep_config->pdma_burst;
4094 }
4095
4096 ucc->needs_epib = ep_config->needs_epib;
4097 ucc->psd_size = ep_config->psd_size;
4098 ucc->metadata_size =
4099 (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) +
4100 ucc->psd_size;
4101
4102 if (ucc->pkt_mode)
4103 ucc->hdesc_size = ALIGN(sizeof(struct cppi5_host_desc_t) +
4104 ucc->metadata_size, ud->desc_align);
4105
4106 dev_dbg(ud->dev, "chan%d: Remote thread: 0x%04x (%s)\n", uc->id,
4107 ucc->remote_thread_id, dmaengine_get_direction_text(ucc->dir));
4108
4109 return true;
4110
4111 triggered_bchan:
4112 dev_dbg(ud->dev, "chan%d: triggered channel (type: %u)\n", uc->id,
4113 ucc->tr_trigger_type);
4114
4115 return true;
4116
4117 }
4118
4119 static struct dma_chan *udma_of_xlate(struct of_phandle_args *dma_spec,
4120 struct of_dma *ofdma)
4121 {
4122 struct udma_dev *ud = ofdma->of_dma_data;
4123 dma_cap_mask_t mask = ud->ddev.cap_mask;
4124 struct udma_filter_param filter_param;
4125 struct dma_chan *chan;
4126
4127 if (ud->match_data->type == DMA_TYPE_BCDMA) {
4128 if (dma_spec->args_count != 3)
4129 return NULL;
4130
4131 filter_param.tr_trigger_type = dma_spec->args[0];
4132 filter_param.remote_thread_id = dma_spec->args[1];
4133 filter_param.asel = dma_spec->args[2];
4134 filter_param.atype = 0;
4135 } else {
4136 if (dma_spec->args_count != 1 && dma_spec->args_count != 2)
4137 return NULL;
4138
4139 filter_param.remote_thread_id = dma_spec->args[0];
4140 filter_param.tr_trigger_type = 0;
4141 if (dma_spec->args_count == 2) {
4142 if (ud->match_data->type == DMA_TYPE_UDMA) {
4143 filter_param.atype = dma_spec->args[1];
4144 filter_param.asel = 0;
4145 } else {
4146 filter_param.atype = 0;
4147 filter_param.asel = dma_spec->args[1];
4148 }
4149 } else {
4150 filter_param.atype = 0;
4151 filter_param.asel = 0;
4152 }
4153 }
4154
4155 chan = __dma_request_channel(&mask, udma_dma_filter_fn, &filter_param,
4156 ofdma->of_node);
4157 if (!chan) {
4158 dev_err(ud->dev, "get channel fail in %s.\n", __func__);
4159 return ERR_PTR(-EINVAL);
4160 }
4161
4162 return chan;
4163 }
4164
4165 static struct udma_match_data am654_main_data = {
4166 .type = DMA_TYPE_UDMA,
4167 .psil_base = 0x1000,
4168 .enable_memcpy_support = true,
4169 .statictr_z_mask = GENMASK(11, 0),
4170 };
4171
4172 static struct udma_match_data am654_mcu_data = {
4173 .type = DMA_TYPE_UDMA,
4174 .psil_base = 0x6000,
4175 .enable_memcpy_support = false,
4176 .statictr_z_mask = GENMASK(11, 0),
4177 };
4178
4179 static struct udma_match_data j721e_main_data = {
4180 .type = DMA_TYPE_UDMA,
4181 .psil_base = 0x1000,
4182 .enable_memcpy_support = true,
4183 .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
4184 .statictr_z_mask = GENMASK(23, 0),
4185 };
4186
4187 static struct udma_match_data j721e_mcu_data = {
4188 .type = DMA_TYPE_UDMA,
4189 .psil_base = 0x6000,
4190 .enable_memcpy_support = false, /* MEM_TO_MEM is slow via MCU UDMA */
4191 .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
4192 .statictr_z_mask = GENMASK(23, 0),
4193 };
4194
4195 static struct udma_match_data am64_bcdma_data = {
4196 .type = DMA_TYPE_BCDMA,
4197 .psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */
4198 .enable_memcpy_support = true, /* Supported via bchan */
4199 .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
4200 .statictr_z_mask = GENMASK(23, 0),
4201 };
4202
4203 static struct udma_match_data am64_pktdma_data = {
4204 .type = DMA_TYPE_PKTDMA,
4205 .psil_base = 0x1000,
4206 .enable_memcpy_support = false, /* PKTDMA does not support MEM_TO_MEM */
4207 .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
4208 .statictr_z_mask = GENMASK(23, 0),
4209 };
4210
4211 static const struct of_device_id udma_of_match[] = {
4212 {
4213 .compatible = "ti,am654-navss-main-udmap",
4214 .data = &am654_main_data,
4215 },
4216 {
4217 .compatible = "ti,am654-navss-mcu-udmap",
4218 .data = &am654_mcu_data,
4219 }, {
4220 .compatible = "ti,j721e-navss-main-udmap",
4221 .data = &j721e_main_data,
4222 }, {
4223 .compatible = "ti,j721e-navss-mcu-udmap",
4224 .data = &j721e_mcu_data,
4225 },
4226 { /* Sentinel */ },
4227 };
4228
4229 static const struct of_device_id bcdma_of_match[] = {
4230 {
4231 .compatible = "ti,am64-dmss-bcdma",
4232 .data = &am64_bcdma_data,
4233 },
4234 { /* Sentinel */ },
4235 };
4236
4237 static const struct of_device_id pktdma_of_match[] = {
4238 {
4239 .compatible = "ti,am64-dmss-pktdma",
4240 .data = &am64_pktdma_data,
4241 },
4242 { /* Sentinel */ },
4243 };
4244
4245 static struct udma_soc_data am654_soc_data = {
4246 .oes = {
4247 .udma_rchan = 0x200,
4248 },
4249 };
4250
4251 static struct udma_soc_data j721e_soc_data = {
4252 .oes = {
4253 .udma_rchan = 0x400,
4254 },
4255 };
4256
4257 static struct udma_soc_data j7200_soc_data = {
4258 .oes = {
4259 .udma_rchan = 0x80,
4260 },
4261 };
4262
4263 static struct udma_soc_data am64_soc_data = {
4264 .oes = {
4265 .bcdma_bchan_data = 0x2200,
4266 .bcdma_bchan_ring = 0x2400,
4267 .bcdma_tchan_data = 0x2800,
4268 .bcdma_tchan_ring = 0x2a00,
4269 .bcdma_rchan_data = 0x2e00,
4270 .bcdma_rchan_ring = 0x3000,
4271 .pktdma_tchan_flow = 0x1200,
4272 .pktdma_rchan_flow = 0x1600,
4273 },
4274 .bcdma_trigger_event_offset = 0xc400,
4275 };
4276
4277 static const struct soc_device_attribute k3_soc_devices[] = {
4278 { .family = "AM65X", .data = &am654_soc_data },
4279 { .family = "J721E", .data = &j721e_soc_data },
4280 { .family = "J7200", .data = &j7200_soc_data },
4281 { .family = "AM64X", .data = &am64_soc_data },
4282 { /* sentinel */ }
4283 };
4284
4285 static int udma_get_mmrs(struct platform_device *pdev, struct udma_dev *ud)
4286 {
4287 u32 cap2, cap3, cap4;
4288 int i;
4289
4290 ud->mmrs[MMR_GCFG] = devm_platform_ioremap_resource_byname(pdev, mmr_names[MMR_GCFG]);
4291 if (IS_ERR(ud->mmrs[MMR_GCFG]))
4292 return PTR_ERR(ud->mmrs[MMR_GCFG]);
4293
4294 cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
4295 cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
4296
4297 switch (ud->match_data->type) {
4298 case DMA_TYPE_UDMA:
4299 ud->rflow_cnt = UDMA_CAP3_RFLOW_CNT(cap3);
4300 ud->tchan_cnt = UDMA_CAP2_TCHAN_CNT(cap2);
4301 ud->echan_cnt = UDMA_CAP2_ECHAN_CNT(cap2);
4302 ud->rchan_cnt = UDMA_CAP2_RCHAN_CNT(cap2);
4303 break;
4304 case DMA_TYPE_BCDMA:
4305 ud->bchan_cnt = BCDMA_CAP2_BCHAN_CNT(cap2);
4306 ud->tchan_cnt = BCDMA_CAP2_TCHAN_CNT(cap2);
4307 ud->rchan_cnt = BCDMA_CAP2_RCHAN_CNT(cap2);
4308 break;
4309 case DMA_TYPE_PKTDMA:
4310 cap4 = udma_read(ud->mmrs[MMR_GCFG], 0x30);
4311 ud->tchan_cnt = UDMA_CAP2_TCHAN_CNT(cap2);
4312 ud->rchan_cnt = UDMA_CAP2_RCHAN_CNT(cap2);
4313 ud->rflow_cnt = UDMA_CAP3_RFLOW_CNT(cap3);
4314 ud->tflow_cnt = PKTDMA_CAP4_TFLOW_CNT(cap4);
4315 break;
4316 default:
4317 return -EINVAL;
4318 }
4319
4320 for (i = 1; i < MMR_LAST; i++) {
4321 if (i == MMR_BCHANRT && ud->bchan_cnt == 0)
4322 continue;
4323 if (i == MMR_TCHANRT && ud->tchan_cnt == 0)
4324 continue;
4325 if (i == MMR_RCHANRT && ud->rchan_cnt == 0)
4326 continue;
4327
4328 ud->mmrs[i] = devm_platform_ioremap_resource_byname(pdev, mmr_names[i]);
4329 if (IS_ERR(ud->mmrs[i]))
4330 return PTR_ERR(ud->mmrs[i]);
4331 }
4332
4333 return 0;
4334 }
4335
4336 static void udma_mark_resource_ranges(struct udma_dev *ud, unsigned long *map,
4337 struct ti_sci_resource_desc *rm_desc,
4338 char *name)
4339 {
4340 bitmap_clear(map, rm_desc->start, rm_desc->num);
4341 bitmap_clear(map, rm_desc->start_sec, rm_desc->num_sec);
4342 dev_dbg(ud->dev, "ti_sci resource range for %s: %d:%d | %d:%d\n", name,
4343 rm_desc->start, rm_desc->num, rm_desc->start_sec,
4344 rm_desc->num_sec);
4345 }
4346
4347 static const char * const range_names[] = {
4348 [RM_RANGE_BCHAN] = "ti,sci-rm-range-bchan",
4349 [RM_RANGE_TCHAN] = "ti,sci-rm-range-tchan",
4350 [RM_RANGE_RCHAN] = "ti,sci-rm-range-rchan",
4351 [RM_RANGE_RFLOW] = "ti,sci-rm-range-rflow",
4352 [RM_RANGE_TFLOW] = "ti,sci-rm-range-tflow",
4353 };
4354
4355 static int udma_setup_resources(struct udma_dev *ud)
4356 {
4357 int ret, i, j;
4358 struct device *dev = ud->dev;
4359 struct ti_sci_resource *rm_res, irq_res;
4360 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
4361 u32 cap3;
4362
4363 /* Set up the throughput level start indexes */
4364 cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
4365 if (of_device_is_compatible(dev->of_node,
4366 "ti,am654-navss-main-udmap")) {
4367 ud->tchan_tpl.levels = 2;
4368 ud->tchan_tpl.start_idx[0] = 8;
4369 } else if (of_device_is_compatible(dev->of_node,
4370 "ti,am654-navss-mcu-udmap")) {
4371 ud->tchan_tpl.levels = 2;
4372 ud->tchan_tpl.start_idx[0] = 2;
4373 } else if (UDMA_CAP3_UCHAN_CNT(cap3)) {
4374 ud->tchan_tpl.levels = 3;
4375 ud->tchan_tpl.start_idx[1] = UDMA_CAP3_UCHAN_CNT(cap3);
4376 ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3);
4377 } else if (UDMA_CAP3_HCHAN_CNT(cap3)) {
4378 ud->tchan_tpl.levels = 2;
4379 ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3);
4380 } else {
4381 ud->tchan_tpl.levels = 1;
4382 }
4383
4384 ud->rchan_tpl.levels = ud->tchan_tpl.levels;
4385 ud->rchan_tpl.start_idx[0] = ud->tchan_tpl.start_idx[0];
4386 ud->rchan_tpl.start_idx[1] = ud->tchan_tpl.start_idx[1];
4387
4388 ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
4389 sizeof(unsigned long), GFP_KERNEL);
4390 ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
4391 GFP_KERNEL);
4392 ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
4393 sizeof(unsigned long), GFP_KERNEL);
4394 ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
4395 GFP_KERNEL);
4396 ud->rflow_gp_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rflow_cnt),
4397 sizeof(unsigned long),
4398 GFP_KERNEL);
4399 ud->rflow_gp_map_allocated = devm_kcalloc(dev,
4400 BITS_TO_LONGS(ud->rflow_cnt),
4401 sizeof(unsigned long),
4402 GFP_KERNEL);
4403 ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
4404 sizeof(unsigned long),
4405 GFP_KERNEL);
4406 ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
4407 GFP_KERNEL);
4408
4409 if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_gp_map ||
4410 !ud->rflow_gp_map_allocated || !ud->tchans || !ud->rchans ||
4411 !ud->rflows || !ud->rflow_in_use)
4412 return -ENOMEM;
4413
4414 /*
4415 * RX flows with the same Ids as RX channels are reserved to be used
4416 * as default flows if remote HW can't generate flow_ids. Those
4417 * RX flows can be requested only explicitly by id.
4418 */
4419 bitmap_set(ud->rflow_gp_map_allocated, 0, ud->rchan_cnt);
4420
4421 /* by default no GP rflows are assigned to Linux */
4422 bitmap_set(ud->rflow_gp_map, 0, ud->rflow_cnt);
4423
4424 /* Get resource ranges from tisci */
4425 for (i = 0; i < RM_RANGE_LAST; i++) {
4426 if (i == RM_RANGE_BCHAN || i == RM_RANGE_TFLOW)
4427 continue;
4428
4429 tisci_rm->rm_ranges[i] =
4430 devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
4431 tisci_rm->tisci_dev_id,
4432 (char *)range_names[i]);
4433 }
4434
4435 /* tchan ranges */
4436 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
4437 if (IS_ERR(rm_res)) {
4438 bitmap_zero(ud->tchan_map, ud->tchan_cnt);
4439 } else {
4440 bitmap_fill(ud->tchan_map, ud->tchan_cnt);
4441 for (i = 0; i < rm_res->sets; i++)
4442 udma_mark_resource_ranges(ud, ud->tchan_map,
4443 &rm_res->desc[i], "tchan");
4444 }
4445 irq_res.sets = rm_res->sets;
4446
4447 /* rchan and matching default flow ranges */
4448 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
4449 if (IS_ERR(rm_res)) {
4450 bitmap_zero(ud->rchan_map, ud->rchan_cnt);
4451 } else {
4452 bitmap_fill(ud->rchan_map, ud->rchan_cnt);
4453 for (i = 0; i < rm_res->sets; i++)
4454 udma_mark_resource_ranges(ud, ud->rchan_map,
4455 &rm_res->desc[i], "rchan");
4456 }
4457
4458 irq_res.sets += rm_res->sets;
4459 irq_res.desc = kcalloc(irq_res.sets, sizeof(*irq_res.desc), GFP_KERNEL);
4460 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
4461 for (i = 0; i < rm_res->sets; i++) {
4462 irq_res.desc[i].start = rm_res->desc[i].start;
4463 irq_res.desc[i].num = rm_res->desc[i].num;
4464 irq_res.desc[i].start_sec = rm_res->desc[i].start_sec;
4465 irq_res.desc[i].num_sec = rm_res->desc[i].num_sec;
4466 }
4467 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
4468 for (j = 0; j < rm_res->sets; j++, i++) {
4469 if (rm_res->desc[j].num) {
4470 irq_res.desc[i].start = rm_res->desc[j].start +
4471 ud->soc_data->oes.udma_rchan;
4472 irq_res.desc[i].num = rm_res->desc[j].num;
4473 }
4474 if (rm_res->desc[j].num_sec) {
4475 irq_res.desc[i].start_sec = rm_res->desc[j].start_sec +
4476 ud->soc_data->oes.udma_rchan;
4477 irq_res.desc[i].num_sec = rm_res->desc[j].num_sec;
4478 }
4479 }
4480 ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res);
4481 kfree(irq_res.desc);
4482 if (ret) {
4483 dev_err(ud->dev, "Failed to allocate MSI interrupts\n");
4484 return ret;
4485 }
4486
4487 /* GP rflow ranges */
4488 rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW];
4489 if (IS_ERR(rm_res)) {
4490 /* all gp flows are assigned exclusively to Linux */
4491 bitmap_clear(ud->rflow_gp_map, ud->rchan_cnt,
4492 ud->rflow_cnt - ud->rchan_cnt);
4493 } else {
4494 for (i = 0; i < rm_res->sets; i++)
4495 udma_mark_resource_ranges(ud, ud->rflow_gp_map,
4496 &rm_res->desc[i], "gp-rflow");
4497 }
4498
4499 return 0;
4500 }
4501
4502 static int bcdma_setup_resources(struct udma_dev *ud)
4503 {
4504 int ret, i, j;
4505 struct device *dev = ud->dev;
4506 struct ti_sci_resource *rm_res, irq_res;
4507 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
4508 const struct udma_oes_offsets *oes = &ud->soc_data->oes;
4509 u32 cap;
4510
4511 /* Set up the throughput level start indexes */
4512 cap = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
4513 if (BCDMA_CAP3_UBCHAN_CNT(cap)) {
4514 ud->bchan_tpl.levels = 3;
4515 ud->bchan_tpl.start_idx[1] = BCDMA_CAP3_UBCHAN_CNT(cap);
4516 ud->bchan_tpl.start_idx[0] = BCDMA_CAP3_HBCHAN_CNT(cap);
4517 } else if (BCDMA_CAP3_HBCHAN_CNT(cap)) {
4518 ud->bchan_tpl.levels = 2;
4519 ud->bchan_tpl.start_idx[0] = BCDMA_CAP3_HBCHAN_CNT(cap);
4520 } else {
4521 ud->bchan_tpl.levels = 1;
4522 }
4523
4524 cap = udma_read(ud->mmrs[MMR_GCFG], 0x30);
4525 if (BCDMA_CAP4_URCHAN_CNT(cap)) {
4526 ud->rchan_tpl.levels = 3;
4527 ud->rchan_tpl.start_idx[1] = BCDMA_CAP4_URCHAN_CNT(cap);
4528 ud->rchan_tpl.start_idx[0] = BCDMA_CAP4_HRCHAN_CNT(cap);
4529 } else if (BCDMA_CAP4_HRCHAN_CNT(cap)) {
4530 ud->rchan_tpl.levels = 2;
4531 ud->rchan_tpl.start_idx[0] = BCDMA_CAP4_HRCHAN_CNT(cap);
4532 } else {
4533 ud->rchan_tpl.levels = 1;
4534 }
4535
4536 if (BCDMA_CAP4_UTCHAN_CNT(cap)) {
4537 ud->tchan_tpl.levels = 3;
4538 ud->tchan_tpl.start_idx[1] = BCDMA_CAP4_UTCHAN_CNT(cap);
4539 ud->tchan_tpl.start_idx[0] = BCDMA_CAP4_HTCHAN_CNT(cap);
4540 } else if (BCDMA_CAP4_HTCHAN_CNT(cap)) {
4541 ud->tchan_tpl.levels = 2;
4542 ud->tchan_tpl.start_idx[0] = BCDMA_CAP4_HTCHAN_CNT(cap);
4543 } else {
4544 ud->tchan_tpl.levels = 1;
4545 }
4546
4547 ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt),
4548 sizeof(unsigned long), GFP_KERNEL);
4549 ud->bchans = devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans),
4550 GFP_KERNEL);
4551 ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
4552 sizeof(unsigned long), GFP_KERNEL);
4553 ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
4554 GFP_KERNEL);
4555 ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
4556 sizeof(unsigned long), GFP_KERNEL);
4557 ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
4558 GFP_KERNEL);
4559 /* BCDMA do not really have flows, but the driver expect it */
4560 ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt),
4561 sizeof(unsigned long),
4562 GFP_KERNEL);
4563 ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows),
4564 GFP_KERNEL);
4565
4566 if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map ||
4567 !ud->rflow_in_use || !ud->bchans || !ud->tchans || !ud->rchans ||
4568 !ud->rflows)
4569 return -ENOMEM;
4570
4571 /* Get resource ranges from tisci */
4572 for (i = 0; i < RM_RANGE_LAST; i++) {
4573 if (i == RM_RANGE_RFLOW || i == RM_RANGE_TFLOW)
4574 continue;
4575 if (i == RM_RANGE_BCHAN && ud->bchan_cnt == 0)
4576 continue;
4577 if (i == RM_RANGE_TCHAN && ud->tchan_cnt == 0)
4578 continue;
4579 if (i == RM_RANGE_RCHAN && ud->rchan_cnt == 0)
4580 continue;
4581
4582 tisci_rm->rm_ranges[i] =
4583 devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
4584 tisci_rm->tisci_dev_id,
4585 (char *)range_names[i]);
4586 }
4587
4588 irq_res.sets = 0;
4589
4590 /* bchan ranges */
4591 if (ud->bchan_cnt) {
4592 rm_res = tisci_rm->rm_ranges[RM_RANGE_BCHAN];
4593 if (IS_ERR(rm_res)) {
4594 bitmap_zero(ud->bchan_map, ud->bchan_cnt);
4595 } else {
4596 bitmap_fill(ud->bchan_map, ud->bchan_cnt);
4597 for (i = 0; i < rm_res->sets; i++)
4598 udma_mark_resource_ranges(ud, ud->bchan_map,
4599 &rm_res->desc[i],
4600 "bchan");
4601 }
4602 irq_res.sets += rm_res->sets;
4603 }
4604
4605 /* tchan ranges */
4606 if (ud->tchan_cnt) {
4607 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
4608 if (IS_ERR(rm_res)) {
4609 bitmap_zero(ud->tchan_map, ud->tchan_cnt);
4610 } else {
4611 bitmap_fill(ud->tchan_map, ud->tchan_cnt);
4612 for (i = 0; i < rm_res->sets; i++)
4613 udma_mark_resource_ranges(ud, ud->tchan_map,
4614 &rm_res->desc[i],
4615 "tchan");
4616 }
4617 irq_res.sets += rm_res->sets * 2;
4618 }
4619
4620 /* rchan ranges */
4621 if (ud->rchan_cnt) {
4622 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
4623 if (IS_ERR(rm_res)) {
4624 bitmap_zero(ud->rchan_map, ud->rchan_cnt);
4625 } else {
4626 bitmap_fill(ud->rchan_map, ud->rchan_cnt);
4627 for (i = 0; i < rm_res->sets; i++)
4628 udma_mark_resource_ranges(ud, ud->rchan_map,
4629 &rm_res->desc[i],
4630 "rchan");
4631 }
4632 irq_res.sets += rm_res->sets * 2;
4633 }
4634
4635 irq_res.desc = kcalloc(irq_res.sets, sizeof(*irq_res.desc), GFP_KERNEL);
4636 if (ud->bchan_cnt) {
4637 rm_res = tisci_rm->rm_ranges[RM_RANGE_BCHAN];
4638 for (i = 0; i < rm_res->sets; i++) {
4639 irq_res.desc[i].start = rm_res->desc[i].start +
4640 oes->bcdma_bchan_ring;
4641 irq_res.desc[i].num = rm_res->desc[i].num;
4642 }
4643 }
4644 if (ud->tchan_cnt) {
4645 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
4646 for (j = 0; j < rm_res->sets; j++, i += 2) {
4647 irq_res.desc[i].start = rm_res->desc[j].start +
4648 oes->bcdma_tchan_data;
4649 irq_res.desc[i].num = rm_res->desc[j].num;
4650
4651 irq_res.desc[i + 1].start = rm_res->desc[j].start +
4652 oes->bcdma_tchan_ring;
4653 irq_res.desc[i + 1].num = rm_res->desc[j].num;
4654 }
4655 }
4656 if (ud->rchan_cnt) {
4657 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
4658 for (j = 0; j < rm_res->sets; j++, i += 2) {
4659 irq_res.desc[i].start = rm_res->desc[j].start +
4660 oes->bcdma_rchan_data;
4661 irq_res.desc[i].num = rm_res->desc[j].num;
4662
4663 irq_res.desc[i + 1].start = rm_res->desc[j].start +
4664 oes->bcdma_rchan_ring;
4665 irq_res.desc[i + 1].num = rm_res->desc[j].num;
4666 }
4667 }
4668
4669 ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res);
4670 kfree(irq_res.desc);
4671 if (ret) {
4672 dev_err(ud->dev, "Failed to allocate MSI interrupts\n");
4673 return ret;
4674 }
4675
4676 return 0;
4677 }
4678
4679 static int pktdma_setup_resources(struct udma_dev *ud)
4680 {
4681 int ret, i, j;
4682 struct device *dev = ud->dev;
4683 struct ti_sci_resource *rm_res, irq_res;
4684 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
4685 const struct udma_oes_offsets *oes = &ud->soc_data->oes;
4686 u32 cap3;
4687
4688 /* Set up the throughput level start indexes */
4689 cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
4690 if (UDMA_CAP3_UCHAN_CNT(cap3)) {
4691 ud->tchan_tpl.levels = 3;
4692 ud->tchan_tpl.start_idx[1] = UDMA_CAP3_UCHAN_CNT(cap3);
4693 ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3);
4694 } else if (UDMA_CAP3_HCHAN_CNT(cap3)) {
4695 ud->tchan_tpl.levels = 2;
4696 ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3);
4697 } else {
4698 ud->tchan_tpl.levels = 1;
4699 }
4700
4701 ud->tchan_tpl.levels = ud->tchan_tpl.levels;
4702 ud->tchan_tpl.start_idx[0] = ud->tchan_tpl.start_idx[0];
4703 ud->tchan_tpl.start_idx[1] = ud->tchan_tpl.start_idx[1];
4704
4705 ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
4706 sizeof(unsigned long), GFP_KERNEL);
4707 ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
4708 GFP_KERNEL);
4709 ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
4710 sizeof(unsigned long), GFP_KERNEL);
4711 ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
4712 GFP_KERNEL);
4713 ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
4714 sizeof(unsigned long),
4715 GFP_KERNEL);
4716 ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
4717 GFP_KERNEL);
4718 ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt),
4719 sizeof(unsigned long), GFP_KERNEL);
4720
4721 if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans ||
4722 !ud->rchans || !ud->rflows || !ud->rflow_in_use)
4723 return -ENOMEM;
4724
4725 /* Get resource ranges from tisci */
4726 for (i = 0; i < RM_RANGE_LAST; i++) {
4727 if (i == RM_RANGE_BCHAN)
4728 continue;
4729
4730 tisci_rm->rm_ranges[i] =
4731 devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
4732 tisci_rm->tisci_dev_id,
4733 (char *)range_names[i]);
4734 }
4735
4736 /* tchan ranges */
4737 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
4738 if (IS_ERR(rm_res)) {
4739 bitmap_zero(ud->tchan_map, ud->tchan_cnt);
4740 } else {
4741 bitmap_fill(ud->tchan_map, ud->tchan_cnt);
4742 for (i = 0; i < rm_res->sets; i++)
4743 udma_mark_resource_ranges(ud, ud->tchan_map,
4744 &rm_res->desc[i], "tchan");
4745 }
4746
4747 /* rchan ranges */
4748 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
4749 if (IS_ERR(rm_res)) {
4750 bitmap_zero(ud->rchan_map, ud->rchan_cnt);
4751 } else {
4752 bitmap_fill(ud->rchan_map, ud->rchan_cnt);
4753 for (i = 0; i < rm_res->sets; i++)
4754 udma_mark_resource_ranges(ud, ud->rchan_map,
4755 &rm_res->desc[i], "rchan");
4756 }
4757
4758 /* rflow ranges */
4759 rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW];
4760 if (IS_ERR(rm_res)) {
4761 /* all rflows are assigned exclusively to Linux */
4762 bitmap_zero(ud->rflow_in_use, ud->rflow_cnt);
4763 } else {
4764 bitmap_fill(ud->rflow_in_use, ud->rflow_cnt);
4765 for (i = 0; i < rm_res->sets; i++)
4766 udma_mark_resource_ranges(ud, ud->rflow_in_use,
4767 &rm_res->desc[i], "rflow");
4768 }
4769 irq_res.sets = rm_res->sets;
4770
4771 /* tflow ranges */
4772 rm_res = tisci_rm->rm_ranges[RM_RANGE_TFLOW];
4773 if (IS_ERR(rm_res)) {
4774 /* all tflows are assigned exclusively to Linux */
4775 bitmap_zero(ud->tflow_map, ud->tflow_cnt);
4776 } else {
4777 bitmap_fill(ud->tflow_map, ud->tflow_cnt);
4778 for (i = 0; i < rm_res->sets; i++)
4779 udma_mark_resource_ranges(ud, ud->tflow_map,
4780 &rm_res->desc[i], "tflow");
4781 }
4782 irq_res.sets += rm_res->sets;
4783
4784 irq_res.desc = kcalloc(irq_res.sets, sizeof(*irq_res.desc), GFP_KERNEL);
4785 rm_res = tisci_rm->rm_ranges[RM_RANGE_TFLOW];
4786 for (i = 0; i < rm_res->sets; i++) {
4787 irq_res.desc[i].start = rm_res->desc[i].start +
4788 oes->pktdma_tchan_flow;
4789 irq_res.desc[i].num = rm_res->desc[i].num;
4790 }
4791 rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW];
4792 for (j = 0; j < rm_res->sets; j++, i++) {
4793 irq_res.desc[i].start = rm_res->desc[j].start +
4794 oes->pktdma_rchan_flow;
4795 irq_res.desc[i].num = rm_res->desc[j].num;
4796 }
4797 ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res);
4798 kfree(irq_res.desc);
4799 if (ret) {
4800 dev_err(ud->dev, "Failed to allocate MSI interrupts\n");
4801 return ret;
4802 }
4803
4804 return 0;
4805 }
4806
4807 static int setup_resources(struct udma_dev *ud)
4808 {
4809 struct device *dev = ud->dev;
4810 int ch_count, ret;
4811
4812 switch (ud->match_data->type) {
4813 case DMA_TYPE_UDMA:
4814 ret = udma_setup_resources(ud);
4815 break;
4816 case DMA_TYPE_BCDMA:
4817 ret = bcdma_setup_resources(ud);
4818 break;
4819 case DMA_TYPE_PKTDMA:
4820 ret = pktdma_setup_resources(ud);
4821 break;
4822 default:
4823 return -EINVAL;
4824 }
4825
4826 if (ret)
4827 return ret;
4828
4829 ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt;
4830 if (ud->bchan_cnt)
4831 ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
4832 ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
4833 ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
4834 if (!ch_count)
4835 return -ENODEV;
4836
4837 ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels),
4838 GFP_KERNEL);
4839 if (!ud->channels)
4840 return -ENOMEM;
4841
4842 switch (ud->match_data->type) {
4843 case DMA_TYPE_UDMA:
4844 dev_info(dev,
4845 "Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n",
4846 ch_count,
4847 ud->tchan_cnt - bitmap_weight(ud->tchan_map,
4848 ud->tchan_cnt),
4849 ud->rchan_cnt - bitmap_weight(ud->rchan_map,
4850 ud->rchan_cnt),
4851 ud->rflow_cnt - bitmap_weight(ud->rflow_gp_map,
4852 ud->rflow_cnt));
4853 break;
4854 case DMA_TYPE_BCDMA:
4855 dev_info(dev,
4856 "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n",
4857 ch_count,
4858 ud->bchan_cnt - bitmap_weight(ud->bchan_map,
4859 ud->bchan_cnt),
4860 ud->tchan_cnt - bitmap_weight(ud->tchan_map,
4861 ud->tchan_cnt),
4862 ud->rchan_cnt - bitmap_weight(ud->rchan_map,
4863 ud->rchan_cnt));
4864 break;
4865 case DMA_TYPE_PKTDMA:
4866 dev_info(dev,
4867 "Channels: %d (tchan: %u, rchan: %u)\n",
4868 ch_count,
4869 ud->tchan_cnt - bitmap_weight(ud->tchan_map,
4870 ud->tchan_cnt),
4871 ud->rchan_cnt - bitmap_weight(ud->rchan_map,
4872 ud->rchan_cnt));
4873 default:
4874 break;
4875 }
4876
4877 return ch_count;
4878 }
4879
4880 static int udma_setup_rx_flush(struct udma_dev *ud)
4881 {
4882 struct udma_rx_flush *rx_flush = &ud->rx_flush;
4883 struct cppi5_desc_hdr_t *tr_desc;
4884 struct cppi5_tr_type1_t *tr_req;
4885 struct cppi5_host_desc_t *desc;
4886 struct device *dev = ud->dev;
4887 struct udma_hwdesc *hwdesc;
4888 size_t tr_size;
4889
4890 /* Allocate 1K buffer for discarded data on RX channel teardown */
4891 rx_flush->buffer_size = SZ_1K;
4892 rx_flush->buffer_vaddr = devm_kzalloc(dev, rx_flush->buffer_size,
4893 GFP_KERNEL);
4894 if (!rx_flush->buffer_vaddr)
4895 return -ENOMEM;
4896
4897 rx_flush->buffer_paddr = dma_map_single(dev, rx_flush->buffer_vaddr,
4898 rx_flush->buffer_size,
4899 DMA_TO_DEVICE);
4900 if (dma_mapping_error(dev, rx_flush->buffer_paddr))
4901 return -ENOMEM;
4902
4903 /* Set up descriptor to be used for TR mode */
4904 hwdesc = &rx_flush->hwdescs[0];
4905 tr_size = sizeof(struct cppi5_tr_type1_t);
4906 hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, 1);
4907 hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size,
4908 ud->desc_align);
4909
4910 hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size,
4911 GFP_KERNEL);
4912 if (!hwdesc->cppi5_desc_vaddr)
4913 return -ENOMEM;
4914
4915 hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr,
4916 hwdesc->cppi5_desc_size,
4917 DMA_TO_DEVICE);
4918 if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr))
4919 return -ENOMEM;
4920
4921 /* Start of the TR req records */
4922 hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size;
4923 /* Start address of the TR response array */
4924 hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size;
4925
4926 tr_desc = hwdesc->cppi5_desc_vaddr;
4927 cppi5_trdesc_init(tr_desc, 1, tr_size, 0, 0);
4928 cppi5_desc_set_pktids(tr_desc, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT);
4929 cppi5_desc_set_retpolicy(tr_desc, 0, 0);
4930
4931 tr_req = hwdesc->tr_req_base;
4932 cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false,
4933 CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
4934 cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT);
4935
4936 tr_req->addr = rx_flush->buffer_paddr;
4937 tr_req->icnt0 = rx_flush->buffer_size;
4938 tr_req->icnt1 = 1;
4939
4940 dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr,
4941 hwdesc->cppi5_desc_size, DMA_TO_DEVICE);
4942
4943 /* Set up descriptor to be used for packet mode */
4944 hwdesc = &rx_flush->hwdescs[1];
4945 hwdesc->cppi5_desc_size = ALIGN(sizeof(struct cppi5_host_desc_t) +
4946 CPPI5_INFO0_HDESC_EPIB_SIZE +
4947 CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE,
4948 ud->desc_align);
4949
4950 hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size,
4951 GFP_KERNEL);
4952 if (!hwdesc->cppi5_desc_vaddr)
4953 return -ENOMEM;
4954
4955 hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr,
4956 hwdesc->cppi5_desc_size,
4957 DMA_TO_DEVICE);
4958 if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr))
4959 return -ENOMEM;
4960
4961 desc = hwdesc->cppi5_desc_vaddr;
4962 cppi5_hdesc_init(desc, 0, 0);
4963 cppi5_desc_set_pktids(&desc->hdr, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT);
4964 cppi5_desc_set_retpolicy(&desc->hdr, 0, 0);
4965
4966 cppi5_hdesc_attach_buf(desc,
4967 rx_flush->buffer_paddr, rx_flush->buffer_size,
4968 rx_flush->buffer_paddr, rx_flush->buffer_size);
4969
4970 dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr,
4971 hwdesc->cppi5_desc_size, DMA_TO_DEVICE);
4972 return 0;
4973 }
4974
4975 #ifdef CONFIG_DEBUG_FS
4976 static void udma_dbg_summary_show_chan(struct seq_file *s,
4977 struct dma_chan *chan)
4978 {
4979 struct udma_chan *uc = to_udma_chan(chan);
4980 struct udma_chan_config *ucc = &uc->config;
4981
4982 seq_printf(s, " %-13s| %s", dma_chan_name(chan),
4983 chan->dbg_client_name ?: "in-use");
4984 if (ucc->tr_trigger_type)
4985 seq_puts(s, " (triggered, ");
4986 else
4987 seq_printf(s, " (%s, ",
4988 dmaengine_get_direction_text(uc->config.dir));
4989
4990 switch (uc->config.dir) {
4991 case DMA_MEM_TO_MEM:
4992 if (uc->ud->match_data->type == DMA_TYPE_BCDMA) {
4993 seq_printf(s, "bchan%d)\n", uc->bchan->id);
4994 return;
4995 }
4996
4997 seq_printf(s, "chan%d pair [0x%04x -> 0x%04x], ", uc->tchan->id,
4998 ucc->src_thread, ucc->dst_thread);
4999 break;
5000 case DMA_DEV_TO_MEM:
5001 seq_printf(s, "rchan%d [0x%04x -> 0x%04x], ", uc->rchan->id,
5002 ucc->src_thread, ucc->dst_thread);
5003 if (uc->ud->match_data->type == DMA_TYPE_PKTDMA)
5004 seq_printf(s, "rflow%d, ", uc->rflow->id);
5005 break;
5006 case DMA_MEM_TO_DEV:
5007 seq_printf(s, "tchan%d [0x%04x -> 0x%04x], ", uc->tchan->id,
5008 ucc->src_thread, ucc->dst_thread);
5009 if (uc->ud->match_data->type == DMA_TYPE_PKTDMA)
5010 seq_printf(s, "tflow%d, ", uc->tchan->tflow_id);
5011 break;
5012 default:
5013 seq_printf(s, ")\n");
5014 return;
5015 }
5016
5017 if (ucc->ep_type == PSIL_EP_NATIVE) {
5018 seq_printf(s, "PSI-L Native");
5019 if (ucc->metadata_size) {
5020 seq_printf(s, "[%s", ucc->needs_epib ? " EPIB" : "");
5021 if (ucc->psd_size)
5022 seq_printf(s, " PSDsize:%u", ucc->psd_size);
5023 seq_printf(s, " ]");
5024 }
5025 } else {
5026 seq_printf(s, "PDMA");
5027 if (ucc->enable_acc32 || ucc->enable_burst)
5028 seq_printf(s, "[%s%s ]",
5029 ucc->enable_acc32 ? " ACC32" : "",
5030 ucc->enable_burst ? " BURST" : "");
5031 }
5032
5033 seq_printf(s, ", %s)\n", ucc->pkt_mode ? "Packet mode" : "TR mode");
5034 }
5035
5036 static void udma_dbg_summary_show(struct seq_file *s,
5037 struct dma_device *dma_dev)
5038 {
5039 struct dma_chan *chan;
5040
5041 list_for_each_entry(chan, &dma_dev->channels, device_node) {
5042 if (chan->client_count)
5043 udma_dbg_summary_show_chan(s, chan);
5044 }
5045 }
5046 #endif /* CONFIG_DEBUG_FS */
5047
5048 #define TI_UDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
5049 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
5050 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
5051 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
5052 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
5053
5054 static int udma_probe(struct platform_device *pdev)
5055 {
5056 struct device_node *navss_node = pdev->dev.parent->of_node;
5057 const struct soc_device_attribute *soc;
5058 struct device *dev = &pdev->dev;
5059 struct udma_dev *ud;
5060 const struct of_device_id *match;
5061 int i, ret;
5062 int ch_count;
5063
5064 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(48));
5065 if (ret)
5066 dev_err(dev, "failed to set dma mask stuff\n");
5067
5068 ud = devm_kzalloc(dev, sizeof(*ud), GFP_KERNEL);
5069 if (!ud)
5070 return -ENOMEM;
5071
5072 match = of_match_node(udma_of_match, dev->of_node);
5073 if (!match)
5074 match = of_match_node(bcdma_of_match, dev->of_node);
5075 if (!match) {
5076 match = of_match_node(pktdma_of_match, dev->of_node);
5077 if (!match) {
5078 dev_err(dev, "No compatible match found\n");
5079 return -ENODEV;
5080 }
5081 }
5082 ud->match_data = match->data;
5083
5084 soc = soc_device_match(k3_soc_devices);
5085 if (!soc) {
5086 dev_err(dev, "No compatible SoC found\n");
5087 return -ENODEV;
5088 }
5089 ud->soc_data = soc->data;
5090
5091 ret = udma_get_mmrs(pdev, ud);
5092 if (ret)
5093 return ret;
5094
5095 ud->tisci_rm.tisci = ti_sci_get_by_phandle(dev->of_node, "ti,sci");
5096 if (IS_ERR(ud->tisci_rm.tisci))
5097 return PTR_ERR(ud->tisci_rm.tisci);
5098
5099 ret = of_property_read_u32(dev->of_node, "ti,sci-dev-id",
5100 &ud->tisci_rm.tisci_dev_id);
5101 if (ret) {
5102 dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
5103 return ret;
5104 }
5105 pdev->id = ud->tisci_rm.tisci_dev_id;
5106
5107 ret = of_property_read_u32(navss_node, "ti,sci-dev-id",
5108 &ud->tisci_rm.tisci_navss_dev_id);
5109 if (ret) {
5110 dev_err(dev, "NAVSS ti,sci-dev-id read failure %d\n", ret);
5111 return ret;
5112 }
5113
5114 if (ud->match_data->type == DMA_TYPE_UDMA) {
5115 ret = of_property_read_u32(dev->of_node, "ti,udma-atype",
5116 &ud->atype);
5117 if (!ret && ud->atype > 2) {
5118 dev_err(dev, "Invalid atype: %u\n", ud->atype);
5119 return -EINVAL;
5120 }
5121 } else {
5122 ret = of_property_read_u32(dev->of_node, "ti,asel",
5123 &ud->asel);
5124 if (!ret && ud->asel > 15) {
5125 dev_err(dev, "Invalid asel: %u\n", ud->asel);
5126 return -EINVAL;
5127 }
5128 }
5129
5130 ud->tisci_rm.tisci_udmap_ops = &ud->tisci_rm.tisci->ops.rm_udmap_ops;
5131 ud->tisci_rm.tisci_psil_ops = &ud->tisci_rm.tisci->ops.rm_psil_ops;
5132
5133 if (ud->match_data->type == DMA_TYPE_UDMA) {
5134 ud->ringacc = of_k3_ringacc_get_by_phandle(dev->of_node, "ti,ringacc");
5135 } else {
5136 struct k3_ringacc_init_data ring_init_data;
5137
5138 ring_init_data.tisci = ud->tisci_rm.tisci;
5139 ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id;
5140 if (ud->match_data->type == DMA_TYPE_BCDMA) {
5141 ring_init_data.num_rings = ud->bchan_cnt +
5142 ud->tchan_cnt +
5143 ud->rchan_cnt;
5144 } else {
5145 ring_init_data.num_rings = ud->rflow_cnt +
5146 ud->tflow_cnt;
5147 }
5148
5149 ud->ringacc = k3_ringacc_dmarings_init(pdev, &ring_init_data);
5150 }
5151
5152 if (IS_ERR(ud->ringacc))
5153 return PTR_ERR(ud->ringacc);
5154
5155 dev->msi_domain = of_msi_get_domain(dev, dev->of_node,
5156 DOMAIN_BUS_TI_SCI_INTA_MSI);
5157 if (!dev->msi_domain) {
5158 dev_err(dev, "Failed to get MSI domain\n");
5159 return -EPROBE_DEFER;
5160 }
5161
5162 dma_cap_set(DMA_SLAVE, ud->ddev.cap_mask);
5163 /* cyclic operation is not supported via PKTDMA */
5164 if (ud->match_data->type != DMA_TYPE_PKTDMA) {
5165 dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask);
5166 ud->ddev.device_prep_dma_cyclic = udma_prep_dma_cyclic;
5167 }
5168
5169 ud->ddev.device_config = udma_slave_config;
5170 ud->ddev.device_prep_slave_sg = udma_prep_slave_sg;
5171 ud->ddev.device_issue_pending = udma_issue_pending;
5172 ud->ddev.device_tx_status = udma_tx_status;
5173 ud->ddev.device_pause = udma_pause;
5174 ud->ddev.device_resume = udma_resume;
5175 ud->ddev.device_terminate_all = udma_terminate_all;
5176 ud->ddev.device_synchronize = udma_synchronize;
5177 #ifdef CONFIG_DEBUG_FS
5178 ud->ddev.dbg_summary_show = udma_dbg_summary_show;
5179 #endif
5180
5181 switch (ud->match_data->type) {
5182 case DMA_TYPE_UDMA:
5183 ud->ddev.device_alloc_chan_resources =
5184 udma_alloc_chan_resources;
5185 break;
5186 case DMA_TYPE_BCDMA:
5187 ud->ddev.device_alloc_chan_resources =
5188 bcdma_alloc_chan_resources;
5189 ud->ddev.device_router_config = bcdma_router_config;
5190 break;
5191 case DMA_TYPE_PKTDMA:
5192 ud->ddev.device_alloc_chan_resources =
5193 pktdma_alloc_chan_resources;
5194 break;
5195 default:
5196 return -EINVAL;
5197 }
5198 ud->ddev.device_free_chan_resources = udma_free_chan_resources;
5199
5200 ud->ddev.src_addr_widths = TI_UDMAC_BUSWIDTHS;
5201 ud->ddev.dst_addr_widths = TI_UDMAC_BUSWIDTHS;
5202 ud->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
5203 ud->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
5204 ud->ddev.copy_align = DMAENGINE_ALIGN_8_BYTES;
5205 ud->ddev.desc_metadata_modes = DESC_METADATA_CLIENT |
5206 DESC_METADATA_ENGINE;
5207 if (ud->match_data->enable_memcpy_support &&
5208 !(ud->match_data->type == DMA_TYPE_BCDMA && ud->bchan_cnt == 0)) {
5209 dma_cap_set(DMA_MEMCPY, ud->ddev.cap_mask);
5210 ud->ddev.device_prep_dma_memcpy = udma_prep_dma_memcpy;
5211 ud->ddev.directions |= BIT(DMA_MEM_TO_MEM);
5212 }
5213
5214 ud->ddev.dev = dev;
5215 ud->dev = dev;
5216 ud->psil_base = ud->match_data->psil_base;
5217
5218 INIT_LIST_HEAD(&ud->ddev.channels);
5219 INIT_LIST_HEAD(&ud->desc_to_purge);
5220
5221 ch_count = setup_resources(ud);
5222 if (ch_count <= 0)
5223 return ch_count;
5224
5225 spin_lock_init(&ud->lock);
5226 INIT_WORK(&ud->purge_work, udma_purge_desc_work);
5227
5228 ud->desc_align = 64;
5229 if (ud->desc_align < dma_get_cache_alignment())
5230 ud->desc_align = dma_get_cache_alignment();
5231
5232 ret = udma_setup_rx_flush(ud);
5233 if (ret)
5234 return ret;
5235
5236 for (i = 0; i < ud->bchan_cnt; i++) {
5237 struct udma_bchan *bchan = &ud->bchans[i];
5238
5239 bchan->id = i;
5240 bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000;
5241 }
5242
5243 for (i = 0; i < ud->tchan_cnt; i++) {
5244 struct udma_tchan *tchan = &ud->tchans[i];
5245
5246 tchan->id = i;
5247 tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + i * 0x1000;
5248 }
5249
5250 for (i = 0; i < ud->rchan_cnt; i++) {
5251 struct udma_rchan *rchan = &ud->rchans[i];
5252
5253 rchan->id = i;
5254 rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + i * 0x1000;
5255 }
5256
5257 for (i = 0; i < ud->rflow_cnt; i++) {
5258 struct udma_rflow *rflow = &ud->rflows[i];
5259
5260 rflow->id = i;
5261 }
5262
5263 for (i = 0; i < ch_count; i++) {
5264 struct udma_chan *uc = &ud->channels[i];
5265
5266 uc->ud = ud;
5267 uc->vc.desc_free = udma_desc_free;
5268 uc->id = i;
5269 uc->bchan = NULL;
5270 uc->tchan = NULL;
5271 uc->rchan = NULL;
5272 uc->config.remote_thread_id = -1;
5273 uc->config.mapped_channel_id = -1;
5274 uc->config.default_flow_id = -1;
5275 uc->config.dir = DMA_MEM_TO_MEM;
5276 uc->name = devm_kasprintf(dev, GFP_KERNEL, "%s chan%d",
5277 dev_name(dev), i);
5278
5279 vchan_init(&uc->vc, &ud->ddev);
5280 /* Use custom vchan completion handling */
5281 tasklet_setup(&uc->vc.task, udma_vchan_complete);
5282 init_completion(&uc->teardown_completed);
5283 INIT_DELAYED_WORK(&uc->tx_drain.work, udma_check_tx_completion);
5284 }
5285
5286 ret = dma_async_device_register(&ud->ddev);
5287 if (ret) {
5288 dev_err(dev, "failed to register slave DMA engine: %d\n", ret);
5289 return ret;
5290 }
5291
5292 platform_set_drvdata(pdev, ud);
5293
5294 ret = of_dma_controller_register(dev->of_node, udma_of_xlate, ud);
5295 if (ret) {
5296 dev_err(dev, "failed to register of_dma controller\n");
5297 dma_async_device_unregister(&ud->ddev);
5298 }
5299
5300 return ret;
5301 }
5302
5303 static struct platform_driver udma_driver = {
5304 .driver = {
5305 .name = "ti-udma",
5306 .of_match_table = udma_of_match,
5307 .suppress_bind_attrs = true,
5308 },
5309 .probe = udma_probe,
5310 };
5311 builtin_platform_driver(udma_driver);
5312
5313 static struct platform_driver bcdma_driver = {
5314 .driver = {
5315 .name = "ti-bcdma",
5316 .of_match_table = bcdma_of_match,
5317 .suppress_bind_attrs = true,
5318 },
5319 .probe = udma_probe,
5320 };
5321 builtin_platform_driver(bcdma_driver);
5322
5323 static struct platform_driver pktdma_driver = {
5324 .driver = {
5325 .name = "ti-pktdma",
5326 .of_match_table = pktdma_of_match,
5327 .suppress_bind_attrs = true,
5328 },
5329 .probe = udma_probe,
5330 };
5331 builtin_platform_driver(pktdma_driver);
5332
5333 /* Private interfaces to UDMA */
5334 #include "k3-udma-private.c"
Linux with added FPC-III support