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Merge tag 'regmap-fix-v5.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / gpio / gpio-dwapb.c
blobd3233cc4b76b4966b140bd0c3cebc8485e74cb98
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2011 Jamie Iles
4 *
5 * All enquiries to support@picochip.com
6 */
7 #include <linux/acpi.h>
8 #include <linux/clk.h>
9 #include <linux/err.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/ioport.h>
15 #include <linux/irq.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_irq.h>
21 #include <linux/platform_device.h>
22 #include <linux/property.h>
23 #include <linux/reset.h>
24 #include <linux/spinlock.h>
25 #include <linux/platform_data/gpio-dwapb.h>
26 #include <linux/slab.h>
27
28 #include "gpiolib.h"
29 #include "gpiolib-acpi.h"
30
31 #define GPIO_SWPORTA_DR 0x00
32 #define GPIO_SWPORTA_DDR 0x04
33 #define GPIO_SWPORTB_DR 0x0c
34 #define GPIO_SWPORTB_DDR 0x10
35 #define GPIO_SWPORTC_DR 0x18
36 #define GPIO_SWPORTC_DDR 0x1c
37 #define GPIO_SWPORTD_DR 0x24
38 #define GPIO_SWPORTD_DDR 0x28
39 #define GPIO_INTEN 0x30
40 #define GPIO_INTMASK 0x34
41 #define GPIO_INTTYPE_LEVEL 0x38
42 #define GPIO_INT_POLARITY 0x3c
43 #define GPIO_INTSTATUS 0x40
44 #define GPIO_PORTA_DEBOUNCE 0x48
45 #define GPIO_PORTA_EOI 0x4c
46 #define GPIO_EXT_PORTA 0x50
47 #define GPIO_EXT_PORTB 0x54
48 #define GPIO_EXT_PORTC 0x58
49 #define GPIO_EXT_PORTD 0x5c
50
51 #define DWAPB_DRIVER_NAME "gpio-dwapb"
52 #define DWAPB_MAX_PORTS 4
53
54 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
55 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
56 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
57
58 #define GPIO_REG_OFFSET_V2 1
59
60 #define GPIO_INTMASK_V2 0x44
61 #define GPIO_INTTYPE_LEVEL_V2 0x34
62 #define GPIO_INT_POLARITY_V2 0x38
63 #define GPIO_INTSTATUS_V2 0x3c
64 #define GPIO_PORTA_EOI_V2 0x40
65
66 #define DWAPB_NR_CLOCKS 2
67
68 struct dwapb_gpio;
69
70 #ifdef CONFIG_PM_SLEEP
71 /* Store GPIO context across system-wide suspend/resume transitions */
72 struct dwapb_context {
73 u32 data;
74 u32 dir;
75 u32 ext;
76 u32 int_en;
77 u32 int_mask;
78 u32 int_type;
79 u32 int_pol;
80 u32 int_deb;
81 u32 wake_en;
82 };
83 #endif
84
85 struct dwapb_gpio_port_irqchip {
86 struct irq_chip irqchip;
87 unsigned int nr_irqs;
88 unsigned int irq[DWAPB_MAX_GPIOS];
89 };
90
91 struct dwapb_gpio_port {
92 struct gpio_chip gc;
93 struct dwapb_gpio_port_irqchip *pirq;
94 struct dwapb_gpio *gpio;
95 #ifdef CONFIG_PM_SLEEP
96 struct dwapb_context *ctx;
97 #endif
98 unsigned int idx;
99 };
100 #define to_dwapb_gpio(_gc) \
101 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
102
103 struct dwapb_gpio {
104 struct device *dev;
105 void __iomem *regs;
106 struct dwapb_gpio_port *ports;
107 unsigned int nr_ports;
108 unsigned int flags;
109 struct reset_control *rst;
110 struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
111 };
112
113 static inline u32 gpio_reg_v2_convert(unsigned int offset)
114 {
115 switch (offset) {
116 case GPIO_INTMASK:
117 return GPIO_INTMASK_V2;
118 case GPIO_INTTYPE_LEVEL:
119 return GPIO_INTTYPE_LEVEL_V2;
120 case GPIO_INT_POLARITY:
121 return GPIO_INT_POLARITY_V2;
122 case GPIO_INTSTATUS:
123 return GPIO_INTSTATUS_V2;
124 case GPIO_PORTA_EOI:
125 return GPIO_PORTA_EOI_V2;
126 }
127
128 return offset;
129 }
130
131 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
132 {
133 if (gpio->flags & GPIO_REG_OFFSET_V2)
134 return gpio_reg_v2_convert(offset);
135
136 return offset;
137 }
138
139 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
140 {
141 struct gpio_chip *gc = &gpio->ports[0].gc;
142 void __iomem *reg_base = gpio->regs;
143
144 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
145 }
146
147 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
148 u32 val)
149 {
150 struct gpio_chip *gc = &gpio->ports[0].gc;
151 void __iomem *reg_base = gpio->regs;
152
153 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
154 }
155
156 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
157 {
158 struct dwapb_gpio_port *port;
159 int i;
160
161 for (i = 0; i < gpio->nr_ports; i++) {
162 port = &gpio->ports[i];
163 if (port->idx == offs / DWAPB_MAX_GPIOS)
164 return port;
165 }
166
167 return NULL;
168 }
169
170 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
171 {
172 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
173 struct gpio_chip *gc;
174 u32 pol;
175 int val;
176
177 if (!port)
178 return;
179 gc = &port->gc;
180
181 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
182 /* Just read the current value right out of the data register */
183 val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
184 if (val)
185 pol &= ~BIT(offs);
186 else
187 pol |= BIT(offs);
188
189 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
190 }
191
192 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
193 {
194 struct gpio_chip *gc = &gpio->ports[0].gc;
195 unsigned long irq_status;
196 irq_hw_number_t hwirq;
197
198 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
199 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
200 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);
201 u32 irq_type = irq_get_trigger_type(gpio_irq);
202
203 generic_handle_irq(gpio_irq);
204
205 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
206 dwapb_toggle_trigger(gpio, hwirq);
207 }
208
209 return irq_status;
210 }
211
212 static void dwapb_irq_handler(struct irq_desc *desc)
213 {
214 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
215 struct irq_chip *chip = irq_desc_get_chip(desc);
216
217 chained_irq_enter(chip, desc);
218 dwapb_do_irq(gpio);
219 chained_irq_exit(chip, desc);
220 }
221
222 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
223 {
224 return IRQ_RETVAL(dwapb_do_irq(dev_id));
225 }
226
227 static void dwapb_irq_ack(struct irq_data *d)
228 {
229 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
230 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
231 u32 val = BIT(irqd_to_hwirq(d));
232 unsigned long flags;
233
234 spin_lock_irqsave(&gc->bgpio_lock, flags);
235 dwapb_write(gpio, GPIO_PORTA_EOI, val);
236 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
237 }
238
239 static void dwapb_irq_mask(struct irq_data *d)
240 {
241 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
242 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
243 unsigned long flags;
244 u32 val;
245
246 spin_lock_irqsave(&gc->bgpio_lock, flags);
247 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d));
248 dwapb_write(gpio, GPIO_INTMASK, val);
249 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
250 }
251
252 static void dwapb_irq_unmask(struct irq_data *d)
253 {
254 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
255 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
256 unsigned long flags;
257 u32 val;
258
259 spin_lock_irqsave(&gc->bgpio_lock, flags);
260 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d));
261 dwapb_write(gpio, GPIO_INTMASK, val);
262 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
263 }
264
265 static void dwapb_irq_enable(struct irq_data *d)
266 {
267 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
268 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
269 unsigned long flags;
270 u32 val;
271
272 spin_lock_irqsave(&gc->bgpio_lock, flags);
273 val = dwapb_read(gpio, GPIO_INTEN);
274 val |= BIT(irqd_to_hwirq(d));
275 dwapb_write(gpio, GPIO_INTEN, val);
276 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
277 }
278
279 static void dwapb_irq_disable(struct irq_data *d)
280 {
281 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
282 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
283 unsigned long flags;
284 u32 val;
285
286 spin_lock_irqsave(&gc->bgpio_lock, flags);
287 val = dwapb_read(gpio, GPIO_INTEN);
288 val &= ~BIT(irqd_to_hwirq(d));
289 dwapb_write(gpio, GPIO_INTEN, val);
290 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
291 }
292
293 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
294 {
295 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
296 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
297 irq_hw_number_t bit = irqd_to_hwirq(d);
298 unsigned long level, polarity, flags;
299
300 if (type & ~IRQ_TYPE_SENSE_MASK)
301 return -EINVAL;
302
303 spin_lock_irqsave(&gc->bgpio_lock, flags);
304 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
305 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
306
307 switch (type) {
308 case IRQ_TYPE_EDGE_BOTH:
309 level |= BIT(bit);
310 dwapb_toggle_trigger(gpio, bit);
311 break;
312 case IRQ_TYPE_EDGE_RISING:
313 level |= BIT(bit);
314 polarity |= BIT(bit);
315 break;
316 case IRQ_TYPE_EDGE_FALLING:
317 level |= BIT(bit);
318 polarity &= ~BIT(bit);
319 break;
320 case IRQ_TYPE_LEVEL_HIGH:
321 level &= ~BIT(bit);
322 polarity |= BIT(bit);
323 break;
324 case IRQ_TYPE_LEVEL_LOW:
325 level &= ~BIT(bit);
326 polarity &= ~BIT(bit);
327 break;
328 }
329
330 if (type & IRQ_TYPE_LEVEL_MASK)
331 irq_set_handler_locked(d, handle_level_irq);
332 else if (type & IRQ_TYPE_EDGE_BOTH)
333 irq_set_handler_locked(d, handle_edge_irq);
334
335 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
336 if (type != IRQ_TYPE_EDGE_BOTH)
337 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
338 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
339
340 return 0;
341 }
342
343 #ifdef CONFIG_PM_SLEEP
344 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
345 {
346 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
347 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
348 struct dwapb_context *ctx = gpio->ports[0].ctx;
349 irq_hw_number_t bit = irqd_to_hwirq(d);
350
351 if (enable)
352 ctx->wake_en |= BIT(bit);
353 else
354 ctx->wake_en &= ~BIT(bit);
355
356 return 0;
357 }
358 #endif
359
360 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
361 unsigned offset, unsigned debounce)
362 {
363 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
364 struct dwapb_gpio *gpio = port->gpio;
365 unsigned long flags, val_deb;
366 unsigned long mask = BIT(offset);
367
368 spin_lock_irqsave(&gc->bgpio_lock, flags);
369
370 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
371 if (debounce)
372 val_deb |= mask;
373 else
374 val_deb &= ~mask;
375 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
376
377 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
378
379 return 0;
380 }
381
382 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
383 unsigned long config)
384 {
385 u32 debounce;
386
387 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
388 return -ENOTSUPP;
389
390 debounce = pinconf_to_config_argument(config);
391 return dwapb_gpio_set_debounce(gc, offset, debounce);
392 }
393
394 static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
395 struct dwapb_port_property *pp)
396 {
397 int i;
398
399 /* Group all available IRQs into an array of parental IRQs. */
400 for (i = 0; i < pp->ngpio; ++i) {
401 if (!pp->irq[i])
402 continue;
403
404 pirq->irq[pirq->nr_irqs++] = pp->irq[i];
405 }
406
407 return pirq->nr_irqs ? 0 : -ENOENT;
408 }
409
410 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
411 struct dwapb_gpio_port *port,
412 struct dwapb_port_property *pp)
413 {
414 struct dwapb_gpio_port_irqchip *pirq;
415 struct gpio_chip *gc = &port->gc;
416 struct gpio_irq_chip *girq;
417 int err;
418
419 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
420 if (!pirq)
421 return;
422
423 if (dwapb_convert_irqs(pirq, pp)) {
424 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
425 goto err_kfree_pirq;
426 }
427
428 girq = &gc->irq;
429 girq->handler = handle_bad_irq;
430 girq->default_type = IRQ_TYPE_NONE;
431
432 port->pirq = pirq;
433 pirq->irqchip.name = DWAPB_DRIVER_NAME;
434 pirq->irqchip.irq_ack = dwapb_irq_ack;
435 pirq->irqchip.irq_mask = dwapb_irq_mask;
436 pirq->irqchip.irq_unmask = dwapb_irq_unmask;
437 pirq->irqchip.irq_set_type = dwapb_irq_set_type;
438 pirq->irqchip.irq_enable = dwapb_irq_enable;
439 pirq->irqchip.irq_disable = dwapb_irq_disable;
440 #ifdef CONFIG_PM_SLEEP
441 pirq->irqchip.irq_set_wake = dwapb_irq_set_wake;
442 #endif
443
444 if (!pp->irq_shared) {
445 girq->num_parents = pirq->nr_irqs;
446 girq->parents = pirq->irq;
447 girq->parent_handler_data = gpio;
448 girq->parent_handler = dwapb_irq_handler;
449 } else {
450 /* This will let us handle the parent IRQ in the driver */
451 girq->num_parents = 0;
452 girq->parents = NULL;
453 girq->parent_handler = NULL;
454
455 /*
456 * Request a shared IRQ since where MFD would have devices
457 * using the same irq pin
458 */
459 err = devm_request_irq(gpio->dev, pp->irq[0],
460 dwapb_irq_handler_mfd,
461 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
462 if (err) {
463 dev_err(gpio->dev, "error requesting IRQ\n");
464 goto err_kfree_pirq;
465 }
466 }
467
468 girq->chip = &pirq->irqchip;
469
470 return;
471
472 err_kfree_pirq:
473 devm_kfree(gpio->dev, pirq);
474 }
475
476 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
477 struct dwapb_port_property *pp,
478 unsigned int offs)
479 {
480 struct dwapb_gpio_port *port;
481 void __iomem *dat, *set, *dirout;
482 int err;
483
484 port = &gpio->ports[offs];
485 port->gpio = gpio;
486 port->idx = pp->idx;
487
488 #ifdef CONFIG_PM_SLEEP
489 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
490 if (!port->ctx)
491 return -ENOMEM;
492 #endif
493
494 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
495 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
496 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
497
498 /* This registers 32 GPIO lines per port */
499 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
500 NULL, 0);
501 if (err) {
502 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
503 port->idx);
504 return err;
505 }
506
507 #ifdef CONFIG_OF_GPIO
508 port->gc.of_node = to_of_node(pp->fwnode);
509 #endif
510 port->gc.ngpio = pp->ngpio;
511 port->gc.base = pp->gpio_base;
512
513 /* Only port A support debounce */
514 if (pp->idx == 0)
515 port->gc.set_config = dwapb_gpio_set_config;
516
517 /* Only port A can provide interrupts in all configurations of the IP */
518 if (pp->idx == 0)
519 dwapb_configure_irqs(gpio, port, pp);
520
521 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
522 if (err) {
523 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
524 port->idx);
525 return err;
526 }
527
528 return 0;
529 }
530
531 static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
532 struct dwapb_port_property *pp)
533 {
534 struct device_node *np = NULL;
535 int irq = -ENXIO, j;
536
537 if (fwnode_property_read_bool(fwnode, "interrupt-controller"))
538 np = to_of_node(fwnode);
539
540 for (j = 0; j < pp->ngpio; j++) {
541 if (np)
542 irq = of_irq_get(np, j);
543 else if (has_acpi_companion(dev))
544 irq = platform_get_irq_optional(to_platform_device(dev), j);
545 if (irq > 0)
546 pp->irq[j] = irq;
547 }
548 }
549
550 static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
551 {
552 struct fwnode_handle *fwnode;
553 struct dwapb_platform_data *pdata;
554 struct dwapb_port_property *pp;
555 int nports;
556 int i;
557
558 nports = device_get_child_node_count(dev);
559 if (nports == 0)
560 return ERR_PTR(-ENODEV);
561
562 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
563 if (!pdata)
564 return ERR_PTR(-ENOMEM);
565
566 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
567 if (!pdata->properties)
568 return ERR_PTR(-ENOMEM);
569
570 pdata->nports = nports;
571
572 i = 0;
573 device_for_each_child_node(dev, fwnode) {
574 pp = &pdata->properties[i++];
575 pp->fwnode = fwnode;
576
577 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
578 pp->idx >= DWAPB_MAX_PORTS) {
579 dev_err(dev,
580 "missing/invalid port index for port%d\n", i);
581 fwnode_handle_put(fwnode);
582 return ERR_PTR(-EINVAL);
583 }
584
585 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
586 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
587 dev_info(dev,
588 "failed to get number of gpios for port%d\n",
589 i);
590 pp->ngpio = DWAPB_MAX_GPIOS;
591 }
592
593 pp->irq_shared = false;
594 pp->gpio_base = -1;
595
596 /*
597 * Only port A can provide interrupts in all configurations of
598 * the IP.
599 */
600 if (pp->idx == 0)
601 dwapb_get_irq(dev, fwnode, pp);
602 }
603
604 return pdata;
605 }
606
607 static void dwapb_assert_reset(void *data)
608 {
609 struct dwapb_gpio *gpio = data;
610
611 reset_control_assert(gpio->rst);
612 }
613
614 static int dwapb_get_reset(struct dwapb_gpio *gpio)
615 {
616 int err;
617
618 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
619 if (IS_ERR(gpio->rst))
620 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
621 "Cannot get reset descriptor\n");
622
623 err = reset_control_deassert(gpio->rst);
624 if (err) {
625 dev_err(gpio->dev, "Cannot deassert reset lane\n");
626 return err;
627 }
628
629 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
630 }
631
632 static void dwapb_disable_clks(void *data)
633 {
634 struct dwapb_gpio *gpio = data;
635
636 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
637 }
638
639 static int dwapb_get_clks(struct dwapb_gpio *gpio)
640 {
641 int err;
642
643 /* Optional bus and debounce clocks */
644 gpio->clks[0].id = "bus";
645 gpio->clks[1].id = "db";
646 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
647 gpio->clks);
648 if (err) {
649 dev_err(gpio->dev, "Cannot get APB/Debounce clocks\n");
650 return err;
651 }
652
653 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
654 if (err) {
655 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
656 return err;
657 }
658
659 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
660 }
661
662 static const struct of_device_id dwapb_of_match[] = {
663 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
664 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
665 { /* Sentinel */ }
666 };
667 MODULE_DEVICE_TABLE(of, dwapb_of_match);
668
669 static const struct acpi_device_id dwapb_acpi_match[] = {
670 {"HISI0181", 0},
671 {"APMC0D07", 0},
672 {"APMC0D81", GPIO_REG_OFFSET_V2},
673 { }
674 };
675 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
676
677 static int dwapb_gpio_probe(struct platform_device *pdev)
678 {
679 unsigned int i;
680 struct dwapb_gpio *gpio;
681 int err;
682 struct device *dev = &pdev->dev;
683 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
684
685 if (!pdata) {
686 pdata = dwapb_gpio_get_pdata(dev);
687 if (IS_ERR(pdata))
688 return PTR_ERR(pdata);
689 }
690
691 if (!pdata->nports)
692 return -ENODEV;
693
694 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
695 if (!gpio)
696 return -ENOMEM;
697
698 gpio->dev = &pdev->dev;
699 gpio->nr_ports = pdata->nports;
700
701 err = dwapb_get_reset(gpio);
702 if (err)
703 return err;
704
705 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
706 sizeof(*gpio->ports), GFP_KERNEL);
707 if (!gpio->ports)
708 return -ENOMEM;
709
710 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
711 if (IS_ERR(gpio->regs))
712 return PTR_ERR(gpio->regs);
713
714 err = dwapb_get_clks(gpio);
715 if (err)
716 return err;
717
718 gpio->flags = (uintptr_t)device_get_match_data(dev);
719
720 for (i = 0; i < gpio->nr_ports; i++) {
721 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
722 if (err)
723 return err;
724 }
725
726 platform_set_drvdata(pdev, gpio);
727
728 return 0;
729 }
730
731 #ifdef CONFIG_PM_SLEEP
732 static int dwapb_gpio_suspend(struct device *dev)
733 {
734 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
735 struct gpio_chip *gc = &gpio->ports[0].gc;
736 unsigned long flags;
737 int i;
738
739 spin_lock_irqsave(&gc->bgpio_lock, flags);
740 for (i = 0; i < gpio->nr_ports; i++) {
741 unsigned int offset;
742 unsigned int idx = gpio->ports[i].idx;
743 struct dwapb_context *ctx = gpio->ports[i].ctx;
744
745 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
746 ctx->dir = dwapb_read(gpio, offset);
747
748 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
749 ctx->data = dwapb_read(gpio, offset);
750
751 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
752 ctx->ext = dwapb_read(gpio, offset);
753
754 /* Only port A can provide interrupts */
755 if (idx == 0) {
756 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
757 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
758 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
759 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
760 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
761
762 /* Mask out interrupts */
763 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
764 }
765 }
766 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
767
768 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
769
770 return 0;
771 }
772
773 static int dwapb_gpio_resume(struct device *dev)
774 {
775 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
776 struct gpio_chip *gc = &gpio->ports[0].gc;
777 unsigned long flags;
778 int i, err;
779
780 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
781 if (err) {
782 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
783 return err;
784 }
785
786 spin_lock_irqsave(&gc->bgpio_lock, flags);
787 for (i = 0; i < gpio->nr_ports; i++) {
788 unsigned int offset;
789 unsigned int idx = gpio->ports[i].idx;
790 struct dwapb_context *ctx = gpio->ports[i].ctx;
791
792 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
793 dwapb_write(gpio, offset, ctx->data);
794
795 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
796 dwapb_write(gpio, offset, ctx->dir);
797
798 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
799 dwapb_write(gpio, offset, ctx->ext);
800
801 /* Only port A can provide interrupts */
802 if (idx == 0) {
803 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
804 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
805 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
806 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
807 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
808
809 /* Clear out spurious interrupts */
810 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
811 }
812 }
813 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
814
815 return 0;
816 }
817 #endif
818
819 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
820 dwapb_gpio_resume);
821
822 static struct platform_driver dwapb_gpio_driver = {
823 .driver = {
824 .name = DWAPB_DRIVER_NAME,
825 .pm = &dwapb_gpio_pm_ops,
826 .of_match_table = dwapb_of_match,
827 .acpi_match_table = dwapb_acpi_match,
828 },
829 .probe = dwapb_gpio_probe,
830 };
831
832 module_platform_driver(dwapb_gpio_driver);
833
834 MODULE_LICENSE("GPL");
835 MODULE_AUTHOR("Jamie Iles");
836 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
837 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);
Linux with added FPC-III support