drivers/iio/adc/cc10001_adc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014-2015 Imagination Technologies Ltd.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/delay.h>
   8 #include <linux/err.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/regulator/consumer.h>
  15 #include <linux/slab.h>
  16
  17 #include <linux/iio/buffer.h>
  18 #include <linux/iio/iio.h>
  19 #include <linux/iio/sysfs.h>
  20 #include <linux/iio/trigger.h>
  21 #include <linux/iio/trigger_consumer.h>
  22 #include <linux/iio/triggered_buffer.h>
  23
  24 /* Registers */
  25 #define CC10001_ADC_CONFIG              0x00
  26 #define CC10001_ADC_START_CONV          BIT(4)
  27 #define CC10001_ADC_MODE_SINGLE_CONV    BIT(5)
  28
  29 #define CC10001_ADC_DDATA_OUT           0x04
  30 #define CC10001_ADC_EOC                 0x08
  31 #define CC10001_ADC_EOC_SET             BIT(0)
  32
  33 #define CC10001_ADC_CHSEL_SAMPLED       0x0c
  34 #define CC10001_ADC_POWER_DOWN          0x10
  35 #define CC10001_ADC_POWER_DOWN_SET      BIT(0)
  36
  37 #define CC10001_ADC_DEBUG               0x14
  38 #define CC10001_ADC_DATA_COUNT          0x20
  39
  40 #define CC10001_ADC_DATA_MASK           GENMASK(9, 0)
  41 #define CC10001_ADC_NUM_CHANNELS        8
  42 #define CC10001_ADC_CH_MASK             GENMASK(2, 0)
  43
  44 #define CC10001_INVALID_SAMPLED         0xffff
  45 #define CC10001_MAX_POLL_COUNT          20
  46
  47 /*
  48  * As per device specification, wait six clock cycles after power-up to
  49  * activate START. Since adding two more clock cycles delay does not
  50  * impact the performance too much, we are adding two additional cycles delay
  51  * intentionally here.
  52  */
  53 #define CC10001_WAIT_CYCLES             8
  54
  55 struct cc10001_adc_device {
  56         void __iomem *reg_base;
  57         struct clk *adc_clk;
  58         struct regulator *reg;
  59         u16 *buf;
  60
  61         bool shared;
  62         struct mutex lock;
  63         unsigned int start_delay_ns;
  64         unsigned int eoc_delay_ns;
  65 };
  66
  67 static inline void cc10001_adc_write_reg(struct cc10001_adc_device *adc_dev,
  68                                          u32 reg, u32 val)
  69 {
  70         writel(val, adc_dev->reg_base + reg);
  71 }
  72
  73 static inline u32 cc10001_adc_read_reg(struct cc10001_adc_device *adc_dev,
  74                                        u32 reg)
  75 {
  76         return readl(adc_dev->reg_base + reg);
  77 }
  78
  79 static void cc10001_adc_power_up(struct cc10001_adc_device *adc_dev)
  80 {
  81         cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN, 0);
  82         ndelay(adc_dev->start_delay_ns);
  83 }
  84
  85 static void cc10001_adc_power_down(struct cc10001_adc_device *adc_dev)
  86 {
  87         cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN,
  88                               CC10001_ADC_POWER_DOWN_SET);
  89 }
  90
  91 static void cc10001_adc_start(struct cc10001_adc_device *adc_dev,
  92                               unsigned int channel)
  93 {
  94         u32 val;
  95
  96         /* Channel selection and mode of operation */
  97         val = (channel & CC10001_ADC_CH_MASK) | CC10001_ADC_MODE_SINGLE_CONV;
  98         cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
  99
 100         udelay(1);
 101         val = cc10001_adc_read_reg(adc_dev, CC10001_ADC_CONFIG);
 102         val = val | CC10001_ADC_START_CONV;
 103         cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
 104 }
 105
 106 static u16 cc10001_adc_poll_done(struct iio_dev *indio_dev,
 107                                  unsigned int channel,
 108                                  unsigned int delay)
 109 {
 110         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 111         unsigned int poll_count = 0;
 112
 113         while (!(cc10001_adc_read_reg(adc_dev, CC10001_ADC_EOC) &
 114                         CC10001_ADC_EOC_SET)) {
 115
 116                 ndelay(delay);
 117                 if (poll_count++ == CC10001_MAX_POLL_COUNT)
 118                         return CC10001_INVALID_SAMPLED;
 119         }
 120
 121         poll_count = 0;
 122         while ((cc10001_adc_read_reg(adc_dev, CC10001_ADC_CHSEL_SAMPLED) &
 123                         CC10001_ADC_CH_MASK) != channel) {
 124
 125                 ndelay(delay);
 126                 if (poll_count++ == CC10001_MAX_POLL_COUNT)
 127                         return CC10001_INVALID_SAMPLED;
 128         }
 129
 130         /* Read the 10 bit output register */
 131         return cc10001_adc_read_reg(adc_dev, CC10001_ADC_DDATA_OUT) &
 132                                CC10001_ADC_DATA_MASK;
 133 }
 134
 135 static irqreturn_t cc10001_adc_trigger_h(int irq, void *p)
 136 {
 137         struct cc10001_adc_device *adc_dev;
 138         struct iio_poll_func *pf = p;
 139         struct iio_dev *indio_dev;
 140         unsigned int delay_ns;
 141         unsigned int channel;
 142         unsigned int scan_idx;
 143         bool sample_invalid;
 144         u16 *data;
 145         int i;
 146
 147         indio_dev = pf->indio_dev;
 148         adc_dev = iio_priv(indio_dev);
 149         data = adc_dev->buf;
 150
 151         mutex_lock(&adc_dev->lock);
 152
 153         if (!adc_dev->shared)
 154                 cc10001_adc_power_up(adc_dev);
 155
 156         /* Calculate delay step for eoc and sampled data */
 157         delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
 158
 159         i = 0;
 160         sample_invalid = false;
 161         for_each_set_bit(scan_idx, indio_dev->active_scan_mask,
 162                                   indio_dev->masklength) {
 163
 164                 channel = indio_dev->channels[scan_idx].channel;
 165                 cc10001_adc_start(adc_dev, channel);
 166
 167                 data[i] = cc10001_adc_poll_done(indio_dev, channel, delay_ns);
 168                 if (data[i] == CC10001_INVALID_SAMPLED) {
 169                         dev_warn(&indio_dev->dev,
 170                                  "invalid sample on channel %d\n", channel);
 171                         sample_invalid = true;
 172                         goto done;
 173                 }
 174                 i++;
 175         }
 176
 177 done:
 178         if (!adc_dev->shared)
 179                 cc10001_adc_power_down(adc_dev);
 180
 181         mutex_unlock(&adc_dev->lock);
 182
 183         if (!sample_invalid)
 184                 iio_push_to_buffers_with_timestamp(indio_dev, data,
 185                                                    iio_get_time_ns(indio_dev));
 186         iio_trigger_notify_done(indio_dev->trig);
 187
 188         return IRQ_HANDLED;
 189 }
 190
 191 static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev,
 192                                         struct iio_chan_spec const *chan)
 193 {
 194         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 195         unsigned int delay_ns;
 196         u16 val;
 197
 198         if (!adc_dev->shared)
 199                 cc10001_adc_power_up(adc_dev);
 200
 201         /* Calculate delay step for eoc and sampled data */
 202         delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
 203
 204         cc10001_adc_start(adc_dev, chan->channel);
 205
 206         val = cc10001_adc_poll_done(indio_dev, chan->channel, delay_ns);
 207
 208         if (!adc_dev->shared)
 209                 cc10001_adc_power_down(adc_dev);
 210
 211         return val;
 212 }
 213
 214 static int cc10001_adc_read_raw(struct iio_dev *indio_dev,
 215                                  struct iio_chan_spec const *chan,
 216                                  int *val, int *val2, long mask)
 217 {
 218         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 219         int ret;
 220
 221         switch (mask) {
 222         case IIO_CHAN_INFO_RAW:
 223                 if (iio_buffer_enabled(indio_dev))
 224                         return -EBUSY;
 225                 mutex_lock(&adc_dev->lock);
 226                 *val = cc10001_adc_read_raw_voltage(indio_dev, chan);
 227                 mutex_unlock(&adc_dev->lock);
 228
 229                 if (*val == CC10001_INVALID_SAMPLED)
 230                         return -EIO;
 231                 return IIO_VAL_INT;
 232
 233         case IIO_CHAN_INFO_SCALE:
 234                 ret = regulator_get_voltage(adc_dev->reg);
 235                 if (ret < 0)
 236                         return ret;
 237
 238                 *val = ret / 1000;
 239                 *val2 = chan->scan_type.realbits;
 240                 return IIO_VAL_FRACTIONAL_LOG2;
 241
 242         default:
 243                 return -EINVAL;
 244         }
 245 }
 246
 247 static int cc10001_update_scan_mode(struct iio_dev *indio_dev,
 248                                     const unsigned long *scan_mask)
 249 {
 250         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 251
 252         kfree(adc_dev->buf);
 253         adc_dev->buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
 254         if (!adc_dev->buf)
 255                 return -ENOMEM;
 256
 257         return 0;
 258 }
 259
 260 static const struct iio_info cc10001_adc_info = {
 261         .read_raw = &cc10001_adc_read_raw,
 262         .update_scan_mode = &cc10001_update_scan_mode,
 263 };
 264
 265 static int cc10001_adc_channel_init(struct iio_dev *indio_dev,
 266                                     unsigned long channel_map)
 267 {
 268         struct iio_chan_spec *chan_array, *timestamp;
 269         unsigned int bit, idx = 0;
 270
 271         indio_dev->num_channels = bitmap_weight(&channel_map,
 272                                                 CC10001_ADC_NUM_CHANNELS) + 1;
 273
 274         chan_array = devm_kcalloc(&indio_dev->dev, indio_dev->num_channels,
 275                                   sizeof(struct iio_chan_spec),
 276                                   GFP_KERNEL);
 277         if (!chan_array)
 278                 return -ENOMEM;
 279
 280         for_each_set_bit(bit, &channel_map, CC10001_ADC_NUM_CHANNELS) {
 281                 struct iio_chan_spec *chan = &chan_array[idx];
 282
 283                 chan->type = IIO_VOLTAGE;
 284                 chan->indexed = 1;
 285                 chan->channel = bit;
 286                 chan->scan_index = idx;
 287                 chan->scan_type.sign = 'u';
 288                 chan->scan_type.realbits = 10;
 289                 chan->scan_type.storagebits = 16;
 290                 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
 291                 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
 292                 idx++;
 293         }
 294
 295         timestamp = &chan_array[idx];
 296         timestamp->type = IIO_TIMESTAMP;
 297         timestamp->channel = -1;
 298         timestamp->scan_index = idx;
 299         timestamp->scan_type.sign = 's';
 300         timestamp->scan_type.realbits = 64;
 301         timestamp->scan_type.storagebits = 64;
 302
 303         indio_dev->channels = chan_array;
 304
 305         return 0;
 306 }
 307
 308 static int cc10001_adc_probe(struct platform_device *pdev)
 309 {
 310         struct device_node *node = pdev->dev.of_node;
 311         struct cc10001_adc_device *adc_dev;
 312         unsigned long adc_clk_rate;
 313         struct iio_dev *indio_dev;
 314         unsigned long channel_map;
 315         int ret;
 316
 317         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
 318         if (indio_dev == NULL)
 319                 return -ENOMEM;
 320
 321         adc_dev = iio_priv(indio_dev);
 322
 323         channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0);
 324         if (!of_property_read_u32(node, "adc-reserved-channels", &ret)) {
 325                 adc_dev->shared = true;
 326                 channel_map &= ~ret;
 327         }
 328
 329         adc_dev->reg = devm_regulator_get(&pdev->dev, "vref");
 330         if (IS_ERR(adc_dev->reg))
 331                 return PTR_ERR(adc_dev->reg);
 332
 333         ret = regulator_enable(adc_dev->reg);
 334         if (ret)
 335                 return ret;
 336
 337         indio_dev->name = dev_name(&pdev->dev);
 338         indio_dev->info = &cc10001_adc_info;
 339         indio_dev->modes = INDIO_DIRECT_MODE;
 340
 341         adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
 342         if (IS_ERR(adc_dev->reg_base)) {
 343                 ret = PTR_ERR(adc_dev->reg_base);
 344                 goto err_disable_reg;
 345         }
 346
 347         adc_dev->adc_clk = devm_clk_get(&pdev->dev, "adc");
 348         if (IS_ERR(adc_dev->adc_clk)) {
 349                 dev_err(&pdev->dev, "failed to get the clock\n");
 350                 ret = PTR_ERR(adc_dev->adc_clk);
 351                 goto err_disable_reg;
 352         }
 353
 354         ret = clk_prepare_enable(adc_dev->adc_clk);
 355         if (ret) {
 356                 dev_err(&pdev->dev, "failed to enable the clock\n");
 357                 goto err_disable_reg;
 358         }
 359
 360         adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
 361         if (!adc_clk_rate) {
 362                 ret = -EINVAL;
 363                 dev_err(&pdev->dev, "null clock rate!\n");
 364                 goto err_disable_clk;
 365         }
 366
 367         adc_dev->eoc_delay_ns = NSEC_PER_SEC / adc_clk_rate;
 368         adc_dev->start_delay_ns = adc_dev->eoc_delay_ns * CC10001_WAIT_CYCLES;
 369
 370         /*
 371          * There is only one register to power-up/power-down the AUX ADC.
 372          * If the ADC is shared among multiple CPUs, always power it up here.
 373          * If the ADC is used only by the MIPS, power-up/power-down at runtime.
 374          */
 375         if (adc_dev->shared)
 376                 cc10001_adc_power_up(adc_dev);
 377
 378         /* Setup the ADC channels available on the device */
 379         ret = cc10001_adc_channel_init(indio_dev, channel_map);
 380         if (ret < 0)
 381                 goto err_disable_clk;
 382
 383         mutex_init(&adc_dev->lock);
 384
 385         ret = iio_triggered_buffer_setup(indio_dev, NULL,
 386                                          &cc10001_adc_trigger_h, NULL);
 387         if (ret < 0)
 388                 goto err_disable_clk;
 389
 390         ret = iio_device_register(indio_dev);
 391         if (ret < 0)
 392                 goto err_cleanup_buffer;
 393
 394         platform_set_drvdata(pdev, indio_dev);
 395
 396         return 0;
 397
 398 err_cleanup_buffer:
 399         iio_triggered_buffer_cleanup(indio_dev);
 400 err_disable_clk:
 401         clk_disable_unprepare(adc_dev->adc_clk);
 402 err_disable_reg:
 403         regulator_disable(adc_dev->reg);
 404         return ret;
 405 }
 406
 407 static int cc10001_adc_remove(struct platform_device *pdev)
 408 {
 409         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 410         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 411
 412         cc10001_adc_power_down(adc_dev);
 413         iio_device_unregister(indio_dev);
 414         iio_triggered_buffer_cleanup(indio_dev);
 415         clk_disable_unprepare(adc_dev->adc_clk);
 416         regulator_disable(adc_dev->reg);
 417
 418         return 0;
 419 }
 420
 421 static const struct of_device_id cc10001_adc_dt_ids[] = {
 422         { .compatible = "cosmic,10001-adc", },
 423         { }
 424 };
 425 MODULE_DEVICE_TABLE(of, cc10001_adc_dt_ids);
 426
 427 static struct platform_driver cc10001_adc_driver = {
 428         .driver = {
 429                 .name   = "cc10001-adc",
 430                 .of_match_table = cc10001_adc_dt_ids,
 431         },
 432         .probe  = cc10001_adc_probe,
 433         .remove = cc10001_adc_remove,
 434 };
 435 module_platform_driver(cc10001_adc_driver);
 436
 437 MODULE_AUTHOR("Phani Movva <Phani.Movva@imgtec.com>");
 438 MODULE_DESCRIPTION("Cosmic Circuits ADC driver");
 439 MODULE_LICENSE("GPL v2");