1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * exynos_adc.c - Support for ADC in EXYNOS SoCs
5 * 8 ~ 10 channel, 10/12-bit ADC
7 * Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
10 #include <linux/compiler.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/interrupt.h>
14 #include <linux/delay.h>
15 #include <linux/errno.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
19 #include <linux/clk.h>
20 #include <linux/completion.h>
22 #include <linux/of_irq.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/of_platform.h>
25 #include <linux/err.h>
26 #include <linux/input.h>
28 #include <linux/iio/iio.h>
29 #include <linux/iio/machine.h>
30 #include <linux/iio/driver.h>
31 #include <linux/mfd/syscon.h>
32 #include <linux/regmap.h>
34 #include <linux/platform_data/touchscreen-s3c2410.h>
36 /* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
37 #define ADC_V1_CON(x) ((x) + 0x00)
38 #define ADC_V1_TSC(x) ((x) + 0x04)
39 #define ADC_V1_DLY(x) ((x) + 0x08)
40 #define ADC_V1_DATX(x) ((x) + 0x0C)
41 #define ADC_V1_DATY(x) ((x) + 0x10)
42 #define ADC_V1_UPDN(x) ((x) + 0x14)
43 #define ADC_V1_INTCLR(x) ((x) + 0x18)
44 #define ADC_V1_MUX(x) ((x) + 0x1c)
45 #define ADC_V1_CLRINTPNDNUP(x) ((x) + 0x20)
47 /* S3C2410 ADC registers definitions */
48 #define ADC_S3C2410_MUX(x) ((x) + 0x18)
50 /* Future ADC_V2 registers definitions */
51 #define ADC_V2_CON1(x) ((x) + 0x00)
52 #define ADC_V2_CON2(x) ((x) + 0x04)
53 #define ADC_V2_STAT(x) ((x) + 0x08)
54 #define ADC_V2_INT_EN(x) ((x) + 0x10)
55 #define ADC_V2_INT_ST(x) ((x) + 0x14)
56 #define ADC_V2_VER(x) ((x) + 0x20)
58 /* Bit definitions for ADC_V1 */
59 #define ADC_V1_CON_RES (1u << 16)
60 #define ADC_V1_CON_PRSCEN (1u << 14)
61 #define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6)
62 #define ADC_V1_CON_STANDBY (1u << 2)
64 /* Bit definitions for S3C2410 ADC */
65 #define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
66 #define ADC_S3C2410_DATX_MASK 0x3FF
67 #define ADC_S3C2416_CON_RES_SEL (1u << 3)
69 /* touch screen always uses channel 0 */
70 #define ADC_S3C2410_MUX_TS 0
72 /* ADCTSC Register Bits */
73 #define ADC_S3C2443_TSC_UD_SEN (1u << 8)
74 #define ADC_S3C2410_TSC_YM_SEN (1u << 7)
75 #define ADC_S3C2410_TSC_YP_SEN (1u << 6)
76 #define ADC_S3C2410_TSC_XM_SEN (1u << 5)
77 #define ADC_S3C2410_TSC_XP_SEN (1u << 4)
78 #define ADC_S3C2410_TSC_PULL_UP_DISABLE (1u << 3)
79 #define ADC_S3C2410_TSC_AUTO_PST (1u << 2)
80 #define ADC_S3C2410_TSC_XY_PST(x) (((x) & 0x3) << 0)
82 #define ADC_TSC_WAIT4INT (ADC_S3C2410_TSC_YM_SEN | \
83 ADC_S3C2410_TSC_YP_SEN | \
84 ADC_S3C2410_TSC_XP_SEN | \
85 ADC_S3C2410_TSC_XY_PST(3))
87 #define ADC_TSC_AUTOPST (ADC_S3C2410_TSC_YM_SEN | \
88 ADC_S3C2410_TSC_YP_SEN | \
89 ADC_S3C2410_TSC_XP_SEN | \
90 ADC_S3C2410_TSC_AUTO_PST | \
91 ADC_S3C2410_TSC_XY_PST(0))
93 /* Bit definitions for ADC_V2 */
94 #define ADC_V2_CON1_SOFT_RESET (1u << 2)
96 #define ADC_V2_CON2_OSEL (1u << 10)
97 #define ADC_V2_CON2_ESEL (1u << 9)
98 #define ADC_V2_CON2_HIGHF (1u << 8)
99 #define ADC_V2_CON2_C_TIME(x) (((x) & 7) << 4)
100 #define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0)
101 #define ADC_V2_CON2_ACH_MASK 0xF
103 #define MAX_ADC_V2_CHANNELS 10
104 #define MAX_ADC_V1_CHANNELS 8
105 #define MAX_EXYNOS3250_ADC_CHANNELS 2
106 #define MAX_EXYNOS4212_ADC_CHANNELS 4
107 #define MAX_S5PV210_ADC_CHANNELS 10
109 /* Bit definitions common for ADC_V1 and ADC_V2 */
110 #define ADC_CON_EN_START (1u << 0)
111 #define ADC_CON_EN_START_MASK (0x3 << 0)
112 #define ADC_DATX_PRESSED (1u << 15)
113 #define ADC_DATX_MASK 0xFFF
114 #define ADC_DATY_MASK 0xFFF
116 #define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
118 #define EXYNOS_ADCV1_PHY_OFFSET 0x0718
119 #define EXYNOS_ADCV2_PHY_OFFSET 0x0720
122 struct exynos_adc_data
*data
;
124 struct input_dev
*input
;
126 struct regmap
*pmu_map
;
132 struct regulator
*vdd
;
134 struct completion completion
;
137 unsigned int version
;
146 * Lock to protect from potential concurrent access to the
147 * completion callback during a manual conversion. For this driver
148 * a wait-callback is used to wait for the conversion result,
149 * so in the meantime no other read request (or conversion start)
150 * must be performed, otherwise it would interfere with the
151 * current conversion result.
156 struct exynos_adc_data
{
163 void (*init_hw
)(struct exynos_adc
*info
);
164 void (*exit_hw
)(struct exynos_adc
*info
);
165 void (*clear_irq
)(struct exynos_adc
*info
);
166 void (*start_conv
)(struct exynos_adc
*info
, unsigned long addr
);
169 static void exynos_adc_unprepare_clk(struct exynos_adc
*info
)
171 if (info
->data
->needs_sclk
)
172 clk_unprepare(info
->sclk
);
173 clk_unprepare(info
->clk
);
176 static int exynos_adc_prepare_clk(struct exynos_adc
*info
)
180 ret
= clk_prepare(info
->clk
);
182 dev_err(info
->dev
, "failed preparing adc clock: %d\n", ret
);
186 if (info
->data
->needs_sclk
) {
187 ret
= clk_prepare(info
->sclk
);
189 clk_unprepare(info
->clk
);
191 "failed preparing sclk_adc clock: %d\n", ret
);
199 static void exynos_adc_disable_clk(struct exynos_adc
*info
)
201 if (info
->data
->needs_sclk
)
202 clk_disable(info
->sclk
);
203 clk_disable(info
->clk
);
206 static int exynos_adc_enable_clk(struct exynos_adc
*info
)
210 ret
= clk_enable(info
->clk
);
212 dev_err(info
->dev
, "failed enabling adc clock: %d\n", ret
);
216 if (info
->data
->needs_sclk
) {
217 ret
= clk_enable(info
->sclk
);
219 clk_disable(info
->clk
);
221 "failed enabling sclk_adc clock: %d\n", ret
);
229 static void exynos_adc_v1_init_hw(struct exynos_adc
*info
)
233 if (info
->data
->needs_adc_phy
)
234 regmap_write(info
->pmu_map
, info
->data
->phy_offset
, 1);
236 /* set default prescaler values and Enable prescaler */
237 con1
= ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN
;
239 /* Enable 12-bit ADC resolution */
240 con1
|= ADC_V1_CON_RES
;
241 writel(con1
, ADC_V1_CON(info
->regs
));
243 /* set touchscreen delay */
244 writel(info
->delay
, ADC_V1_DLY(info
->regs
));
247 static void exynos_adc_v1_exit_hw(struct exynos_adc
*info
)
251 if (info
->data
->needs_adc_phy
)
252 regmap_write(info
->pmu_map
, info
->data
->phy_offset
, 0);
254 con
= readl(ADC_V1_CON(info
->regs
));
255 con
|= ADC_V1_CON_STANDBY
;
256 writel(con
, ADC_V1_CON(info
->regs
));
259 static void exynos_adc_v1_clear_irq(struct exynos_adc
*info
)
261 writel(1, ADC_V1_INTCLR(info
->regs
));
264 static void exynos_adc_v1_start_conv(struct exynos_adc
*info
,
269 writel(addr
, ADC_V1_MUX(info
->regs
));
271 con1
= readl(ADC_V1_CON(info
->regs
));
272 writel(con1
| ADC_CON_EN_START
, ADC_V1_CON(info
->regs
));
275 /* Exynos4212 and 4412 is like ADCv1 but with four channels only */
276 static const struct exynos_adc_data exynos4212_adc_data
= {
277 .num_channels
= MAX_EXYNOS4212_ADC_CHANNELS
,
278 .mask
= ADC_DATX_MASK
, /* 12 bit ADC resolution */
279 .needs_adc_phy
= true,
280 .phy_offset
= EXYNOS_ADCV1_PHY_OFFSET
,
282 .init_hw
= exynos_adc_v1_init_hw
,
283 .exit_hw
= exynos_adc_v1_exit_hw
,
284 .clear_irq
= exynos_adc_v1_clear_irq
,
285 .start_conv
= exynos_adc_v1_start_conv
,
288 static const struct exynos_adc_data exynos_adc_v1_data
= {
289 .num_channels
= MAX_ADC_V1_CHANNELS
,
290 .mask
= ADC_DATX_MASK
, /* 12 bit ADC resolution */
291 .needs_adc_phy
= true,
292 .phy_offset
= EXYNOS_ADCV1_PHY_OFFSET
,
294 .init_hw
= exynos_adc_v1_init_hw
,
295 .exit_hw
= exynos_adc_v1_exit_hw
,
296 .clear_irq
= exynos_adc_v1_clear_irq
,
297 .start_conv
= exynos_adc_v1_start_conv
,
300 static const struct exynos_adc_data exynos_adc_s5pv210_data
= {
301 .num_channels
= MAX_S5PV210_ADC_CHANNELS
,
302 .mask
= ADC_DATX_MASK
, /* 12 bit ADC resolution */
304 .init_hw
= exynos_adc_v1_init_hw
,
305 .exit_hw
= exynos_adc_v1_exit_hw
,
306 .clear_irq
= exynos_adc_v1_clear_irq
,
307 .start_conv
= exynos_adc_v1_start_conv
,
310 static void exynos_adc_s3c2416_start_conv(struct exynos_adc
*info
,
315 /* Enable 12 bit ADC resolution */
316 con1
= readl(ADC_V1_CON(info
->regs
));
317 con1
|= ADC_S3C2416_CON_RES_SEL
;
318 writel(con1
, ADC_V1_CON(info
->regs
));
320 /* Select channel for S3C2416 */
321 writel(addr
, ADC_S3C2410_MUX(info
->regs
));
323 con1
= readl(ADC_V1_CON(info
->regs
));
324 writel(con1
| ADC_CON_EN_START
, ADC_V1_CON(info
->regs
));
327 static struct exynos_adc_data
const exynos_adc_s3c2416_data
= {
328 .num_channels
= MAX_ADC_V1_CHANNELS
,
329 .mask
= ADC_DATX_MASK
, /* 12 bit ADC resolution */
331 .init_hw
= exynos_adc_v1_init_hw
,
332 .exit_hw
= exynos_adc_v1_exit_hw
,
333 .start_conv
= exynos_adc_s3c2416_start_conv
,
336 static void exynos_adc_s3c2443_start_conv(struct exynos_adc
*info
,
341 /* Select channel for S3C2433 */
342 writel(addr
, ADC_S3C2410_MUX(info
->regs
));
344 con1
= readl(ADC_V1_CON(info
->regs
));
345 writel(con1
| ADC_CON_EN_START
, ADC_V1_CON(info
->regs
));
348 static struct exynos_adc_data
const exynos_adc_s3c2443_data
= {
349 .num_channels
= MAX_ADC_V1_CHANNELS
,
350 .mask
= ADC_S3C2410_DATX_MASK
, /* 10 bit ADC resolution */
352 .init_hw
= exynos_adc_v1_init_hw
,
353 .exit_hw
= exynos_adc_v1_exit_hw
,
354 .start_conv
= exynos_adc_s3c2443_start_conv
,
357 static void exynos_adc_s3c64xx_start_conv(struct exynos_adc
*info
,
362 con1
= readl(ADC_V1_CON(info
->regs
));
363 con1
&= ~ADC_S3C2410_CON_SELMUX(0x7);
364 con1
|= ADC_S3C2410_CON_SELMUX(addr
);
365 writel(con1
| ADC_CON_EN_START
, ADC_V1_CON(info
->regs
));
368 static struct exynos_adc_data
const exynos_adc_s3c24xx_data
= {
369 .num_channels
= MAX_ADC_V1_CHANNELS
,
370 .mask
= ADC_S3C2410_DATX_MASK
, /* 10 bit ADC resolution */
372 .init_hw
= exynos_adc_v1_init_hw
,
373 .exit_hw
= exynos_adc_v1_exit_hw
,
374 .start_conv
= exynos_adc_s3c64xx_start_conv
,
377 static struct exynos_adc_data
const exynos_adc_s3c64xx_data
= {
378 .num_channels
= MAX_ADC_V1_CHANNELS
,
379 .mask
= ADC_DATX_MASK
, /* 12 bit ADC resolution */
381 .init_hw
= exynos_adc_v1_init_hw
,
382 .exit_hw
= exynos_adc_v1_exit_hw
,
383 .clear_irq
= exynos_adc_v1_clear_irq
,
384 .start_conv
= exynos_adc_s3c64xx_start_conv
,
387 static void exynos_adc_v2_init_hw(struct exynos_adc
*info
)
391 if (info
->data
->needs_adc_phy
)
392 regmap_write(info
->pmu_map
, info
->data
->phy_offset
, 1);
394 con1
= ADC_V2_CON1_SOFT_RESET
;
395 writel(con1
, ADC_V2_CON1(info
->regs
));
397 con2
= ADC_V2_CON2_OSEL
| ADC_V2_CON2_ESEL
|
398 ADC_V2_CON2_HIGHF
| ADC_V2_CON2_C_TIME(0);
399 writel(con2
, ADC_V2_CON2(info
->regs
));
401 /* Enable interrupts */
402 writel(1, ADC_V2_INT_EN(info
->regs
));
405 static void exynos_adc_v2_exit_hw(struct exynos_adc
*info
)
409 if (info
->data
->needs_adc_phy
)
410 regmap_write(info
->pmu_map
, info
->data
->phy_offset
, 0);
412 con
= readl(ADC_V2_CON1(info
->regs
));
413 con
&= ~ADC_CON_EN_START
;
414 writel(con
, ADC_V2_CON1(info
->regs
));
417 static void exynos_adc_v2_clear_irq(struct exynos_adc
*info
)
419 writel(1, ADC_V2_INT_ST(info
->regs
));
422 static void exynos_adc_v2_start_conv(struct exynos_adc
*info
,
427 con2
= readl(ADC_V2_CON2(info
->regs
));
428 con2
&= ~ADC_V2_CON2_ACH_MASK
;
429 con2
|= ADC_V2_CON2_ACH_SEL(addr
);
430 writel(con2
, ADC_V2_CON2(info
->regs
));
432 con1
= readl(ADC_V2_CON1(info
->regs
));
433 writel(con1
| ADC_CON_EN_START
, ADC_V2_CON1(info
->regs
));
436 static const struct exynos_adc_data exynos_adc_v2_data
= {
437 .num_channels
= MAX_ADC_V2_CHANNELS
,
438 .mask
= ADC_DATX_MASK
, /* 12 bit ADC resolution */
439 .needs_adc_phy
= true,
440 .phy_offset
= EXYNOS_ADCV2_PHY_OFFSET
,
442 .init_hw
= exynos_adc_v2_init_hw
,
443 .exit_hw
= exynos_adc_v2_exit_hw
,
444 .clear_irq
= exynos_adc_v2_clear_irq
,
445 .start_conv
= exynos_adc_v2_start_conv
,
448 static const struct exynos_adc_data exynos3250_adc_data
= {
449 .num_channels
= MAX_EXYNOS3250_ADC_CHANNELS
,
450 .mask
= ADC_DATX_MASK
, /* 12 bit ADC resolution */
452 .needs_adc_phy
= true,
453 .phy_offset
= EXYNOS_ADCV1_PHY_OFFSET
,
455 .init_hw
= exynos_adc_v2_init_hw
,
456 .exit_hw
= exynos_adc_v2_exit_hw
,
457 .clear_irq
= exynos_adc_v2_clear_irq
,
458 .start_conv
= exynos_adc_v2_start_conv
,
461 static void exynos_adc_exynos7_init_hw(struct exynos_adc
*info
)
465 con1
= ADC_V2_CON1_SOFT_RESET
;
466 writel(con1
, ADC_V2_CON1(info
->regs
));
468 con2
= readl(ADC_V2_CON2(info
->regs
));
469 con2
&= ~ADC_V2_CON2_C_TIME(7);
470 con2
|= ADC_V2_CON2_C_TIME(0);
471 writel(con2
, ADC_V2_CON2(info
->regs
));
473 /* Enable interrupts */
474 writel(1, ADC_V2_INT_EN(info
->regs
));
477 static const struct exynos_adc_data exynos7_adc_data
= {
478 .num_channels
= MAX_ADC_V1_CHANNELS
,
479 .mask
= ADC_DATX_MASK
, /* 12 bit ADC resolution */
481 .init_hw
= exynos_adc_exynos7_init_hw
,
482 .exit_hw
= exynos_adc_v2_exit_hw
,
483 .clear_irq
= exynos_adc_v2_clear_irq
,
484 .start_conv
= exynos_adc_v2_start_conv
,
487 static const struct of_device_id exynos_adc_match
[] = {
489 .compatible
= "samsung,s3c2410-adc",
490 .data
= &exynos_adc_s3c24xx_data
,
492 .compatible
= "samsung,s3c2416-adc",
493 .data
= &exynos_adc_s3c2416_data
,
495 .compatible
= "samsung,s3c2440-adc",
496 .data
= &exynos_adc_s3c24xx_data
,
498 .compatible
= "samsung,s3c2443-adc",
499 .data
= &exynos_adc_s3c2443_data
,
501 .compatible
= "samsung,s3c6410-adc",
502 .data
= &exynos_adc_s3c64xx_data
,
504 .compatible
= "samsung,s5pv210-adc",
505 .data
= &exynos_adc_s5pv210_data
,
507 .compatible
= "samsung,exynos4212-adc",
508 .data
= &exynos4212_adc_data
,
510 .compatible
= "samsung,exynos-adc-v1",
511 .data
= &exynos_adc_v1_data
,
513 .compatible
= "samsung,exynos-adc-v2",
514 .data
= &exynos_adc_v2_data
,
516 .compatible
= "samsung,exynos3250-adc",
517 .data
= &exynos3250_adc_data
,
519 .compatible
= "samsung,exynos7-adc",
520 .data
= &exynos7_adc_data
,
524 MODULE_DEVICE_TABLE(of
, exynos_adc_match
);
526 static struct exynos_adc_data
*exynos_adc_get_data(struct platform_device
*pdev
)
528 const struct of_device_id
*match
;
530 match
= of_match_node(exynos_adc_match
, pdev
->dev
.of_node
);
531 return (struct exynos_adc_data
*)match
->data
;
534 static int exynos_read_raw(struct iio_dev
*indio_dev
,
535 struct iio_chan_spec
const *chan
,
540 struct exynos_adc
*info
= iio_priv(indio_dev
);
541 unsigned long timeout
;
544 if (mask
== IIO_CHAN_INFO_SCALE
) {
545 ret
= regulator_get_voltage(info
->vdd
);
549 /* Regulator voltage is in uV, but need mV */
551 *val2
= info
->data
->mask
;
553 return IIO_VAL_FRACTIONAL
;
554 } else if (mask
!= IIO_CHAN_INFO_RAW
) {
558 mutex_lock(&info
->lock
);
559 reinit_completion(&info
->completion
);
561 /* Select the channel to be used and Trigger conversion */
562 if (info
->data
->start_conv
)
563 info
->data
->start_conv(info
, chan
->address
);
565 timeout
= wait_for_completion_timeout(&info
->completion
,
568 dev_warn(&indio_dev
->dev
, "Conversion timed out! Resetting\n");
569 if (info
->data
->init_hw
)
570 info
->data
->init_hw(info
);
578 mutex_unlock(&info
->lock
);
583 static int exynos_read_s3c64xx_ts(struct iio_dev
*indio_dev
, int *x
, int *y
)
585 struct exynos_adc
*info
= iio_priv(indio_dev
);
586 unsigned long timeout
;
589 mutex_lock(&info
->lock
);
590 info
->read_ts
= true;
592 reinit_completion(&info
->completion
);
594 writel(ADC_S3C2410_TSC_PULL_UP_DISABLE
| ADC_TSC_AUTOPST
,
595 ADC_V1_TSC(info
->regs
));
597 /* Select the ts channel to be used and Trigger conversion */
598 info
->data
->start_conv(info
, ADC_S3C2410_MUX_TS
);
600 timeout
= wait_for_completion_timeout(&info
->completion
,
603 dev_warn(&indio_dev
->dev
, "Conversion timed out! Resetting\n");
604 if (info
->data
->init_hw
)
605 info
->data
->init_hw(info
);
613 info
->read_ts
= false;
614 mutex_unlock(&info
->lock
);
619 static irqreturn_t
exynos_adc_isr(int irq
, void *dev_id
)
621 struct exynos_adc
*info
= dev_id
;
622 u32 mask
= info
->data
->mask
;
626 info
->ts_x
= readl(ADC_V1_DATX(info
->regs
));
627 info
->ts_y
= readl(ADC_V1_DATY(info
->regs
));
628 writel(ADC_TSC_WAIT4INT
| ADC_S3C2443_TSC_UD_SEN
, ADC_V1_TSC(info
->regs
));
630 info
->value
= readl(ADC_V1_DATX(info
->regs
)) & mask
;
634 if (info
->data
->clear_irq
)
635 info
->data
->clear_irq(info
);
637 complete(&info
->completion
);
643 * Here we (ab)use a threaded interrupt handler to stay running
644 * for as long as the touchscreen remains pressed, we report
645 * a new event with the latest data and then sleep until the
646 * next timer tick. This mirrors the behavior of the old
647 * driver, with much less code.
649 static irqreturn_t
exynos_ts_isr(int irq
, void *dev_id
)
651 struct exynos_adc
*info
= dev_id
;
652 struct iio_dev
*dev
= dev_get_drvdata(info
->dev
);
657 while (READ_ONCE(info
->ts_enabled
)) {
658 ret
= exynos_read_s3c64xx_ts(dev
, &x
, &y
);
659 if (ret
== -ETIMEDOUT
)
662 pressed
= x
& y
& ADC_DATX_PRESSED
;
664 input_report_key(info
->input
, BTN_TOUCH
, 0);
665 input_sync(info
->input
);
669 input_report_abs(info
->input
, ABS_X
, x
& ADC_DATX_MASK
);
670 input_report_abs(info
->input
, ABS_Y
, y
& ADC_DATY_MASK
);
671 input_report_key(info
->input
, BTN_TOUCH
, 1);
672 input_sync(info
->input
);
674 usleep_range(1000, 1100);
677 writel(0, ADC_V1_CLRINTPNDNUP(info
->regs
));
682 static int exynos_adc_reg_access(struct iio_dev
*indio_dev
,
683 unsigned reg
, unsigned writeval
,
686 struct exynos_adc
*info
= iio_priv(indio_dev
);
691 *readval
= readl(info
->regs
+ reg
);
696 static const struct iio_info exynos_adc_iio_info
= {
697 .read_raw
= &exynos_read_raw
,
698 .debugfs_reg_access
= &exynos_adc_reg_access
,
701 #define ADC_CHANNEL(_index, _id) { \
702 .type = IIO_VOLTAGE, \
706 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
707 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE), \
708 .datasheet_name = _id, \
711 static const struct iio_chan_spec exynos_adc_iio_channels
[] = {
712 ADC_CHANNEL(0, "adc0"),
713 ADC_CHANNEL(1, "adc1"),
714 ADC_CHANNEL(2, "adc2"),
715 ADC_CHANNEL(3, "adc3"),
716 ADC_CHANNEL(4, "adc4"),
717 ADC_CHANNEL(5, "adc5"),
718 ADC_CHANNEL(6, "adc6"),
719 ADC_CHANNEL(7, "adc7"),
720 ADC_CHANNEL(8, "adc8"),
721 ADC_CHANNEL(9, "adc9"),
724 static int exynos_adc_remove_devices(struct device
*dev
, void *c
)
726 struct platform_device
*pdev
= to_platform_device(dev
);
728 platform_device_unregister(pdev
);
733 static int exynos_adc_ts_open(struct input_dev
*dev
)
735 struct exynos_adc
*info
= input_get_drvdata(dev
);
737 WRITE_ONCE(info
->ts_enabled
, true);
738 enable_irq(info
->tsirq
);
743 static void exynos_adc_ts_close(struct input_dev
*dev
)
745 struct exynos_adc
*info
= input_get_drvdata(dev
);
747 WRITE_ONCE(info
->ts_enabled
, false);
748 disable_irq(info
->tsirq
);
751 static int exynos_adc_ts_init(struct exynos_adc
*info
)
755 if (info
->tsirq
<= 0)
758 info
->input
= input_allocate_device();
762 info
->input
->evbit
[0] = BIT_MASK(EV_KEY
) | BIT_MASK(EV_ABS
);
763 info
->input
->keybit
[BIT_WORD(BTN_TOUCH
)] = BIT_MASK(BTN_TOUCH
);
765 input_set_abs_params(info
->input
, ABS_X
, 0, 0x3FF, 0, 0);
766 input_set_abs_params(info
->input
, ABS_Y
, 0, 0x3FF, 0, 0);
768 info
->input
->name
= "S3C24xx TouchScreen";
769 info
->input
->id
.bustype
= BUS_HOST
;
770 info
->input
->open
= exynos_adc_ts_open
;
771 info
->input
->close
= exynos_adc_ts_close
;
773 input_set_drvdata(info
->input
, info
);
775 ret
= input_register_device(info
->input
);
777 input_free_device(info
->input
);
781 disable_irq(info
->tsirq
);
782 ret
= request_threaded_irq(info
->tsirq
, NULL
, exynos_ts_isr
,
783 IRQF_ONESHOT
, "touchscreen", info
);
785 input_unregister_device(info
->input
);
790 static int exynos_adc_probe(struct platform_device
*pdev
)
792 struct exynos_adc
*info
= NULL
;
793 struct device_node
*np
= pdev
->dev
.of_node
;
794 struct s3c2410_ts_mach_info
*pdata
= dev_get_platdata(&pdev
->dev
);
795 struct iio_dev
*indio_dev
= NULL
;
800 indio_dev
= devm_iio_device_alloc(&pdev
->dev
, sizeof(struct exynos_adc
));
802 dev_err(&pdev
->dev
, "failed allocating iio device\n");
806 info
= iio_priv(indio_dev
);
808 info
->data
= exynos_adc_get_data(pdev
);
810 dev_err(&pdev
->dev
, "failed getting exynos_adc_data\n");
814 info
->regs
= devm_platform_ioremap_resource(pdev
, 0);
815 if (IS_ERR(info
->regs
))
816 return PTR_ERR(info
->regs
);
819 if (info
->data
->needs_adc_phy
) {
820 info
->pmu_map
= syscon_regmap_lookup_by_phandle(
822 "samsung,syscon-phandle");
823 if (IS_ERR(info
->pmu_map
)) {
824 dev_err(&pdev
->dev
, "syscon regmap lookup failed.\n");
825 return PTR_ERR(info
->pmu_map
);
829 irq
= platform_get_irq(pdev
, 0);
834 irq
= platform_get_irq(pdev
, 1);
835 if (irq
== -EPROBE_DEFER
)
840 info
->dev
= &pdev
->dev
;
842 init_completion(&info
->completion
);
844 info
->clk
= devm_clk_get(&pdev
->dev
, "adc");
845 if (IS_ERR(info
->clk
)) {
846 dev_err(&pdev
->dev
, "failed getting clock, err = %ld\n",
848 return PTR_ERR(info
->clk
);
851 if (info
->data
->needs_sclk
) {
852 info
->sclk
= devm_clk_get(&pdev
->dev
, "sclk");
853 if (IS_ERR(info
->sclk
)) {
855 "failed getting sclk clock, err = %ld\n",
856 PTR_ERR(info
->sclk
));
857 return PTR_ERR(info
->sclk
);
861 info
->vdd
= devm_regulator_get(&pdev
->dev
, "vdd");
862 if (IS_ERR(info
->vdd
))
863 return dev_err_probe(&pdev
->dev
, PTR_ERR(info
->vdd
),
864 "failed getting regulator");
866 ret
= regulator_enable(info
->vdd
);
870 ret
= exynos_adc_prepare_clk(info
);
872 goto err_disable_reg
;
874 ret
= exynos_adc_enable_clk(info
);
876 goto err_unprepare_clk
;
878 platform_set_drvdata(pdev
, indio_dev
);
880 indio_dev
->name
= dev_name(&pdev
->dev
);
881 indio_dev
->info
= &exynos_adc_iio_info
;
882 indio_dev
->modes
= INDIO_DIRECT_MODE
;
883 indio_dev
->channels
= exynos_adc_iio_channels
;
884 indio_dev
->num_channels
= info
->data
->num_channels
;
886 mutex_init(&info
->lock
);
888 ret
= request_irq(info
->irq
, exynos_adc_isr
,
889 0, dev_name(&pdev
->dev
), info
);
891 dev_err(&pdev
->dev
, "failed requesting irq, irq = %d\n",
893 goto err_disable_clk
;
896 ret
= iio_device_register(indio_dev
);
900 if (info
->data
->init_hw
)
901 info
->data
->init_hw(info
);
903 /* leave out any TS related code if unreachable */
904 if (IS_REACHABLE(CONFIG_INPUT
)) {
905 has_ts
= of_property_read_bool(pdev
->dev
.of_node
,
906 "has-touchscreen") || pdata
;
910 info
->delay
= pdata
->delay
;
915 ret
= exynos_adc_ts_init(info
);
919 ret
= of_platform_populate(np
, exynos_adc_match
, NULL
, &indio_dev
->dev
);
921 dev_err(&pdev
->dev
, "failed adding child nodes\n");
922 goto err_of_populate
;
928 device_for_each_child(&indio_dev
->dev
, NULL
,
929 exynos_adc_remove_devices
);
931 input_unregister_device(info
->input
);
932 free_irq(info
->tsirq
, info
);
935 iio_device_unregister(indio_dev
);
937 free_irq(info
->irq
, info
);
939 if (info
->data
->exit_hw
)
940 info
->data
->exit_hw(info
);
941 exynos_adc_disable_clk(info
);
943 exynos_adc_unprepare_clk(info
);
945 regulator_disable(info
->vdd
);
949 static int exynos_adc_remove(struct platform_device
*pdev
)
951 struct iio_dev
*indio_dev
= platform_get_drvdata(pdev
);
952 struct exynos_adc
*info
= iio_priv(indio_dev
);
954 if (IS_REACHABLE(CONFIG_INPUT
) && info
->input
) {
955 free_irq(info
->tsirq
, info
);
956 input_unregister_device(info
->input
);
958 device_for_each_child(&indio_dev
->dev
, NULL
,
959 exynos_adc_remove_devices
);
960 iio_device_unregister(indio_dev
);
961 free_irq(info
->irq
, info
);
962 if (info
->data
->exit_hw
)
963 info
->data
->exit_hw(info
);
964 exynos_adc_disable_clk(info
);
965 exynos_adc_unprepare_clk(info
);
966 regulator_disable(info
->vdd
);
971 #ifdef CONFIG_PM_SLEEP
972 static int exynos_adc_suspend(struct device
*dev
)
974 struct iio_dev
*indio_dev
= dev_get_drvdata(dev
);
975 struct exynos_adc
*info
= iio_priv(indio_dev
);
977 if (info
->data
->exit_hw
)
978 info
->data
->exit_hw(info
);
979 exynos_adc_disable_clk(info
);
980 regulator_disable(info
->vdd
);
985 static int exynos_adc_resume(struct device
*dev
)
987 struct iio_dev
*indio_dev
= dev_get_drvdata(dev
);
988 struct exynos_adc
*info
= iio_priv(indio_dev
);
991 ret
= regulator_enable(info
->vdd
);
995 ret
= exynos_adc_enable_clk(info
);
999 if (info
->data
->init_hw
)
1000 info
->data
->init_hw(info
);
1006 static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops
,
1010 static struct platform_driver exynos_adc_driver
= {
1011 .probe
= exynos_adc_probe
,
1012 .remove
= exynos_adc_remove
,
1014 .name
= "exynos-adc",
1015 .of_match_table
= exynos_adc_match
,
1016 .pm
= &exynos_adc_pm_ops
,
1020 module_platform_driver(exynos_adc_driver
);
1022 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
1023 MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
1024 MODULE_LICENSE("GPL v2");