drivers/iio/adc/ti_am335x_adc.c

   1 /*
   2  * TI ADC MFD driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/err.h>
  18 #include <linux/module.h>
  19 #include <linux/slab.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/io.h>
  23 #include <linux/iio/iio.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/iio/machine.h>
  27 #include <linux/iio/driver.h>
  28
  29 #include <linux/mfd/ti_am335x_tscadc.h>
  30 #include <linux/iio/buffer.h>
  31 #include <linux/iio/kfifo_buf.h>
  32
  33 #include <linux/dmaengine.h>
  34 #include <linux/dma-mapping.h>
  35
  36 #define DMA_BUFFER_SIZE         SZ_2K
  37
  38 struct tiadc_dma {
  39         struct dma_slave_config conf;
  40         struct dma_chan         *chan;
  41         dma_addr_t              addr;
  42         dma_cookie_t            cookie;
  43         u8                      *buf;
  44         int                     current_period;
  45         int                     period_size;
  46         u8                      fifo_thresh;
  47 };
  48
  49 struct tiadc_device {
  50         struct ti_tscadc_dev *mfd_tscadc;
  51         struct tiadc_dma dma;
  52         struct mutex fifo1_lock; /* to protect fifo access */
  53         int channels;
  54         int total_ch_enabled;
  55         u8 channel_line[8];
  56         u8 channel_step[8];
  57         int buffer_en_ch_steps;
  58         u16 data[8];
  59         u32 open_delay[8], sample_delay[8], step_avg[8];
  60 };
  61
  62 static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg)
  63 {
  64         return readl(adc->mfd_tscadc->tscadc_base + reg);
  65 }
  66
  67 static void tiadc_writel(struct tiadc_device *adc, unsigned int reg,
  68                                         unsigned int val)
  69 {
  70         writel(val, adc->mfd_tscadc->tscadc_base + reg);
  71 }
  72
  73 static u32 get_adc_step_mask(struct tiadc_device *adc_dev)
  74 {
  75         u32 step_en;
  76
  77         step_en = ((1 << adc_dev->channels) - 1);
  78         step_en <<= TOTAL_STEPS - adc_dev->channels + 1;
  79         return step_en;
  80 }
  81
  82 static u32 get_adc_chan_step_mask(struct tiadc_device *adc_dev,
  83                 struct iio_chan_spec const *chan)
  84 {
  85         int i;
  86
  87         for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) {
  88                 if (chan->channel == adc_dev->channel_line[i]) {
  89                         u32 step;
  90
  91                         step = adc_dev->channel_step[i];
  92                         /* +1 for the charger */
  93                         return 1 << (step + 1);
  94                 }
  95         }
  96         WARN_ON(1);
  97         return 0;
  98 }
  99
 100 static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan)
 101 {
 102         return 1 << adc_dev->channel_step[chan];
 103 }
 104
 105 static void tiadc_step_config(struct iio_dev *indio_dev)
 106 {
 107         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 108         struct device *dev = adc_dev->mfd_tscadc->dev;
 109         unsigned int stepconfig;
 110         int i, steps = 0;
 111
 112         /*
 113          * There are 16 configurable steps and 8 analog input
 114          * lines available which are shared between Touchscreen and ADC.
 115          *
 116          * Steps forwards i.e. from 0 towards 16 are used by ADC
 117          * depending on number of input lines needed.
 118          * Channel would represent which analog input
 119          * needs to be given to ADC to digitalize data.
 120          */
 121
 122
 123         for (i = 0; i < adc_dev->channels; i++) {
 124                 int chan;
 125
 126                 chan = adc_dev->channel_line[i];
 127
 128                 if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) {
 129                         dev_warn(dev, "chan %d step_avg truncating to %d\n",
 130                                  chan, STEPCONFIG_AVG_16);
 131                         adc_dev->step_avg[i] = STEPCONFIG_AVG_16;
 132                 }
 133
 134                 if (adc_dev->step_avg[i])
 135                         stepconfig =
 136                         STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) |
 137                         STEPCONFIG_FIFO1;
 138                 else
 139                         stepconfig = STEPCONFIG_FIFO1;
 140
 141                 if (iio_buffer_enabled(indio_dev))
 142                         stepconfig |= STEPCONFIG_MODE_SWCNT;
 143
 144                 tiadc_writel(adc_dev, REG_STEPCONFIG(steps),
 145                                 stepconfig | STEPCONFIG_INP(chan) |
 146                                 STEPCONFIG_INM_ADCREFM |
 147                                 STEPCONFIG_RFP_VREFP |
 148                                 STEPCONFIG_RFM_VREFN);
 149
 150                 if (adc_dev->open_delay[i] > STEPDELAY_OPEN_MASK) {
 151                         dev_warn(dev, "chan %d open delay truncating to 0x3FFFF\n",
 152                                  chan);
 153                         adc_dev->open_delay[i] = STEPDELAY_OPEN_MASK;
 154                 }
 155
 156                 if (adc_dev->sample_delay[i] > 0xFF) {
 157                         dev_warn(dev, "chan %d sample delay truncating to 0xFF\n",
 158                                  chan);
 159                         adc_dev->sample_delay[i] = 0xFF;
 160                 }
 161
 162                 tiadc_writel(adc_dev, REG_STEPDELAY(steps),
 163                                 STEPDELAY_OPEN(adc_dev->open_delay[i]) |
 164                                 STEPDELAY_SAMPLE(adc_dev->sample_delay[i]));
 165
 166                 adc_dev->channel_step[i] = steps;
 167                 steps++;
 168         }
 169 }
 170
 171 static irqreturn_t tiadc_irq_h(int irq, void *private)
 172 {
 173         struct iio_dev *indio_dev = private;
 174         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 175         unsigned int status, config, adc_fsm;
 176         unsigned short count = 0;
 177
 178         status = tiadc_readl(adc_dev, REG_IRQSTATUS);
 179
 180         /*
 181          * ADC and touchscreen share the IRQ line.
 182          * FIFO0 interrupts are used by TSC. Handle FIFO1 IRQs here only
 183          */
 184         if (status & IRQENB_FIFO1OVRRUN) {
 185                 /* FIFO Overrun. Clear flag. Disable/Enable ADC to recover */
 186                 config = tiadc_readl(adc_dev, REG_CTRL);
 187                 config &= ~(CNTRLREG_TSCSSENB);
 188                 tiadc_writel(adc_dev, REG_CTRL, config);
 189                 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1OVRRUN
 190                                 | IRQENB_FIFO1UNDRFLW | IRQENB_FIFO1THRES);
 191
 192                 /* wait for idle state.
 193                  * ADC needs to finish the current conversion
 194                  * before disabling the module
 195                  */
 196                 do {
 197                         adc_fsm = tiadc_readl(adc_dev, REG_ADCFSM);
 198                 } while (adc_fsm != 0x10 && count++ < 100);
 199
 200                 tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_TSCSSENB));
 201                 return IRQ_HANDLED;
 202         } else if (status & IRQENB_FIFO1THRES) {
 203                 /* Disable irq and wake worker thread */
 204                 tiadc_writel(adc_dev, REG_IRQCLR, IRQENB_FIFO1THRES);
 205                 return IRQ_WAKE_THREAD;
 206         }
 207
 208         return IRQ_NONE;
 209 }
 210
 211 static irqreturn_t tiadc_worker_h(int irq, void *private)
 212 {
 213         struct iio_dev *indio_dev = private;
 214         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 215         int i, k, fifo1count, read;
 216         u16 *data = adc_dev->data;
 217
 218         fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 219         for (k = 0; k < fifo1count; k = k + i) {
 220                 for (i = 0; i < (indio_dev->scan_bytes)/2; i++) {
 221                         read = tiadc_readl(adc_dev, REG_FIFO1);
 222                         data[i] = read & FIFOREAD_DATA_MASK;
 223                 }
 224                 iio_push_to_buffers(indio_dev, (u8 *) data);
 225         }
 226
 227         tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES);
 228         tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES);
 229
 230         return IRQ_HANDLED;
 231 }
 232
 233 static void tiadc_dma_rx_complete(void *param)
 234 {
 235         struct iio_dev *indio_dev = param;
 236         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 237         struct tiadc_dma *dma = &adc_dev->dma;
 238         u8 *data;
 239         int i;
 240
 241         data = dma->buf + dma->current_period * dma->period_size;
 242         dma->current_period = 1 - dma->current_period; /* swap the buffer ID */
 243
 244         for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) {
 245                 iio_push_to_buffers(indio_dev, data);
 246                 data += indio_dev->scan_bytes;
 247         }
 248 }
 249
 250 static int tiadc_start_dma(struct iio_dev *indio_dev)
 251 {
 252         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 253         struct tiadc_dma *dma = &adc_dev->dma;
 254         struct dma_async_tx_descriptor *desc;
 255
 256         dma->current_period = 0; /* We start to fill period 0 */
 257         /*
 258          * Make the fifo thresh as the multiple of total number of
 259          * channels enabled, so make sure that cyclic DMA period
 260          * length is also a multiple of total number of channels
 261          * enabled. This ensures that no invalid data is reported
 262          * to the stack via iio_push_to_buffers().
 263          */
 264         dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1,
 265                                      adc_dev->total_ch_enabled) - 1;
 266         /* Make sure that period length is multiple of fifo thresh level */
 267         dma->period_size = rounddown(DMA_BUFFER_SIZE / 2,
 268                                     (dma->fifo_thresh + 1) * sizeof(u16));
 269
 270         dma->conf.src_maxburst = dma->fifo_thresh + 1;
 271         dmaengine_slave_config(dma->chan, &dma->conf);
 272
 273         desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr,
 274                                          dma->period_size * 2,
 275                                          dma->period_size, DMA_DEV_TO_MEM,
 276                                          DMA_PREP_INTERRUPT);
 277         if (!desc)
 278                 return -EBUSY;
 279
 280         desc->callback = tiadc_dma_rx_complete;
 281         desc->callback_param = indio_dev;
 282
 283         dma->cookie = dmaengine_submit(desc);
 284
 285         dma_async_issue_pending(dma->chan);
 286
 287         tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh);
 288         tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh);
 289         tiadc_writel(adc_dev, REG_DMAENABLE_SET, DMA_FIFO1);
 290
 291         return 0;
 292 }
 293
 294 static int tiadc_buffer_preenable(struct iio_dev *indio_dev)
 295 {
 296         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 297         int i, fifo1count;
 298
 299         tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES |
 300                                 IRQENB_FIFO1OVRRUN |
 301                                 IRQENB_FIFO1UNDRFLW));
 302
 303         /* Flush FIFO. Needed in corner cases in simultaneous tsc/adc use */
 304         fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 305         for (i = 0; i < fifo1count; i++)
 306                 tiadc_readl(adc_dev, REG_FIFO1);
 307
 308         return 0;
 309 }
 310
 311 static int tiadc_buffer_postenable(struct iio_dev *indio_dev)
 312 {
 313         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 314         struct tiadc_dma *dma = &adc_dev->dma;
 315         unsigned int irq_enable;
 316         unsigned int enb = 0;
 317         u8 bit;
 318
 319         tiadc_step_config(indio_dev);
 320         for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) {
 321                 enb |= (get_adc_step_bit(adc_dev, bit) << 1);
 322                 adc_dev->total_ch_enabled++;
 323         }
 324         adc_dev->buffer_en_ch_steps = enb;
 325
 326         if (dma->chan)
 327                 tiadc_start_dma(indio_dev);
 328
 329         am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb);
 330
 331         tiadc_writel(adc_dev,  REG_IRQSTATUS, IRQENB_FIFO1THRES
 332                                 | IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW);
 333
 334         irq_enable = IRQENB_FIFO1OVRRUN;
 335         if (!dma->chan)
 336                 irq_enable |= IRQENB_FIFO1THRES;
 337         tiadc_writel(adc_dev,  REG_IRQENABLE, irq_enable);
 338
 339         return 0;
 340 }
 341
 342 static int tiadc_buffer_predisable(struct iio_dev *indio_dev)
 343 {
 344         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 345         struct tiadc_dma *dma = &adc_dev->dma;
 346         int fifo1count, i;
 347
 348         tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES |
 349                                 IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW));
 350         am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps);
 351         adc_dev->buffer_en_ch_steps = 0;
 352         adc_dev->total_ch_enabled = 0;
 353         if (dma->chan) {
 354                 tiadc_writel(adc_dev, REG_DMAENABLE_CLEAR, 0x2);
 355                 dmaengine_terminate_async(dma->chan);
 356         }
 357
 358         /* Flush FIFO of leftover data in the time it takes to disable adc */
 359         fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 360         for (i = 0; i < fifo1count; i++)
 361                 tiadc_readl(adc_dev, REG_FIFO1);
 362
 363         return 0;
 364 }
 365
 366 static int tiadc_buffer_postdisable(struct iio_dev *indio_dev)
 367 {
 368         tiadc_step_config(indio_dev);
 369
 370         return 0;
 371 }
 372
 373 static const struct iio_buffer_setup_ops tiadc_buffer_setup_ops = {
 374         .preenable = &tiadc_buffer_preenable,
 375         .postenable = &tiadc_buffer_postenable,
 376         .predisable = &tiadc_buffer_predisable,
 377         .postdisable = &tiadc_buffer_postdisable,
 378 };
 379
 380 static int tiadc_iio_buffered_hardware_setup(struct device *dev,
 381         struct iio_dev *indio_dev,
 382         irqreturn_t (*pollfunc_bh)(int irq, void *p),
 383         irqreturn_t (*pollfunc_th)(int irq, void *p),
 384         int irq,
 385         unsigned long flags,
 386         const struct iio_buffer_setup_ops *setup_ops)
 387 {
 388         struct iio_buffer *buffer;
 389         int ret;
 390
 391         buffer = devm_iio_kfifo_allocate(dev);
 392         if (!buffer)
 393                 return -ENOMEM;
 394
 395         iio_device_attach_buffer(indio_dev, buffer);
 396
 397         ret = devm_request_threaded_irq(dev, irq, pollfunc_th, pollfunc_bh,
 398                                 flags, indio_dev->name, indio_dev);
 399         if (ret)
 400                 goto error_kfifo_free;
 401
 402         indio_dev->setup_ops = setup_ops;
 403         indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
 404
 405         return 0;
 406
 407 error_kfifo_free:
 408         iio_kfifo_free(indio_dev->buffer);
 409         return ret;
 410 }
 411
 412 static const char * const chan_name_ain[] = {
 413         "AIN0",
 414         "AIN1",
 415         "AIN2",
 416         "AIN3",
 417         "AIN4",
 418         "AIN5",
 419         "AIN6",
 420         "AIN7",
 421 };
 422
 423 static int tiadc_channel_init(struct device *dev, struct iio_dev *indio_dev,
 424                               int channels)
 425 {
 426         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 427         struct iio_chan_spec *chan_array;
 428         struct iio_chan_spec *chan;
 429         int i;
 430
 431         indio_dev->num_channels = channels;
 432         chan_array = devm_kcalloc(dev, channels, sizeof(*chan_array),
 433                                   GFP_KERNEL);
 434         if (chan_array == NULL)
 435                 return -ENOMEM;
 436
 437         chan = chan_array;
 438         for (i = 0; i < channels; i++, chan++) {
 439
 440                 chan->type = IIO_VOLTAGE;
 441                 chan->indexed = 1;
 442                 chan->channel = adc_dev->channel_line[i];
 443                 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
 444                 chan->datasheet_name = chan_name_ain[chan->channel];
 445                 chan->scan_index = i;
 446                 chan->scan_type.sign = 'u';
 447                 chan->scan_type.realbits = 12;
 448                 chan->scan_type.storagebits = 16;
 449         }
 450
 451         indio_dev->channels = chan_array;
 452
 453         return 0;
 454 }
 455
 456 static int tiadc_read_raw(struct iio_dev *indio_dev,
 457                 struct iio_chan_spec const *chan,
 458                 int *val, int *val2, long mask)
 459 {
 460         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 461         int ret = IIO_VAL_INT;
 462         int i, map_val;
 463         unsigned int fifo1count, read, stepid;
 464         bool found = false;
 465         u32 step_en;
 466         unsigned long timeout;
 467
 468         if (iio_buffer_enabled(indio_dev))
 469                 return -EBUSY;
 470
 471         step_en = get_adc_chan_step_mask(adc_dev, chan);
 472         if (!step_en)
 473                 return -EINVAL;
 474
 475         mutex_lock(&adc_dev->fifo1_lock);
 476         fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 477         while (fifo1count--)
 478                 tiadc_readl(adc_dev, REG_FIFO1);
 479
 480         am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en);
 481
 482         timeout = jiffies + msecs_to_jiffies
 483                                 (IDLE_TIMEOUT * adc_dev->channels);
 484         /* Wait for Fifo threshold interrupt */
 485         while (1) {
 486                 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 487                 if (fifo1count)
 488                         break;
 489
 490                 if (time_after(jiffies, timeout)) {
 491                         am335x_tsc_se_adc_done(adc_dev->mfd_tscadc);
 492                         ret = -EAGAIN;
 493                         goto err_unlock;
 494                 }
 495         }
 496         map_val = adc_dev->channel_step[chan->scan_index];
 497
 498         /*
 499          * We check the complete FIFO. We programmed just one entry but in case
 500          * something went wrong we left empty handed (-EAGAIN previously) and
 501          * then the value apeared somehow in the FIFO we would have two entries.
 502          * Therefore we read every item and keep only the latest version of the
 503          * requested channel.
 504          */
 505         for (i = 0; i < fifo1count; i++) {
 506                 read = tiadc_readl(adc_dev, REG_FIFO1);
 507                 stepid = read & FIFOREAD_CHNLID_MASK;
 508                 stepid = stepid >> 0x10;
 509
 510                 if (stepid == map_val) {
 511                         read = read & FIFOREAD_DATA_MASK;
 512                         found = true;
 513                         *val = (u16) read;
 514                 }
 515         }
 516         am335x_tsc_se_adc_done(adc_dev->mfd_tscadc);
 517
 518         if (!found)
 519                 ret =  -EBUSY;
 520
 521 err_unlock:
 522         mutex_unlock(&adc_dev->fifo1_lock);
 523         return ret;
 524 }
 525
 526 static const struct iio_info tiadc_info = {
 527         .read_raw = &tiadc_read_raw,
 528 };
 529
 530 static int tiadc_request_dma(struct platform_device *pdev,
 531                              struct tiadc_device *adc_dev)
 532 {
 533         struct tiadc_dma        *dma = &adc_dev->dma;
 534         dma_cap_mask_t          mask;
 535
 536         /* Default slave configuration parameters */
 537         dma->conf.direction = DMA_DEV_TO_MEM;
 538         dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 539         dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1;
 540
 541         dma_cap_zero(mask);
 542         dma_cap_set(DMA_CYCLIC, mask);
 543
 544         /* Get a channel for RX */
 545         dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1");
 546         if (IS_ERR(dma->chan)) {
 547                 int ret = PTR_ERR(dma->chan);
 548
 549                 dma->chan = NULL;
 550                 return ret;
 551         }
 552
 553         /* RX buffer */
 554         dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
 555                                       &dma->addr, GFP_KERNEL);
 556         if (!dma->buf)
 557                 goto err;
 558
 559         return 0;
 560 err:
 561         dma_release_channel(dma->chan);
 562         return -ENOMEM;
 563 }
 564
 565 static int tiadc_parse_dt(struct platform_device *pdev,
 566                           struct tiadc_device *adc_dev)
 567 {
 568         struct device_node *node = pdev->dev.of_node;
 569         struct property *prop;
 570         const __be32 *cur;
 571         int channels = 0;
 572         u32 val;
 573
 574         of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
 575                 adc_dev->channel_line[channels] = val;
 576
 577                 /* Set Default values for optional DT parameters */
 578                 adc_dev->open_delay[channels] = STEPCONFIG_OPENDLY;
 579                 adc_dev->sample_delay[channels] = STEPCONFIG_SAMPLEDLY;
 580                 adc_dev->step_avg[channels] = 16;
 581
 582                 channels++;
 583         }
 584
 585         of_property_read_u32_array(node, "ti,chan-step-avg",
 586                                    adc_dev->step_avg, channels);
 587         of_property_read_u32_array(node, "ti,chan-step-opendelay",
 588                                    adc_dev->open_delay, channels);
 589         of_property_read_u32_array(node, "ti,chan-step-sampledelay",
 590                                    adc_dev->sample_delay, channels);
 591
 592         adc_dev->channels = channels;
 593         return 0;
 594 }
 595
 596 static int tiadc_probe(struct platform_device *pdev)
 597 {
 598         struct iio_dev          *indio_dev;
 599         struct tiadc_device     *adc_dev;
 600         struct device_node      *node = pdev->dev.of_node;
 601         int                     err;
 602
 603         if (!node) {
 604                 dev_err(&pdev->dev, "Could not find valid DT data.\n");
 605                 return -EINVAL;
 606         }
 607
 608         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
 609         if (indio_dev == NULL) {
 610                 dev_err(&pdev->dev, "failed to allocate iio device\n");
 611                 return -ENOMEM;
 612         }
 613         adc_dev = iio_priv(indio_dev);
 614
 615         adc_dev->mfd_tscadc = ti_tscadc_dev_get(pdev);
 616         tiadc_parse_dt(pdev, adc_dev);
 617
 618         indio_dev->name = dev_name(&pdev->dev);
 619         indio_dev->modes = INDIO_DIRECT_MODE;
 620         indio_dev->info = &tiadc_info;
 621
 622         tiadc_step_config(indio_dev);
 623         tiadc_writel(adc_dev, REG_FIFO1THR, FIFO1_THRESHOLD);
 624         mutex_init(&adc_dev->fifo1_lock);
 625
 626         err = tiadc_channel_init(&pdev->dev, indio_dev, adc_dev->channels);
 627         if (err < 0)
 628                 return err;
 629
 630         err = tiadc_iio_buffered_hardware_setup(&pdev->dev, indio_dev,
 631                 &tiadc_worker_h,
 632                 &tiadc_irq_h,
 633                 adc_dev->mfd_tscadc->irq,
 634                 IRQF_SHARED,
 635                 &tiadc_buffer_setup_ops);
 636
 637         if (err)
 638                 goto err_free_channels;
 639
 640         err = iio_device_register(indio_dev);
 641         if (err)
 642                 goto err_buffer_unregister;
 643
 644         platform_set_drvdata(pdev, indio_dev);
 645
 646         err = tiadc_request_dma(pdev, adc_dev);
 647         if (err && err == -EPROBE_DEFER)
 648                 goto err_dma;
 649
 650         return 0;
 651
 652 err_dma:
 653         iio_device_unregister(indio_dev);
 654 err_buffer_unregister:
 655 err_free_channels:
 656         return err;
 657 }
 658
 659 static int tiadc_remove(struct platform_device *pdev)
 660 {
 661         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 662         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 663         struct tiadc_dma *dma = &adc_dev->dma;
 664         u32 step_en;
 665
 666         if (dma->chan) {
 667                 dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
 668                                   dma->buf, dma->addr);
 669                 dma_release_channel(dma->chan);
 670         }
 671         iio_device_unregister(indio_dev);
 672
 673         step_en = get_adc_step_mask(adc_dev);
 674         am335x_tsc_se_clr(adc_dev->mfd_tscadc, step_en);
 675
 676         return 0;
 677 }
 678
 679 static int __maybe_unused tiadc_suspend(struct device *dev)
 680 {
 681         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 682         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 683         unsigned int idle;
 684
 685         idle = tiadc_readl(adc_dev, REG_CTRL);
 686         idle &= ~(CNTRLREG_TSCSSENB);
 687         tiadc_writel(adc_dev, REG_CTRL, (idle |
 688                         CNTRLREG_POWERDOWN));
 689
 690         return 0;
 691 }
 692
 693 static int __maybe_unused tiadc_resume(struct device *dev)
 694 {
 695         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 696         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 697         unsigned int restore;
 698
 699         /* Make sure ADC is powered up */
 700         restore = tiadc_readl(adc_dev, REG_CTRL);
 701         restore &= ~(CNTRLREG_POWERDOWN);
 702         tiadc_writel(adc_dev, REG_CTRL, restore);
 703
 704         tiadc_step_config(indio_dev);
 705         am335x_tsc_se_set_cache(adc_dev->mfd_tscadc,
 706                         adc_dev->buffer_en_ch_steps);
 707         return 0;
 708 }
 709
 710 static SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume);
 711
 712 static const struct of_device_id ti_adc_dt_ids[] = {
 713         { .compatible = "ti,am3359-adc", },
 714         { }
 715 };
 716 MODULE_DEVICE_TABLE(of, ti_adc_dt_ids);
 717
 718 static struct platform_driver tiadc_driver = {
 719         .driver = {
 720                 .name   = "TI-am335x-adc",
 721                 .pm     = &tiadc_pm_ops,
 722                 .of_match_table = ti_adc_dt_ids,
 723         },
 724         .probe  = tiadc_probe,
 725         .remove = tiadc_remove,
 726 };
 727 module_platform_driver(tiadc_driver);
 728
 729 MODULE_DESCRIPTION("TI ADC controller driver");
 730 MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
 731 MODULE_LICENSE("GPL");