drivers/iio/dac/ad5755.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * AD5755, AD5755-1, AD5757, AD5735, AD5737 Digital to analog converters driver
   4  *
   5  * Copyright 2012 Analog Devices Inc.
   6  */
   7
   8 #include <linux/device.h>
   9 #include <linux/err.h>
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/spi/spi.h>
  13 #include <linux/slab.h>
  14 #include <linux/sysfs.h>
  15 #include <linux/delay.h>
  16 #include <linux/of.h>
  17 #include <linux/iio/iio.h>
  18 #include <linux/iio/sysfs.h>
  19 #include <linux/platform_data/ad5755.h>
  20
  21 #define AD5755_NUM_CHANNELS 4
  22
  23 #define AD5755_ADDR(x)                  ((x) << 16)
  24
  25 #define AD5755_WRITE_REG_DATA(chan)     (chan)
  26 #define AD5755_WRITE_REG_GAIN(chan)     (0x08 | (chan))
  27 #define AD5755_WRITE_REG_OFFSET(chan)   (0x10 | (chan))
  28 #define AD5755_WRITE_REG_CTRL(chan)     (0x1c | (chan))
  29
  30 #define AD5755_READ_REG_DATA(chan)      (chan)
  31 #define AD5755_READ_REG_CTRL(chan)      (0x4 | (chan))
  32 #define AD5755_READ_REG_GAIN(chan)      (0x8 | (chan))
  33 #define AD5755_READ_REG_OFFSET(chan)    (0xc | (chan))
  34 #define AD5755_READ_REG_CLEAR(chan)     (0x10 | (chan))
  35 #define AD5755_READ_REG_SLEW(chan)      (0x14 | (chan))
  36 #define AD5755_READ_REG_STATUS          0x18
  37 #define AD5755_READ_REG_MAIN            0x19
  38 #define AD5755_READ_REG_DC_DC           0x1a
  39
  40 #define AD5755_CTRL_REG_SLEW    0x0
  41 #define AD5755_CTRL_REG_MAIN    0x1
  42 #define AD5755_CTRL_REG_DAC     0x2
  43 #define AD5755_CTRL_REG_DC_DC   0x3
  44 #define AD5755_CTRL_REG_SW      0x4
  45
  46 #define AD5755_READ_FLAG 0x800000
  47
  48 #define AD5755_NOOP 0x1CE000
  49
  50 #define AD5755_DAC_INT_EN                       BIT(8)
  51 #define AD5755_DAC_CLR_EN                       BIT(7)
  52 #define AD5755_DAC_OUT_EN                       BIT(6)
  53 #define AD5755_DAC_INT_CURRENT_SENSE_RESISTOR   BIT(5)
  54 #define AD5755_DAC_DC_DC_EN                     BIT(4)
  55 #define AD5755_DAC_VOLTAGE_OVERRANGE_EN         BIT(3)
  56
  57 #define AD5755_DC_DC_MAXV                       0
  58 #define AD5755_DC_DC_FREQ_SHIFT                 2
  59 #define AD5755_DC_DC_PHASE_SHIFT                4
  60 #define AD5755_EXT_DC_DC_COMP_RES               BIT(6)
  61
  62 #define AD5755_SLEW_STEP_SIZE_SHIFT             0
  63 #define AD5755_SLEW_RATE_SHIFT                  3
  64 #define AD5755_SLEW_ENABLE                      BIT(12)
  65
  66 /**
  67  * struct ad5755_chip_info - chip specific information
  68  * @channel_template:   channel specification
  69  * @calib_shift:        shift for the calibration data registers
  70  * @has_voltage_out:    whether the chip has voltage outputs
  71  */
  72 struct ad5755_chip_info {
  73         const struct iio_chan_spec channel_template;
  74         unsigned int calib_shift;
  75         bool has_voltage_out;
  76 };
  77
  78 /**
  79  * struct ad5755_state - driver instance specific data
  80  * @spi:        spi device the driver is attached to
  81  * @chip_info:  chip model specific constants, available modes etc
  82  * @pwr_down:   bitmask which contains  hether a channel is powered down or not
  83  * @ctrl:       software shadow of the channel ctrl registers
  84  * @channels:   iio channel spec for the device
  85  * @lock:       lock to protect the data buffer during SPI ops
  86  * @data:       spi transfer buffers
  87  */
  88 struct ad5755_state {
  89         struct spi_device               *spi;
  90         const struct ad5755_chip_info   *chip_info;
  91         unsigned int                    pwr_down;
  92         unsigned int                    ctrl[AD5755_NUM_CHANNELS];
  93         struct iio_chan_spec            channels[AD5755_NUM_CHANNELS];
  94         struct mutex                    lock;
  95
  96         /*
  97          * DMA (thus cache coherency maintenance) requires the
  98          * transfer buffers to live in their own cache lines.
  99          */
 100
 101         union {
 102                 __be32 d32;
 103                 u8 d8[4];
 104         } data[2] ____cacheline_aligned;
 105 };
 106
 107 enum ad5755_type {
 108         ID_AD5755,
 109         ID_AD5757,
 110         ID_AD5735,
 111         ID_AD5737,
 112 };
 113
 114 #ifdef CONFIG_OF
 115 static const int ad5755_dcdc_freq_table[][2] = {
 116         { 250000, AD5755_DC_DC_FREQ_250kHZ },
 117         { 410000, AD5755_DC_DC_FREQ_410kHZ },
 118         { 650000, AD5755_DC_DC_FREQ_650kHZ }
 119 };
 120
 121 static const int ad5755_dcdc_maxv_table[][2] = {
 122         { 23000000, AD5755_DC_DC_MAXV_23V },
 123         { 24500000, AD5755_DC_DC_MAXV_24V5 },
 124         { 27000000, AD5755_DC_DC_MAXV_27V },
 125         { 29500000, AD5755_DC_DC_MAXV_29V5 },
 126 };
 127
 128 static const int ad5755_slew_rate_table[][2] = {
 129         { 64000, AD5755_SLEW_RATE_64k },
 130         { 32000, AD5755_SLEW_RATE_32k },
 131         { 16000, AD5755_SLEW_RATE_16k },
 132         { 8000, AD5755_SLEW_RATE_8k },
 133         { 4000, AD5755_SLEW_RATE_4k },
 134         { 2000, AD5755_SLEW_RATE_2k },
 135         { 1000, AD5755_SLEW_RATE_1k },
 136         { 500, AD5755_SLEW_RATE_500 },
 137         { 250, AD5755_SLEW_RATE_250 },
 138         { 125, AD5755_SLEW_RATE_125 },
 139         { 64, AD5755_SLEW_RATE_64 },
 140         { 32, AD5755_SLEW_RATE_32 },
 141         { 16, AD5755_SLEW_RATE_16 },
 142         { 8, AD5755_SLEW_RATE_8 },
 143         { 4, AD5755_SLEW_RATE_4 },
 144         { 0, AD5755_SLEW_RATE_0_5 },
 145 };
 146
 147 static const int ad5755_slew_step_table[][2] = {
 148         { 256, AD5755_SLEW_STEP_SIZE_256 },
 149         { 128, AD5755_SLEW_STEP_SIZE_128 },
 150         { 64, AD5755_SLEW_STEP_SIZE_64 },
 151         { 32, AD5755_SLEW_STEP_SIZE_32 },
 152         { 16, AD5755_SLEW_STEP_SIZE_16 },
 153         { 4, AD5755_SLEW_STEP_SIZE_4 },
 154         { 2, AD5755_SLEW_STEP_SIZE_2 },
 155         { 1, AD5755_SLEW_STEP_SIZE_1 },
 156 };
 157 #endif
 158
 159 static int ad5755_write_unlocked(struct iio_dev *indio_dev,
 160         unsigned int reg, unsigned int val)
 161 {
 162         struct ad5755_state *st = iio_priv(indio_dev);
 163
 164         st->data[0].d32 = cpu_to_be32((reg << 16) | val);
 165
 166         return spi_write(st->spi, &st->data[0].d8[1], 3);
 167 }
 168
 169 static int ad5755_write_ctrl_unlocked(struct iio_dev *indio_dev,
 170         unsigned int channel, unsigned int reg, unsigned int val)
 171 {
 172         return ad5755_write_unlocked(indio_dev,
 173                 AD5755_WRITE_REG_CTRL(channel), (reg << 13) | val);
 174 }
 175
 176 static int ad5755_write(struct iio_dev *indio_dev, unsigned int reg,
 177         unsigned int val)
 178 {
 179         struct ad5755_state *st = iio_priv(indio_dev);
 180         int ret;
 181
 182         mutex_lock(&st->lock);
 183         ret = ad5755_write_unlocked(indio_dev, reg, val);
 184         mutex_unlock(&st->lock);
 185
 186         return ret;
 187 }
 188
 189 static int ad5755_write_ctrl(struct iio_dev *indio_dev, unsigned int channel,
 190         unsigned int reg, unsigned int val)
 191 {
 192         struct ad5755_state *st = iio_priv(indio_dev);
 193         int ret;
 194
 195         mutex_lock(&st->lock);
 196         ret = ad5755_write_ctrl_unlocked(indio_dev, channel, reg, val);
 197         mutex_unlock(&st->lock);
 198
 199         return ret;
 200 }
 201
 202 static int ad5755_read(struct iio_dev *indio_dev, unsigned int addr)
 203 {
 204         struct ad5755_state *st = iio_priv(indio_dev);
 205         int ret;
 206         struct spi_transfer t[] = {
 207                 {
 208                         .tx_buf = &st->data[0].d8[1],
 209                         .len = 3,
 210                         .cs_change = 1,
 211                 }, {
 212                         .tx_buf = &st->data[1].d8[1],
 213                         .rx_buf = &st->data[1].d8[1],
 214                         .len = 3,
 215                 },
 216         };
 217
 218         mutex_lock(&st->lock);
 219
 220         st->data[0].d32 = cpu_to_be32(AD5755_READ_FLAG | (addr << 16));
 221         st->data[1].d32 = cpu_to_be32(AD5755_NOOP);
 222
 223         ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
 224         if (ret >= 0)
 225                 ret = be32_to_cpu(st->data[1].d32) & 0xffff;
 226
 227         mutex_unlock(&st->lock);
 228
 229         return ret;
 230 }
 231
 232 static int ad5755_update_dac_ctrl(struct iio_dev *indio_dev,
 233         unsigned int channel, unsigned int set, unsigned int clr)
 234 {
 235         struct ad5755_state *st = iio_priv(indio_dev);
 236         int ret;
 237
 238         st->ctrl[channel] |= set;
 239         st->ctrl[channel] &= ~clr;
 240
 241         ret = ad5755_write_ctrl_unlocked(indio_dev, channel,
 242                 AD5755_CTRL_REG_DAC, st->ctrl[channel]);
 243
 244         return ret;
 245 }
 246
 247 static int ad5755_set_channel_pwr_down(struct iio_dev *indio_dev,
 248         unsigned int channel, bool pwr_down)
 249 {
 250         struct ad5755_state *st = iio_priv(indio_dev);
 251         unsigned int mask = BIT(channel);
 252
 253         mutex_lock(&st->lock);
 254
 255         if ((bool)(st->pwr_down & mask) == pwr_down)
 256                 goto out_unlock;
 257
 258         if (!pwr_down) {
 259                 st->pwr_down &= ~mask;
 260                 ad5755_update_dac_ctrl(indio_dev, channel,
 261                         AD5755_DAC_INT_EN | AD5755_DAC_DC_DC_EN, 0);
 262                 udelay(200);
 263                 ad5755_update_dac_ctrl(indio_dev, channel,
 264                         AD5755_DAC_OUT_EN, 0);
 265         } else {
 266                 st->pwr_down |= mask;
 267                 ad5755_update_dac_ctrl(indio_dev, channel,
 268                         0, AD5755_DAC_INT_EN | AD5755_DAC_OUT_EN |
 269                                 AD5755_DAC_DC_DC_EN);
 270         }
 271
 272 out_unlock:
 273         mutex_unlock(&st->lock);
 274
 275         return 0;
 276 }
 277
 278 static const int ad5755_min_max_table[][2] = {
 279         [AD5755_MODE_VOLTAGE_0V_5V] = { 0, 5000 },
 280         [AD5755_MODE_VOLTAGE_0V_10V] = { 0, 10000 },
 281         [AD5755_MODE_VOLTAGE_PLUSMINUS_5V] = { -5000, 5000 },
 282         [AD5755_MODE_VOLTAGE_PLUSMINUS_10V] = { -10000, 10000 },
 283         [AD5755_MODE_CURRENT_4mA_20mA] = { 4, 20 },
 284         [AD5755_MODE_CURRENT_0mA_20mA] = { 0, 20 },
 285         [AD5755_MODE_CURRENT_0mA_24mA] = { 0, 24 },
 286 };
 287
 288 static void ad5755_get_min_max(struct ad5755_state *st,
 289         struct iio_chan_spec const *chan, int *min, int *max)
 290 {
 291         enum ad5755_mode mode = st->ctrl[chan->channel] & 7;
 292         *min = ad5755_min_max_table[mode][0];
 293         *max = ad5755_min_max_table[mode][1];
 294 }
 295
 296 static inline int ad5755_get_offset(struct ad5755_state *st,
 297         struct iio_chan_spec const *chan)
 298 {
 299         int min, max;
 300
 301         ad5755_get_min_max(st, chan, &min, &max);
 302         return (min * (1 << chan->scan_type.realbits)) / (max - min);
 303 }
 304
 305 static int ad5755_chan_reg_info(struct ad5755_state *st,
 306         struct iio_chan_spec const *chan, long info, bool write,
 307         unsigned int *reg, unsigned int *shift, unsigned int *offset)
 308 {
 309         switch (info) {
 310         case IIO_CHAN_INFO_RAW:
 311                 if (write)
 312                         *reg = AD5755_WRITE_REG_DATA(chan->address);
 313                 else
 314                         *reg = AD5755_READ_REG_DATA(chan->address);
 315                 *shift = chan->scan_type.shift;
 316                 *offset = 0;
 317                 break;
 318         case IIO_CHAN_INFO_CALIBBIAS:
 319                 if (write)
 320                         *reg = AD5755_WRITE_REG_OFFSET(chan->address);
 321                 else
 322                         *reg = AD5755_READ_REG_OFFSET(chan->address);
 323                 *shift = st->chip_info->calib_shift;
 324                 *offset = 32768;
 325                 break;
 326         case IIO_CHAN_INFO_CALIBSCALE:
 327                 if (write)
 328                         *reg =  AD5755_WRITE_REG_GAIN(chan->address);
 329                 else
 330                         *reg =  AD5755_READ_REG_GAIN(chan->address);
 331                 *shift = st->chip_info->calib_shift;
 332                 *offset = 0;
 333                 break;
 334         default:
 335                 return -EINVAL;
 336         }
 337
 338         return 0;
 339 }
 340
 341 static int ad5755_read_raw(struct iio_dev *indio_dev,
 342         const struct iio_chan_spec *chan, int *val, int *val2, long info)
 343 {
 344         struct ad5755_state *st = iio_priv(indio_dev);
 345         unsigned int reg, shift, offset;
 346         int min, max;
 347         int ret;
 348
 349         switch (info) {
 350         case IIO_CHAN_INFO_SCALE:
 351                 ad5755_get_min_max(st, chan, &min, &max);
 352                 *val = max - min;
 353                 *val2 = chan->scan_type.realbits;
 354                 return IIO_VAL_FRACTIONAL_LOG2;
 355         case IIO_CHAN_INFO_OFFSET:
 356                 *val = ad5755_get_offset(st, chan);
 357                 return IIO_VAL_INT;
 358         default:
 359                 ret = ad5755_chan_reg_info(st, chan, info, false,
 360                                                 &reg, &shift, &offset);
 361                 if (ret)
 362                         return ret;
 363
 364                 ret = ad5755_read(indio_dev, reg);
 365                 if (ret < 0)
 366                         return ret;
 367
 368                 *val = (ret - offset) >> shift;
 369
 370                 return IIO_VAL_INT;
 371         }
 372
 373         return -EINVAL;
 374 }
 375
 376 static int ad5755_write_raw(struct iio_dev *indio_dev,
 377         const struct iio_chan_spec *chan, int val, int val2, long info)
 378 {
 379         struct ad5755_state *st = iio_priv(indio_dev);
 380         unsigned int shift, reg, offset;
 381         int ret;
 382
 383         ret = ad5755_chan_reg_info(st, chan, info, true,
 384                                         &reg, &shift, &offset);
 385         if (ret)
 386                 return ret;
 387
 388         val <<= shift;
 389         val += offset;
 390
 391         if (val < 0 || val > 0xffff)
 392                 return -EINVAL;
 393
 394         return ad5755_write(indio_dev, reg, val);
 395 }
 396
 397 static ssize_t ad5755_read_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
 398         const struct iio_chan_spec *chan, char *buf)
 399 {
 400         struct ad5755_state *st = iio_priv(indio_dev);
 401
 402         return sprintf(buf, "%d\n",
 403                        (bool)(st->pwr_down & (1 << chan->channel)));
 404 }
 405
 406 static ssize_t ad5755_write_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
 407         struct iio_chan_spec const *chan, const char *buf, size_t len)
 408 {
 409         bool pwr_down;
 410         int ret;
 411
 412         ret = strtobool(buf, &pwr_down);
 413         if (ret)
 414                 return ret;
 415
 416         ret = ad5755_set_channel_pwr_down(indio_dev, chan->channel, pwr_down);
 417         return ret ? ret : len;
 418 }
 419
 420 static const struct iio_info ad5755_info = {
 421         .read_raw = ad5755_read_raw,
 422         .write_raw = ad5755_write_raw,
 423 };
 424
 425 static const struct iio_chan_spec_ext_info ad5755_ext_info[] = {
 426         {
 427                 .name = "powerdown",
 428                 .read = ad5755_read_powerdown,
 429                 .write = ad5755_write_powerdown,
 430                 .shared = IIO_SEPARATE,
 431         },
 432         { },
 433 };
 434
 435 #define AD5755_CHANNEL(_bits) {                                 \
 436         .indexed = 1,                                           \
 437         .output = 1,                                            \
 438         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
 439                 BIT(IIO_CHAN_INFO_SCALE) |                      \
 440                 BIT(IIO_CHAN_INFO_OFFSET) |                     \
 441                 BIT(IIO_CHAN_INFO_CALIBSCALE) |                 \
 442                 BIT(IIO_CHAN_INFO_CALIBBIAS),                   \
 443         .scan_type = {                                          \
 444                 .sign = 'u',                                    \
 445                 .realbits = (_bits),                            \
 446                 .storagebits = 16,                              \
 447                 .shift = 16 - (_bits),                          \
 448         },                                                      \
 449         .ext_info = ad5755_ext_info,                            \
 450 }
 451
 452 static const struct ad5755_chip_info ad5755_chip_info_tbl[] = {
 453         [ID_AD5735] = {
 454                 .channel_template = AD5755_CHANNEL(14),
 455                 .has_voltage_out = true,
 456                 .calib_shift = 4,
 457         },
 458         [ID_AD5737] = {
 459                 .channel_template = AD5755_CHANNEL(14),
 460                 .has_voltage_out = false,
 461                 .calib_shift = 4,
 462         },
 463         [ID_AD5755] = {
 464                 .channel_template = AD5755_CHANNEL(16),
 465                 .has_voltage_out = true,
 466                 .calib_shift = 0,
 467         },
 468         [ID_AD5757] = {
 469                 .channel_template = AD5755_CHANNEL(16),
 470                 .has_voltage_out = false,
 471                 .calib_shift = 0,
 472         },
 473 };
 474
 475 static bool ad5755_is_valid_mode(struct ad5755_state *st, enum ad5755_mode mode)
 476 {
 477         switch (mode) {
 478         case AD5755_MODE_VOLTAGE_0V_5V:
 479         case AD5755_MODE_VOLTAGE_0V_10V:
 480         case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
 481         case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
 482                 return st->chip_info->has_voltage_out;
 483         case AD5755_MODE_CURRENT_4mA_20mA:
 484         case AD5755_MODE_CURRENT_0mA_20mA:
 485         case AD5755_MODE_CURRENT_0mA_24mA:
 486                 return true;
 487         default:
 488                 return false;
 489         }
 490 }
 491
 492 static int ad5755_setup_pdata(struct iio_dev *indio_dev,
 493                               const struct ad5755_platform_data *pdata)
 494 {
 495         struct ad5755_state *st = iio_priv(indio_dev);
 496         unsigned int val;
 497         unsigned int i;
 498         int ret;
 499
 500         if (pdata->dc_dc_phase > AD5755_DC_DC_PHASE_90_DEGREE ||
 501                 pdata->dc_dc_freq > AD5755_DC_DC_FREQ_650kHZ ||
 502                 pdata->dc_dc_maxv > AD5755_DC_DC_MAXV_29V5)
 503                 return -EINVAL;
 504
 505         val = pdata->dc_dc_maxv << AD5755_DC_DC_MAXV;
 506         val |= pdata->dc_dc_freq << AD5755_DC_DC_FREQ_SHIFT;
 507         val |= pdata->dc_dc_phase << AD5755_DC_DC_PHASE_SHIFT;
 508         if (pdata->ext_dc_dc_compenstation_resistor)
 509                 val |= AD5755_EXT_DC_DC_COMP_RES;
 510
 511         ret = ad5755_write_ctrl(indio_dev, 0, AD5755_CTRL_REG_DC_DC, val);
 512         if (ret < 0)
 513                 return ret;
 514
 515         for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
 516                 val = pdata->dac[i].slew.step_size <<
 517                         AD5755_SLEW_STEP_SIZE_SHIFT;
 518                 val |= pdata->dac[i].slew.rate <<
 519                         AD5755_SLEW_RATE_SHIFT;
 520                 if (pdata->dac[i].slew.enable)
 521                         val |= AD5755_SLEW_ENABLE;
 522
 523                 ret = ad5755_write_ctrl(indio_dev, i,
 524                                         AD5755_CTRL_REG_SLEW, val);
 525                 if (ret < 0)
 526                         return ret;
 527         }
 528
 529         for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
 530                 if (!ad5755_is_valid_mode(st, pdata->dac[i].mode))
 531                         return -EINVAL;
 532
 533                 val = 0;
 534                 if (!pdata->dac[i].ext_current_sense_resistor)
 535                         val |= AD5755_DAC_INT_CURRENT_SENSE_RESISTOR;
 536                 if (pdata->dac[i].enable_voltage_overrange)
 537                         val |= AD5755_DAC_VOLTAGE_OVERRANGE_EN;
 538                 val |= pdata->dac[i].mode;
 539
 540                 ret = ad5755_update_dac_ctrl(indio_dev, i, val, 0);
 541                 if (ret < 0)
 542                         return ret;
 543         }
 544
 545         return 0;
 546 }
 547
 548 static bool ad5755_is_voltage_mode(enum ad5755_mode mode)
 549 {
 550         switch (mode) {
 551         case AD5755_MODE_VOLTAGE_0V_5V:
 552         case AD5755_MODE_VOLTAGE_0V_10V:
 553         case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
 554         case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
 555                 return true;
 556         default:
 557                 return false;
 558         }
 559 }
 560
 561 static int ad5755_init_channels(struct iio_dev *indio_dev,
 562                                 const struct ad5755_platform_data *pdata)
 563 {
 564         struct ad5755_state *st = iio_priv(indio_dev);
 565         struct iio_chan_spec *channels = st->channels;
 566         unsigned int i;
 567
 568         for (i = 0; i < AD5755_NUM_CHANNELS; ++i) {
 569                 channels[i] = st->chip_info->channel_template;
 570                 channels[i].channel = i;
 571                 channels[i].address = i;
 572                 if (pdata && ad5755_is_voltage_mode(pdata->dac[i].mode))
 573                         channels[i].type = IIO_VOLTAGE;
 574                 else
 575                         channels[i].type = IIO_CURRENT;
 576         }
 577
 578         indio_dev->channels = channels;
 579
 580         return 0;
 581 }
 582
 583 #define AD5755_DEFAULT_DAC_PDATA { \
 584                 .mode = AD5755_MODE_CURRENT_4mA_20mA, \
 585                 .ext_current_sense_resistor = true, \
 586                 .enable_voltage_overrange = false, \
 587                 .slew = { \
 588                         .enable = false, \
 589                         .rate = AD5755_SLEW_RATE_64k, \
 590                         .step_size = AD5755_SLEW_STEP_SIZE_1, \
 591                 }, \
 592         }
 593
 594 static const struct ad5755_platform_data ad5755_default_pdata = {
 595         .ext_dc_dc_compenstation_resistor = false,
 596         .dc_dc_phase = AD5755_DC_DC_PHASE_ALL_SAME_EDGE,
 597         .dc_dc_freq = AD5755_DC_DC_FREQ_410kHZ,
 598         .dc_dc_maxv = AD5755_DC_DC_MAXV_23V,
 599         .dac = {
 600                 [0] = AD5755_DEFAULT_DAC_PDATA,
 601                 [1] = AD5755_DEFAULT_DAC_PDATA,
 602                 [2] = AD5755_DEFAULT_DAC_PDATA,
 603                 [3] = AD5755_DEFAULT_DAC_PDATA,
 604         },
 605 };
 606
 607 #ifdef CONFIG_OF
 608 static struct ad5755_platform_data *ad5755_parse_dt(struct device *dev)
 609 {
 610         struct device_node *np = dev->of_node;
 611         struct device_node *pp;
 612         struct ad5755_platform_data *pdata;
 613         unsigned int tmp;
 614         unsigned int tmparray[3];
 615         int devnr, i;
 616
 617         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 618         if (!pdata)
 619                 return NULL;
 620
 621         pdata->ext_dc_dc_compenstation_resistor =
 622             of_property_read_bool(np, "adi,ext-dc-dc-compenstation-resistor");
 623
 624         if (!of_property_read_u32(np, "adi,dc-dc-phase", &tmp))
 625                 pdata->dc_dc_phase = tmp;
 626         else
 627                 pdata->dc_dc_phase = AD5755_DC_DC_PHASE_ALL_SAME_EDGE;
 628
 629         pdata->dc_dc_freq = AD5755_DC_DC_FREQ_410kHZ;
 630         if (!of_property_read_u32(np, "adi,dc-dc-freq-hz", &tmp)) {
 631                 for (i = 0; i < ARRAY_SIZE(ad5755_dcdc_freq_table); i++) {
 632                         if (tmp == ad5755_dcdc_freq_table[i][0]) {
 633                                 pdata->dc_dc_freq = ad5755_dcdc_freq_table[i][1];
 634                                 break;
 635                         }
 636                 }
 637
 638                 if (i == ARRAY_SIZE(ad5755_dcdc_freq_table))
 639                         dev_err(dev,
 640                                 "adi,dc-dc-freq out of range selecting 410kHz\n");
 641         }
 642
 643         pdata->dc_dc_maxv = AD5755_DC_DC_MAXV_23V;
 644         if (!of_property_read_u32(np, "adi,dc-dc-max-microvolt", &tmp)) {
 645                 for (i = 0; i < ARRAY_SIZE(ad5755_dcdc_maxv_table); i++) {
 646                         if (tmp == ad5755_dcdc_maxv_table[i][0]) {
 647                                 pdata->dc_dc_maxv = ad5755_dcdc_maxv_table[i][1];
 648                                 break;
 649                         }
 650                 }
 651                 if (i == ARRAY_SIZE(ad5755_dcdc_maxv_table))
 652                                 dev_err(dev,
 653                                         "adi,dc-dc-maxv out of range selecting 23V\n");
 654         }
 655
 656         devnr = 0;
 657         for_each_child_of_node(np, pp) {
 658                 if (devnr >= AD5755_NUM_CHANNELS) {
 659                         dev_err(dev,
 660                                 "There are too many channels defined in DT\n");
 661                         goto error_out;
 662                 }
 663
 664                 if (!of_property_read_u32(pp, "adi,mode", &tmp))
 665                         pdata->dac[devnr].mode = tmp;
 666                 else
 667                         pdata->dac[devnr].mode = AD5755_MODE_CURRENT_4mA_20mA;
 668
 669                 pdata->dac[devnr].ext_current_sense_resistor =
 670                     of_property_read_bool(pp, "adi,ext-current-sense-resistor");
 671
 672                 pdata->dac[devnr].enable_voltage_overrange =
 673                     of_property_read_bool(pp, "adi,enable-voltage-overrange");
 674
 675                 if (!of_property_read_u32_array(pp, "adi,slew", tmparray, 3)) {
 676                         pdata->dac[devnr].slew.enable = tmparray[0];
 677
 678                         pdata->dac[devnr].slew.rate = AD5755_SLEW_RATE_64k;
 679                         for (i = 0; i < ARRAY_SIZE(ad5755_slew_rate_table); i++) {
 680                                 if (tmparray[1] == ad5755_slew_rate_table[i][0]) {
 681                                         pdata->dac[devnr].slew.rate =
 682                                                 ad5755_slew_rate_table[i][1];
 683                                         break;
 684                                 }
 685                         }
 686                         if (i == ARRAY_SIZE(ad5755_slew_rate_table))
 687                                 dev_err(dev,
 688                                         "channel %d slew rate out of range selecting 64kHz\n",
 689                                         devnr);
 690
 691                         pdata->dac[devnr].slew.step_size = AD5755_SLEW_STEP_SIZE_1;
 692                         for (i = 0; i < ARRAY_SIZE(ad5755_slew_step_table); i++) {
 693                                 if (tmparray[2] == ad5755_slew_step_table[i][0]) {
 694                                         pdata->dac[devnr].slew.step_size =
 695                                                 ad5755_slew_step_table[i][1];
 696                                         break;
 697                                 }
 698                         }
 699                         if (i == ARRAY_SIZE(ad5755_slew_step_table))
 700                                 dev_err(dev,
 701                                         "channel %d slew step size out of range selecting 1 LSB\n",
 702                                         devnr);
 703                 } else {
 704                         pdata->dac[devnr].slew.enable = false;
 705                         pdata->dac[devnr].slew.rate = AD5755_SLEW_RATE_64k;
 706                         pdata->dac[devnr].slew.step_size =
 707                             AD5755_SLEW_STEP_SIZE_1;
 708                 }
 709                 devnr++;
 710         }
 711
 712         return pdata;
 713
 714  error_out:
 715         devm_kfree(dev, pdata);
 716         return NULL;
 717 }
 718 #else
 719 static
 720 struct ad5755_platform_data *ad5755_parse_dt(struct device *dev)
 721 {
 722         return NULL;
 723 }
 724 #endif
 725
 726 static int ad5755_probe(struct spi_device *spi)
 727 {
 728         enum ad5755_type type = spi_get_device_id(spi)->driver_data;
 729         const struct ad5755_platform_data *pdata = dev_get_platdata(&spi->dev);
 730         struct iio_dev *indio_dev;
 731         struct ad5755_state *st;
 732         int ret;
 733
 734         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 735         if (indio_dev == NULL) {
 736                 dev_err(&spi->dev, "Failed to allocate iio device\n");
 737                 return  -ENOMEM;
 738         }
 739
 740         st = iio_priv(indio_dev);
 741         spi_set_drvdata(spi, indio_dev);
 742
 743         st->chip_info = &ad5755_chip_info_tbl[type];
 744         st->spi = spi;
 745         st->pwr_down = 0xf;
 746
 747         indio_dev->name = spi_get_device_id(spi)->name;
 748         indio_dev->info = &ad5755_info;
 749         indio_dev->modes = INDIO_DIRECT_MODE;
 750         indio_dev->num_channels = AD5755_NUM_CHANNELS;
 751
 752         mutex_init(&st->lock);
 753
 754         if (spi->dev.of_node)
 755                 pdata = ad5755_parse_dt(&spi->dev);
 756         else
 757                 pdata = spi->dev.platform_data;
 758
 759         if (!pdata) {
 760                 dev_warn(&spi->dev, "no platform data? using default\n");
 761                 pdata = &ad5755_default_pdata;
 762         }
 763
 764         ret = ad5755_init_channels(indio_dev, pdata);
 765         if (ret)
 766                 return ret;
 767
 768         ret = ad5755_setup_pdata(indio_dev, pdata);
 769         if (ret)
 770                 return ret;
 771
 772         return devm_iio_device_register(&spi->dev, indio_dev);
 773 }
 774
 775 static const struct spi_device_id ad5755_id[] = {
 776         { "ad5755", ID_AD5755 },
 777         { "ad5755-1", ID_AD5755 },
 778         { "ad5757", ID_AD5757 },
 779         { "ad5735", ID_AD5735 },
 780         { "ad5737", ID_AD5737 },
 781         {}
 782 };
 783 MODULE_DEVICE_TABLE(spi, ad5755_id);
 784
 785 static const struct of_device_id ad5755_of_match[] = {
 786         { .compatible = "adi,ad5755" },
 787         { .compatible = "adi,ad5755-1" },
 788         { .compatible = "adi,ad5757" },
 789         { .compatible = "adi,ad5735" },
 790         { .compatible = "adi,ad5737" },
 791         { }
 792 };
 793 MODULE_DEVICE_TABLE(of, ad5755_of_match);
 794
 795 static struct spi_driver ad5755_driver = {
 796         .driver = {
 797                 .name = "ad5755",
 798         },
 799         .probe = ad5755_probe,
 800         .id_table = ad5755_id,
 801 };
 802 module_spi_driver(ad5755_driver);
 803
 804 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 805 MODULE_DESCRIPTION("Analog Devices AD5755/55-1/57/35/37 DAC");
 806 MODULE_LICENSE("GPL v2");