1 // SPDX-License-Identifier: GPL-2.0
3 * ARM Message Handling Unit Version 2 (MHUv2) driver.
5 * Copyright (C) 2020 ARM Ltd.
6 * Copyright (C) 2020 Linaro Ltd.
8 * An MHUv2 mailbox controller can provide up to 124 channel windows (each 32
9 * bit long) and the driver allows any combination of both the transport
10 * protocol modes: data-transfer and doorbell, to be used on those channel
13 * The transport protocols should be specified in the device tree entry for the
14 * device. The transport protocols determine how the underlying hardware
15 * resources of the device are utilized when transmitting data. Refer to the
16 * device tree bindings of the ARM MHUv2 controller for more details.
18 * The number of registered mailbox channels is dependent on both the underlying
19 * hardware - mainly the number of channel windows implemented by the platform,
20 * as well as the selected transport protocols.
22 * The MHUv2 controller can work both as a sender and receiver, but the driver
23 * and the DT bindings support unidirectional transfers for better allocation of
24 * the channels. That is, this driver will be probed for two separate devices
25 * for each mailbox controller, a sender device and a receiver device.
28 #include <linux/amba/bus.h>
29 #include <linux/interrupt.h>
30 #include <linux/mailbox_controller.h>
31 #include <linux/mailbox/arm_mhuv2_message.h>
32 #include <linux/module.h>
33 #include <linux/of_address.h>
34 #include <linux/spinlock.h>
36 /* ====== MHUv2 Registers ====== */
38 /* Maximum number of channel windows */
39 #define MHUV2_CH_WN_MAX 124
40 /* Number of combined interrupt status registers */
41 #define MHUV2_CMB_INT_ST_REG_CNT 4
42 #define MHUV2_STAT_BYTES (sizeof(u32))
43 #define MHUV2_STAT_BITS (MHUV2_STAT_BYTES * __CHAR_BIT__)
45 #define LSB_MASK(n) ((1 << (n * __CHAR_BIT__)) - 1)
46 #define MHUV2_PROTOCOL_PROP "arm,mhuv2-protocols"
48 /* Register Message Handling Unit Configuration fields */
54 /* register Interrupt Status fields */
61 /* Register Interrupt Clear fields */
68 /* Register Interrupt Enable fields */
76 /* Register Implementer Identification fields */
84 /* Register Architecture Identification Register fields */
86 u32 arch_minor_rev
: 4;
87 u32 arch_major_rev
: 4;
91 /* Sender Channel Window fields */
92 struct mhu2_send_ch_wn_reg
{
102 /* Sender frame register fields */
103 struct mhu2_send_frame_reg
{
104 struct mhu2_send_ch_wn_reg ch_wn
[MHUV2_CH_WN_MAX
];
105 struct mhu_cfg_t mhu_cfg
;
109 struct int_st_t int_st
;
110 struct int_clr_t int_clr
;
111 struct int_en_t int_en
;
113 u32 chcomb_int_st
[MHUV2_CMB_INT_ST_REG_CNT
];
114 u8 pad
[0xFC8 - 0xFB0];
119 /* Receiver Channel Window fields */
120 struct mhu2_recv_ch_wn_reg
{
124 u8 reserved0
[0x10 - 0x0C];
131 /* Receiver frame register fields */
132 struct mhu2_recv_frame_reg
{
133 struct mhu2_recv_ch_wn_reg ch_wn
[MHUV2_CH_WN_MAX
];
134 struct mhu_cfg_t mhu_cfg
;
135 u8 reserved0
[0xF90 - 0xF84];
136 struct int_st_t int_st
;
137 struct int_clr_t int_clr
;
138 struct int_en_t int_en
;
140 u32 chcomb_int_st
[MHUV2_CMB_INT_ST_REG_CNT
];
141 u8 reserved2
[0xFC8 - 0xFB0];
147 /* ====== MHUv2 data structures ====== */
149 enum mhuv2_transport_protocol
{
160 * struct mhuv2 - MHUv2 mailbox controller data
162 * @mbox: Mailbox controller belonging to the MHU frame.
163 * @send/recv: Base address of the register mapping region.
164 * @frame: Frame type: RECEIVER_FRAME or SENDER_FRAME.
166 * @windows: Channel windows implemented by the platform.
167 * @minor: Minor version of the controller.
168 * @length: Length of the protocols array in bytes.
169 * @protocols: Raw protocol information, derived from device tree.
170 * @doorbell_pending_lock: spinlock required for correct operation of Tx
171 * interrupt for doorbells.
174 struct mbox_controller mbox
;
176 struct mhu2_send_frame_reg __iomem
*send
;
177 struct mhu2_recv_frame_reg __iomem
*recv
;
179 enum mhuv2_frame frame
;
181 unsigned int windows
;
186 spinlock_t doorbell_pending_lock
;
189 #define mhu_from_mbox(_mbox) container_of(_mbox, struct mhuv2, mbox)
192 * struct mhuv2_protocol_ops - MHUv2 operations
194 * Each transport protocol must provide an implementation of the operations
197 * @rx_startup: Startup callback for receiver.
198 * @rx_shutdown: Shutdown callback for receiver.
199 * @read_data: Reads and clears newly available data.
200 * @tx_startup: Startup callback for receiver.
201 * @tx_shutdown: Shutdown callback for receiver.
202 * @last_tx_done: Report back if the last tx is completed or not.
203 * @send_data: Send data to the receiver.
205 struct mhuv2_protocol_ops
{
206 int (*rx_startup
)(struct mhuv2
*mhu
, struct mbox_chan
*chan
);
207 void (*rx_shutdown
)(struct mhuv2
*mhu
, struct mbox_chan
*chan
);
208 void *(*read_data
)(struct mhuv2
*mhu
, struct mbox_chan
*chan
);
210 void (*tx_startup
)(struct mhuv2
*mhu
, struct mbox_chan
*chan
);
211 void (*tx_shutdown
)(struct mhuv2
*mhu
, struct mbox_chan
*chan
);
212 int (*last_tx_done
)(struct mhuv2
*mhu
, struct mbox_chan
*chan
);
213 int (*send_data
)(struct mhuv2
*mhu
, struct mbox_chan
*chan
, void *arg
);
217 * MHUv2 mailbox channel's private information
219 * @ops: protocol specific ops for the channel.
220 * @ch_wn_idx: Channel window index allocated to the channel.
221 * @windows: Total number of windows consumed by the channel, only relevant
222 * in DATA_TRANSFER protocol.
223 * @doorbell: Doorbell bit number within the ch_wn_idx window, only relevant
224 * in DOORBELL protocol.
225 * @pending: Flag indicating pending doorbell interrupt, only relevant in
228 struct mhuv2_mbox_chan_priv
{
229 const struct mhuv2_protocol_ops
*ops
;
240 /* Macro for reading a bitfield within a physically mapped packed struct */
241 #define readl_relaxed_bitfield(_regptr, _field) \
244 _regval = readl_relaxed((_regptr)); \
245 (*(typeof((_regptr)))(&_regval))._field; \
248 /* Macro for writing a bitfield within a physically mapped packed struct */
249 #define writel_relaxed_bitfield(_value, _regptr, _field) \
252 _regval = readl_relaxed(_regptr); \
253 (*(typeof(_regptr))(&_regval))._field = _value; \
254 writel_relaxed(_regval, _regptr); \
258 /* =================== Doorbell transport protocol operations =============== */
260 static int mhuv2_doorbell_rx_startup(struct mhuv2
*mhu
, struct mbox_chan
*chan
)
262 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
264 writel_relaxed(BIT(priv
->doorbell
),
265 &mhu
->recv
->ch_wn
[priv
->ch_wn_idx
].mask_clear
);
269 static void mhuv2_doorbell_rx_shutdown(struct mhuv2
*mhu
,
270 struct mbox_chan
*chan
)
272 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
274 writel_relaxed(BIT(priv
->doorbell
),
275 &mhu
->recv
->ch_wn
[priv
->ch_wn_idx
].mask_set
);
278 static void *mhuv2_doorbell_read_data(struct mhuv2
*mhu
, struct mbox_chan
*chan
)
280 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
282 writel_relaxed(BIT(priv
->doorbell
),
283 &mhu
->recv
->ch_wn
[priv
->ch_wn_idx
].stat_clear
);
287 static int mhuv2_doorbell_last_tx_done(struct mhuv2
*mhu
,
288 struct mbox_chan
*chan
)
290 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
292 return !(readl_relaxed(&mhu
->send
->ch_wn
[priv
->ch_wn_idx
].stat
) &
293 BIT(priv
->doorbell
));
296 static int mhuv2_doorbell_send_data(struct mhuv2
*mhu
, struct mbox_chan
*chan
,
299 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
302 spin_lock_irqsave(&mhu
->doorbell_pending_lock
, flags
);
305 writel_relaxed(BIT(priv
->doorbell
),
306 &mhu
->send
->ch_wn
[priv
->ch_wn_idx
].stat_set
);
308 spin_unlock_irqrestore(&mhu
->doorbell_pending_lock
, flags
);
313 static const struct mhuv2_protocol_ops mhuv2_doorbell_ops
= {
314 .rx_startup
= mhuv2_doorbell_rx_startup
,
315 .rx_shutdown
= mhuv2_doorbell_rx_shutdown
,
316 .read_data
= mhuv2_doorbell_read_data
,
317 .last_tx_done
= mhuv2_doorbell_last_tx_done
,
318 .send_data
= mhuv2_doorbell_send_data
,
320 #define IS_PROTOCOL_DOORBELL(_priv) (_priv->ops == &mhuv2_doorbell_ops)
322 /* ============= Data transfer transport protocol operations ================ */
324 static int mhuv2_data_transfer_rx_startup(struct mhuv2
*mhu
,
325 struct mbox_chan
*chan
)
327 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
328 int i
= priv
->ch_wn_idx
+ priv
->windows
- 1;
331 * The protocol mandates that all but the last status register must be
334 writel_relaxed(0xFFFFFFFF, &mhu
->recv
->ch_wn
[i
].mask_clear
);
338 static void mhuv2_data_transfer_rx_shutdown(struct mhuv2
*mhu
,
339 struct mbox_chan
*chan
)
341 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
342 int i
= priv
->ch_wn_idx
+ priv
->windows
- 1;
344 writel_relaxed(0xFFFFFFFF, &mhu
->recv
->ch_wn
[i
].mask_set
);
347 static void *mhuv2_data_transfer_read_data(struct mhuv2
*mhu
,
348 struct mbox_chan
*chan
)
350 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
351 const int windows
= priv
->windows
;
352 struct arm_mhuv2_mbox_msg
*msg
;
356 msg
= kzalloc(sizeof(*msg
) + windows
* MHUV2_STAT_BYTES
, GFP_KERNEL
);
358 return ERR_PTR(-ENOMEM
);
360 data
= msg
->data
= msg
+ 1;
361 msg
->len
= windows
* MHUV2_STAT_BYTES
;
364 * Messages are expected in order of most significant word to least
365 * significant word. Refer mhuv2_data_transfer_send_data() for more
368 * We also need to read the stat register instead of stat_masked, as we
369 * masked all but the last window.
371 * Last channel window must be cleared as the final operation. Upon
372 * clearing the last channel window register, which is unmasked in
373 * data-transfer protocol, the interrupt is de-asserted.
375 for (i
= 0; i
< windows
; i
++) {
376 idx
= priv
->ch_wn_idx
+ i
;
377 data
[windows
- 1 - i
] = readl_relaxed(&mhu
->recv
->ch_wn
[idx
].stat
);
378 writel_relaxed(0xFFFFFFFF, &mhu
->recv
->ch_wn
[idx
].stat_clear
);
384 static void mhuv2_data_transfer_tx_startup(struct mhuv2
*mhu
,
385 struct mbox_chan
*chan
)
387 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
388 int i
= priv
->ch_wn_idx
+ priv
->windows
- 1;
390 /* Enable interrupts only for the last window */
392 writel_relaxed(0x1, &mhu
->send
->ch_wn
[i
].int_clr
);
393 writel_relaxed(0x1, &mhu
->send
->ch_wn
[i
].int_en
);
397 static void mhuv2_data_transfer_tx_shutdown(struct mhuv2
*mhu
,
398 struct mbox_chan
*chan
)
400 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
401 int i
= priv
->ch_wn_idx
+ priv
->windows
- 1;
404 writel_relaxed(0x0, &mhu
->send
->ch_wn
[i
].int_en
);
407 static int mhuv2_data_transfer_last_tx_done(struct mhuv2
*mhu
,
408 struct mbox_chan
*chan
)
410 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
411 int i
= priv
->ch_wn_idx
+ priv
->windows
- 1;
413 /* Just checking the last channel window should be enough */
414 return !readl_relaxed(&mhu
->send
->ch_wn
[i
].stat
);
418 * Message will be transmitted from most significant to least significant word.
419 * This is to allow for messages shorter than channel windows to still trigger
420 * the receiver interrupt which gets activated when the last stat register is
421 * written. As an example, a 6-word message is to be written on a 4-channel MHU
422 * connection: Registers marked with '*' are masked, and will not generate an
423 * interrupt on the receiver side once written.
425 * u32 *data = [0x00000001], [0x00000002], [0x00000003], [0x00000004],
426 * [0x00000005], [0x00000006]
429 * stat reg To write Write sequence
430 * [ stat 3 ] <- [0x00000001] 4 <- triggers interrupt on receiver
431 * [ stat 2 ] <- [0x00000002] 3
432 * [ stat 1 ] <- [0x00000003] 2
433 * [ stat 0 ] <- [0x00000004] 1
435 * data += 4 // Increment data pointer by number of stat regs
438 * stat reg To write Write sequence
439 * [ stat 3 ] <- [0x00000005] 2 <- triggers interrupt on receiver
440 * [ stat 2 ] <- [0x00000006] 1
441 * [ stat 1 ] <- [0x00000000]
442 * [ stat 0 ] <- [0x00000000]
444 static int mhuv2_data_transfer_send_data(struct mhuv2
*mhu
,
445 struct mbox_chan
*chan
, void *arg
)
447 const struct arm_mhuv2_mbox_msg
*msg
= arg
;
448 int bytes_left
= msg
->len
, bytes_to_send
, bytes_in_round
, i
;
449 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
450 int windows
= priv
->windows
;
451 u32
*data
= msg
->data
, word
;
455 dev_err(mhu
->mbox
.dev
, "Data aligned at first window can't be zero to guarantee interrupt generation at receiver");
459 while(!mhuv2_data_transfer_last_tx_done(mhu
, chan
))
462 bytes_in_round
= min(bytes_left
, (int)(windows
* MHUV2_STAT_BYTES
));
464 for (i
= windows
- 1; i
>= 0; i
--) {
465 /* Data less than windows can transfer ? */
466 if (unlikely(bytes_in_round
<= i
* MHUV2_STAT_BYTES
))
470 bytes_to_send
= bytes_in_round
& (MHUV2_STAT_BYTES
- 1);
471 if (unlikely(bytes_to_send
))
472 word
&= LSB_MASK(bytes_to_send
);
474 bytes_to_send
= MHUV2_STAT_BYTES
;
476 writel_relaxed(word
, &mhu
->send
->ch_wn
[priv
->ch_wn_idx
+ windows
- 1 - i
].stat_set
);
477 bytes_left
-= bytes_to_send
;
478 bytes_in_round
-= bytes_to_send
;
487 static const struct mhuv2_protocol_ops mhuv2_data_transfer_ops
= {
488 .rx_startup
= mhuv2_data_transfer_rx_startup
,
489 .rx_shutdown
= mhuv2_data_transfer_rx_shutdown
,
490 .read_data
= mhuv2_data_transfer_read_data
,
491 .tx_startup
= mhuv2_data_transfer_tx_startup
,
492 .tx_shutdown
= mhuv2_data_transfer_tx_shutdown
,
493 .last_tx_done
= mhuv2_data_transfer_last_tx_done
,
494 .send_data
= mhuv2_data_transfer_send_data
,
497 /* Interrupt handlers */
499 static struct mbox_chan
*get_irq_chan_comb(struct mhuv2
*mhu
, u32
*reg
)
501 struct mbox_chan
*chans
= mhu
->mbox
.chans
;
502 int channel
= 0, i
, offset
= 0, windows
, protocol
, ch_wn
;
505 for (i
= 0; i
< MHUV2_CMB_INT_ST_REG_CNT
; i
++) {
506 stat
= readl_relaxed(reg
+ i
);
510 ch_wn
= i
* MHUV2_STAT_BITS
+ __builtin_ctz(stat
);
512 for (i
= 0; i
< mhu
->length
; i
+= 2) {
513 protocol
= mhu
->protocols
[i
];
514 windows
= mhu
->protocols
[i
+ 1];
516 if (ch_wn
>= offset
+ windows
) {
517 if (protocol
== DOORBELL
)
518 channel
+= MHUV2_STAT_BITS
* windows
;
526 /* Return first chan of the window in doorbell mode */
527 if (protocol
== DOORBELL
)
528 channel
+= MHUV2_STAT_BITS
* (ch_wn
- offset
);
530 return &chans
[channel
];
534 return ERR_PTR(-EIO
);
537 static irqreturn_t
mhuv2_sender_interrupt(int irq
, void *data
)
539 struct mhuv2
*mhu
= data
;
540 struct device
*dev
= mhu
->mbox
.dev
;
541 struct mhuv2_mbox_chan_priv
*priv
;
542 struct mbox_chan
*chan
;
547 chan
= get_irq_chan_comb(mhu
, mhu
->send
->chcomb_int_st
);
549 dev_warn(dev
, "Failed to find channel for the Tx interrupt\n");
552 priv
= chan
->con_priv
;
554 if (!IS_PROTOCOL_DOORBELL(priv
)) {
555 writel_relaxed(1, &mhu
->send
->ch_wn
[priv
->ch_wn_idx
+ priv
->windows
- 1].int_clr
);
558 mbox_chan_txdone(chan
, 0);
562 dev_warn(dev
, "Tx interrupt Received on channel (%u) not currently attached to a mailbox client\n",
567 /* Clear the interrupt first, so we don't miss any doorbell later */
568 writel_relaxed(1, &mhu
->send
->ch_wn
[priv
->ch_wn_idx
].int_clr
);
571 * In Doorbell mode, make sure no new transitions happen while the
572 * interrupt handler is trying to find the finished doorbell tx
573 * operations, else we may think few of the transfers were complete
574 * before they actually were.
576 spin_lock_irqsave(&mhu
->doorbell_pending_lock
, flags
);
579 * In case of doorbell mode, the first channel of the window is returned
580 * by get_irq_chan_comb(). Find all the pending channels here.
582 stat
= readl_relaxed(&mhu
->send
->ch_wn
[priv
->ch_wn_idx
].stat
);
584 for (i
= 0; i
< MHUV2_STAT_BITS
; i
++) {
585 priv
= chan
[i
].con_priv
;
587 /* Find cases where pending was 1, but stat's bit is cleared */
588 if (priv
->pending
^ ((stat
>> i
) & 0x1)) {
589 BUG_ON(!priv
->pending
);
592 dev_warn(dev
, "Tx interrupt received on doorbell (%u : %u) channel not currently attached to a mailbox client\n",
597 mbox_chan_txdone(&chan
[i
], 0);
603 spin_unlock_irqrestore(&mhu
->doorbell_pending_lock
, flags
);
607 * We may have already processed the doorbell in the previous
608 * iteration if the interrupt came right after we cleared it but
609 * before we read the stat register.
611 dev_dbg(dev
, "Couldn't find the doorbell (%u) for the Tx interrupt interrupt\n",
619 static struct mbox_chan
*get_irq_chan_comb_rx(struct mhuv2
*mhu
)
621 struct mhuv2_mbox_chan_priv
*priv
;
622 struct mbox_chan
*chan
;
625 chan
= get_irq_chan_comb(mhu
, mhu
->recv
->chcomb_int_st
);
629 priv
= chan
->con_priv
;
630 if (!IS_PROTOCOL_DOORBELL(priv
))
634 * In case of doorbell mode, the first channel of the window is returned
635 * by the routine. Find the exact channel here.
637 stat
= readl_relaxed(&mhu
->recv
->ch_wn
[priv
->ch_wn_idx
].stat_masked
);
640 return chan
+ __builtin_ctz(stat
);
643 static struct mbox_chan
*get_irq_chan_stat_rx(struct mhuv2
*mhu
)
645 struct mbox_chan
*chans
= mhu
->mbox
.chans
;
646 struct mhuv2_mbox_chan_priv
*priv
;
650 while (i
< mhu
->mbox
.num_chans
) {
651 priv
= chans
[i
].con_priv
;
652 stat
= readl_relaxed(&mhu
->recv
->ch_wn
[priv
->ch_wn_idx
].stat_masked
);
655 if (IS_PROTOCOL_DOORBELL(priv
))
656 i
+= __builtin_ctz(stat
);
660 i
+= IS_PROTOCOL_DOORBELL(priv
) ? MHUV2_STAT_BITS
: 1;
663 return ERR_PTR(-EIO
);
666 static struct mbox_chan
*get_irq_chan_rx(struct mhuv2
*mhu
)
669 return get_irq_chan_stat_rx(mhu
);
671 return get_irq_chan_comb_rx(mhu
);
674 static irqreturn_t
mhuv2_receiver_interrupt(int irq
, void *arg
)
676 struct mhuv2
*mhu
= arg
;
677 struct mbox_chan
*chan
= get_irq_chan_rx(mhu
);
678 struct device
*dev
= mhu
->mbox
.dev
;
679 struct mhuv2_mbox_chan_priv
*priv
;
684 dev_warn(dev
, "Failed to find channel for the rx interrupt\n");
687 priv
= chan
->con_priv
;
689 /* Read and clear the data first */
690 data
= priv
->ops
->read_data(mhu
, chan
);
693 dev_warn(dev
, "Received data on channel (%u) not currently attached to a mailbox client\n",
695 } else if (IS_ERR(data
)) {
696 dev_err(dev
, "Failed to read data: %lu\n", PTR_ERR(data
));
698 mbox_chan_received_data(chan
, data
);
706 /* Sender and receiver ops */
707 static bool mhuv2_sender_last_tx_done(struct mbox_chan
*chan
)
709 struct mhuv2
*mhu
= mhu_from_mbox(chan
->mbox
);
710 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
712 return priv
->ops
->last_tx_done(mhu
, chan
);
715 static int mhuv2_sender_send_data(struct mbox_chan
*chan
, void *data
)
717 struct mhuv2
*mhu
= mhu_from_mbox(chan
->mbox
);
718 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
720 if (!priv
->ops
->last_tx_done(mhu
, chan
))
723 return priv
->ops
->send_data(mhu
, chan
, data
);
726 static int mhuv2_sender_startup(struct mbox_chan
*chan
)
728 struct mhuv2
*mhu
= mhu_from_mbox(chan
->mbox
);
729 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
731 if (priv
->ops
->tx_startup
)
732 priv
->ops
->tx_startup(mhu
, chan
);
736 static void mhuv2_sender_shutdown(struct mbox_chan
*chan
)
738 struct mhuv2
*mhu
= mhu_from_mbox(chan
->mbox
);
739 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
741 if (priv
->ops
->tx_shutdown
)
742 priv
->ops
->tx_shutdown(mhu
, chan
);
745 static const struct mbox_chan_ops mhuv2_sender_ops
= {
746 .send_data
= mhuv2_sender_send_data
,
747 .startup
= mhuv2_sender_startup
,
748 .shutdown
= mhuv2_sender_shutdown
,
749 .last_tx_done
= mhuv2_sender_last_tx_done
,
752 static int mhuv2_receiver_startup(struct mbox_chan
*chan
)
754 struct mhuv2
*mhu
= mhu_from_mbox(chan
->mbox
);
755 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
757 return priv
->ops
->rx_startup(mhu
, chan
);
760 static void mhuv2_receiver_shutdown(struct mbox_chan
*chan
)
762 struct mhuv2
*mhu
= mhu_from_mbox(chan
->mbox
);
763 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
765 priv
->ops
->rx_shutdown(mhu
, chan
);
768 static int mhuv2_receiver_send_data(struct mbox_chan
*chan
, void *data
)
770 dev_err(chan
->mbox
->dev
,
771 "Trying to transmit on a receiver MHU frame\n");
775 static bool mhuv2_receiver_last_tx_done(struct mbox_chan
*chan
)
777 dev_err(chan
->mbox
->dev
, "Trying to Tx poll on a receiver MHU frame\n");
781 static const struct mbox_chan_ops mhuv2_receiver_ops
= {
782 .send_data
= mhuv2_receiver_send_data
,
783 .startup
= mhuv2_receiver_startup
,
784 .shutdown
= mhuv2_receiver_shutdown
,
785 .last_tx_done
= mhuv2_receiver_last_tx_done
,
788 static struct mbox_chan
*mhuv2_mbox_of_xlate(struct mbox_controller
*mbox
,
789 const struct of_phandle_args
*pa
)
791 struct mhuv2
*mhu
= mhu_from_mbox(mbox
);
792 struct mbox_chan
*chans
= mbox
->chans
;
793 int channel
= 0, i
, offset
, doorbell
, protocol
, windows
;
795 if (pa
->args_count
!= 2)
796 return ERR_PTR(-EINVAL
);
798 offset
= pa
->args
[0];
799 doorbell
= pa
->args
[1];
800 if (doorbell
>= MHUV2_STAT_BITS
)
803 for (i
= 0; i
< mhu
->length
; i
+= 2) {
804 protocol
= mhu
->protocols
[i
];
805 windows
= mhu
->protocols
[i
+ 1];
807 if (protocol
== DOORBELL
) {
808 if (offset
< windows
)
809 return &chans
[channel
+ MHUV2_STAT_BITS
* offset
+ doorbell
];
811 channel
+= MHUV2_STAT_BITS
* windows
;
818 return &chans
[channel
];
827 dev_err(mbox
->dev
, "Couldn't xlate to a valid channel (%d: %d)\n",
828 pa
->args
[0], doorbell
);
829 return ERR_PTR(-ENODEV
);
832 static int mhuv2_verify_protocol(struct mhuv2
*mhu
)
834 struct device
*dev
= mhu
->mbox
.dev
;
835 int protocol
, windows
, channels
= 0, total_windows
= 0, i
;
837 for (i
= 0; i
< mhu
->length
; i
+= 2) {
838 protocol
= mhu
->protocols
[i
];
839 windows
= mhu
->protocols
[i
+ 1];
842 dev_err(dev
, "Window size can't be zero (%d)\n", i
);
845 total_windows
+= windows
;
847 if (protocol
== DOORBELL
) {
848 channels
+= MHUV2_STAT_BITS
* windows
;
849 } else if (protocol
== DATA_TRANSFER
) {
852 dev_err(dev
, "Invalid protocol (%d) present in %s property at index %d\n",
853 protocol
, MHUV2_PROTOCOL_PROP
, i
);
858 if (total_windows
> mhu
->windows
) {
859 dev_err(dev
, "Channel windows can't be more than what's implemented by the hardware ( %d: %d)\n",
860 total_windows
, mhu
->windows
);
864 mhu
->mbox
.num_chans
= channels
;
868 static int mhuv2_allocate_channels(struct mhuv2
*mhu
)
870 struct mbox_controller
*mbox
= &mhu
->mbox
;
871 struct mhuv2_mbox_chan_priv
*priv
;
872 struct device
*dev
= mbox
->dev
;
873 struct mbox_chan
*chans
;
874 int protocol
, windows
= 0, next_window
= 0, i
, j
, k
;
876 chans
= devm_kcalloc(dev
, mbox
->num_chans
, sizeof(*chans
), GFP_KERNEL
);
882 for (i
= 0; i
< mhu
->length
; i
+= 2) {
883 next_window
+= windows
;
885 protocol
= mhu
->protocols
[i
];
886 windows
= mhu
->protocols
[i
+ 1];
888 if (protocol
== DATA_TRANSFER
) {
889 priv
= devm_kmalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
893 priv
->ch_wn_idx
= next_window
;
894 priv
->ops
= &mhuv2_data_transfer_ops
;
895 priv
->windows
= windows
;
896 chans
++->con_priv
= priv
;
900 for (j
= 0; j
< windows
; j
++) {
901 for (k
= 0; k
< MHUV2_STAT_BITS
; k
++) {
902 priv
= devm_kmalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
906 priv
->ch_wn_idx
= next_window
+ j
;
907 priv
->ops
= &mhuv2_doorbell_ops
;
909 chans
++->con_priv
= priv
;
913 * Permanently enable interrupt as we can't
914 * control it per doorbell.
916 if (mhu
->frame
== SENDER_FRAME
&& mhu
->minor
)
917 writel_relaxed(0x1, &mhu
->send
->ch_wn
[priv
->ch_wn_idx
].int_en
);
921 /* Make sure we have initialized all channels */
922 BUG_ON(chans
- mbox
->chans
!= mbox
->num_chans
);
927 static int mhuv2_parse_channels(struct mhuv2
*mhu
)
929 struct device
*dev
= mhu
->mbox
.dev
;
930 const struct device_node
*np
= dev
->of_node
;
934 count
= of_property_count_u32_elems(np
, MHUV2_PROTOCOL_PROP
);
935 if (count
<= 0 || count
% 2) {
936 dev_err(dev
, "Invalid %s property (%d)\n", MHUV2_PROTOCOL_PROP
,
941 protocols
= devm_kmalloc_array(dev
, count
, sizeof(*protocols
), GFP_KERNEL
);
945 ret
= of_property_read_u32_array(np
, MHUV2_PROTOCOL_PROP
, protocols
, count
);
947 dev_err(dev
, "Failed to read %s property: %d\n",
948 MHUV2_PROTOCOL_PROP
, ret
);
952 mhu
->protocols
= protocols
;
955 ret
= mhuv2_verify_protocol(mhu
);
959 return mhuv2_allocate_channels(mhu
);
962 static int mhuv2_tx_init(struct amba_device
*adev
, struct mhuv2
*mhu
,
965 struct device
*dev
= mhu
->mbox
.dev
;
968 mhu
->frame
= SENDER_FRAME
;
969 mhu
->mbox
.ops
= &mhuv2_sender_ops
;
972 mhu
->windows
= readl_relaxed_bitfield(&mhu
->send
->mhu_cfg
, num_ch
);
973 mhu
->minor
= readl_relaxed_bitfield(&mhu
->send
->aidr
, arch_minor_rev
);
975 spin_lock_init(&mhu
->doorbell_pending_lock
);
978 * For minor version 1 and forward, tx interrupt is provided by
981 if (mhu
->minor
&& adev
->irq
[0]) {
982 ret
= devm_request_threaded_irq(dev
, adev
->irq
[0], NULL
,
983 mhuv2_sender_interrupt
,
984 IRQF_ONESHOT
, "mhuv2-tx", mhu
);
986 dev_err(dev
, "Failed to request tx IRQ, fallback to polling mode: %d\n",
989 mhu
->mbox
.txdone_irq
= true;
990 mhu
->mbox
.txdone_poll
= false;
991 mhu
->irq
= adev
->irq
[0];
993 writel_relaxed_bitfield(1, &mhu
->send
->int_en
, chcomb
);
995 /* Disable all channel interrupts */
996 for (i
= 0; i
< mhu
->windows
; i
++)
997 writel_relaxed(0x0, &mhu
->send
->ch_wn
[i
].int_en
);
1003 mhu
->mbox
.txdone_irq
= false;
1004 mhu
->mbox
.txdone_poll
= true;
1005 mhu
->mbox
.txpoll_period
= 1;
1008 /* Wait for receiver to be ready */
1009 writel_relaxed(0x1, &mhu
->send
->access_request
);
1010 while (!readl_relaxed(&mhu
->send
->access_ready
))
1016 static int mhuv2_rx_init(struct amba_device
*adev
, struct mhuv2
*mhu
,
1019 struct device
*dev
= mhu
->mbox
.dev
;
1022 mhu
->frame
= RECEIVER_FRAME
;
1023 mhu
->mbox
.ops
= &mhuv2_receiver_ops
;
1026 mhu
->windows
= readl_relaxed_bitfield(&mhu
->recv
->mhu_cfg
, num_ch
);
1027 mhu
->minor
= readl_relaxed_bitfield(&mhu
->recv
->aidr
, arch_minor_rev
);
1029 mhu
->irq
= adev
->irq
[0];
1031 dev_err(dev
, "Missing receiver IRQ\n");
1035 ret
= devm_request_threaded_irq(dev
, mhu
->irq
, NULL
,
1036 mhuv2_receiver_interrupt
, IRQF_ONESHOT
,
1039 dev_err(dev
, "Failed to request rx IRQ\n");
1043 /* Mask all the channel windows */
1044 for (i
= 0; i
< mhu
->windows
; i
++)
1045 writel_relaxed(0xFFFFFFFF, &mhu
->recv
->ch_wn
[i
].mask_set
);
1048 writel_relaxed_bitfield(1, &mhu
->recv
->int_en
, chcomb
);
1053 static int mhuv2_probe(struct amba_device
*adev
, const struct amba_id
*id
)
1055 struct device
*dev
= &adev
->dev
;
1056 const struct device_node
*np
= dev
->of_node
;
1061 reg
= devm_of_iomap(dev
, dev
->of_node
, 0, NULL
);
1065 mhu
= devm_kzalloc(dev
, sizeof(*mhu
), GFP_KERNEL
);
1069 mhu
->mbox
.dev
= dev
;
1070 mhu
->mbox
.of_xlate
= mhuv2_mbox_of_xlate
;
1072 if (of_device_is_compatible(np
, "arm,mhuv2-tx"))
1073 ret
= mhuv2_tx_init(adev
, mhu
, reg
);
1074 else if (of_device_is_compatible(np
, "arm,mhuv2-rx"))
1075 ret
= mhuv2_rx_init(adev
, mhu
, reg
);
1077 dev_err(dev
, "Invalid compatible property\n");
1082 /* Channel windows can't be 0 */
1083 BUG_ON(!mhu
->windows
);
1085 ret
= mhuv2_parse_channels(mhu
);
1089 amba_set_drvdata(adev
, mhu
);
1091 ret
= devm_mbox_controller_register(dev
, &mhu
->mbox
);
1093 dev_err(dev
, "failed to register ARM MHUv2 driver %d\n", ret
);
1098 static int mhuv2_remove(struct amba_device
*adev
)
1100 struct mhuv2
*mhu
= amba_get_drvdata(adev
);
1102 if (mhu
->frame
== SENDER_FRAME
)
1103 writel_relaxed(0x0, &mhu
->send
->access_request
);
1108 static struct amba_id mhuv2_ids
[] = {
1121 MODULE_DEVICE_TABLE(amba
, mhuv2_ids
);
1123 static struct amba_driver mhuv2_driver
= {
1125 .name
= "arm-mhuv2",
1127 .id_table
= mhuv2_ids
,
1128 .probe
= mhuv2_probe
,
1129 .remove
= mhuv2_remove
,
1131 module_amba_driver(mhuv2_driver
);
1133 MODULE_LICENSE("GPL v2");
1134 MODULE_DESCRIPTION("ARM MHUv2 Driver");
1135 MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
1136 MODULE_AUTHOR("Tushar Khandelwal <tushar.khandelwal@arm.com>");