| blob | d68d38841ae767ef3ee4213605d89ae0b2d5c808 |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (C) 2008-2009 Texas Instruments Inc
4 */
5 #ifndef _ISIF_REGS_H
6 #define _ISIF_REGS_H
8 /* ISIF registers relative offsets */
9 #define SYNCEN 0x00
10 #define MODESET 0x04
11 #define HDW 0x08
12 #define VDW 0x0c
13 #define PPLN 0x10
14 #define LPFR 0x14
15 #define SPH 0x18
16 #define LNH 0x1c
17 #define SLV0 0x20
18 #define SLV1 0x24
19 #define LNV 0x28
20 #define CULH 0x2c
21 #define CULV 0x30
22 #define HSIZE 0x34
23 #define SDOFST 0x38
24 #define CADU 0x3c
25 #define CADL 0x40
26 #define LINCFG0 0x44
27 #define LINCFG1 0x48
28 #define CCOLP 0x4c
29 #define CRGAIN 0x50
30 #define CGRGAIN 0x54
31 #define CGBGAIN 0x58
32 #define CBGAIN 0x5c
33 #define COFSTA 0x60
34 #define FLSHCFG0 0x64
35 #define FLSHCFG1 0x68
36 #define FLSHCFG2 0x6c
37 #define VDINT0 0x70
38 #define VDINT1 0x74
39 #define VDINT2 0x78
40 #define MISC 0x7c
41 #define CGAMMAWD 0x80
42 #define REC656IF 0x84
43 #define CCDCFG 0x88
44 /*****************************************************
45 * Defect Correction registers
46 *****************************************************/
47 #define DFCCTL 0x8c
48 #define VDFSATLV 0x90
49 #define DFCMEMCTL 0x94
50 #define DFCMEM0 0x98
51 #define DFCMEM1 0x9c
52 #define DFCMEM2 0xa0
53 #define DFCMEM3 0xa4
54 #define DFCMEM4 0xa8
55 /****************************************************
56 * Black Clamp registers
57 ****************************************************/
58 #define CLAMPCFG 0xac
59 #define CLDCOFST 0xb0
60 #define CLSV 0xb4
61 #define CLHWIN0 0xb8
62 #define CLHWIN1 0xbc
63 #define CLHWIN2 0xc0
64 #define CLVRV 0xc4
65 #define CLVWIN0 0xc8
66 #define CLVWIN1 0xcc
67 #define CLVWIN2 0xd0
68 #define CLVWIN3 0xd4
69 /****************************************************
70 * Lense Shading Correction
71 ****************************************************/
72 #define DATAHOFST 0xd8
73 #define DATAVOFST 0xdc
74 #define LSCHVAL 0xe0
75 #define LSCVVAL 0xe4
76 #define TWODLSCCFG 0xe8
77 #define TWODLSCOFST 0xec
78 #define TWODLSCINI 0xf0
79 #define TWODLSCGRBU 0xf4
80 #define TWODLSCGRBL 0xf8
81 #define TWODLSCGROF 0xfc
82 #define TWODLSCORBU 0x100
83 #define TWODLSCORBL 0x104
84 #define TWODLSCOROF 0x108
85 #define TWODLSCIRQEN 0x10c
86 #define TWODLSCIRQST 0x110
87 /****************************************************
88 * Data formatter
89 ****************************************************/
90 #define FMTCFG 0x114
91 #define FMTPLEN 0x118
92 #define FMTSPH 0x11c
93 #define FMTLNH 0x120
94 #define FMTSLV 0x124
95 #define FMTLNV 0x128
96 #define FMTRLEN 0x12c
97 #define FMTHCNT 0x130
98 #define FMTAPTR_BASE 0x134
99 /* Below macro for addresses FMTAPTR0 - FMTAPTR15 */
100 #define FMTAPTR(i) (FMTAPTR_BASE + (i * 4))
101 #define FMTPGMVF0 0x174
102 #define FMTPGMVF1 0x178
103 #define FMTPGMAPU0 0x17c
104 #define FMTPGMAPU1 0x180
105 #define FMTPGMAPS0 0x184
106 #define FMTPGMAPS1 0x188
107 #define FMTPGMAPS2 0x18c
108 #define FMTPGMAPS3 0x190
109 #define FMTPGMAPS4 0x194
110 #define FMTPGMAPS5 0x198
111 #define FMTPGMAPS6 0x19c
112 #define FMTPGMAPS7 0x1a0
113 /************************************************
114 * Color Space Converter
115 ************************************************/
116 #define CSCCTL 0x1a4
117 #define CSCM0 0x1a8
118 #define CSCM1 0x1ac
119 #define CSCM2 0x1b0
120 #define CSCM3 0x1b4
121 #define CSCM4 0x1b8
122 #define CSCM5 0x1bc
123 #define CSCM6 0x1c0
124 #define CSCM7 0x1c4
125 #define OBWIN0 0x1c8
126 #define OBWIN1 0x1cc
127 #define OBWIN2 0x1d0
128 #define OBWIN3 0x1d4
129 #define OBVAL0 0x1d8
130 #define OBVAL1 0x1dc
131 #define OBVAL2 0x1e0
132 #define OBVAL3 0x1e4
133 #define OBVAL4 0x1e8
134 #define OBVAL5 0x1ec
135 #define OBVAL6 0x1f0
136 #define OBVAL7 0x1f4
137 #define CLKCTL 0x1f8
139 /* Masks & Shifts below */
140 #define START_PX_HOR_MASK 0x7FFF
141 #define NUM_PX_HOR_MASK 0x7FFF
142 #define START_VER_ONE_MASK 0x7FFF
143 #define START_VER_TWO_MASK 0x7FFF
144 #define NUM_LINES_VER 0x7FFF
146 /* gain - offset masks */
147 #define GAIN_INTEGER_SHIFT 9
148 #define OFFSET_MASK 0xFFF
149 #define GAIN_SDRAM_EN_SHIFT 12
150 #define GAIN_IPIPE_EN_SHIFT 13
151 #define GAIN_H3A_EN_SHIFT 14
152 #define OFST_SDRAM_EN_SHIFT 8
153 #define OFST_IPIPE_EN_SHIFT 9
154 #define OFST_H3A_EN_SHIFT 10
155 #define GAIN_OFFSET_EN_MASK 0x7700
157 /* Culling */
158 #define CULL_PAT_EVEN_LINE_SHIFT 8
160 /* CCDCFG register */
161 #define ISIF_YCINSWP_RAW (0x00 << 4)
162 #define ISIF_YCINSWP_YCBCR (0x01 << 4)
163 #define ISIF_CCDCFG_FIDMD_LATCH_VSYNC (0x00 << 6)
164 #define ISIF_CCDCFG_WENLOG_AND (0x00 << 8)
165 #define ISIF_CCDCFG_TRGSEL_WEN (0x00 << 9)
166 #define ISIF_CCDCFG_EXTRG_DISABLE (0x00 << 10)
167 #define ISIF_LATCH_ON_VSYNC_DISABLE (0x01 << 15)
168 #define ISIF_LATCH_ON_VSYNC_ENABLE (0x00 << 15)
169 #define ISIF_DATA_PACK_MASK 3
170 #define ISIF_DATA_PACK16 0
171 #define ISIF_DATA_PACK12 1
172 #define ISIF_DATA_PACK8 2
173 #define ISIF_PIX_ORDER_SHIFT 11
174 #define ISIF_BW656_ENABLE (0x01 << 5)
176 /* MODESET registers */
177 #define ISIF_VDHDOUT_INPUT (0x00 << 0)
178 #define ISIF_INPUT_SHIFT 12
179 #define ISIF_RAW_INPUT_MODE 0
180 #define ISIF_FID_POL_SHIFT 4
181 #define ISIF_HD_POL_SHIFT 3
182 #define ISIF_VD_POL_SHIFT 2
183 #define ISIF_DATAPOL_NORMAL 0
184 #define ISIF_DATAPOL_SHIFT 6
185 #define ISIF_EXWEN_DISABLE 0
186 #define ISIF_EXWEN_SHIFT 5
187 #define ISIF_FRM_FMT_SHIFT 7
188 #define ISIF_DATASFT_SHIFT 8
189 #define ISIF_LPF_SHIFT 14
190 #define ISIF_LPF_MASK 1
192 /* GAMMAWD registers */
193 #define ISIF_ALAW_GAMMA_WD_MASK 0xF
194 #define ISIF_ALAW_GAMMA_WD_SHIFT 1
195 #define ISIF_ALAW_ENABLE 1
196 #define ISIF_GAMMAWD_CFA_SHIFT 5
198 /* HSIZE registers */
199 #define ISIF_HSIZE_FLIP_MASK 1
200 #define ISIF_HSIZE_FLIP_SHIFT 12
202 /* MISC registers */
203 #define ISIF_DPCM_EN_SHIFT 12
204 #define ISIF_DPCM_PREDICTOR_SHIFT 13
206 /* Black clamp related */
207 #define ISIF_BC_MODE_COLOR_SHIFT 4
208 #define ISIF_HORZ_BC_MODE_SHIFT 1
209 #define ISIF_HORZ_BC_WIN_SEL_SHIFT 5
210 #define ISIF_HORZ_BC_PIX_LIMIT_SHIFT 6
211 #define ISIF_HORZ_BC_WIN_H_SIZE_SHIFT 8
212 #define ISIF_HORZ_BC_WIN_V_SIZE_SHIFT 12
213 #define ISIF_VERT_BC_RST_VAL_SEL_SHIFT 4
214 #define ISIF_VERT_BC_LINE_AVE_COEF_SHIFT 8
216 /* VDFC registers */
217 #define ISIF_VDFC_EN_SHIFT 4
218 #define ISIF_VDFC_CORR_MOD_SHIFT 5
219 #define ISIF_VDFC_CORR_WHOLE_LN_SHIFT 7
220 #define ISIF_VDFC_LEVEL_SHFT_SHIFT 8
221 #define ISIF_VDFC_POS_MASK 0x1FFF
222 #define ISIF_DFCMEMCTL_DFCMARST_SHIFT 2
224 /* CSC registers */
225 #define ISIF_CSC_COEF_INTEG_MASK 7
226 #define ISIF_CSC_COEF_DECIMAL_MASK 0x1f
227 #define ISIF_CSC_COEF_INTEG_SHIFT 5
228 #define ISIF_CSCM_MSB_SHIFT 8
229 #define ISIF_DF_CSC_SPH_MASK 0x1FFF
230 #define ISIF_DF_CSC_LNH_MASK 0x1FFF
231 #define ISIF_DF_CSC_SLV_MASK 0x1FFF
232 #define ISIF_DF_CSC_LNV_MASK 0x1FFF
233 #define ISIF_DF_NUMLINES 0x7FFF
234 #define ISIF_DF_NUMPIX 0x1FFF
236 /* Offsets for LSC/DFC/Gain */
237 #define ISIF_DATA_H_OFFSET_MASK 0x1FFF
238 #define ISIF_DATA_V_OFFSET_MASK 0x1FFF
240 /* Linearization */
241 #define ISIF_LIN_CORRSFT_SHIFT 4
242 #define ISIF_LIN_SCALE_FACT_INTEG_SHIFT 10
245 /* Pattern registers */
246 #define ISIF_PG_EN (1 << 3)
247 #define ISIF_SEL_PG_SRC (3 << 4)
248 #define ISIF_PG_VD_POL_SHIFT 0
249 #define ISIF_PG_HD_POL_SHIFT 1
251 /*random other junk*/
252 #define ISIF_SYNCEN_VDHDEN_MASK (1 << 0)
253 #define ISIF_SYNCEN_WEN_MASK (1 << 1)
254 #define ISIF_SYNCEN_WEN_SHIFT 1
256 #endif