drivers/media/platform/omap3isp/isph3a.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * isph3a.h
   4  *
   5  * TI OMAP3 ISP - H3A AF module
   6  *
   7  * Copyright (C) 2010 Nokia Corporation
   8  * Copyright (C) 2009 Texas Instruments, Inc.
   9  *
  10  * Contacts: David Cohen <dacohen@gmail.com>
  11  *           Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  12  *           Sakari Ailus <sakari.ailus@iki.fi>
  13  */
  14
  15 #ifndef OMAP3_ISP_H3A_H
  16 #define OMAP3_ISP_H3A_H
  17
  18 #include <linux/omap3isp.h>
  19
  20 /*
  21  * ----------
  22  * -H3A AEWB-
  23  * ----------
  24  */
  25
  26 #define AEWB_PACKET_SIZE        16
  27 #define AEWB_SATURATION_LIMIT   0x3ff
  28
  29 /* Flags for changed registers */
  30 #define PCR_CHNG                (1 << 0)
  31 #define AEWWIN1_CHNG            (1 << 1)
  32 #define AEWINSTART_CHNG         (1 << 2)
  33 #define AEWINBLK_CHNG           (1 << 3)
  34 #define AEWSUBWIN_CHNG          (1 << 4)
  35 #define PRV_WBDGAIN_CHNG        (1 << 5)
  36 #define PRV_WBGAIN_CHNG         (1 << 6)
  37
  38 /* ISPH3A REGISTERS bits */
  39 #define ISPH3A_PCR_AF_EN        (1 << 0)
  40 #define ISPH3A_PCR_AF_ALAW_EN   (1 << 1)
  41 #define ISPH3A_PCR_AF_MED_EN    (1 << 2)
  42 #define ISPH3A_PCR_AF_BUSY      (1 << 15)
  43 #define ISPH3A_PCR_AEW_EN       (1 << 16)
  44 #define ISPH3A_PCR_AEW_ALAW_EN  (1 << 17)
  45 #define ISPH3A_PCR_AEW_BUSY     (1 << 18)
  46 #define ISPH3A_PCR_AEW_MASK     (ISPH3A_PCR_AEW_ALAW_EN | \
  47                                  ISPH3A_PCR_AEW_AVE2LMT_MASK)
  48
  49 /*
  50  * --------
  51  * -H3A AF-
  52  * --------
  53  */
  54
  55 /* Peripheral Revision */
  56 #define AFPID                           0x0
  57
  58 #define AFCOEF_OFFSET                   0x00000004      /* COEF base address */
  59
  60 /* PCR fields */
  61 #define AF_BUSYAF                       (1 << 15)
  62 #define AF_FVMODE                       (1 << 14)
  63 #define AF_RGBPOS                       (0x7 << 11)
  64 #define AF_MED_TH                       (0xFF << 3)
  65 #define AF_MED_EN                       (1 << 2)
  66 #define AF_ALAW_EN                      (1 << 1)
  67 #define AF_EN                           (1 << 0)
  68 #define AF_PCR_MASK                     (AF_FVMODE | AF_RGBPOS | AF_MED_TH | \
  69                                          AF_MED_EN | AF_ALAW_EN)
  70
  71 /* AFPAX1 fields */
  72 #define AF_PAXW                         (0x7F << 16)
  73 #define AF_PAXH                         0x7F
  74
  75 /* AFPAX2 fields */
  76 #define AF_AFINCV                       (0xF << 13)
  77 #define AF_PAXVC                        (0x7F << 6)
  78 #define AF_PAXHC                        0x3F
  79
  80 /* AFPAXSTART fields */
  81 #define AF_PAXSH                        (0xFFF<<16)
  82 #define AF_PAXSV                        0xFFF
  83
  84 /* COEFFICIENT MASK */
  85 #define AF_COEF_MASK0                   0xFFF
  86 #define AF_COEF_MASK1                   (0xFFF<<16)
  87
  88 /* BIT SHIFTS */
  89 #define AF_RGBPOS_SHIFT                 11
  90 #define AF_MED_TH_SHIFT                 3
  91 #define AF_PAXW_SHIFT                   16
  92 #define AF_LINE_INCR_SHIFT              13
  93 #define AF_VT_COUNT_SHIFT               6
  94 #define AF_HZ_START_SHIFT               16
  95 #define AF_COEF_SHIFT                   16
  96
  97 /* Init and cleanup functions */
  98 int omap3isp_h3a_aewb_init(struct isp_device *isp);
  99 int omap3isp_h3a_af_init(struct isp_device *isp);
 100
 101 void omap3isp_h3a_aewb_cleanup(struct isp_device *isp);
 102 void omap3isp_h3a_af_cleanup(struct isp_device *isp);
 103
 104 #endif /* OMAP3_ISP_H3A_H */