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Merge tag 'regmap-fix-v5.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / media / platform / pxa_camera.c
blobb664ce7558a1a59d891494b9a4c20e3a4479ffaa
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * V4L2 Driver for PXA camera host
4 *
5 * Copyright (C) 2006, Sascha Hauer, Pengutronix
6 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr>
8 */
9
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/io.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/errno.h>
18 #include <linux/fs.h>
19 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/mm.h>
22 #include <linux/moduleparam.h>
23 #include <linux/of.h>
24 #include <linux/of_graph.h>
25 #include <linux/time.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/dmaengine.h>
31 #include <linux/dma/pxa-dma.h>
32
33 #include <media/v4l2-async.h>
34 #include <media/v4l2-clk.h>
35 #include <media/v4l2-common.h>
36 #include <media/v4l2-ctrls.h>
37 #include <media/v4l2-device.h>
38 #include <media/v4l2-event.h>
39 #include <media/v4l2-ioctl.h>
40 #include <media/v4l2-fwnode.h>
41
42 #include <media/videobuf2-dma-sg.h>
43
44 #include <linux/videodev2.h>
45
46 #include <linux/platform_data/media/camera-pxa.h>
47
48 #define PXA_CAM_VERSION "0.0.6"
49 #define PXA_CAM_DRV_NAME "pxa27x-camera"
50
51 #define DEFAULT_WIDTH 640
52 #define DEFAULT_HEIGHT 480
53
54 /* Camera Interface */
55 #define CICR0 0x0000
56 #define CICR1 0x0004
57 #define CICR2 0x0008
58 #define CICR3 0x000C
59 #define CICR4 0x0010
60 #define CISR 0x0014
61 #define CIFR 0x0018
62 #define CITOR 0x001C
63 #define CIBR0 0x0028
64 #define CIBR1 0x0030
65 #define CIBR2 0x0038
66
67 #define CICR0_DMAEN (1UL << 31) /* DMA request enable */
68 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
69 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
70 #define CICR0_ENB (1 << 28) /* Camera interface enable */
71 #define CICR0_DIS (1 << 27) /* Camera interface disable */
72 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
73 #define CICR0_TOM (1 << 9) /* Time-out mask */
74 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
75 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
76 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
77 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
78 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
79 #define CICR0_CDM (1 << 3) /* Disable-done mask */
80 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
81 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
82 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
83
84 #define CICR1_TBIT (1UL << 31) /* Transparency bit */
85 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
86 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
87 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
88 #define CICR1_RGB_F (1 << 11) /* RGB format */
89 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
90 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
91 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
92 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
93 #define CICR1_DW (0x7 << 0) /* Data width mask */
94
95 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
96 wait count mask */
97 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
98 wait count mask */
99 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
100 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
101 wait count mask */
102 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
103 wait count mask */
104
105 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
106 wait count mask */
107 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
108 wait count mask */
109 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
110 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
111 wait count mask */
112 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
113
114 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
115 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
116 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
117 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
118 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
119 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
120 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
121 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
122
123 #define CISR_FTO (1 << 15) /* FIFO time-out */
124 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
125 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
126 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
127 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
128 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
129 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
130 #define CISR_EOL (1 << 8) /* End of line */
131 #define CISR_PAR_ERR (1 << 7) /* Parity error */
132 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
133 #define CISR_CDD (1 << 5) /* Camera interface disable done */
134 #define CISR_SOF (1 << 4) /* Start of frame */
135 #define CISR_EOF (1 << 3) /* End of frame */
136 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
137 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
138 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
139
140 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
141 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
142 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
143 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
144 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
145 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
146 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
147 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
148
149 #define CICR0_SIM_MP (0 << 24)
150 #define CICR0_SIM_SP (1 << 24)
151 #define CICR0_SIM_MS (2 << 24)
152 #define CICR0_SIM_EP (3 << 24)
153 #define CICR0_SIM_ES (4 << 24)
154
155 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
156 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
157 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
158 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
159 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
160
161 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
162 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
163 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
164 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
165 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
166
167 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
168 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
169 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
170 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
171
172 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
173 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
174 CICR0_EOFM | CICR0_FOM)
175
176 #define sensor_call(cam, o, f, args...) \
177 v4l2_subdev_call(cam->sensor, o, f, ##args)
178
179 /*
180 * Format handling
181 */
182
183 /**
184 * enum pxa_mbus_packing - data packing types on the media-bus
185 * @PXA_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM, one
186 * sample represents one pixel
187 * @PXA_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
188 * possibly incomplete byte high bits are padding
189 * @PXA_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended
190 * to 16 bits
191 */
192 enum pxa_mbus_packing {
193 PXA_MBUS_PACKING_NONE,
194 PXA_MBUS_PACKING_2X8_PADHI,
195 PXA_MBUS_PACKING_EXTEND16,
196 };
197
198 /**
199 * enum pxa_mbus_order - sample order on the media bus
200 * @PXA_MBUS_ORDER_LE: least significant sample first
201 * @PXA_MBUS_ORDER_BE: most significant sample first
202 */
203 enum pxa_mbus_order {
204 PXA_MBUS_ORDER_LE,
205 PXA_MBUS_ORDER_BE,
206 };
207
208 /**
209 * enum pxa_mbus_layout - planes layout in memory
210 * @PXA_MBUS_LAYOUT_PACKED: color components packed
211 * @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V: YUV components stored in 3 planes (4:2:2)
212 * @PXA_MBUS_LAYOUT_PLANAR_2Y_C: YUV components stored in a luma and a
213 * chroma plane (C plane is half the size
214 * of Y plane)
215 * @PXA_MBUS_LAYOUT_PLANAR_Y_C: YUV components stored in a luma and a
216 * chroma plane (C plane is the same size
217 * as Y plane)
218 */
219 enum pxa_mbus_layout {
220 PXA_MBUS_LAYOUT_PACKED = 0,
221 PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
222 PXA_MBUS_LAYOUT_PLANAR_2Y_C,
223 PXA_MBUS_LAYOUT_PLANAR_Y_C,
224 };
225
226 /**
227 * struct pxa_mbus_pixelfmt - Data format on the media bus
228 * @name: Name of the format
229 * @fourcc: Fourcc code, that will be obtained if the data is
230 * stored in memory in the following way:
231 * @packing: Type of sample-packing, that has to be used
232 * @order: Sample order when storing in memory
233 * @layout: Planes layout in memory
234 * @bits_per_sample: How many bits the bridge has to sample
235 */
236 struct pxa_mbus_pixelfmt {
237 const char *name;
238 u32 fourcc;
239 enum pxa_mbus_packing packing;
240 enum pxa_mbus_order order;
241 enum pxa_mbus_layout layout;
242 u8 bits_per_sample;
243 };
244
245 /**
246 * struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
247 * @code: mediabus pixel-code
248 * @fmt: pixel format description
249 */
250 struct pxa_mbus_lookup {
251 u32 code;
252 struct pxa_mbus_pixelfmt fmt;
253 };
254
255 static const struct pxa_mbus_lookup mbus_fmt[] = {
256 {
257 .code = MEDIA_BUS_FMT_YUYV8_2X8,
258 .fmt = {
259 .fourcc = V4L2_PIX_FMT_YUYV,
260 .name = "YUYV",
261 .bits_per_sample = 8,
262 .packing = PXA_MBUS_PACKING_2X8_PADHI,
263 .order = PXA_MBUS_ORDER_LE,
264 .layout = PXA_MBUS_LAYOUT_PACKED,
265 },
266 }, {
267 .code = MEDIA_BUS_FMT_YVYU8_2X8,
268 .fmt = {
269 .fourcc = V4L2_PIX_FMT_YVYU,
270 .name = "YVYU",
271 .bits_per_sample = 8,
272 .packing = PXA_MBUS_PACKING_2X8_PADHI,
273 .order = PXA_MBUS_ORDER_LE,
274 .layout = PXA_MBUS_LAYOUT_PACKED,
275 },
276 }, {
277 .code = MEDIA_BUS_FMT_UYVY8_2X8,
278 .fmt = {
279 .fourcc = V4L2_PIX_FMT_UYVY,
280 .name = "UYVY",
281 .bits_per_sample = 8,
282 .packing = PXA_MBUS_PACKING_2X8_PADHI,
283 .order = PXA_MBUS_ORDER_LE,
284 .layout = PXA_MBUS_LAYOUT_PACKED,
285 },
286 }, {
287 .code = MEDIA_BUS_FMT_VYUY8_2X8,
288 .fmt = {
289 .fourcc = V4L2_PIX_FMT_VYUY,
290 .name = "VYUY",
291 .bits_per_sample = 8,
292 .packing = PXA_MBUS_PACKING_2X8_PADHI,
293 .order = PXA_MBUS_ORDER_LE,
294 .layout = PXA_MBUS_LAYOUT_PACKED,
295 },
296 }, {
297 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
298 .fmt = {
299 .fourcc = V4L2_PIX_FMT_RGB555,
300 .name = "RGB555",
301 .bits_per_sample = 8,
302 .packing = PXA_MBUS_PACKING_2X8_PADHI,
303 .order = PXA_MBUS_ORDER_LE,
304 .layout = PXA_MBUS_LAYOUT_PACKED,
305 },
306 }, {
307 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
308 .fmt = {
309 .fourcc = V4L2_PIX_FMT_RGB555X,
310 .name = "RGB555X",
311 .bits_per_sample = 8,
312 .packing = PXA_MBUS_PACKING_2X8_PADHI,
313 .order = PXA_MBUS_ORDER_BE,
314 .layout = PXA_MBUS_LAYOUT_PACKED,
315 },
316 }, {
317 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
318 .fmt = {
319 .fourcc = V4L2_PIX_FMT_RGB565,
320 .name = "RGB565",
321 .bits_per_sample = 8,
322 .packing = PXA_MBUS_PACKING_2X8_PADHI,
323 .order = PXA_MBUS_ORDER_LE,
324 .layout = PXA_MBUS_LAYOUT_PACKED,
325 },
326 }, {
327 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
328 .fmt = {
329 .fourcc = V4L2_PIX_FMT_RGB565X,
330 .name = "RGB565X",
331 .bits_per_sample = 8,
332 .packing = PXA_MBUS_PACKING_2X8_PADHI,
333 .order = PXA_MBUS_ORDER_BE,
334 .layout = PXA_MBUS_LAYOUT_PACKED,
335 },
336 }, {
337 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
338 .fmt = {
339 .fourcc = V4L2_PIX_FMT_SBGGR8,
340 .name = "Bayer 8 BGGR",
341 .bits_per_sample = 8,
342 .packing = PXA_MBUS_PACKING_NONE,
343 .order = PXA_MBUS_ORDER_LE,
344 .layout = PXA_MBUS_LAYOUT_PACKED,
345 },
346 }, {
347 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
348 .fmt = {
349 .fourcc = V4L2_PIX_FMT_SGBRG8,
350 .name = "Bayer 8 GBRG",
351 .bits_per_sample = 8,
352 .packing = PXA_MBUS_PACKING_NONE,
353 .order = PXA_MBUS_ORDER_LE,
354 .layout = PXA_MBUS_LAYOUT_PACKED,
355 },
356 }, {
357 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
358 .fmt = {
359 .fourcc = V4L2_PIX_FMT_SGRBG8,
360 .name = "Bayer 8 GRBG",
361 .bits_per_sample = 8,
362 .packing = PXA_MBUS_PACKING_NONE,
363 .order = PXA_MBUS_ORDER_LE,
364 .layout = PXA_MBUS_LAYOUT_PACKED,
365 },
366 }, {
367 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
368 .fmt = {
369 .fourcc = V4L2_PIX_FMT_SRGGB8,
370 .name = "Bayer 8 RGGB",
371 .bits_per_sample = 8,
372 .packing = PXA_MBUS_PACKING_NONE,
373 .order = PXA_MBUS_ORDER_LE,
374 .layout = PXA_MBUS_LAYOUT_PACKED,
375 },
376 }, {
377 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
378 .fmt = {
379 .fourcc = V4L2_PIX_FMT_SBGGR10,
380 .name = "Bayer 10 BGGR",
381 .bits_per_sample = 10,
382 .packing = PXA_MBUS_PACKING_EXTEND16,
383 .order = PXA_MBUS_ORDER_LE,
384 .layout = PXA_MBUS_LAYOUT_PACKED,
385 },
386 }, {
387 .code = MEDIA_BUS_FMT_Y8_1X8,
388 .fmt = {
389 .fourcc = V4L2_PIX_FMT_GREY,
390 .name = "Grey",
391 .bits_per_sample = 8,
392 .packing = PXA_MBUS_PACKING_NONE,
393 .order = PXA_MBUS_ORDER_LE,
394 .layout = PXA_MBUS_LAYOUT_PACKED,
395 },
396 }, {
397 .code = MEDIA_BUS_FMT_Y10_1X10,
398 .fmt = {
399 .fourcc = V4L2_PIX_FMT_Y10,
400 .name = "Grey 10bit",
401 .bits_per_sample = 10,
402 .packing = PXA_MBUS_PACKING_EXTEND16,
403 .order = PXA_MBUS_ORDER_LE,
404 .layout = PXA_MBUS_LAYOUT_PACKED,
405 },
406 }, {
407 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
408 .fmt = {
409 .fourcc = V4L2_PIX_FMT_SBGGR10,
410 .name = "Bayer 10 BGGR",
411 .bits_per_sample = 8,
412 .packing = PXA_MBUS_PACKING_2X8_PADHI,
413 .order = PXA_MBUS_ORDER_LE,
414 .layout = PXA_MBUS_LAYOUT_PACKED,
415 },
416 }, {
417 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE,
418 .fmt = {
419 .fourcc = V4L2_PIX_FMT_SBGGR10,
420 .name = "Bayer 10 BGGR",
421 .bits_per_sample = 8,
422 .packing = PXA_MBUS_PACKING_2X8_PADHI,
423 .order = PXA_MBUS_ORDER_BE,
424 .layout = PXA_MBUS_LAYOUT_PACKED,
425 },
426 }, {
427 .code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE,
428 .fmt = {
429 .fourcc = V4L2_PIX_FMT_RGB444,
430 .name = "RGB444",
431 .bits_per_sample = 8,
432 .packing = PXA_MBUS_PACKING_2X8_PADHI,
433 .order = PXA_MBUS_ORDER_BE,
434 .layout = PXA_MBUS_LAYOUT_PACKED,
435 },
436 }, {
437 .code = MEDIA_BUS_FMT_UYVY8_1X16,
438 .fmt = {
439 .fourcc = V4L2_PIX_FMT_UYVY,
440 .name = "UYVY 16bit",
441 .bits_per_sample = 16,
442 .packing = PXA_MBUS_PACKING_EXTEND16,
443 .order = PXA_MBUS_ORDER_LE,
444 .layout = PXA_MBUS_LAYOUT_PACKED,
445 },
446 }, {
447 .code = MEDIA_BUS_FMT_VYUY8_1X16,
448 .fmt = {
449 .fourcc = V4L2_PIX_FMT_VYUY,
450 .name = "VYUY 16bit",
451 .bits_per_sample = 16,
452 .packing = PXA_MBUS_PACKING_EXTEND16,
453 .order = PXA_MBUS_ORDER_LE,
454 .layout = PXA_MBUS_LAYOUT_PACKED,
455 },
456 }, {
457 .code = MEDIA_BUS_FMT_YUYV8_1X16,
458 .fmt = {
459 .fourcc = V4L2_PIX_FMT_YUYV,
460 .name = "YUYV 16bit",
461 .bits_per_sample = 16,
462 .packing = PXA_MBUS_PACKING_EXTEND16,
463 .order = PXA_MBUS_ORDER_LE,
464 .layout = PXA_MBUS_LAYOUT_PACKED,
465 },
466 }, {
467 .code = MEDIA_BUS_FMT_YVYU8_1X16,
468 .fmt = {
469 .fourcc = V4L2_PIX_FMT_YVYU,
470 .name = "YVYU 16bit",
471 .bits_per_sample = 16,
472 .packing = PXA_MBUS_PACKING_EXTEND16,
473 .order = PXA_MBUS_ORDER_LE,
474 .layout = PXA_MBUS_LAYOUT_PACKED,
475 },
476 }, {
477 .code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
478 .fmt = {
479 .fourcc = V4L2_PIX_FMT_SGRBG10DPCM8,
480 .name = "Bayer 10 BGGR DPCM 8",
481 .bits_per_sample = 8,
482 .packing = PXA_MBUS_PACKING_NONE,
483 .order = PXA_MBUS_ORDER_LE,
484 .layout = PXA_MBUS_LAYOUT_PACKED,
485 },
486 }, {
487 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
488 .fmt = {
489 .fourcc = V4L2_PIX_FMT_SGBRG10,
490 .name = "Bayer 10 GBRG",
491 .bits_per_sample = 10,
492 .packing = PXA_MBUS_PACKING_EXTEND16,
493 .order = PXA_MBUS_ORDER_LE,
494 .layout = PXA_MBUS_LAYOUT_PACKED,
495 },
496 }, {
497 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
498 .fmt = {
499 .fourcc = V4L2_PIX_FMT_SGRBG10,
500 .name = "Bayer 10 GRBG",
501 .bits_per_sample = 10,
502 .packing = PXA_MBUS_PACKING_EXTEND16,
503 .order = PXA_MBUS_ORDER_LE,
504 .layout = PXA_MBUS_LAYOUT_PACKED,
505 },
506 }, {
507 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
508 .fmt = {
509 .fourcc = V4L2_PIX_FMT_SRGGB10,
510 .name = "Bayer 10 RGGB",
511 .bits_per_sample = 10,
512 .packing = PXA_MBUS_PACKING_EXTEND16,
513 .order = PXA_MBUS_ORDER_LE,
514 .layout = PXA_MBUS_LAYOUT_PACKED,
515 },
516 }, {
517 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
518 .fmt = {
519 .fourcc = V4L2_PIX_FMT_SBGGR12,
520 .name = "Bayer 12 BGGR",
521 .bits_per_sample = 12,
522 .packing = PXA_MBUS_PACKING_EXTEND16,
523 .order = PXA_MBUS_ORDER_LE,
524 .layout = PXA_MBUS_LAYOUT_PACKED,
525 },
526 }, {
527 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
528 .fmt = {
529 .fourcc = V4L2_PIX_FMT_SGBRG12,
530 .name = "Bayer 12 GBRG",
531 .bits_per_sample = 12,
532 .packing = PXA_MBUS_PACKING_EXTEND16,
533 .order = PXA_MBUS_ORDER_LE,
534 .layout = PXA_MBUS_LAYOUT_PACKED,
535 },
536 }, {
537 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
538 .fmt = {
539 .fourcc = V4L2_PIX_FMT_SGRBG12,
540 .name = "Bayer 12 GRBG",
541 .bits_per_sample = 12,
542 .packing = PXA_MBUS_PACKING_EXTEND16,
543 .order = PXA_MBUS_ORDER_LE,
544 .layout = PXA_MBUS_LAYOUT_PACKED,
545 },
546 }, {
547 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
548 .fmt = {
549 .fourcc = V4L2_PIX_FMT_SRGGB12,
550 .name = "Bayer 12 RGGB",
551 .bits_per_sample = 12,
552 .packing = PXA_MBUS_PACKING_EXTEND16,
553 .order = PXA_MBUS_ORDER_LE,
554 .layout = PXA_MBUS_LAYOUT_PACKED,
555 },
556 },
557 };
558
559 static s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf)
560 {
561 if (mf->layout != PXA_MBUS_LAYOUT_PACKED)
562 return width * mf->bits_per_sample / 8;
563
564 switch (mf->packing) {
565 case PXA_MBUS_PACKING_NONE:
566 return width * mf->bits_per_sample / 8;
567 case PXA_MBUS_PACKING_2X8_PADHI:
568 case PXA_MBUS_PACKING_EXTEND16:
569 return width * 2;
570 }
571 return -EINVAL;
572 }
573
574 static s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf,
575 u32 bytes_per_line, u32 height)
576 {
577 if (mf->layout == PXA_MBUS_LAYOUT_PACKED)
578 return bytes_per_line * height;
579
580 switch (mf->packing) {
581 case PXA_MBUS_PACKING_2X8_PADHI:
582 return bytes_per_line * height * 2;
583 default:
584 return -EINVAL;
585 }
586 }
587
588 static const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc(
589 u32 code,
590 const struct pxa_mbus_lookup *lookup,
591 int n)
592 {
593 int i;
594
595 for (i = 0; i < n; i++)
596 if (lookup[i].code == code)
597 return &lookup[i].fmt;
598
599 return NULL;
600 }
601
602 static const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc(
603 u32 code)
604 {
605 return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
606 }
607
608 /**
609 * struct pxa_camera_format_xlate - match between host and sensor formats
610 * @code: code of a sensor provided format
611 * @host_fmt: host format after host translation from code
612 *
613 * Host and sensor translation structure. Used in table of host and sensor
614 * formats matchings in pxa_camera_device. A host can override the generic list
615 * generation by implementing get_formats(), and use it for format checks and
616 * format setup.
617 */
618 struct pxa_camera_format_xlate {
619 u32 code;
620 const struct pxa_mbus_pixelfmt *host_fmt;
621 };
622
623 /*
624 * Structures
625 */
626 enum pxa_camera_active_dma {
627 DMA_Y = 0x1,
628 DMA_U = 0x2,
629 DMA_V = 0x4,
630 };
631
632 /* buffer for one video frame */
633 struct pxa_buffer {
634 /* common v4l buffer stuff -- must be first */
635 struct vb2_v4l2_buffer vbuf;
636 struct list_head queue;
637 u32 code;
638 int nb_planes;
639 /* our descriptor lists for Y, U and V channels */
640 struct dma_async_tx_descriptor *descs[3];
641 dma_cookie_t cookie[3];
642 struct scatterlist *sg[3];
643 int sg_len[3];
644 size_t plane_sizes[3];
645 int inwork;
646 enum pxa_camera_active_dma active_dma;
647 };
648
649 struct pxa_camera_dev {
650 struct v4l2_device v4l2_dev;
651 struct video_device vdev;
652 struct v4l2_async_notifier notifier;
653 struct vb2_queue vb2_vq;
654 struct v4l2_subdev *sensor;
655 struct pxa_camera_format_xlate *user_formats;
656 const struct pxa_camera_format_xlate *current_fmt;
657 struct v4l2_pix_format current_pix;
658
659 struct v4l2_async_subdev asd;
660
661 /*
662 * PXA27x is only supposed to handle one camera on its Quick Capture
663 * interface. If anyone ever builds hardware to enable more than
664 * one camera, they will have to modify this driver too
665 */
666 struct clk *clk;
667
668 unsigned int irq;
669 void __iomem *base;
670
671 int channels;
672 struct dma_chan *dma_chans[3];
673
674 struct pxacamera_platform_data *pdata;
675 struct resource *res;
676 unsigned long platform_flags;
677 unsigned long ciclk;
678 unsigned long mclk;
679 u32 mclk_divisor;
680 struct v4l2_clk *mclk_clk;
681 u16 width_flags; /* max 10 bits */
682
683 struct list_head capture;
684
685 spinlock_t lock;
686 struct mutex mlock;
687 unsigned int buf_sequence;
688
689 struct pxa_buffer *active;
690 struct tasklet_struct task_eof;
691
692 u32 save_cicr[5];
693 };
694
695 struct pxa_cam {
696 unsigned long flags;
697 };
698
699 static const char *pxa_cam_driver_description = "PXA_Camera";
700
701 /*
702 * Format translation functions
703 */
704 static const struct pxa_camera_format_xlate
705 *pxa_mbus_xlate_by_fourcc(struct pxa_camera_format_xlate *user_formats,
706 unsigned int fourcc)
707 {
708 unsigned int i;
709
710 for (i = 0; user_formats[i].code; i++)
711 if (user_formats[i].host_fmt->fourcc == fourcc)
712 return user_formats + i;
713 return NULL;
714 }
715
716 static struct pxa_camera_format_xlate *pxa_mbus_build_fmts_xlate(
717 struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev,
718 int (*get_formats)(struct v4l2_device *, unsigned int,
719 struct pxa_camera_format_xlate *xlate))
720 {
721 unsigned int i, fmts = 0, raw_fmts = 0;
722 int ret;
723 struct v4l2_subdev_mbus_code_enum code = {
724 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
725 };
726 struct pxa_camera_format_xlate *user_formats;
727
728 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
729 raw_fmts++;
730 code.index++;
731 }
732
733 /*
734 * First pass - only count formats this host-sensor
735 * configuration can provide
736 */
737 for (i = 0; i < raw_fmts; i++) {
738 ret = get_formats(v4l2_dev, i, NULL);
739 if (ret < 0)
740 return ERR_PTR(ret);
741 fmts += ret;
742 }
743
744 if (!fmts)
745 return ERR_PTR(-ENXIO);
746
747 user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL);
748 if (!user_formats)
749 return ERR_PTR(-ENOMEM);
750
751 /* Second pass - actually fill data formats */
752 fmts = 0;
753 for (i = 0; i < raw_fmts; i++) {
754 ret = get_formats(v4l2_dev, i, user_formats + fmts);
755 if (ret < 0)
756 goto egfmt;
757 fmts += ret;
758 }
759 user_formats[fmts].code = 0;
760
761 return user_formats;
762 egfmt:
763 kfree(user_formats);
764 return ERR_PTR(ret);
765 }
766
767 /*
768 * Videobuf operations
769 */
770 static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
771 {
772 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
773
774 return container_of(vbuf, struct pxa_buffer, vbuf);
775 }
776
777 static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
778 {
779 return pcdev->v4l2_dev.dev;
780 }
781
782 static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
783 {
784 return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev);
785 }
786
787 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
788 enum pxa_camera_active_dma act_dma);
789
790 static void pxa_camera_dma_irq_y(void *data)
791 {
792 struct pxa_camera_dev *pcdev = data;
793
794 pxa_camera_dma_irq(pcdev, DMA_Y);
795 }
796
797 static void pxa_camera_dma_irq_u(void *data)
798 {
799 struct pxa_camera_dev *pcdev = data;
800
801 pxa_camera_dma_irq(pcdev, DMA_U);
802 }
803
804 static void pxa_camera_dma_irq_v(void *data)
805 {
806 struct pxa_camera_dev *pcdev = data;
807
808 pxa_camera_dma_irq(pcdev, DMA_V);
809 }
810
811 /**
812 * pxa_init_dma_channel - init dma descriptors
813 * @pcdev: pxa camera device
814 * @buf: pxa camera buffer
815 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
816 * @sg: dma scatter list
817 * @sglen: dma scatter list length
818 *
819 * Prepares the pxa dma descriptors to transfer one camera channel.
820 *
821 * Returns 0 if success or -ENOMEM if no memory is available
822 */
823 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
824 struct pxa_buffer *buf, int channel,
825 struct scatterlist *sg, int sglen)
826 {
827 struct dma_chan *dma_chan = pcdev->dma_chans[channel];
828 struct dma_async_tx_descriptor *tx;
829
830 tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
831 DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
832 if (!tx) {
833 dev_err(pcdev_to_dev(pcdev),
834 "dmaengine_prep_slave_sg failed\n");
835 goto fail;
836 }
837
838 tx->callback_param = pcdev;
839 switch (channel) {
840 case 0:
841 tx->callback = pxa_camera_dma_irq_y;
842 break;
843 case 1:
844 tx->callback = pxa_camera_dma_irq_u;
845 break;
846 case 2:
847 tx->callback = pxa_camera_dma_irq_v;
848 break;
849 }
850
851 buf->descs[channel] = tx;
852 return 0;
853 fail:
854 dev_dbg(pcdev_to_dev(pcdev),
855 "%s (vb=%p) dma_tx=%p\n",
856 __func__, buf, tx);
857
858 return -ENOMEM;
859 }
860
861 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
862 struct pxa_buffer *buf)
863 {
864 buf->active_dma = DMA_Y;
865 if (buf->nb_planes == 3)
866 buf->active_dma |= DMA_U | DMA_V;
867 }
868
869 /**
870 * pxa_dma_start_channels - start DMA channel for active buffer
871 * @pcdev: pxa camera device
872 *
873 * Initialize DMA channels to the beginning of the active video buffer, and
874 * start these channels.
875 */
876 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
877 {
878 int i;
879
880 for (i = 0; i < pcdev->channels; i++) {
881 dev_dbg(pcdev_to_dev(pcdev),
882 "%s (channel=%d)\n", __func__, i);
883 dma_async_issue_pending(pcdev->dma_chans[i]);
884 }
885 }
886
887 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
888 {
889 int i;
890
891 for (i = 0; i < pcdev->channels; i++) {
892 dev_dbg(pcdev_to_dev(pcdev),
893 "%s (channel=%d)\n", __func__, i);
894 dmaengine_terminate_all(pcdev->dma_chans[i]);
895 }
896 }
897
898 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
899 struct pxa_buffer *buf)
900 {
901 int i;
902
903 for (i = 0; i < pcdev->channels; i++) {
904 buf->cookie[i] = dmaengine_submit(buf->descs[i]);
905 dev_dbg(pcdev_to_dev(pcdev),
906 "%s (channel=%d) : submit vb=%p cookie=%d\n",
907 __func__, i, buf, buf->descs[i]->cookie);
908 }
909 }
910
911 /**
912 * pxa_camera_start_capture - start video capturing
913 * @pcdev: camera device
914 *
915 * Launch capturing. DMA channels should not be active yet. They should get
916 * activated at the end of frame interrupt, to capture only whole frames, and
917 * never begin the capture of a partial frame.
918 */
919 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
920 {
921 unsigned long cicr0;
922
923 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
924 __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
925 /* Enable End-Of-Frame Interrupt */
926 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
927 cicr0 &= ~CICR0_EOFM;
928 __raw_writel(cicr0, pcdev->base + CICR0);
929 }
930
931 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
932 {
933 unsigned long cicr0;
934
935 pxa_dma_stop_channels(pcdev);
936
937 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
938 __raw_writel(cicr0, pcdev->base + CICR0);
939
940 pcdev->active = NULL;
941 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
942 }
943
944 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
945 struct pxa_buffer *buf,
946 enum vb2_buffer_state state)
947 {
948 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
949 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
950
951 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
952 list_del_init(&buf->queue);
953 vb->timestamp = ktime_get_ns();
954 vbuf->sequence = pcdev->buf_sequence++;
955 vbuf->field = V4L2_FIELD_NONE;
956 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
957 dev_dbg(pcdev_to_dev(pcdev), "%s dequeued buffer (buf=0x%p)\n",
958 __func__, buf);
959
960 if (list_empty(&pcdev->capture)) {
961 pxa_camera_stop_capture(pcdev);
962 return;
963 }
964
965 pcdev->active = list_entry(pcdev->capture.next,
966 struct pxa_buffer, queue);
967 }
968
969 /**
970 * pxa_camera_check_link_miss - check missed DMA linking
971 * @pcdev: camera device
972 * @last_submitted: an opaque DMA cookie for last submitted
973 * @last_issued: an opaque DMA cookie for last issued
974 *
975 * The DMA chaining is done with DMA running. This means a tiny temporal window
976 * remains, where a buffer is queued on the chain, while the chain is already
977 * stopped. This means the tailed buffer would never be transferred by DMA.
978 * This function restarts the capture for this corner case, where :
979 * - DADR() == DADDR_STOP
980 * - a videobuffer is queued on the pcdev->capture list
981 *
982 * Please check the "DMA hot chaining timeslice issue" in
983 * Documentation/driver-api/media/drivers/pxa_camera.rst
984 *
985 * Context: should only be called within the dma irq handler
986 */
987 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
988 dma_cookie_t last_submitted,
989 dma_cookie_t last_issued)
990 {
991 bool is_dma_stopped = last_submitted != last_issued;
992
993 dev_dbg(pcdev_to_dev(pcdev),
994 "%s : top queued buffer=%p, is_dma_stopped=%d\n",
995 __func__, pcdev->active, is_dma_stopped);
996
997 if (pcdev->active && is_dma_stopped)
998 pxa_camera_start_capture(pcdev);
999 }
1000
1001 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
1002 enum pxa_camera_active_dma act_dma)
1003 {
1004 struct pxa_buffer *buf, *last_buf;
1005 unsigned long flags;
1006 u32 camera_status, overrun;
1007 int chan;
1008 enum dma_status last_status;
1009 dma_cookie_t last_issued;
1010
1011 spin_lock_irqsave(&pcdev->lock, flags);
1012
1013 camera_status = __raw_readl(pcdev->base + CISR);
1014 dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
1015 camera_status, act_dma);
1016 overrun = CISR_IFO_0;
1017 if (pcdev->channels == 3)
1018 overrun |= CISR_IFO_1 | CISR_IFO_2;
1019
1020 /*
1021 * pcdev->active should not be NULL in DMA irq handler.
1022 *
1023 * But there is one corner case : if capture was stopped due to an
1024 * overrun of channel 1, and at that same channel 2 was completed.
1025 *
1026 * When handling the overrun in DMA irq for channel 1, we'll stop the
1027 * capture and restart it (and thus set pcdev->active to NULL). But the
1028 * DMA irq handler will already be pending for channel 2. So on entering
1029 * the DMA irq handler for channel 2 there will be no active buffer, yet
1030 * that is normal.
1031 */
1032 if (!pcdev->active)
1033 goto out;
1034
1035 buf = pcdev->active;
1036 WARN_ON(buf->inwork || list_empty(&buf->queue));
1037
1038 /*
1039 * It's normal if the last frame creates an overrun, as there
1040 * are no more DMA descriptors to fetch from QCI fifos
1041 */
1042 switch (act_dma) {
1043 case DMA_U:
1044 chan = 1;
1045 break;
1046 case DMA_V:
1047 chan = 2;
1048 break;
1049 default:
1050 chan = 0;
1051 break;
1052 }
1053 last_buf = list_entry(pcdev->capture.prev,
1054 struct pxa_buffer, queue);
1055 last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
1056 last_buf->cookie[chan],
1057 NULL, &last_issued);
1058 if (camera_status & overrun &&
1059 last_status != DMA_COMPLETE) {
1060 dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
1061 camera_status);
1062 pxa_camera_stop_capture(pcdev);
1063 list_for_each_entry(buf, &pcdev->capture, queue)
1064 pxa_dma_add_tail_buf(pcdev, buf);
1065 pxa_camera_start_capture(pcdev);
1066 goto out;
1067 }
1068 buf->active_dma &= ~act_dma;
1069 if (!buf->active_dma) {
1070 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE);
1071 pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
1072 last_issued);
1073 }
1074
1075 out:
1076 spin_unlock_irqrestore(&pcdev->lock, flags);
1077 }
1078
1079 static u32 mclk_get_divisor(struct platform_device *pdev,
1080 struct pxa_camera_dev *pcdev)
1081 {
1082 unsigned long mclk = pcdev->mclk;
1083 u32 div;
1084 unsigned long lcdclk;
1085
1086 lcdclk = clk_get_rate(pcdev->clk);
1087 pcdev->ciclk = lcdclk;
1088
1089 /* mclk <= ciclk / 4 (27.4.2) */
1090 if (mclk > lcdclk / 4) {
1091 mclk = lcdclk / 4;
1092 dev_warn(&pdev->dev,
1093 "Limiting master clock to %lu\n", mclk);
1094 }
1095
1096 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
1097 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
1098
1099 /* If we're not supplying MCLK, leave it at 0 */
1100 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1101 pcdev->mclk = lcdclk / (2 * (div + 1));
1102
1103 dev_dbg(&pdev->dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
1104 lcdclk, mclk, div);
1105
1106 return div;
1107 }
1108
1109 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
1110 unsigned long pclk)
1111 {
1112 /* We want a timeout > 1 pixel time, not ">=" */
1113 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
1114
1115 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
1116 }
1117
1118 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
1119 {
1120 u32 cicr4 = 0;
1121
1122 /* disable all interrupts */
1123 __raw_writel(0x3ff, pcdev->base + CICR0);
1124
1125 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1126 cicr4 |= CICR4_PCLK_EN;
1127 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1128 cicr4 |= CICR4_MCLK_EN;
1129 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1130 cicr4 |= CICR4_PCP;
1131 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1132 cicr4 |= CICR4_HSP;
1133 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1134 cicr4 |= CICR4_VSP;
1135
1136 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
1137
1138 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1139 /* Initialise the timeout under the assumption pclk = mclk */
1140 recalculate_fifo_timeout(pcdev, pcdev->mclk);
1141 else
1142 /* "Safe default" - 13MHz */
1143 recalculate_fifo_timeout(pcdev, 13000000);
1144
1145 clk_prepare_enable(pcdev->clk);
1146 }
1147
1148 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
1149 {
1150 clk_disable_unprepare(pcdev->clk);
1151 }
1152
1153 static void pxa_camera_eof(struct tasklet_struct *t)
1154 {
1155 struct pxa_camera_dev *pcdev = from_tasklet(pcdev, t, task_eof);
1156 unsigned long cifr;
1157 struct pxa_buffer *buf;
1158
1159 dev_dbg(pcdev_to_dev(pcdev),
1160 "Camera interrupt status 0x%x\n",
1161 __raw_readl(pcdev->base + CISR));
1162
1163 /* Reset the FIFOs */
1164 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1165 __raw_writel(cifr, pcdev->base + CIFR);
1166
1167 pcdev->active = list_first_entry(&pcdev->capture,
1168 struct pxa_buffer, queue);
1169 buf = pcdev->active;
1170 pxa_videobuf_set_actdma(pcdev, buf);
1171
1172 pxa_dma_start_channels(pcdev);
1173 }
1174
1175 static irqreturn_t pxa_camera_irq(int irq, void *data)
1176 {
1177 struct pxa_camera_dev *pcdev = data;
1178 unsigned long status, cicr0;
1179
1180 status = __raw_readl(pcdev->base + CISR);
1181 dev_dbg(pcdev_to_dev(pcdev),
1182 "Camera interrupt status 0x%lx\n", status);
1183
1184 if (!status)
1185 return IRQ_NONE;
1186
1187 __raw_writel(status, pcdev->base + CISR);
1188
1189 if (status & CISR_EOF) {
1190 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
1191 __raw_writel(cicr0, pcdev->base + CICR0);
1192 tasklet_schedule(&pcdev->task_eof);
1193 }
1194
1195 return IRQ_HANDLED;
1196 }
1197
1198 static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
1199 unsigned long flags, __u32 pixfmt)
1200 {
1201 unsigned long dw, bpp;
1202 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1203 int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
1204
1205 if (ret < 0)
1206 y_skip_top = 0;
1207
1208 /*
1209 * Datawidth is now guaranteed to be equal to one of the three values.
1210 * We fix bit-per-pixel equal to data-width...
1211 */
1212 switch (pcdev->current_fmt->host_fmt->bits_per_sample) {
1213 case 10:
1214 dw = 4;
1215 bpp = 0x40;
1216 break;
1217 case 9:
1218 dw = 3;
1219 bpp = 0x20;
1220 break;
1221 default:
1222 /*
1223 * Actually it can only be 8 now,
1224 * default is just to silence compiler warnings
1225 */
1226 case 8:
1227 dw = 2;
1228 bpp = 0;
1229 }
1230
1231 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1232 cicr4 |= CICR4_PCLK_EN;
1233 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1234 cicr4 |= CICR4_MCLK_EN;
1235 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1236 cicr4 |= CICR4_PCP;
1237 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1238 cicr4 |= CICR4_HSP;
1239 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1240 cicr4 |= CICR4_VSP;
1241
1242 cicr0 = __raw_readl(pcdev->base + CICR0);
1243 if (cicr0 & CICR0_ENB)
1244 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1245
1246 cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw;
1247
1248 switch (pixfmt) {
1249 case V4L2_PIX_FMT_YUV422P:
1250 pcdev->channels = 3;
1251 cicr1 |= CICR1_YCBCR_F;
1252 /*
1253 * Normally, pxa bus wants as input UYVY format. We allow all
1254 * reorderings of the YUV422 format, as no processing is done,
1255 * and the YUV stream is just passed through without any
1256 * transformation. Note that UYVY is the only format that
1257 * should be used if pxa framebuffer Overlay2 is used.
1258 */
1259 fallthrough;
1260 case V4L2_PIX_FMT_UYVY:
1261 case V4L2_PIX_FMT_VYUY:
1262 case V4L2_PIX_FMT_YUYV:
1263 case V4L2_PIX_FMT_YVYU:
1264 cicr1 |= CICR1_COLOR_SP_VAL(2);
1265 break;
1266 case V4L2_PIX_FMT_RGB555:
1267 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1268 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1269 break;
1270 case V4L2_PIX_FMT_RGB565:
1271 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1272 break;
1273 }
1274
1275 cicr2 = 0;
1276 cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) |
1277 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1278 cicr4 |= pcdev->mclk_divisor;
1279
1280 __raw_writel(cicr1, pcdev->base + CICR1);
1281 __raw_writel(cicr2, pcdev->base + CICR2);
1282 __raw_writel(cicr3, pcdev->base + CICR3);
1283 __raw_writel(cicr4, pcdev->base + CICR4);
1284
1285 /* CIF interrupts are not used, only DMA */
1286 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1287 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1288 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1289 __raw_writel(cicr0, pcdev->base + CICR0);
1290 }
1291
1292 /*
1293 * Videobuf2 section
1294 */
1295 static void pxa_buffer_cleanup(struct pxa_buffer *buf)
1296 {
1297 int i;
1298
1299 for (i = 0; i < 3 && buf->descs[i]; i++) {
1300 dmaengine_desc_free(buf->descs[i]);
1301 kfree(buf->sg[i]);
1302 buf->descs[i] = NULL;
1303 buf->sg[i] = NULL;
1304 buf->sg_len[i] = 0;
1305 buf->plane_sizes[i] = 0;
1306 }
1307 buf->nb_planes = 0;
1308 }
1309
1310 static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
1311 struct pxa_buffer *buf)
1312 {
1313 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
1314 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
1315 int nb_channels = pcdev->channels;
1316 int i, ret = 0;
1317 unsigned long size = vb2_plane_size(vb, 0);
1318
1319 switch (nb_channels) {
1320 case 1:
1321 buf->plane_sizes[0] = size;
1322 break;
1323 case 3:
1324 buf->plane_sizes[0] = size / 2;
1325 buf->plane_sizes[1] = size / 4;
1326 buf->plane_sizes[2] = size / 4;
1327 break;
1328 default:
1329 return -EINVAL;
1330 }
1331 buf->nb_planes = nb_channels;
1332
1333 ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
1334 buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
1335 if (ret < 0) {
1336 dev_err(pcdev_to_dev(pcdev),
1337 "sg_split failed: %d\n", ret);
1338 return ret;
1339 }
1340 for (i = 0; i < nb_channels; i++) {
1341 ret = pxa_init_dma_channel(pcdev, buf, i,
1342 buf->sg[i], buf->sg_len[i]);
1343 if (ret) {
1344 pxa_buffer_cleanup(buf);
1345 return ret;
1346 }
1347 }
1348 INIT_LIST_HEAD(&buf->queue);
1349
1350 return ret;
1351 }
1352
1353 static void pxac_vb2_cleanup(struct vb2_buffer *vb)
1354 {
1355 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1356 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1357
1358 dev_dbg(pcdev_to_dev(pcdev),
1359 "%s(vb=%p)\n", __func__, vb);
1360 pxa_buffer_cleanup(buf);
1361 }
1362
1363 static void pxac_vb2_queue(struct vb2_buffer *vb)
1364 {
1365 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1366 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1367
1368 dev_dbg(pcdev_to_dev(pcdev),
1369 "%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
1370 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
1371 pcdev->active);
1372
1373 list_add_tail(&buf->queue, &pcdev->capture);
1374
1375 pxa_dma_add_tail_buf(pcdev, buf);
1376 }
1377
1378 /*
1379 * Please check the DMA prepared buffer structure in :
1380 * Documentation/driver-api/media/drivers/pxa_camera.rst
1381 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
1382 * modification while DMA chain is running will work anyway.
1383 */
1384 static int pxac_vb2_prepare(struct vb2_buffer *vb)
1385 {
1386 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1387 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1388 int ret = 0;
1389
1390 switch (pcdev->channels) {
1391 case 1:
1392 case 3:
1393 vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage);
1394 break;
1395 default:
1396 return -EINVAL;
1397 }
1398
1399 dev_dbg(pcdev_to_dev(pcdev),
1400 "%s (vb=%p) nb_channels=%d size=%lu\n",
1401 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));
1402
1403 WARN_ON(!pcdev->current_fmt);
1404
1405 #ifdef DEBUG
1406 /*
1407 * This can be useful if you want to see if we actually fill
1408 * the buffer with something
1409 */
1410 for (i = 0; i < vb->num_planes; i++)
1411 memset((void *)vb2_plane_vaddr(vb, i),
1412 0xaa, vb2_get_plane_payload(vb, i));
1413 #endif
1414
1415 /*
1416 * I think, in buf_prepare you only have to protect global data,
1417 * the actual buffer is yours
1418 */
1419 buf->inwork = 0;
1420 pxa_videobuf_set_actdma(pcdev, buf);
1421
1422 return ret;
1423 }
1424
1425 static int pxac_vb2_init(struct vb2_buffer *vb)
1426 {
1427 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1428 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1429
1430 dev_dbg(pcdev_to_dev(pcdev),
1431 "%s(nb_channels=%d)\n",
1432 __func__, pcdev->channels);
1433
1434 return pxa_buffer_init(pcdev, buf);
1435 }
1436
1437 static int pxac_vb2_queue_setup(struct vb2_queue *vq,
1438 unsigned int *nbufs,
1439 unsigned int *num_planes, unsigned int sizes[],
1440 struct device *alloc_devs[])
1441 {
1442 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1443 int size = pcdev->current_pix.sizeimage;
1444
1445 dev_dbg(pcdev_to_dev(pcdev),
1446 "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
1447 __func__, vq, *nbufs, *num_planes, size);
1448 /*
1449 * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
1450 * format, even if there are 3 planes Y, U and V, we reply there is only
1451 * one plane, containing Y, U and V data, one after the other.
1452 */
1453 if (*num_planes)
1454 return sizes[0] < size ? -EINVAL : 0;
1455
1456 *num_planes = 1;
1457 switch (pcdev->channels) {
1458 case 1:
1459 case 3:
1460 sizes[0] = size;
1461 break;
1462 default:
1463 return -EINVAL;
1464 }
1465
1466 if (!*nbufs)
1467 *nbufs = 1;
1468
1469 return 0;
1470 }
1471
1472 static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
1473 {
1474 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1475
1476 dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
1477 __func__, count, pcdev->active);
1478
1479 pcdev->buf_sequence = 0;
1480 if (!pcdev->active)
1481 pxa_camera_start_capture(pcdev);
1482
1483 return 0;
1484 }
1485
1486 static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
1487 {
1488 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1489 struct pxa_buffer *buf, *tmp;
1490
1491 dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n",
1492 __func__, pcdev->active);
1493 pxa_camera_stop_capture(pcdev);
1494
1495 list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue)
1496 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR);
1497 }
1498
1499 static const struct vb2_ops pxac_vb2_ops = {
1500 .queue_setup = pxac_vb2_queue_setup,
1501 .buf_init = pxac_vb2_init,
1502 .buf_prepare = pxac_vb2_prepare,
1503 .buf_queue = pxac_vb2_queue,
1504 .buf_cleanup = pxac_vb2_cleanup,
1505 .start_streaming = pxac_vb2_start_streaming,
1506 .stop_streaming = pxac_vb2_stop_streaming,
1507 .wait_prepare = vb2_ops_wait_prepare,
1508 .wait_finish = vb2_ops_wait_finish,
1509 };
1510
1511 static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev)
1512 {
1513 int ret;
1514 struct vb2_queue *vq = &pcdev->vb2_vq;
1515
1516 memset(vq, 0, sizeof(*vq));
1517 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1518 vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1519 vq->drv_priv = pcdev;
1520 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1521 vq->buf_struct_size = sizeof(struct pxa_buffer);
1522 vq->dev = pcdev->v4l2_dev.dev;
1523
1524 vq->ops = &pxac_vb2_ops;
1525 vq->mem_ops = &vb2_dma_sg_memops;
1526 vq->lock = &pcdev->mlock;
1527
1528 ret = vb2_queue_init(vq);
1529 dev_dbg(pcdev_to_dev(pcdev),
1530 "vb2_queue_init(vq=%p): %d\n", vq, ret);
1531
1532 return ret;
1533 }
1534
1535 /*
1536 * Video ioctls section
1537 */
1538 static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev)
1539 {
1540 unsigned int bus_width = pcdev->current_fmt->host_fmt->bits_per_sample;
1541 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1542 u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc;
1543 int mbus_config;
1544 int ret;
1545
1546 if (!((1 << (bus_width - 1)) & pcdev->width_flags)) {
1547 dev_err(pcdev_to_dev(pcdev), "Unsupported bus width %u",
1548 bus_width);
1549 return -EINVAL;
1550 }
1551
1552 pcdev->channels = 1;
1553
1554 /* Make choices, based on platform preferences */
1555 mbus_config = 0;
1556 if (pcdev->platform_flags & PXA_CAMERA_MASTER)
1557 mbus_config |= V4L2_MBUS_MASTER;
1558 else
1559 mbus_config |= V4L2_MBUS_SLAVE;
1560
1561 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1562 mbus_config |= V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1563 else
1564 mbus_config |= V4L2_MBUS_HSYNC_ACTIVE_LOW;
1565
1566 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1567 mbus_config |= V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1568 else
1569 mbus_config |= V4L2_MBUS_VSYNC_ACTIVE_LOW;
1570
1571 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1572 mbus_config |= V4L2_MBUS_PCLK_SAMPLE_RISING;
1573 else
1574 mbus_config |= V4L2_MBUS_PCLK_SAMPLE_FALLING;
1575 mbus_config |= V4L2_MBUS_DATA_ACTIVE_HIGH;
1576
1577 cfg.flags = mbus_config;
1578 ret = sensor_call(pcdev, pad, set_mbus_config, 0, &cfg);
1579 if (ret < 0 && ret != -ENOIOCTLCMD) {
1580 dev_err(pcdev_to_dev(pcdev),
1581 "Failed to call set_mbus_config: %d\n", ret);
1582 return ret;
1583 }
1584
1585 /*
1586 * If the requested media bus configuration has not been fully applied
1587 * make sure it is supported by the platform.
1588 *
1589 * PXA does not support V4L2_MBUS_DATA_ACTIVE_LOW and the bus mastering
1590 * roles should match.
1591 */
1592 if (cfg.flags != mbus_config) {
1593 unsigned int pxa_mbus_role = mbus_config & (V4L2_MBUS_MASTER |
1594 V4L2_MBUS_SLAVE);
1595 if (pxa_mbus_role != (cfg.flags & (V4L2_MBUS_MASTER |
1596 V4L2_MBUS_SLAVE))) {
1597 dev_err(pcdev_to_dev(pcdev),
1598 "Unsupported mbus configuration: bus mastering\n");
1599 return -EINVAL;
1600 }
1601
1602 if (cfg.flags & V4L2_MBUS_DATA_ACTIVE_LOW) {
1603 dev_err(pcdev_to_dev(pcdev),
1604 "Unsupported mbus configuration: DATA_ACTIVE_LOW\n");
1605 return -EINVAL;
1606 }
1607 }
1608
1609 pxa_camera_setup_cicr(pcdev, cfg.flags, pixfmt);
1610
1611 return 0;
1612 }
1613
1614 static const struct pxa_mbus_pixelfmt pxa_camera_formats[] = {
1615 {
1616 .fourcc = V4L2_PIX_FMT_YUV422P,
1617 .name = "Planar YUV422 16 bit",
1618 .bits_per_sample = 8,
1619 .packing = PXA_MBUS_PACKING_2X8_PADHI,
1620 .order = PXA_MBUS_ORDER_LE,
1621 .layout = PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
1622 },
1623 };
1624
1625 /* This will be corrected as we get more formats */
1626 static bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt)
1627 {
1628 return fmt->packing == PXA_MBUS_PACKING_NONE ||
1629 (fmt->bits_per_sample == 8 &&
1630 fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) ||
1631 (fmt->bits_per_sample > 8 &&
1632 fmt->packing == PXA_MBUS_PACKING_EXTEND16);
1633 }
1634
1635 static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
1636 unsigned int idx,
1637 struct pxa_camera_format_xlate *xlate)
1638 {
1639 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
1640 int formats = 0, ret;
1641 struct v4l2_subdev_mbus_code_enum code = {
1642 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1643 .index = idx,
1644 };
1645 const struct pxa_mbus_pixelfmt *fmt;
1646
1647 ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
1648 if (ret < 0)
1649 /* No more formats */
1650 return 0;
1651
1652 fmt = pxa_mbus_get_fmtdesc(code.code);
1653 if (!fmt) {
1654 dev_err(pcdev_to_dev(pcdev),
1655 "Invalid format code #%u: %d\n", idx, code.code);
1656 return 0;
1657 }
1658
1659 switch (code.code) {
1660 case MEDIA_BUS_FMT_UYVY8_2X8:
1661 formats++;
1662 if (xlate) {
1663 xlate->host_fmt = &pxa_camera_formats[0];
1664 xlate->code = code.code;
1665 xlate++;
1666 dev_dbg(pcdev_to_dev(pcdev),
1667 "Providing format %s using code %d\n",
1668 pxa_camera_formats[0].name, code.code);
1669 }
1670 fallthrough;
1671 case MEDIA_BUS_FMT_VYUY8_2X8:
1672 case MEDIA_BUS_FMT_YUYV8_2X8:
1673 case MEDIA_BUS_FMT_YVYU8_2X8:
1674 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1675 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1676 if (xlate)
1677 dev_dbg(pcdev_to_dev(pcdev),
1678 "Providing format %s packed\n",
1679 fmt->name);
1680 break;
1681 default:
1682 if (!pxa_camera_packing_supported(fmt))
1683 return 0;
1684 if (xlate)
1685 dev_dbg(pcdev_to_dev(pcdev),
1686 "Providing format %s in pass-through mode\n",
1687 fmt->name);
1688 break;
1689 }
1690
1691 /* Generic pass-through */
1692 formats++;
1693 if (xlate) {
1694 xlate->host_fmt = fmt;
1695 xlate->code = code.code;
1696 xlate++;
1697 }
1698
1699 return formats;
1700 }
1701
1702 static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev)
1703 {
1704 struct pxa_camera_format_xlate *xlate;
1705
1706 xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor,
1707 pxa_camera_get_formats);
1708 if (IS_ERR(xlate))
1709 return PTR_ERR(xlate);
1710
1711 pcdev->user_formats = xlate;
1712 return 0;
1713 }
1714
1715 static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev)
1716 {
1717 kfree(pcdev->user_formats);
1718 }
1719
1720 static int pxa_camera_check_frame(u32 width, u32 height)
1721 {
1722 /* limit to pxa hardware capabilities */
1723 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1724 (width & 0x01);
1725 }
1726
1727 #ifdef CONFIG_VIDEO_ADV_DEBUG
1728 static int pxac_vidioc_g_register(struct file *file, void *priv,
1729 struct v4l2_dbg_register *reg)
1730 {
1731 struct pxa_camera_dev *pcdev = video_drvdata(file);
1732
1733 if (reg->reg > CIBR2)
1734 return -ERANGE;
1735
1736 reg->val = __raw_readl(pcdev->base + reg->reg);
1737 reg->size = sizeof(__u32);
1738 return 0;
1739 }
1740
1741 static int pxac_vidioc_s_register(struct file *file, void *priv,
1742 const struct v4l2_dbg_register *reg)
1743 {
1744 struct pxa_camera_dev *pcdev = video_drvdata(file);
1745
1746 if (reg->reg > CIBR2)
1747 return -ERANGE;
1748 if (reg->size != sizeof(__u32))
1749 return -EINVAL;
1750 __raw_writel(reg->val, pcdev->base + reg->reg);
1751 return 0;
1752 }
1753 #endif
1754
1755 static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void *priv,
1756 struct v4l2_fmtdesc *f)
1757 {
1758 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1759 const struct pxa_mbus_pixelfmt *format;
1760 unsigned int idx;
1761
1762 for (idx = 0; pcdev->user_formats[idx].code; idx++);
1763 if (f->index >= idx)
1764 return -EINVAL;
1765
1766 format = pcdev->user_formats[f->index].host_fmt;
1767 f->pixelformat = format->fourcc;
1768 return 0;
1769 }
1770
1771 static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1772 struct v4l2_format *f)
1773 {
1774 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1775 struct v4l2_pix_format *pix = &f->fmt.pix;
1776
1777 pix->width = pcdev->current_pix.width;
1778 pix->height = pcdev->current_pix.height;
1779 pix->bytesperline = pcdev->current_pix.bytesperline;
1780 pix->sizeimage = pcdev->current_pix.sizeimage;
1781 pix->field = pcdev->current_pix.field;
1782 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
1783 pix->colorspace = pcdev->current_pix.colorspace;
1784 dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n",
1785 pcdev->current_fmt->host_fmt->fourcc);
1786 return 0;
1787 }
1788
1789 static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1790 struct v4l2_format *f)
1791 {
1792 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1793 const struct pxa_camera_format_xlate *xlate;
1794 struct v4l2_pix_format *pix = &f->fmt.pix;
1795 struct v4l2_subdev_pad_config pad_cfg;
1796 struct v4l2_subdev_format format = {
1797 .which = V4L2_SUBDEV_FORMAT_TRY,
1798 };
1799 struct v4l2_mbus_framefmt *mf = &format.format;
1800 __u32 pixfmt = pix->pixelformat;
1801 int ret;
1802
1803 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt);
1804 if (!xlate) {
1805 dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
1806 return -EINVAL;
1807 }
1808
1809 /*
1810 * Limit to pxa hardware capabilities. YUV422P planar format requires
1811 * images size to be a multiple of 16 bytes. If not, zeros will be
1812 * inserted between Y and U planes, and U and V planes, which violates
1813 * the YUV422P standard.
1814 */
1815 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1816 &pix->height, 32, 2048, 0,
1817 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1818
1819 v4l2_fill_mbus_format(mf, pix, xlate->code);
1820 ret = sensor_call(pcdev, pad, set_fmt, &pad_cfg, &format);
1821 if (ret < 0)
1822 return ret;
1823
1824 v4l2_fill_pix_format(pix, mf);
1825
1826 /* Only progressive video supported so far */
1827 switch (mf->field) {
1828 case V4L2_FIELD_ANY:
1829 case V4L2_FIELD_NONE:
1830 pix->field = V4L2_FIELD_NONE;
1831 break;
1832 default:
1833 /* TODO: support interlaced at least in pass-through mode */
1834 dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
1835 mf->field);
1836 return -EINVAL;
1837 }
1838
1839 ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt);
1840 if (ret < 0)
1841 return ret;
1842
1843 pix->bytesperline = ret;
1844 ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline,
1845 pix->height);
1846 if (ret < 0)
1847 return ret;
1848
1849 pix->sizeimage = ret;
1850 return 0;
1851 }
1852
1853 static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1854 struct v4l2_format *f)
1855 {
1856 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1857 const struct pxa_camera_format_xlate *xlate;
1858 struct v4l2_pix_format *pix = &f->fmt.pix;
1859 struct v4l2_subdev_format format = {
1860 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1861 };
1862 unsigned long flags;
1863 int ret, is_busy;
1864
1865 dev_dbg(pcdev_to_dev(pcdev),
1866 "s_fmt_vid_cap(pix=%dx%d:%x)\n",
1867 pix->width, pix->height, pix->pixelformat);
1868
1869 spin_lock_irqsave(&pcdev->lock, flags);
1870 is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq);
1871 spin_unlock_irqrestore(&pcdev->lock, flags);
1872
1873 if (is_busy)
1874 return -EBUSY;
1875
1876 ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f);
1877 if (ret)
1878 return ret;
1879
1880 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats,
1881 pix->pixelformat);
1882 v4l2_fill_mbus_format(&format.format, pix, xlate->code);
1883 ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
1884 if (ret < 0) {
1885 dev_warn(pcdev_to_dev(pcdev),
1886 "Failed to configure for format %x\n",
1887 pix->pixelformat);
1888 } else if (pxa_camera_check_frame(pix->width, pix->height)) {
1889 dev_warn(pcdev_to_dev(pcdev),
1890 "Camera driver produced an unsupported frame %dx%d\n",
1891 pix->width, pix->height);
1892 return -EINVAL;
1893 }
1894
1895 pcdev->current_fmt = xlate;
1896 pcdev->current_pix = *pix;
1897
1898 ret = pxa_camera_set_bus_param(pcdev);
1899 return ret;
1900 }
1901
1902 static int pxac_vidioc_querycap(struct file *file, void *priv,
1903 struct v4l2_capability *cap)
1904 {
1905 strscpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info));
1906 strscpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver));
1907 strscpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1908 return 0;
1909 }
1910
1911 static int pxac_vidioc_enum_input(struct file *file, void *priv,
1912 struct v4l2_input *i)
1913 {
1914 if (i->index > 0)
1915 return -EINVAL;
1916
1917 i->type = V4L2_INPUT_TYPE_CAMERA;
1918 strscpy(i->name, "Camera", sizeof(i->name));
1919
1920 return 0;
1921 }
1922
1923 static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1924 {
1925 *i = 0;
1926
1927 return 0;
1928 }
1929
1930 static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i)
1931 {
1932 if (i > 0)
1933 return -EINVAL;
1934
1935 return 0;
1936 }
1937
1938 static int pxac_sensor_set_power(struct pxa_camera_dev *pcdev, int on)
1939 {
1940 int ret;
1941
1942 ret = sensor_call(pcdev, core, s_power, on);
1943 if (ret == -ENOIOCTLCMD)
1944 ret = 0;
1945 if (ret) {
1946 dev_warn(pcdev_to_dev(pcdev),
1947 "Failed to put subdevice in %s mode: %d\n",
1948 on ? "normal operation" : "power saving", ret);
1949 }
1950
1951 return ret;
1952 }
1953
1954 static int pxac_fops_camera_open(struct file *filp)
1955 {
1956 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1957 int ret;
1958
1959 mutex_lock(&pcdev->mlock);
1960 ret = v4l2_fh_open(filp);
1961 if (ret < 0)
1962 goto out;
1963
1964 if (!v4l2_fh_is_singular_file(filp))
1965 goto out;
1966
1967 ret = pxac_sensor_set_power(pcdev, 1);
1968 if (ret)
1969 v4l2_fh_release(filp);
1970 out:
1971 mutex_unlock(&pcdev->mlock);
1972 return ret;
1973 }
1974
1975 static int pxac_fops_camera_release(struct file *filp)
1976 {
1977 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1978 int ret;
1979 bool fh_singular;
1980
1981 mutex_lock(&pcdev->mlock);
1982
1983 fh_singular = v4l2_fh_is_singular_file(filp);
1984
1985 ret = _vb2_fop_release(filp, NULL);
1986
1987 if (fh_singular)
1988 ret = pxac_sensor_set_power(pcdev, 0);
1989
1990 mutex_unlock(&pcdev->mlock);
1991
1992 return ret;
1993 }
1994
1995 static const struct v4l2_file_operations pxa_camera_fops = {
1996 .owner = THIS_MODULE,
1997 .open = pxac_fops_camera_open,
1998 .release = pxac_fops_camera_release,
1999 .read = vb2_fop_read,
2000 .poll = vb2_fop_poll,
2001 .mmap = vb2_fop_mmap,
2002 .unlocked_ioctl = video_ioctl2,
2003 };
2004
2005 static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = {
2006 .vidioc_querycap = pxac_vidioc_querycap,
2007
2008 .vidioc_enum_input = pxac_vidioc_enum_input,
2009 .vidioc_g_input = pxac_vidioc_g_input,
2010 .vidioc_s_input = pxac_vidioc_s_input,
2011
2012 .vidioc_enum_fmt_vid_cap = pxac_vidioc_enum_fmt_vid_cap,
2013 .vidioc_g_fmt_vid_cap = pxac_vidioc_g_fmt_vid_cap,
2014 .vidioc_s_fmt_vid_cap = pxac_vidioc_s_fmt_vid_cap,
2015 .vidioc_try_fmt_vid_cap = pxac_vidioc_try_fmt_vid_cap,
2016
2017 .vidioc_reqbufs = vb2_ioctl_reqbufs,
2018 .vidioc_create_bufs = vb2_ioctl_create_bufs,
2019 .vidioc_querybuf = vb2_ioctl_querybuf,
2020 .vidioc_qbuf = vb2_ioctl_qbuf,
2021 .vidioc_dqbuf = vb2_ioctl_dqbuf,
2022 .vidioc_expbuf = vb2_ioctl_expbuf,
2023 .vidioc_streamon = vb2_ioctl_streamon,
2024 .vidioc_streamoff = vb2_ioctl_streamoff,
2025 #ifdef CONFIG_VIDEO_ADV_DEBUG
2026 .vidioc_g_register = pxac_vidioc_g_register,
2027 .vidioc_s_register = pxac_vidioc_s_register,
2028 #endif
2029 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
2030 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2031 };
2032
2033 static const struct v4l2_clk_ops pxa_camera_mclk_ops = {
2034 };
2035
2036 static const struct video_device pxa_camera_videodev_template = {
2037 .name = "pxa-camera",
2038 .minor = -1,
2039 .fops = &pxa_camera_fops,
2040 .ioctl_ops = &pxa_camera_ioctl_ops,
2041 .release = video_device_release_empty,
2042 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
2043 };
2044
2045 static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier,
2046 struct v4l2_subdev *subdev,
2047 struct v4l2_async_subdev *asd)
2048 {
2049 int err;
2050 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
2051 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
2052 struct video_device *vdev = &pcdev->vdev;
2053 struct v4l2_pix_format *pix = &pcdev->current_pix;
2054 struct v4l2_subdev_format format = {
2055 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2056 };
2057 struct v4l2_mbus_framefmt *mf = &format.format;
2058
2059 dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n",
2060 __func__);
2061 mutex_lock(&pcdev->mlock);
2062 *vdev = pxa_camera_videodev_template;
2063 vdev->v4l2_dev = v4l2_dev;
2064 vdev->lock = &pcdev->mlock;
2065 pcdev->sensor = subdev;
2066 pcdev->vdev.queue = &pcdev->vb2_vq;
2067 pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev;
2068 pcdev->vdev.ctrl_handler = subdev->ctrl_handler;
2069 video_set_drvdata(&pcdev->vdev, pcdev);
2070
2071 err = pxa_camera_build_formats(pcdev);
2072 if (err) {
2073 dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n",
2074 err);
2075 goto out;
2076 }
2077
2078 pcdev->current_fmt = pcdev->user_formats;
2079 pix->field = V4L2_FIELD_NONE;
2080 pix->width = DEFAULT_WIDTH;
2081 pix->height = DEFAULT_HEIGHT;
2082 pix->bytesperline =
2083 pxa_mbus_bytes_per_line(pix->width,
2084 pcdev->current_fmt->host_fmt);
2085 pix->sizeimage =
2086 pxa_mbus_image_size(pcdev->current_fmt->host_fmt,
2087 pix->bytesperline, pix->height);
2088 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
2089 v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code);
2090
2091 err = pxac_sensor_set_power(pcdev, 1);
2092 if (err)
2093 goto out;
2094
2095 err = sensor_call(pcdev, pad, set_fmt, NULL, &format);
2096 if (err)
2097 goto out_sensor_poweroff;
2098
2099 v4l2_fill_pix_format(pix, mf);
2100 pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n",
2101 __func__, pix->colorspace, pix->pixelformat);
2102
2103 err = pxa_camera_init_videobuf2(pcdev);
2104 if (err)
2105 goto out_sensor_poweroff;
2106
2107 err = video_register_device(&pcdev->vdev, VFL_TYPE_VIDEO, -1);
2108 if (err) {
2109 v4l2_err(v4l2_dev, "register video device failed: %d\n", err);
2110 pcdev->sensor = NULL;
2111 } else {
2112 dev_info(pcdev_to_dev(pcdev),
2113 "PXA Camera driver attached to camera %s\n",
2114 subdev->name);
2115 }
2116
2117 out_sensor_poweroff:
2118 err = pxac_sensor_set_power(pcdev, 0);
2119 out:
2120 mutex_unlock(&pcdev->mlock);
2121 return err;
2122 }
2123
2124 static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
2125 struct v4l2_subdev *subdev,
2126 struct v4l2_async_subdev *asd)
2127 {
2128 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev);
2129
2130 mutex_lock(&pcdev->mlock);
2131 dev_info(pcdev_to_dev(pcdev),
2132 "PXA Camera driver detached from camera %s\n",
2133 subdev->name);
2134
2135 /* disable capture, disable interrupts */
2136 __raw_writel(0x3ff, pcdev->base + CICR0);
2137
2138 /* Stop DMA engine */
2139 pxa_dma_stop_channels(pcdev);
2140
2141 pxa_camera_destroy_formats(pcdev);
2142
2143 if (pcdev->mclk_clk) {
2144 v4l2_clk_unregister(pcdev->mclk_clk);
2145 pcdev->mclk_clk = NULL;
2146 }
2147
2148 video_unregister_device(&pcdev->vdev);
2149 pcdev->sensor = NULL;
2150
2151 mutex_unlock(&pcdev->mlock);
2152 }
2153
2154 static const struct v4l2_async_notifier_operations pxa_camera_sensor_ops = {
2155 .bound = pxa_camera_sensor_bound,
2156 .unbind = pxa_camera_sensor_unbind,
2157 };
2158
2159 /*
2160 * Driver probe, remove, suspend and resume operations
2161 */
2162 static int pxa_camera_suspend(struct device *dev)
2163 {
2164 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2165 int i = 0, ret = 0;
2166
2167 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
2168 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
2169 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
2170 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
2171 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
2172
2173 if (pcdev->sensor)
2174 ret = pxac_sensor_set_power(pcdev, 0);
2175
2176 return ret;
2177 }
2178
2179 static int pxa_camera_resume(struct device *dev)
2180 {
2181 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2182 int i = 0, ret = 0;
2183
2184 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
2185 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
2186 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
2187 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
2188 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
2189
2190 if (pcdev->sensor) {
2191 ret = pxac_sensor_set_power(pcdev, 1);
2192 }
2193
2194 /* Restart frame capture if active buffer exists */
2195 if (!ret && pcdev->active)
2196 pxa_camera_start_capture(pcdev);
2197
2198 return ret;
2199 }
2200
2201 static int pxa_camera_pdata_from_dt(struct device *dev,
2202 struct pxa_camera_dev *pcdev,
2203 struct v4l2_async_subdev *asd)
2204 {
2205 u32 mclk_rate;
2206 struct device_node *remote, *np = dev->of_node;
2207 struct v4l2_fwnode_endpoint ep = { .bus_type = 0 };
2208 int err = of_property_read_u32(np, "clock-frequency",
2209 &mclk_rate);
2210 if (!err) {
2211 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
2212 pcdev->mclk = mclk_rate;
2213 }
2214
2215 np = of_graph_get_next_endpoint(np, NULL);
2216 if (!np) {
2217 dev_err(dev, "could not find endpoint\n");
2218 return -EINVAL;
2219 }
2220
2221 err = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep);
2222 if (err) {
2223 dev_err(dev, "could not parse endpoint\n");
2224 goto out;
2225 }
2226
2227 switch (ep.bus.parallel.bus_width) {
2228 case 4:
2229 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
2230 break;
2231 case 5:
2232 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
2233 break;
2234 case 8:
2235 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
2236 break;
2237 case 9:
2238 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
2239 break;
2240 case 10:
2241 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2242 break;
2243 default:
2244 break;
2245 }
2246
2247 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
2248 pcdev->platform_flags |= PXA_CAMERA_MASTER;
2249 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2250 pcdev->platform_flags |= PXA_CAMERA_HSP;
2251 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2252 pcdev->platform_flags |= PXA_CAMERA_VSP;
2253 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2254 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
2255 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
2256 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
2257
2258 asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
2259 remote = of_graph_get_remote_port_parent(np);
2260 if (remote)
2261 asd->match.fwnode = of_fwnode_handle(remote);
2262 else
2263 dev_notice(dev, "no remote for %pOF\n", np);
2264
2265 out:
2266 of_node_put(np);
2267
2268 return err;
2269 }
2270
2271 static int pxa_camera_probe(struct platform_device *pdev)
2272 {
2273 struct pxa_camera_dev *pcdev;
2274 struct resource *res;
2275 void __iomem *base;
2276 struct dma_slave_config config = {
2277 .src_addr_width = 0,
2278 .src_maxburst = 8,
2279 .direction = DMA_DEV_TO_MEM,
2280 };
2281 char clk_name[V4L2_CLK_NAME_SIZE];
2282 int irq;
2283 int err = 0, i;
2284
2285 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2286 irq = platform_get_irq(pdev, 0);
2287 if (!res || irq < 0)
2288 return -ENODEV;
2289
2290 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
2291 if (!pcdev) {
2292 dev_err(&pdev->dev, "Could not allocate pcdev\n");
2293 return -ENOMEM;
2294 }
2295
2296 pcdev->clk = devm_clk_get(&pdev->dev, NULL);
2297 if (IS_ERR(pcdev->clk))
2298 return PTR_ERR(pcdev->clk);
2299
2300 pcdev->res = res;
2301
2302 pcdev->pdata = pdev->dev.platform_data;
2303 if (pcdev->pdata) {
2304 pcdev->platform_flags = pcdev->pdata->flags;
2305 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
2306 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2307 pcdev->asd.match.i2c.adapter_id =
2308 pcdev->pdata->sensor_i2c_adapter_id;
2309 pcdev->asd.match.i2c.address = pcdev->pdata->sensor_i2c_address;
2310 } else if (pdev->dev.of_node) {
2311 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev, &pcdev->asd);
2312 } else {
2313 return -ENODEV;
2314 }
2315 if (err < 0)
2316 return err;
2317
2318 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
2319 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
2320 /*
2321 * Platform hasn't set available data widths. This is bad.
2322 * Warn and use a default.
2323 */
2324 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available data widths, using default 10 bit\n");
2325 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2326 }
2327 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
2328 pcdev->width_flags = 1 << 7;
2329 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
2330 pcdev->width_flags |= 1 << 8;
2331 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
2332 pcdev->width_flags |= 1 << 9;
2333 if (!pcdev->mclk) {
2334 dev_warn(&pdev->dev,
2335 "mclk == 0! Please, fix your platform data. Using default 20MHz\n");
2336 pcdev->mclk = 20000000;
2337 }
2338
2339 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
2340
2341 INIT_LIST_HEAD(&pcdev->capture);
2342 spin_lock_init(&pcdev->lock);
2343 mutex_init(&pcdev->mlock);
2344
2345 /*
2346 * Request the regions.
2347 */
2348 base = devm_ioremap_resource(&pdev->dev, res);
2349 if (IS_ERR(base))
2350 return PTR_ERR(base);
2351
2352 pcdev->irq = irq;
2353 pcdev->base = base;
2354
2355 /* request dma */
2356 pcdev->dma_chans[0] = dma_request_chan(&pdev->dev, "CI_Y");
2357 if (IS_ERR(pcdev->dma_chans[0])) {
2358 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2359 return PTR_ERR(pcdev->dma_chans[0]);
2360 }
2361
2362 pcdev->dma_chans[1] = dma_request_chan(&pdev->dev, "CI_U");
2363 if (IS_ERR(pcdev->dma_chans[1])) {
2364 dev_err(&pdev->dev, "Can't request DMA for U\n");
2365 err = PTR_ERR(pcdev->dma_chans[1]);
2366 goto exit_free_dma_y;
2367 }
2368
2369 pcdev->dma_chans[2] = dma_request_chan(&pdev->dev, "CI_V");
2370 if (IS_ERR(pcdev->dma_chans[2])) {
2371 dev_err(&pdev->dev, "Can't request DMA for V\n");
2372 err = PTR_ERR(pcdev->dma_chans[2]);
2373 goto exit_free_dma_u;
2374 }
2375
2376 for (i = 0; i < 3; i++) {
2377 config.src_addr = pcdev->res->start + CIBR0 + i * 8;
2378 err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
2379 if (err < 0) {
2380 dev_err(&pdev->dev, "dma slave config failed: %d\n",
2381 err);
2382 goto exit_free_dma;
2383 }
2384 }
2385
2386 /* request irq */
2387 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
2388 PXA_CAM_DRV_NAME, pcdev);
2389 if (err) {
2390 dev_err(&pdev->dev, "Camera interrupt register failed\n");
2391 goto exit_free_dma;
2392 }
2393
2394 tasklet_setup(&pcdev->task_eof, pxa_camera_eof);
2395
2396 pxa_camera_activate(pcdev);
2397
2398 dev_set_drvdata(&pdev->dev, pcdev);
2399 err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
2400 if (err)
2401 goto exit_deactivate;
2402
2403 v4l2_async_notifier_init(&pcdev->notifier);
2404
2405 err = v4l2_async_notifier_add_subdev(&pcdev->notifier, &pcdev->asd);
2406 if (err) {
2407 fwnode_handle_put(pcdev->asd.match.fwnode);
2408 goto exit_free_v4l2dev;
2409 }
2410
2411 pcdev->notifier.ops = &pxa_camera_sensor_ops;
2412
2413 if (!of_have_populated_dt())
2414 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2415
2416 err = pxa_camera_init_videobuf2(pcdev);
2417 if (err)
2418 goto exit_notifier_cleanup;
2419
2420 v4l2_clk_name_i2c(clk_name, sizeof(clk_name),
2421 pcdev->asd.match.i2c.adapter_id,
2422 pcdev->asd.match.i2c.address);
2423
2424 pcdev->mclk_clk = v4l2_clk_register(&pxa_camera_mclk_ops, clk_name, NULL);
2425 if (IS_ERR(pcdev->mclk_clk)) {
2426 err = PTR_ERR(pcdev->mclk_clk);
2427 goto exit_notifier_cleanup;
2428 }
2429
2430 err = v4l2_async_notifier_register(&pcdev->v4l2_dev, &pcdev->notifier);
2431 if (err)
2432 goto exit_free_clk;
2433
2434 return 0;
2435 exit_free_clk:
2436 v4l2_clk_unregister(pcdev->mclk_clk);
2437 exit_notifier_cleanup:
2438 v4l2_async_notifier_cleanup(&pcdev->notifier);
2439 exit_free_v4l2dev:
2440 v4l2_device_unregister(&pcdev->v4l2_dev);
2441 exit_deactivate:
2442 pxa_camera_deactivate(pcdev);
2443 tasklet_kill(&pcdev->task_eof);
2444 exit_free_dma:
2445 dma_release_channel(pcdev->dma_chans[2]);
2446 exit_free_dma_u:
2447 dma_release_channel(pcdev->dma_chans[1]);
2448 exit_free_dma_y:
2449 dma_release_channel(pcdev->dma_chans[0]);
2450 return err;
2451 }
2452
2453 static int pxa_camera_remove(struct platform_device *pdev)
2454 {
2455 struct pxa_camera_dev *pcdev = dev_get_drvdata(&pdev->dev);
2456
2457 pxa_camera_deactivate(pcdev);
2458 tasklet_kill(&pcdev->task_eof);
2459 dma_release_channel(pcdev->dma_chans[0]);
2460 dma_release_channel(pcdev->dma_chans[1]);
2461 dma_release_channel(pcdev->dma_chans[2]);
2462
2463 v4l2_async_notifier_unregister(&pcdev->notifier);
2464 v4l2_async_notifier_cleanup(&pcdev->notifier);
2465
2466 if (pcdev->mclk_clk) {
2467 v4l2_clk_unregister(pcdev->mclk_clk);
2468 pcdev->mclk_clk = NULL;
2469 }
2470
2471 v4l2_device_unregister(&pcdev->v4l2_dev);
2472
2473 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
2474
2475 return 0;
2476 }
2477
2478 static const struct dev_pm_ops pxa_camera_pm = {
2479 .suspend = pxa_camera_suspend,
2480 .resume = pxa_camera_resume,
2481 };
2482
2483 static const struct of_device_id pxa_camera_of_match[] = {
2484 { .compatible = "marvell,pxa270-qci", },
2485 {},
2486 };
2487 MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
2488
2489 static struct platform_driver pxa_camera_driver = {
2490 .driver = {
2491 .name = PXA_CAM_DRV_NAME,
2492 .pm = &pxa_camera_pm,
2493 .of_match_table = of_match_ptr(pxa_camera_of_match),
2494 },
2495 .probe = pxa_camera_probe,
2496 .remove = pxa_camera_remove,
2497 };
2498
2499 module_platform_driver(pxa_camera_driver);
2500
2501 MODULE_DESCRIPTION("PXA27x Camera Driver");
2502 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
2503 MODULE_LICENSE("GPL");
2504 MODULE_VERSION(PXA_CAM_VERSION);
2505 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
Linux with added FPC-III support