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Merge tag 'regmap-fix-v5.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / media / platform / rcar-vin / rcar-csi2.c
blob945d2eb8723367f04d7d4c31affc8f347352ba0c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Renesas R-Car MIPI CSI-2 Receiver
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/reset.h>
18 #include <linux/sys_soc.h>
19
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-mc.h>
24 #include <media/v4l2-subdev.h>
25
26 struct rcar_csi2;
27
28 /* Register offsets and bits */
29
30 /* Control Timing Select */
31 #define TREF_REG 0x00
32 #define TREF_TREF BIT(0)
33
34 /* Software Reset */
35 #define SRST_REG 0x04
36 #define SRST_SRST BIT(0)
37
38 /* PHY Operation Control */
39 #define PHYCNT_REG 0x08
40 #define PHYCNT_SHUTDOWNZ BIT(17)
41 #define PHYCNT_RSTZ BIT(16)
42 #define PHYCNT_ENABLECLK BIT(4)
43 #define PHYCNT_ENABLE_3 BIT(3)
44 #define PHYCNT_ENABLE_2 BIT(2)
45 #define PHYCNT_ENABLE_1 BIT(1)
46 #define PHYCNT_ENABLE_0 BIT(0)
47
48 /* Checksum Control */
49 #define CHKSUM_REG 0x0c
50 #define CHKSUM_ECC_EN BIT(1)
51 #define CHKSUM_CRC_EN BIT(0)
52
53 /*
54 * Channel Data Type Select
55 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1
56 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3
57 */
58 #define VCDT_REG 0x10
59 #define VCDT2_REG 0x14
60 #define VCDT_VCDTN_EN BIT(15)
61 #define VCDT_SEL_VC(n) (((n) & 0x3) << 8)
62 #define VCDT_SEL_DTN_ON BIT(6)
63 #define VCDT_SEL_DT(n) (((n) & 0x3f) << 0)
64
65 /* Frame Data Type Select */
66 #define FRDT_REG 0x18
67
68 /* Field Detection Control */
69 #define FLD_REG 0x1c
70 #define FLD_FLD_NUM(n) (((n) & 0xff) << 16)
71 #define FLD_DET_SEL(n) (((n) & 0x3) << 4)
72 #define FLD_FLD_EN4 BIT(3)
73 #define FLD_FLD_EN3 BIT(2)
74 #define FLD_FLD_EN2 BIT(1)
75 #define FLD_FLD_EN BIT(0)
76
77 /* Automatic Standby Control */
78 #define ASTBY_REG 0x20
79
80 /* Long Data Type Setting 0 */
81 #define LNGDT0_REG 0x28
82
83 /* Long Data Type Setting 1 */
84 #define LNGDT1_REG 0x2c
85
86 /* Interrupt Enable */
87 #define INTEN_REG 0x30
88 #define INTEN_INT_AFIFO_OF BIT(27)
89 #define INTEN_INT_ERRSOTHS BIT(4)
90 #define INTEN_INT_ERRSOTSYNCHS BIT(3)
91
92 /* Interrupt Source Mask */
93 #define INTCLOSE_REG 0x34
94
95 /* Interrupt Status Monitor */
96 #define INTSTATE_REG 0x38
97 #define INTSTATE_INT_ULPS_START BIT(7)
98 #define INTSTATE_INT_ULPS_END BIT(6)
99
100 /* Interrupt Error Status Monitor */
101 #define INTERRSTATE_REG 0x3c
102
103 /* Short Packet Data */
104 #define SHPDAT_REG 0x40
105
106 /* Short Packet Count */
107 #define SHPCNT_REG 0x44
108
109 /* LINK Operation Control */
110 #define LINKCNT_REG 0x48
111 #define LINKCNT_MONITOR_EN BIT(31)
112 #define LINKCNT_REG_MONI_PACT_EN BIT(25)
113 #define LINKCNT_ICLK_NONSTOP BIT(24)
114
115 /* Lane Swap */
116 #define LSWAP_REG 0x4c
117 #define LSWAP_L3SEL(n) (((n) & 0x3) << 6)
118 #define LSWAP_L2SEL(n) (((n) & 0x3) << 4)
119 #define LSWAP_L1SEL(n) (((n) & 0x3) << 2)
120 #define LSWAP_L0SEL(n) (((n) & 0x3) << 0)
121
122 /* PHY Test Interface Write Register */
123 #define PHTW_REG 0x50
124 #define PHTW_DWEN BIT(24)
125 #define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16)
126 #define PHTW_CWEN BIT(8)
127 #define PHTW_TESTDIN_CODE(n) ((n & 0xff))
128
129 struct phtw_value {
130 u16 data;
131 u16 code;
132 };
133
134 struct rcsi2_mbps_reg {
135 u16 mbps;
136 u16 reg;
137 };
138
139 static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = {
140 { .mbps = 80, .reg = 0x86 },
141 { .mbps = 90, .reg = 0x86 },
142 { .mbps = 100, .reg = 0x87 },
143 { .mbps = 110, .reg = 0x87 },
144 { .mbps = 120, .reg = 0x88 },
145 { .mbps = 130, .reg = 0x88 },
146 { .mbps = 140, .reg = 0x89 },
147 { .mbps = 150, .reg = 0x89 },
148 { .mbps = 160, .reg = 0x8a },
149 { .mbps = 170, .reg = 0x8a },
150 { .mbps = 180, .reg = 0x8b },
151 { .mbps = 190, .reg = 0x8b },
152 { .mbps = 205, .reg = 0x8c },
153 { .mbps = 220, .reg = 0x8d },
154 { .mbps = 235, .reg = 0x8e },
155 { .mbps = 250, .reg = 0x8e },
156 { /* sentinel */ },
157 };
158
159 static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = {
160 { .mbps = 80, .reg = 0x00 },
161 { .mbps = 90, .reg = 0x20 },
162 { .mbps = 100, .reg = 0x40 },
163 { .mbps = 110, .reg = 0x02 },
164 { .mbps = 130, .reg = 0x22 },
165 { .mbps = 140, .reg = 0x42 },
166 { .mbps = 150, .reg = 0x04 },
167 { .mbps = 170, .reg = 0x24 },
168 { .mbps = 180, .reg = 0x44 },
169 { .mbps = 200, .reg = 0x06 },
170 { .mbps = 220, .reg = 0x26 },
171 { .mbps = 240, .reg = 0x46 },
172 { .mbps = 250, .reg = 0x08 },
173 { .mbps = 270, .reg = 0x28 },
174 { .mbps = 300, .reg = 0x0a },
175 { .mbps = 330, .reg = 0x2a },
176 { .mbps = 360, .reg = 0x4a },
177 { .mbps = 400, .reg = 0x0c },
178 { .mbps = 450, .reg = 0x2c },
179 { .mbps = 500, .reg = 0x0e },
180 { .mbps = 550, .reg = 0x2e },
181 { .mbps = 600, .reg = 0x10 },
182 { .mbps = 650, .reg = 0x30 },
183 { .mbps = 700, .reg = 0x12 },
184 { .mbps = 750, .reg = 0x32 },
185 { .mbps = 800, .reg = 0x52 },
186 { .mbps = 850, .reg = 0x72 },
187 { .mbps = 900, .reg = 0x14 },
188 { .mbps = 950, .reg = 0x34 },
189 { .mbps = 1000, .reg = 0x54 },
190 { .mbps = 1050, .reg = 0x74 },
191 { .mbps = 1125, .reg = 0x16 },
192 { /* sentinel */ },
193 };
194
195 /* PHY Test Interface Clear */
196 #define PHTC_REG 0x58
197 #define PHTC_TESTCLR BIT(0)
198
199 /* PHY Frequency Control */
200 #define PHYPLL_REG 0x68
201 #define PHYPLL_HSFREQRANGE(n) ((n) << 16)
202
203 static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = {
204 { .mbps = 80, .reg = 0x00 },
205 { .mbps = 90, .reg = 0x10 },
206 { .mbps = 100, .reg = 0x20 },
207 { .mbps = 110, .reg = 0x30 },
208 { .mbps = 120, .reg = 0x01 },
209 { .mbps = 130, .reg = 0x11 },
210 { .mbps = 140, .reg = 0x21 },
211 { .mbps = 150, .reg = 0x31 },
212 { .mbps = 160, .reg = 0x02 },
213 { .mbps = 170, .reg = 0x12 },
214 { .mbps = 180, .reg = 0x22 },
215 { .mbps = 190, .reg = 0x32 },
216 { .mbps = 205, .reg = 0x03 },
217 { .mbps = 220, .reg = 0x13 },
218 { .mbps = 235, .reg = 0x23 },
219 { .mbps = 250, .reg = 0x33 },
220 { .mbps = 275, .reg = 0x04 },
221 { .mbps = 300, .reg = 0x14 },
222 { .mbps = 325, .reg = 0x25 },
223 { .mbps = 350, .reg = 0x35 },
224 { .mbps = 400, .reg = 0x05 },
225 { .mbps = 450, .reg = 0x16 },
226 { .mbps = 500, .reg = 0x26 },
227 { .mbps = 550, .reg = 0x37 },
228 { .mbps = 600, .reg = 0x07 },
229 { .mbps = 650, .reg = 0x18 },
230 { .mbps = 700, .reg = 0x28 },
231 { .mbps = 750, .reg = 0x39 },
232 { .mbps = 800, .reg = 0x09 },
233 { .mbps = 850, .reg = 0x19 },
234 { .mbps = 900, .reg = 0x29 },
235 { .mbps = 950, .reg = 0x3a },
236 { .mbps = 1000, .reg = 0x0a },
237 { .mbps = 1050, .reg = 0x1a },
238 { .mbps = 1100, .reg = 0x2a },
239 { .mbps = 1150, .reg = 0x3b },
240 { .mbps = 1200, .reg = 0x0b },
241 { .mbps = 1250, .reg = 0x1b },
242 { .mbps = 1300, .reg = 0x2b },
243 { .mbps = 1350, .reg = 0x3c },
244 { .mbps = 1400, .reg = 0x0c },
245 { .mbps = 1450, .reg = 0x1c },
246 { .mbps = 1500, .reg = 0x2c },
247 { /* sentinel */ },
248 };
249
250 static const struct rcsi2_mbps_reg hsfreqrange_m3w_h3es1[] = {
251 { .mbps = 80, .reg = 0x00 },
252 { .mbps = 90, .reg = 0x10 },
253 { .mbps = 100, .reg = 0x20 },
254 { .mbps = 110, .reg = 0x30 },
255 { .mbps = 120, .reg = 0x01 },
256 { .mbps = 130, .reg = 0x11 },
257 { .mbps = 140, .reg = 0x21 },
258 { .mbps = 150, .reg = 0x31 },
259 { .mbps = 160, .reg = 0x02 },
260 { .mbps = 170, .reg = 0x12 },
261 { .mbps = 180, .reg = 0x22 },
262 { .mbps = 190, .reg = 0x32 },
263 { .mbps = 205, .reg = 0x03 },
264 { .mbps = 220, .reg = 0x13 },
265 { .mbps = 235, .reg = 0x23 },
266 { .mbps = 250, .reg = 0x33 },
267 { .mbps = 275, .reg = 0x04 },
268 { .mbps = 300, .reg = 0x14 },
269 { .mbps = 325, .reg = 0x05 },
270 { .mbps = 350, .reg = 0x15 },
271 { .mbps = 400, .reg = 0x25 },
272 { .mbps = 450, .reg = 0x06 },
273 { .mbps = 500, .reg = 0x16 },
274 { .mbps = 550, .reg = 0x07 },
275 { .mbps = 600, .reg = 0x17 },
276 { .mbps = 650, .reg = 0x08 },
277 { .mbps = 700, .reg = 0x18 },
278 { .mbps = 750, .reg = 0x09 },
279 { .mbps = 800, .reg = 0x19 },
280 { .mbps = 850, .reg = 0x29 },
281 { .mbps = 900, .reg = 0x39 },
282 { .mbps = 950, .reg = 0x0a },
283 { .mbps = 1000, .reg = 0x1a },
284 { .mbps = 1050, .reg = 0x2a },
285 { .mbps = 1100, .reg = 0x3a },
286 { .mbps = 1150, .reg = 0x0b },
287 { .mbps = 1200, .reg = 0x1b },
288 { .mbps = 1250, .reg = 0x2b },
289 { .mbps = 1300, .reg = 0x3b },
290 { .mbps = 1350, .reg = 0x0c },
291 { .mbps = 1400, .reg = 0x1c },
292 { .mbps = 1450, .reg = 0x2c },
293 { .mbps = 1500, .reg = 0x3c },
294 { /* sentinel */ },
295 };
296
297 /* PHY ESC Error Monitor */
298 #define PHEERM_REG 0x74
299
300 /* PHY Clock Lane Monitor */
301 #define PHCLM_REG 0x78
302 #define PHCLM_STOPSTATECKL BIT(0)
303
304 /* PHY Data Lane Monitor */
305 #define PHDLM_REG 0x7c
306
307 /* CSI0CLK Frequency Configuration Preset Register */
308 #define CSI0CLKFCPR_REG 0x260
309 #define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16)
310
311 struct rcar_csi2_format {
312 u32 code;
313 unsigned int datatype;
314 unsigned int bpp;
315 };
316
317 static const struct rcar_csi2_format rcar_csi2_formats[] = {
318 { .code = MEDIA_BUS_FMT_RGB888_1X24, .datatype = 0x24, .bpp = 24 },
319 { .code = MEDIA_BUS_FMT_UYVY8_1X16, .datatype = 0x1e, .bpp = 16 },
320 { .code = MEDIA_BUS_FMT_YUYV8_1X16, .datatype = 0x1e, .bpp = 16 },
321 { .code = MEDIA_BUS_FMT_UYVY8_2X8, .datatype = 0x1e, .bpp = 16 },
322 { .code = MEDIA_BUS_FMT_YUYV10_2X10, .datatype = 0x1e, .bpp = 20 },
323 { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .datatype = 0x2a, .bpp = 8 },
324 { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .datatype = 0x2a, .bpp = 8 },
325 { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .datatype = 0x2a, .bpp = 8 },
326 { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .datatype = 0x2a, .bpp = 8 },
327 };
328
329 static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code)
330 {
331 unsigned int i;
332
333 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++)
334 if (rcar_csi2_formats[i].code == code)
335 return &rcar_csi2_formats[i];
336
337 return NULL;
338 }
339
340 enum rcar_csi2_pads {
341 RCAR_CSI2_SINK,
342 RCAR_CSI2_SOURCE_VC0,
343 RCAR_CSI2_SOURCE_VC1,
344 RCAR_CSI2_SOURCE_VC2,
345 RCAR_CSI2_SOURCE_VC3,
346 NR_OF_RCAR_CSI2_PAD,
347 };
348
349 struct rcar_csi2_info {
350 int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps);
351 int (*phy_post_init)(struct rcar_csi2 *priv);
352 const struct rcsi2_mbps_reg *hsfreqrange;
353 unsigned int csi0clkfreqrange;
354 unsigned int num_channels;
355 bool clear_ulps;
356 };
357
358 struct rcar_csi2 {
359 struct device *dev;
360 void __iomem *base;
361 const struct rcar_csi2_info *info;
362 struct reset_control *rstc;
363
364 struct v4l2_subdev subdev;
365 struct media_pad pads[NR_OF_RCAR_CSI2_PAD];
366
367 struct v4l2_async_notifier notifier;
368 struct v4l2_subdev *remote;
369 unsigned int remote_pad;
370
371 struct v4l2_mbus_framefmt mf;
372
373 struct mutex lock;
374 int stream_count;
375
376 unsigned short lanes;
377 unsigned char lane_swap[4];
378 };
379
380 static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
381 {
382 return container_of(sd, struct rcar_csi2, subdev);
383 }
384
385 static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)
386 {
387 return container_of(n, struct rcar_csi2, notifier);
388 }
389
390 static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg)
391 {
392 return ioread32(priv->base + reg);
393 }
394
395 static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data)
396 {
397 iowrite32(data, priv->base + reg);
398 }
399
400 static void rcsi2_enter_standby(struct rcar_csi2 *priv)
401 {
402 rcsi2_write(priv, PHYCNT_REG, 0);
403 rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR);
404 reset_control_assert(priv->rstc);
405 usleep_range(100, 150);
406 pm_runtime_put(priv->dev);
407 }
408
409 static void rcsi2_exit_standby(struct rcar_csi2 *priv)
410 {
411 pm_runtime_get_sync(priv->dev);
412 reset_control_deassert(priv->rstc);
413 }
414
415 static int rcsi2_wait_phy_start(struct rcar_csi2 *priv,
416 unsigned int lanes)
417 {
418 unsigned int timeout;
419
420 /* Wait for the clock and data lanes to enter LP-11 state. */
421 for (timeout = 0; timeout <= 20; timeout++) {
422 const u32 lane_mask = (1 << lanes) - 1;
423
424 if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) &&
425 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask)
426 return 0;
427
428 usleep_range(1000, 2000);
429 }
430
431 dev_err(priv->dev, "Timeout waiting for LP-11 state\n");
432
433 return -ETIMEDOUT;
434 }
435
436 static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps)
437 {
438 const struct rcsi2_mbps_reg *hsfreq;
439
440 for (hsfreq = priv->info->hsfreqrange; hsfreq->mbps != 0; hsfreq++)
441 if (hsfreq->mbps >= mbps)
442 break;
443
444 if (!hsfreq->mbps) {
445 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
446 return -ERANGE;
447 }
448
449 rcsi2_write(priv, PHYPLL_REG, PHYPLL_HSFREQRANGE(hsfreq->reg));
450
451 return 0;
452 }
453
454 static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp,
455 unsigned int lanes)
456 {
457 struct v4l2_subdev *source;
458 struct v4l2_ctrl *ctrl;
459 u64 mbps;
460
461 if (!priv->remote)
462 return -ENODEV;
463
464 source = priv->remote;
465
466 /* Read the pixel rate control from remote. */
467 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE);
468 if (!ctrl) {
469 dev_err(priv->dev, "no pixel rate control in subdev %s\n",
470 source->name);
471 return -EINVAL;
472 }
473
474 /*
475 * Calculate the phypll in mbps.
476 * link_freq = (pixel_rate * bits_per_sample) / (2 * nr_of_lanes)
477 * bps = link_freq * 2
478 */
479 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp;
480 do_div(mbps, lanes * 1000000);
481
482 return mbps;
483 }
484
485 static int rcsi2_get_active_lanes(struct rcar_csi2 *priv,
486 unsigned int *lanes)
487 {
488 struct v4l2_mbus_config mbus_config = { 0 };
489 unsigned int num_lanes = UINT_MAX;
490 int ret;
491
492 *lanes = priv->lanes;
493
494 ret = v4l2_subdev_call(priv->remote, pad, get_mbus_config,
495 priv->remote_pad, &mbus_config);
496 if (ret == -ENOIOCTLCMD) {
497 dev_dbg(priv->dev, "No remote mbus configuration available\n");
498 return 0;
499 }
500
501 if (ret) {
502 dev_err(priv->dev, "Failed to get remote mbus configuration\n");
503 return ret;
504 }
505
506 if (mbus_config.type != V4L2_MBUS_CSI2_DPHY) {
507 dev_err(priv->dev, "Unsupported media bus type %u\n",
508 mbus_config.type);
509 return -EINVAL;
510 }
511
512 if (mbus_config.flags & V4L2_MBUS_CSI2_1_LANE)
513 num_lanes = 1;
514 else if (mbus_config.flags & V4L2_MBUS_CSI2_2_LANE)
515 num_lanes = 2;
516 else if (mbus_config.flags & V4L2_MBUS_CSI2_3_LANE)
517 num_lanes = 3;
518 else if (mbus_config.flags & V4L2_MBUS_CSI2_4_LANE)
519 num_lanes = 4;
520
521 if (num_lanes > priv->lanes) {
522 dev_err(priv->dev,
523 "Unsupported mbus config: too many data lanes %u\n",
524 num_lanes);
525 return -EINVAL;
526 }
527
528 *lanes = num_lanes;
529
530 return 0;
531 }
532
533 static int rcsi2_start_receiver(struct rcar_csi2 *priv)
534 {
535 const struct rcar_csi2_format *format;
536 u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0;
537 unsigned int lanes;
538 unsigned int i;
539 int mbps, ret;
540
541 dev_dbg(priv->dev, "Input size (%ux%u%c)\n",
542 priv->mf.width, priv->mf.height,
543 priv->mf.field == V4L2_FIELD_NONE ? 'p' : 'i');
544
545 /* Code is validated in set_fmt. */
546 format = rcsi2_code_to_fmt(priv->mf.code);
547
548 /*
549 * Enable all supported CSI-2 channels with virtual channel and
550 * data type matching.
551 *
552 * NOTE: It's not possible to get individual datatype for each
553 * source virtual channel. Once this is possible in V4L2
554 * it should be used here.
555 */
556 for (i = 0; i < priv->info->num_channels; i++) {
557 u32 vcdt_part;
558
559 vcdt_part = VCDT_SEL_VC(i) | VCDT_VCDTN_EN | VCDT_SEL_DTN_ON |
560 VCDT_SEL_DT(format->datatype);
561
562 /* Store in correct reg and offset. */
563 if (i < 2)
564 vcdt |= vcdt_part << ((i % 2) * 16);
565 else
566 vcdt2 |= vcdt_part << ((i % 2) * 16);
567 }
568
569 if (priv->mf.field == V4L2_FIELD_ALTERNATE) {
570 fld = FLD_DET_SEL(1) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2
571 | FLD_FLD_EN;
572
573 if (priv->mf.height == 240)
574 fld |= FLD_FLD_NUM(0);
575 else
576 fld |= FLD_FLD_NUM(1);
577 }
578
579 /*
580 * Get the number of active data lanes inspecting the remote mbus
581 * configuration.
582 */
583 ret = rcsi2_get_active_lanes(priv, &lanes);
584 if (ret)
585 return ret;
586
587 phycnt = PHYCNT_ENABLECLK;
588 phycnt |= (1 << lanes) - 1;
589
590 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes);
591 if (mbps < 0)
592 return mbps;
593
594 /* Enable interrupts. */
595 rcsi2_write(priv, INTEN_REG, INTEN_INT_AFIFO_OF | INTEN_INT_ERRSOTHS
596 | INTEN_INT_ERRSOTSYNCHS);
597
598 /* Init */
599 rcsi2_write(priv, TREF_REG, TREF_TREF);
600 rcsi2_write(priv, PHTC_REG, 0);
601
602 /* Configure */
603 rcsi2_write(priv, VCDT_REG, vcdt);
604 if (vcdt2)
605 rcsi2_write(priv, VCDT2_REG, vcdt2);
606 /* Lanes are zero indexed. */
607 rcsi2_write(priv, LSWAP_REG,
608 LSWAP_L0SEL(priv->lane_swap[0] - 1) |
609 LSWAP_L1SEL(priv->lane_swap[1] - 1) |
610 LSWAP_L2SEL(priv->lane_swap[2] - 1) |
611 LSWAP_L3SEL(priv->lane_swap[3] - 1));
612
613 /* Start */
614 if (priv->info->init_phtw) {
615 ret = priv->info->init_phtw(priv, mbps);
616 if (ret)
617 return ret;
618 }
619
620 if (priv->info->hsfreqrange) {
621 ret = rcsi2_set_phypll(priv, mbps);
622 if (ret)
623 return ret;
624 }
625
626 if (priv->info->csi0clkfreqrange)
627 rcsi2_write(priv, CSI0CLKFCPR_REG,
628 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange));
629
630 rcsi2_write(priv, PHYCNT_REG, phycnt);
631 rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN |
632 LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP);
633 rcsi2_write(priv, FLD_REG, fld);
634 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ);
635 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ);
636
637 ret = rcsi2_wait_phy_start(priv, lanes);
638 if (ret)
639 return ret;
640
641 /* Run post PHY start initialization, if needed. */
642 if (priv->info->phy_post_init) {
643 ret = priv->info->phy_post_init(priv);
644 if (ret)
645 return ret;
646 }
647
648 /* Clear Ultra Low Power interrupt. */
649 if (priv->info->clear_ulps)
650 rcsi2_write(priv, INTSTATE_REG,
651 INTSTATE_INT_ULPS_START |
652 INTSTATE_INT_ULPS_END);
653 return 0;
654 }
655
656 static int rcsi2_start(struct rcar_csi2 *priv)
657 {
658 int ret;
659
660 rcsi2_exit_standby(priv);
661
662 ret = rcsi2_start_receiver(priv);
663 if (ret) {
664 rcsi2_enter_standby(priv);
665 return ret;
666 }
667
668 ret = v4l2_subdev_call(priv->remote, video, s_stream, 1);
669 if (ret) {
670 rcsi2_enter_standby(priv);
671 return ret;
672 }
673
674 return 0;
675 }
676
677 static void rcsi2_stop(struct rcar_csi2 *priv)
678 {
679 rcsi2_enter_standby(priv);
680 v4l2_subdev_call(priv->remote, video, s_stream, 0);
681 }
682
683 static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable)
684 {
685 struct rcar_csi2 *priv = sd_to_csi2(sd);
686 int ret = 0;
687
688 mutex_lock(&priv->lock);
689
690 if (!priv->remote) {
691 ret = -ENODEV;
692 goto out;
693 }
694
695 if (enable && priv->stream_count == 0) {
696 ret = rcsi2_start(priv);
697 if (ret)
698 goto out;
699 } else if (!enable && priv->stream_count == 1) {
700 rcsi2_stop(priv);
701 }
702
703 priv->stream_count += enable ? 1 : -1;
704 out:
705 mutex_unlock(&priv->lock);
706
707 return ret;
708 }
709
710 static int rcsi2_set_pad_format(struct v4l2_subdev *sd,
711 struct v4l2_subdev_pad_config *cfg,
712 struct v4l2_subdev_format *format)
713 {
714 struct rcar_csi2 *priv = sd_to_csi2(sd);
715 struct v4l2_mbus_framefmt *framefmt;
716
717 if (!rcsi2_code_to_fmt(format->format.code))
718 format->format.code = rcar_csi2_formats[0].code;
719
720 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
721 priv->mf = format->format;
722 } else {
723 framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
724 *framefmt = format->format;
725 }
726
727 return 0;
728 }
729
730 static int rcsi2_get_pad_format(struct v4l2_subdev *sd,
731 struct v4l2_subdev_pad_config *cfg,
732 struct v4l2_subdev_format *format)
733 {
734 struct rcar_csi2 *priv = sd_to_csi2(sd);
735
736 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
737 format->format = priv->mf;
738 else
739 format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
740
741 return 0;
742 }
743
744 static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = {
745 .s_stream = rcsi2_s_stream,
746 };
747
748 static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = {
749 .set_fmt = rcsi2_set_pad_format,
750 .get_fmt = rcsi2_get_pad_format,
751 };
752
753 static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = {
754 .video = &rcar_csi2_video_ops,
755 .pad = &rcar_csi2_pad_ops,
756 };
757
758 static irqreturn_t rcsi2_irq(int irq, void *data)
759 {
760 struct rcar_csi2 *priv = data;
761 u32 status, err_status;
762
763 status = rcsi2_read(priv, INTSTATE_REG);
764 err_status = rcsi2_read(priv, INTERRSTATE_REG);
765
766 if (!status)
767 return IRQ_HANDLED;
768
769 rcsi2_write(priv, INTSTATE_REG, status);
770
771 if (!err_status)
772 return IRQ_HANDLED;
773
774 rcsi2_write(priv, INTERRSTATE_REG, err_status);
775
776 dev_info(priv->dev, "Transfer error, restarting CSI-2 receiver\n");
777
778 return IRQ_WAKE_THREAD;
779 }
780
781 static irqreturn_t rcsi2_irq_thread(int irq, void *data)
782 {
783 struct rcar_csi2 *priv = data;
784
785 mutex_lock(&priv->lock);
786 rcsi2_stop(priv);
787 usleep_range(1000, 2000);
788 if (rcsi2_start(priv))
789 dev_warn(priv->dev, "Failed to restart CSI-2 receiver\n");
790 mutex_unlock(&priv->lock);
791
792 return IRQ_HANDLED;
793 }
794
795 /* -----------------------------------------------------------------------------
796 * Async handling and registration of subdevices and links.
797 */
798
799 static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier,
800 struct v4l2_subdev *subdev,
801 struct v4l2_async_subdev *asd)
802 {
803 struct rcar_csi2 *priv = notifier_to_csi2(notifier);
804 int pad;
805
806 pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode,
807 MEDIA_PAD_FL_SOURCE);
808 if (pad < 0) {
809 dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name);
810 return pad;
811 }
812
813 priv->remote = subdev;
814 priv->remote_pad = pad;
815
816 dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad);
817
818 return media_create_pad_link(&subdev->entity, pad,
819 &priv->subdev.entity, 0,
820 MEDIA_LNK_FL_ENABLED |
821 MEDIA_LNK_FL_IMMUTABLE);
822 }
823
824 static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier,
825 struct v4l2_subdev *subdev,
826 struct v4l2_async_subdev *asd)
827 {
828 struct rcar_csi2 *priv = notifier_to_csi2(notifier);
829
830 priv->remote = NULL;
831
832 dev_dbg(priv->dev, "Unbind %s\n", subdev->name);
833 }
834
835 static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = {
836 .bound = rcsi2_notify_bound,
837 .unbind = rcsi2_notify_unbind,
838 };
839
840 static int rcsi2_parse_v4l2(struct rcar_csi2 *priv,
841 struct v4l2_fwnode_endpoint *vep)
842 {
843 unsigned int i;
844
845 /* Only port 0 endpoint 0 is valid. */
846 if (vep->base.port || vep->base.id)
847 return -ENOTCONN;
848
849 if (vep->bus_type != V4L2_MBUS_CSI2_DPHY) {
850 dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type);
851 return -EINVAL;
852 }
853
854 priv->lanes = vep->bus.mipi_csi2.num_data_lanes;
855 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) {
856 dev_err(priv->dev, "Unsupported number of data-lanes: %u\n",
857 priv->lanes);
858 return -EINVAL;
859 }
860
861 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) {
862 priv->lane_swap[i] = i < priv->lanes ?
863 vep->bus.mipi_csi2.data_lanes[i] : i;
864
865 /* Check for valid lane number. */
866 if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) {
867 dev_err(priv->dev, "data-lanes must be in 1-4 range\n");
868 return -EINVAL;
869 }
870 }
871
872 return 0;
873 }
874
875 static int rcsi2_parse_dt(struct rcar_csi2 *priv)
876 {
877 struct v4l2_async_subdev *asd;
878 struct fwnode_handle *fwnode;
879 struct fwnode_handle *ep;
880 struct v4l2_fwnode_endpoint v4l2_ep = {
881 .bus_type = V4L2_MBUS_CSI2_DPHY
882 };
883 int ret;
884
885 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0);
886 if (!ep) {
887 dev_err(priv->dev, "Not connected to subdevice\n");
888 return -EINVAL;
889 }
890
891 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep);
892 if (ret) {
893 dev_err(priv->dev, "Could not parse v4l2 endpoint\n");
894 fwnode_handle_put(ep);
895 return -EINVAL;
896 }
897
898 ret = rcsi2_parse_v4l2(priv, &v4l2_ep);
899 if (ret) {
900 fwnode_handle_put(ep);
901 return ret;
902 }
903
904 fwnode = fwnode_graph_get_remote_endpoint(ep);
905 fwnode_handle_put(ep);
906
907 dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode));
908
909 v4l2_async_notifier_init(&priv->notifier);
910 priv->notifier.ops = &rcar_csi2_notify_ops;
911
912 asd = v4l2_async_notifier_add_fwnode_subdev(&priv->notifier, fwnode,
913 sizeof(*asd));
914 fwnode_handle_put(fwnode);
915 if (IS_ERR(asd))
916 return PTR_ERR(asd);
917
918 ret = v4l2_async_subdev_notifier_register(&priv->subdev,
919 &priv->notifier);
920 if (ret)
921 v4l2_async_notifier_cleanup(&priv->notifier);
922
923 return ret;
924 }
925
926 /* -----------------------------------------------------------------------------
927 * PHTW initialization sequences.
928 *
929 * NOTE: Magic values are from the datasheet and lack documentation.
930 */
931
932 static int rcsi2_phtw_write(struct rcar_csi2 *priv, u16 data, u16 code)
933 {
934 unsigned int timeout;
935
936 rcsi2_write(priv, PHTW_REG,
937 PHTW_DWEN | PHTW_TESTDIN_DATA(data) |
938 PHTW_CWEN | PHTW_TESTDIN_CODE(code));
939
940 /* Wait for DWEN and CWEN to be cleared by hardware. */
941 for (timeout = 0; timeout <= 20; timeout++) {
942 if (!(rcsi2_read(priv, PHTW_REG) & (PHTW_DWEN | PHTW_CWEN)))
943 return 0;
944
945 usleep_range(1000, 2000);
946 }
947
948 dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n");
949
950 return -ETIMEDOUT;
951 }
952
953 static int rcsi2_phtw_write_array(struct rcar_csi2 *priv,
954 const struct phtw_value *values)
955 {
956 const struct phtw_value *value;
957 int ret;
958
959 for (value = values; value->data || value->code; value++) {
960 ret = rcsi2_phtw_write(priv, value->data, value->code);
961 if (ret)
962 return ret;
963 }
964
965 return 0;
966 }
967
968 static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps,
969 const struct rcsi2_mbps_reg *values, u16 code)
970 {
971 const struct rcsi2_mbps_reg *value;
972
973 for (value = values; value->mbps; value++)
974 if (value->mbps >= mbps)
975 break;
976
977 if (!value->mbps) {
978 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
979 return -ERANGE;
980 }
981
982 return rcsi2_phtw_write(priv, value->reg, code);
983 }
984
985 static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv,
986 unsigned int mbps)
987 {
988 static const struct phtw_value step1[] = {
989 { .data = 0xcc, .code = 0xe2 },
990 { .data = 0x01, .code = 0xe3 },
991 { .data = 0x11, .code = 0xe4 },
992 { .data = 0x01, .code = 0xe5 },
993 { .data = 0x10, .code = 0x04 },
994 { /* sentinel */ },
995 };
996
997 static const struct phtw_value step2[] = {
998 { .data = 0x38, .code = 0x08 },
999 { .data = 0x01, .code = 0x00 },
1000 { .data = 0x4b, .code = 0xac },
1001 { .data = 0x03, .code = 0x00 },
1002 { .data = 0x80, .code = 0x07 },
1003 { /* sentinel */ },
1004 };
1005
1006 int ret;
1007
1008 ret = rcsi2_phtw_write_array(priv, step1);
1009 if (ret)
1010 return ret;
1011
1012 if (mbps != 0 && mbps <= 250) {
1013 ret = rcsi2_phtw_write(priv, 0x39, 0x05);
1014 if (ret)
1015 return ret;
1016
1017 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n,
1018 0xf1);
1019 if (ret)
1020 return ret;
1021 }
1022
1023 return rcsi2_phtw_write_array(priv, step2);
1024 }
1025
1026 static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps)
1027 {
1028 return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps);
1029 }
1030
1031 static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps)
1032 {
1033 return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0);
1034 }
1035
1036 static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps)
1037 {
1038 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44);
1039 }
1040
1041 static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv)
1042 {
1043 static const struct phtw_value step1[] = {
1044 { .data = 0xee, .code = 0x34 },
1045 { .data = 0xee, .code = 0x44 },
1046 { .data = 0xee, .code = 0x54 },
1047 { .data = 0xee, .code = 0x84 },
1048 { .data = 0xee, .code = 0x94 },
1049 { /* sentinel */ },
1050 };
1051
1052 return rcsi2_phtw_write_array(priv, step1);
1053 }
1054
1055 /* -----------------------------------------------------------------------------
1056 * Platform Device Driver.
1057 */
1058
1059 static const struct media_entity_operations rcar_csi2_entity_ops = {
1060 .link_validate = v4l2_subdev_link_validate,
1061 };
1062
1063 static int rcsi2_probe_resources(struct rcar_csi2 *priv,
1064 struct platform_device *pdev)
1065 {
1066 struct resource *res;
1067 int irq, ret;
1068
1069 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1070 priv->base = devm_ioremap_resource(&pdev->dev, res);
1071 if (IS_ERR(priv->base))
1072 return PTR_ERR(priv->base);
1073
1074 irq = platform_get_irq(pdev, 0);
1075 if (irq < 0)
1076 return irq;
1077
1078 ret = devm_request_threaded_irq(&pdev->dev, irq, rcsi2_irq,
1079 rcsi2_irq_thread, IRQF_SHARED,
1080 KBUILD_MODNAME, priv);
1081 if (ret)
1082 return ret;
1083
1084 priv->rstc = devm_reset_control_get(&pdev->dev, NULL);
1085
1086 return PTR_ERR_OR_ZERO(priv->rstc);
1087 }
1088
1089 static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = {
1090 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1091 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1092 .csi0clkfreqrange = 0x20,
1093 .num_channels = 4,
1094 .clear_ulps = true,
1095 };
1096
1097 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es1 = {
1098 .hsfreqrange = hsfreqrange_m3w_h3es1,
1099 .num_channels = 4,
1100 };
1101
1102 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = {
1103 .init_phtw = rcsi2_init_phtw_h3es2,
1104 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1105 .csi0clkfreqrange = 0x20,
1106 .num_channels = 4,
1107 .clear_ulps = true,
1108 };
1109
1110 static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = {
1111 .hsfreqrange = hsfreqrange_m3w_h3es1,
1112 .num_channels = 4,
1113 };
1114
1115 static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = {
1116 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1117 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1118 .csi0clkfreqrange = 0x20,
1119 .num_channels = 4,
1120 .clear_ulps = true,
1121 };
1122
1123 static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = {
1124 .init_phtw = rcsi2_init_phtw_v3m_e3,
1125 .phy_post_init = rcsi2_phy_post_init_v3m_e3,
1126 .num_channels = 4,
1127 };
1128
1129 static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = {
1130 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1131 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1132 .csi0clkfreqrange = 0x20,
1133 .clear_ulps = true,
1134 };
1135
1136 static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = {
1137 .init_phtw = rcsi2_init_phtw_v3m_e3,
1138 .phy_post_init = rcsi2_phy_post_init_v3m_e3,
1139 .num_channels = 2,
1140 };
1141
1142 static const struct of_device_id rcar_csi2_of_table[] = {
1143 {
1144 .compatible = "renesas,r8a774a1-csi2",
1145 .data = &rcar_csi2_info_r8a7796,
1146 },
1147 {
1148 .compatible = "renesas,r8a774b1-csi2",
1149 .data = &rcar_csi2_info_r8a77965,
1150 },
1151 {
1152 .compatible = "renesas,r8a774c0-csi2",
1153 .data = &rcar_csi2_info_r8a77990,
1154 },
1155 {
1156 .compatible = "renesas,r8a774e1-csi2",
1157 .data = &rcar_csi2_info_r8a7795,
1158 },
1159 {
1160 .compatible = "renesas,r8a7795-csi2",
1161 .data = &rcar_csi2_info_r8a7795,
1162 },
1163 {
1164 .compatible = "renesas,r8a7796-csi2",
1165 .data = &rcar_csi2_info_r8a7796,
1166 },
1167 {
1168 .compatible = "renesas,r8a77965-csi2",
1169 .data = &rcar_csi2_info_r8a77965,
1170 },
1171 {
1172 .compatible = "renesas,r8a77970-csi2",
1173 .data = &rcar_csi2_info_r8a77970,
1174 },
1175 {
1176 .compatible = "renesas,r8a77980-csi2",
1177 .data = &rcar_csi2_info_r8a77980,
1178 },
1179 {
1180 .compatible = "renesas,r8a77990-csi2",
1181 .data = &rcar_csi2_info_r8a77990,
1182 },
1183 { /* sentinel */ },
1184 };
1185 MODULE_DEVICE_TABLE(of, rcar_csi2_of_table);
1186
1187 static const struct soc_device_attribute r8a7795[] = {
1188 {
1189 .soc_id = "r8a7795", .revision = "ES1.*",
1190 .data = &rcar_csi2_info_r8a7795es1,
1191 },
1192 {
1193 .soc_id = "r8a7795", .revision = "ES2.*",
1194 .data = &rcar_csi2_info_r8a7795es2,
1195 },
1196 { /* sentinel */ },
1197 };
1198
1199 static int rcsi2_probe(struct platform_device *pdev)
1200 {
1201 const struct soc_device_attribute *attr;
1202 struct rcar_csi2 *priv;
1203 unsigned int i;
1204 int ret;
1205
1206 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1207 if (!priv)
1208 return -ENOMEM;
1209
1210 priv->info = of_device_get_match_data(&pdev->dev);
1211
1212 /*
1213 * The different ES versions of r8a7795 (H3) behave differently but
1214 * share the same compatible string.
1215 */
1216 attr = soc_device_match(r8a7795);
1217 if (attr)
1218 priv->info = attr->data;
1219
1220 priv->dev = &pdev->dev;
1221
1222 mutex_init(&priv->lock);
1223 priv->stream_count = 0;
1224
1225 ret = rcsi2_probe_resources(priv, pdev);
1226 if (ret) {
1227 dev_err(priv->dev, "Failed to get resources\n");
1228 return ret;
1229 }
1230
1231 platform_set_drvdata(pdev, priv);
1232
1233 ret = rcsi2_parse_dt(priv);
1234 if (ret)
1235 return ret;
1236
1237 priv->subdev.owner = THIS_MODULE;
1238 priv->subdev.dev = &pdev->dev;
1239 v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops);
1240 v4l2_set_subdevdata(&priv->subdev, &pdev->dev);
1241 snprintf(priv->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s %s",
1242 KBUILD_MODNAME, dev_name(&pdev->dev));
1243 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1244
1245 priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1246 priv->subdev.entity.ops = &rcar_csi2_entity_ops;
1247
1248 priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK;
1249 for (i = RCAR_CSI2_SOURCE_VC0; i < NR_OF_RCAR_CSI2_PAD; i++)
1250 priv->pads[i].flags = MEDIA_PAD_FL_SOURCE;
1251
1252 ret = media_entity_pads_init(&priv->subdev.entity, NR_OF_RCAR_CSI2_PAD,
1253 priv->pads);
1254 if (ret)
1255 goto error;
1256
1257 pm_runtime_enable(&pdev->dev);
1258
1259 ret = v4l2_async_register_subdev(&priv->subdev);
1260 if (ret < 0)
1261 goto error;
1262
1263 dev_info(priv->dev, "%d lanes found\n", priv->lanes);
1264
1265 return 0;
1266
1267 error:
1268 v4l2_async_notifier_unregister(&priv->notifier);
1269 v4l2_async_notifier_cleanup(&priv->notifier);
1270
1271 return ret;
1272 }
1273
1274 static int rcsi2_remove(struct platform_device *pdev)
1275 {
1276 struct rcar_csi2 *priv = platform_get_drvdata(pdev);
1277
1278 v4l2_async_notifier_unregister(&priv->notifier);
1279 v4l2_async_notifier_cleanup(&priv->notifier);
1280 v4l2_async_unregister_subdev(&priv->subdev);
1281
1282 pm_runtime_disable(&pdev->dev);
1283
1284 return 0;
1285 }
1286
1287 static struct platform_driver rcar_csi2_pdrv = {
1288 .remove = rcsi2_remove,
1289 .probe = rcsi2_probe,
1290 .driver = {
1291 .name = "rcar-csi2",
1292 .of_match_table = rcar_csi2_of_table,
1293 },
1294 };
1295
1296 module_platform_driver(rcar_csi2_pdrv);
1297
1298 MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>");
1299 MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver");
1300 MODULE_LICENSE("GPL");
Linux with added FPC-III support