drivers/memstick/host/r592.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2010 - Maxim Levitsky
   4  * driver for Ricoh memstick readers
   5  */
   6
   7 #ifndef R592_H
   8
   9 #include <linux/memstick.h>
  10 #include <linux/spinlock.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/workqueue.h>
  13 #include <linux/kfifo.h>
  14 #include <linux/ctype.h>
  15
  16 /* write to this reg (number,len) triggers TPC execution */
  17 #define R592_TPC_EXEC                   0x00
  18 #define R592_TPC_EXEC_LEN_SHIFT         16              /* Bits 16..25 are TPC len */
  19 #define R592_TPC_EXEC_BIG_FIFO          (1 << 26)       /* If bit 26 is set, large fifo is used (reg 48) */
  20 #define R592_TPC_EXEC_TPC_SHIFT         28              /* Bits 28..31 are the TPC number */
  21
  22
  23 /* Window for small TPC fifo (big endian)*/
  24 /* reads and writes always are done in  8 byte chunks */
  25 /* Not used in driver, because large fifo does better job */
  26 #define R592_SFIFO                      0x08
  27
  28
  29 /* Status register (ms int, small fifo, IO)*/
  30 #define R592_STATUS                     0x10
  31                                                         /* Parallel INT bits */
  32 #define R592_STATUS_P_CMDNACK           (1 << 16)       /* INT reg: NACK (parallel mode) */
  33 #define R592_STATUS_P_BREQ              (1 << 17)       /* INT reg: card ready (parallel mode)*/
  34 #define R592_STATUS_P_INTERR            (1 << 18)       /* INT reg: int error (parallel mode)*/
  35 #define R592_STATUS_P_CED               (1 << 19)       /* INT reg: command done (parallel mode) */
  36
  37                                                         /* Fifo status */
  38 #define R592_STATUS_SFIFO_FULL          (1 << 20)       /* Small Fifo almost full (last chunk is written) */
  39 #define R592_STATUS_SFIFO_EMPTY         (1 << 21)       /* Small Fifo empty */
  40
  41                                                         /* Error detection via CRC */
  42 #define R592_STATUS_SEND_ERR            (1 << 24)       /* Send failed */
  43 #define R592_STATUS_RECV_ERR            (1 << 25)       /* Receive failed */
  44
  45                                                         /* Card state */
  46 #define R592_STATUS_RDY                 (1 << 28)       /* RDY signal received */
  47 #define R592_STATUS_CED                 (1 << 29)       /* INT: Command done (serial mode)*/
  48 #define R592_STATUS_SFIFO_INPUT         (1 << 30)       /* Small fifo received data*/
  49
  50 #define R592_SFIFO_SIZE                 32              /* total size of small fifo is 32 bytes */
  51 #define R592_SFIFO_PACKET               8               /* packet size of small fifo */
  52
  53 /* IO control */
  54 #define R592_IO                         0x18
  55 #define R592_IO_16                      (1 << 16)       /* Set by default, can be cleared */
  56 #define R592_IO_18                      (1 << 18)       /* Set by default, can be cleared */
  57 #define R592_IO_SERIAL1                 (1 << 20)       /* Set by default, can be cleared, (cleared on parallel) */
  58 #define R592_IO_22                      (1 << 22)       /* Set by default, can be cleared */
  59 #define R592_IO_DIRECTION               (1 << 24)       /* TPC direction (1 write 0 read) */
  60 #define R592_IO_26                      (1 << 26)       /* Set by default, can be cleared */
  61 #define R592_IO_SERIAL2                 (1 << 30)       /* Set by default, can be cleared (cleared on parallel), serial doesn't work if unset */
  62 #define R592_IO_RESET                   (1 << 31)       /* Reset, sets defaults*/
  63
  64
  65 /* Turns hardware on/off */
  66 #define R592_POWER                      0x20            /* bits 0-7 writeable */
  67 #define R592_POWER_0                    (1 << 0)        /* set on start, cleared on stop - must be set*/
  68 #define R592_POWER_1                    (1 << 1)        /* set on start, cleared on stop - must be set*/
  69 #define R592_POWER_3                    (1 << 3)        /* must be clear */
  70 #define R592_POWER_20                   (1 << 5)        /* set before switch to parallel */
  71
  72 /* IO mode*/
  73 #define R592_IO_MODE                    0x24
  74 #define R592_IO_MODE_SERIAL             1
  75 #define R592_IO_MODE_PARALLEL           3
  76
  77
  78 /* IRQ,card detection,large fifo (first word irq status, second enable) */
  79 /* IRQs are ACKed by clearing the bits */
  80 #define R592_REG_MSC                    0x28
  81 #define R592_REG_MSC_PRSNT              (1 << 1)        /* card present (only status)*/
  82 #define R592_REG_MSC_IRQ_INSERT         (1 << 8)        /* detect insert / card insered */
  83 #define R592_REG_MSC_IRQ_REMOVE         (1 << 9)        /* detect removal / card removed */
  84 #define R592_REG_MSC_FIFO_EMPTY         (1 << 10)       /* fifo is empty */
  85 #define R592_REG_MSC_FIFO_DMA_DONE      (1 << 11)       /* dma enable / dma done */
  86
  87 #define R592_REG_MSC_FIFO_USER_ORN      (1 << 12)       /* set if software reads empty fifo (if R592_REG_MSC_FIFO_EMPTY is set) */
  88 #define R592_REG_MSC_FIFO_MISMATH       (1 << 13)       /* set if amount of data in fifo doesn't match amount in TPC */
  89 #define R592_REG_MSC_FIFO_DMA_ERR       (1 << 14)       /* IO failure */
  90 #define R592_REG_MSC_LED                (1 << 15)       /* clear to turn led off (only status)*/
  91
  92 #define DMA_IRQ_ACK_MASK \
  93         (R592_REG_MSC_FIFO_DMA_DONE | R592_REG_MSC_FIFO_DMA_ERR)
  94
  95 #define DMA_IRQ_EN_MASK (DMA_IRQ_ACK_MASK << 16)
  96
  97 #define IRQ_ALL_ACK_MASK 0x00007F00
  98 #define IRQ_ALL_EN_MASK (IRQ_ALL_ACK_MASK << 16)
  99
 100 /* DMA address for large FIFO read/writes*/
 101 #define R592_FIFO_DMA                   0x2C
 102
 103 /* PIO access to large FIFO (512 bytes) (big endian)*/
 104 #define R592_FIFO_PIO                   0x30
 105 #define R592_LFIFO_SIZE                 512             /* large fifo size */
 106
 107
 108 /* large FIFO DMA settings */
 109 #define R592_FIFO_DMA_SETTINGS          0x34
 110 #define R592_FIFO_DMA_SETTINGS_EN       (1 << 0)        /* DMA enabled */
 111 #define R592_FIFO_DMA_SETTINGS_DIR      (1 << 1)        /* Dma direction (1 read, 0 write) */
 112 #define R592_FIFO_DMA_SETTINGS_CAP      (1 << 24)       /* Dma is aviable */
 113
 114 /* Maybe just an delay */
 115 /* Bits 17..19 are just number */
 116 /* bit 16 is set, then bit 20 is waited */
 117 /* time to wait is about 50 spins * 2 ^ (bits 17..19) */
 118 /* seems to be possible just to ignore */
 119 /* Probably debug register */
 120 #define R592_REG38                      0x38
 121 #define R592_REG38_CHANGE               (1 << 16)       /* Start bit */
 122 #define R592_REG38_DONE                 (1 << 20)       /* HW set this after the delay */
 123 #define R592_REG38_SHIFT                17
 124
 125 /* Debug register, written (0xABCDEF00) when error happens - not used*/
 126 #define R592_REG_3C                     0x3C
 127
 128 struct r592_device {
 129         struct pci_dev *pci_dev;
 130         struct memstick_host    *host;          /* host backpointer */
 131         struct memstick_request *req;           /* current request */
 132
 133         /* Registers, IRQ */
 134         void __iomem *mmio;
 135         int irq;
 136         spinlock_t irq_lock;
 137         spinlock_t io_thread_lock;
 138         struct timer_list detect_timer;
 139
 140         struct task_struct *io_thread;
 141         bool parallel_mode;
 142
 143         DECLARE_KFIFO(pio_fifo, u8, sizeof(u32));
 144
 145         /* DMA area */
 146         int dma_capable;
 147         int dma_error;
 148         struct completion dma_done;
 149         void *dummy_dma_page;
 150         dma_addr_t dummy_dma_page_physical_address;
 151
 152 };
 153
 154 #define DRV_NAME "r592"
 155
 156
 157 #define message(format, ...) \
 158         printk(KERN_INFO DRV_NAME ": " format "\n", ## __VA_ARGS__)
 159
 160 #define __dbg(level, format, ...) \
 161         do { \
 162                 if (debug >= level) \
 163                         printk(KERN_DEBUG DRV_NAME \
 164                                 ": " format "\n", ## __VA_ARGS__); \
 165         } while (0)
 166
 167
 168 #define dbg(format, ...)                __dbg(1, format, ## __VA_ARGS__)
 169 #define dbg_verbose(format, ...)        __dbg(2, format, ## __VA_ARGS__)
 170 #define dbg_reg(format, ...)            __dbg(3, format, ## __VA_ARGS__)
 171
 172 #endif