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Merge tag 'regmap-fix-v5.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / mmc / host / renesas_sdhi_core.c
blob38f028e70633b336e421d7526e0969ddec368a30
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas SDHI
4 *
5 * Copyright (C) 2015-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
8 * Copyright (C) 2009 Magnus Damm
9 *
10 * Based on "Compaq ASIC3 support":
11 *
12 * Copyright 2001 Compaq Computer Corporation.
13 * Copyright 2004-2005 Phil Blundell
14 * Copyright 2007-2008 OpenedHand Ltd.
15 *
16 * Authors: Phil Blundell <pb@handhelds.org>,
17 * Samuel Ortiz <sameo@openedhand.com>
18 *
19 */
20
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/kernel.h>
24 #include <linux/mfd/tmio.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/mmc.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/module.h>
29 #include <linux/of_device.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/pinctrl/pinctrl-state.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_domain.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/sh_dma.h>
36 #include <linux/slab.h>
37 #include <linux/sys_soc.h>
38
39 #include "renesas_sdhi.h"
40 #include "tmio_mmc.h"
41
42 #define CTL_HOST_MODE 0xe4
43 #define HOST_MODE_GEN2_SDR50_WMODE BIT(0)
44 #define HOST_MODE_GEN2_SDR104_WMODE BIT(0)
45 #define HOST_MODE_GEN3_WMODE BIT(0)
46 #define HOST_MODE_GEN3_BUSWIDTH BIT(8)
47
48 #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE
49 #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH)
50 #define HOST_MODE_GEN3_64BIT 0
51
52 #define CTL_SDIF_MODE 0xe6
53 #define SDIF_MODE_HS400 BIT(0)
54
55 #define SDHI_VER_GEN2_SDR50 0x490c
56 #define SDHI_VER_RZ_A1 0x820b
57 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
58 #define SDHI_VER_GEN2_SDR104 0xcb0d
59 #define SDHI_VER_GEN3_SD 0xcc10
60 #define SDHI_VER_GEN3_SDMMC 0xcd10
61
62 #define SDHI_GEN3_MMC0_ADDR 0xee140000
63
64 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
65 {
66 u32 val;
67
68 /*
69 * see also
70 * renesas_sdhi_of_data :: dma_buswidth
71 */
72 switch (sd_ctrl_read16(host, CTL_VERSION)) {
73 case SDHI_VER_GEN2_SDR50:
74 val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0;
75 break;
76 case SDHI_VER_GEN2_SDR104:
77 val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE;
78 break;
79 case SDHI_VER_GEN3_SD:
80 case SDHI_VER_GEN3_SDMMC:
81 if (width == 64)
82 val = HOST_MODE_GEN3_64BIT;
83 else if (width == 32)
84 val = HOST_MODE_GEN3_32BIT;
85 else
86 val = HOST_MODE_GEN3_16BIT;
87 break;
88 default:
89 /* nothing to do */
90 return;
91 }
92
93 sd_ctrl_write16(host, CTL_HOST_MODE, val);
94 }
95
96 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
97 {
98 struct mmc_host *mmc = host->mmc;
99 struct renesas_sdhi *priv = host_to_priv(host);
100 int ret;
101
102 ret = clk_prepare_enable(priv->clk_cd);
103 if (ret < 0)
104 return ret;
105
106 /*
107 * The clock driver may not know what maximum frequency
108 * actually works, so it should be set with the max-frequency
109 * property which will already have been read to f_max. If it
110 * was missing, assume the current frequency is the maximum.
111 */
112 if (!mmc->f_max)
113 mmc->f_max = clk_get_rate(priv->clk);
114
115 /*
116 * Minimum frequency is the minimum input clock frequency
117 * divided by our maximum divider.
118 */
119 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
120
121 /* enable 16bit data access on SDBUF as default */
122 renesas_sdhi_sdbuf_width(host, 16);
123
124 return 0;
125 }
126
127 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
128 unsigned int new_clock)
129 {
130 struct renesas_sdhi *priv = host_to_priv(host);
131 unsigned int freq, diff, best_freq = 0, diff_min = ~0;
132 int i;
133
134 /*
135 * We simply return the current rate if a) we are not on a R-Car Gen2+
136 * SoC (may work for others, but untested) or b) if the SCC needs its
137 * clock during tuning, so we don't change the external clock setup.
138 */
139 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
140 return clk_get_rate(priv->clk);
141
142 /*
143 * We want the bus clock to be as close as possible to, but no
144 * greater than, new_clock. As we can divide by 1 << i for
145 * any i in [0, 9] we want the input clock to be as close as
146 * possible, but no greater than, new_clock << i.
147 */
148 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
149 freq = clk_round_rate(priv->clk, new_clock << i);
150 if (freq > (new_clock << i)) {
151 /* Too fast; look for a slightly slower option */
152 freq = clk_round_rate(priv->clk,
153 (new_clock << i) / 4 * 3);
154 if (freq > (new_clock << i))
155 continue;
156 }
157
158 diff = new_clock - (freq >> i);
159 if (diff <= diff_min) {
160 best_freq = freq;
161 diff_min = diff;
162 }
163 }
164
165 clk_set_rate(priv->clk, best_freq);
166
167 return clk_get_rate(priv->clk);
168 }
169
170 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
171 unsigned int new_clock)
172 {
173 u32 clk = 0, clock;
174
175 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
176 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
177
178 if (new_clock == 0) {
179 host->mmc->actual_clock = 0;
180 goto out;
181 }
182
183 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
184 clock = host->mmc->actual_clock / 512;
185
186 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
187 clock <<= 1;
188
189 /* 1/1 clock is option */
190 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
191 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
192 clk |= 0xff;
193 else
194 clk &= ~0xff;
195 }
196
197 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
198 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
199 usleep_range(10000, 11000);
200
201 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
202 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
203
204 out:
205 /* HW engineers overrode docs: no sleep needed on R-Car2+ */
206 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
207 usleep_range(10000, 11000);
208 }
209
210 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
211 {
212 struct renesas_sdhi *priv = host_to_priv(host);
213
214 clk_disable_unprepare(priv->clk_cd);
215 }
216
217 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
218 {
219 struct tmio_mmc_host *host = mmc_priv(mmc);
220
221 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
222 TMIO_STAT_DAT0);
223 }
224
225 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
226 struct mmc_ios *ios)
227 {
228 struct tmio_mmc_host *host = mmc_priv(mmc);
229 struct renesas_sdhi *priv = host_to_priv(host);
230 struct pinctrl_state *pin_state;
231 int ret;
232
233 switch (ios->signal_voltage) {
234 case MMC_SIGNAL_VOLTAGE_330:
235 pin_state = priv->pins_default;
236 break;
237 case MMC_SIGNAL_VOLTAGE_180:
238 pin_state = priv->pins_uhs;
239 break;
240 default:
241 return -EINVAL;
242 }
243
244 /*
245 * If anything is missing, assume signal voltage is fixed at
246 * 3.3V and succeed/fail accordingly.
247 */
248 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
249 return ios->signal_voltage ==
250 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
251
252 ret = mmc_regulator_set_vqmmc(host->mmc, ios);
253 if (ret < 0)
254 return ret;
255
256 return pinctrl_select_state(priv->pinctrl, pin_state);
257 }
258
259 /* SCC registers */
260 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
261 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002
262 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004
263 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006
264 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
265 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
266 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C
267 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
268 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014
269 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016
270 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018
271 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A
272 #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C
273
274 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
275 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
276 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
277
278 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
279
280 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
281
282 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
283 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
284 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
285
286 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
287 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
288 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24))
289
290 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
291 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
292
293 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */
294 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
295
296 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */
297 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
298 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
299 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
300
301 /* Definitions for values the SH_MOBILE_SDHI_SCC register */
302 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
303 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
304 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
305
306 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
307 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15,
308 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
309 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11,
310 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
311 };
312
313 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
314 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
315 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
316 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17,
317 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
318 };
319
320 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
321 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
322 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
323 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10,
324 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
325 };
326
327 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
328 struct renesas_sdhi *priv, int addr)
329 {
330 return readl(priv->scc_ctl + (addr << host->bus_shift));
331 }
332
333 static inline void sd_scc_write32(struct tmio_mmc_host *host,
334 struct renesas_sdhi *priv,
335 int addr, u32 val)
336 {
337 writel(val, priv->scc_ctl + (addr << host->bus_shift));
338 }
339
340 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
341 {
342 struct renesas_sdhi *priv;
343
344 priv = host_to_priv(host);
345
346 /* Initialize SCC */
347 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
348
349 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
350 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
351
352 /* set sampling clock selection range */
353 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
354 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
355 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
356
357 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
358 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
359 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
360
361 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
362 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
363 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
364
365 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
366
367 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
368 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
369
370 /* Read TAPNUM */
371 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
372 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
373 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
374 }
375
376 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
377 {
378 struct tmio_mmc_host *host = mmc_priv(mmc);
379 struct renesas_sdhi *priv = host_to_priv(host);
380 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
381 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
382
383 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
384 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
385
386 /* Set HS400 mode */
387 sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 |
388 sd_ctrl_read16(host, CTL_SDIF_MODE));
389
390 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
391 priv->scc_tappos_hs400);
392
393 /* Gen3 can't do automatic tap correction with HS400, so disable it */
394 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC)
395 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
396 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
397 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
398
399 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
400 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
401 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
402 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
403
404 /* Set the sampling clock selection range of HS400 mode */
405 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
406 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
407 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
408
409 /* Avoid bad TAP */
410 if (bad_taps & BIT(priv->tap_set)) {
411 u32 new_tap = (priv->tap_set + 1) % priv->tap_num;
412
413 if (bad_taps & BIT(new_tap))
414 new_tap = (priv->tap_set - 1) % priv->tap_num;
415
416 if (bad_taps & BIT(new_tap)) {
417 new_tap = priv->tap_set;
418 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n");
419 }
420
421 priv->tap_set = new_tap;
422 }
423
424 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
425 priv->tap_set / (use_4tap ? 2 : 1));
426
427 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
428 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
429 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
430
431 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
432 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
433
434 if (priv->adjust_hs400_calib_table)
435 priv->needs_adjust_hs400 = true;
436 }
437
438 static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
439 {
440 struct tmio_mmc_host *host = mmc_priv(mmc);
441 struct renesas_sdhi *priv = host_to_priv(host);
442
443 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
444 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
445
446 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
447 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
448 sd_scc_read32(host, priv,
449 SH_MOBILE_SDHI_SCC_CKSEL));
450
451 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
452 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
453 sd_scc_read32(host, priv,
454 SH_MOBILE_SDHI_SCC_DTCNTL));
455
456 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
457 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
458 }
459
460 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host,
461 struct renesas_sdhi *priv, u32 addr)
462 {
463 /* read mode */
464 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
465 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
466 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
467
468 /* access start and stop */
469 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
470 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
471 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
472
473 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7);
474 }
475
476 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host,
477 struct renesas_sdhi *priv, u32 addr, u32 val)
478 {
479 /* write mode */
480 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
481 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
482 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
483
484 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val);
485
486 /* access start and stop */
487 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
488 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
489 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
490 }
491
492 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host)
493 {
494 struct renesas_sdhi *priv = host_to_priv(host);
495 u32 calib_code;
496
497 /* disable write protect */
498 sd_scc_tmpport_write32(host, priv, 0x00,
499 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
500 /* read calibration code and adjust */
501 calib_code = sd_scc_tmpport_read32(host, priv, 0x26);
502 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
503
504 sd_scc_tmpport_write32(host, priv, 0x22,
505 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE |
506 priv->adjust_hs400_calib_table[calib_code]);
507
508 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */
509 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3);
510
511 /* adjustment done, clear flag */
512 priv->needs_adjust_hs400 = false;
513 }
514
515 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host)
516 {
517 struct renesas_sdhi *priv = host_to_priv(host);
518
519 /* disable write protect */
520 sd_scc_tmpport_write32(host, priv, 0x00,
521 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
522 /* disable manual calibration */
523 sd_scc_tmpport_write32(host, priv, 0x22, 0);
524 /* clear offset value of TMPPORT3 */
525 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0);
526 }
527
528 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
529 struct renesas_sdhi *priv)
530 {
531 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
532 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
533
534 /* Reset HS400 mode */
535 sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 &
536 sd_ctrl_read16(host, CTL_SDIF_MODE));
537
538 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
539
540 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
541 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
542 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
543 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
544
545 if (priv->adjust_hs400_calib_table)
546 renesas_sdhi_adjust_hs400_mode_disable(host);
547
548 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
549 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
550 }
551
552 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
553 {
554 struct tmio_mmc_host *host = mmc_priv(mmc);
555
556 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
557 return 0;
558 }
559
560 /* only populated for TMIO_MMC_MIN_RCAR2 */
561 static void renesas_sdhi_reset(struct tmio_mmc_host *host)
562 {
563 struct renesas_sdhi *priv = host_to_priv(host);
564 u16 val;
565
566 if (priv->scc_ctl) {
567 renesas_sdhi_disable_scc(host->mmc);
568 renesas_sdhi_reset_hs400_mode(host, priv);
569 priv->needs_adjust_hs400 = false;
570
571 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
572 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
573 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
574 }
575
576 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, TMIO_MASK_INIT_RCAR2);
577
578 if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) {
579 val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
580 val |= CARD_OPT_EXTOP;
581 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val);
582 }
583 }
584
585 static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host)
586 {
587 u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
588
589 num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT;
590 return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num);
591
592 }
593
594 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3
595
596 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
597 {
598 struct renesas_sdhi *priv = host_to_priv(host);
599 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
600 unsigned int taps_size = priv->tap_num * 2, min_tap_row;
601 unsigned long *bitmap;
602
603 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
604
605 /*
606 * When tuning CMD19 is issued twice for each tap, merge the
607 * result requiring the tap to be good in both runs before
608 * considering it for tuning selection.
609 */
610 for (i = 0; i < taps_size; i++) {
611 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
612
613 if (!test_bit(i, priv->taps))
614 clear_bit(i + offset, priv->taps);
615
616 if (!test_bit(i, priv->smpcmp))
617 clear_bit(i + offset, priv->smpcmp);
618 }
619
620 /*
621 * If all TAP are OK, the sampling clock position is selected by
622 * identifying the change point of data.
623 */
624 if (bitmap_full(priv->taps, taps_size)) {
625 bitmap = priv->smpcmp;
626 min_tap_row = 1;
627 } else {
628 bitmap = priv->taps;
629 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW;
630 }
631
632 /*
633 * Find the longest consecutive run of successful probes. If that
634 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the
635 * center index as the tap, otherwise bail out.
636 */
637 bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) {
638 if (re - rs > tap_cnt) {
639 tap_end = re;
640 tap_start = rs;
641 tap_cnt = tap_end - tap_start;
642 }
643 }
644
645 if (tap_cnt >= min_tap_row)
646 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
647 else
648 return -EIO;
649
650 /* Set SCC */
651 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
652
653 /* Enable auto re-tuning */
654 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
655 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
656 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
657
658 return 0;
659 }
660
661 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode)
662 {
663 struct tmio_mmc_host *host = mmc_priv(mmc);
664 struct renesas_sdhi *priv = host_to_priv(host);
665 int i, ret;
666
667 priv->tap_num = renesas_sdhi_init_tuning(host);
668 if (!priv->tap_num)
669 return 0; /* Tuning is not supported */
670
671 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
672 dev_err(&host->pdev->dev,
673 "Too many taps, please update 'taps' in tmio_mmc_host!\n");
674 return -EINVAL;
675 }
676
677 bitmap_zero(priv->taps, priv->tap_num * 2);
678 bitmap_zero(priv->smpcmp, priv->tap_num * 2);
679
680 /* Issue CMD19 twice for each tap */
681 for (i = 0; i < 2 * priv->tap_num; i++) {
682 /* Set sampling clock position */
683 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
684
685 if (mmc_send_tuning(mmc, opcode, NULL) == 0)
686 set_bit(i, priv->taps);
687
688 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
689 set_bit(i, priv->smpcmp);
690 }
691
692 ret = renesas_sdhi_select_tuning(host);
693 if (ret < 0)
694 renesas_sdhi_reset(host);
695 return ret;
696 }
697
698 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
699 {
700 struct renesas_sdhi *priv = host_to_priv(host);
701 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set;
702 u32 val;
703
704 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
705 if (!val)
706 return false;
707
708 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
709
710 /* Change TAP position according to correction status */
711 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC &&
712 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
713 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
714 /*
715 * With HS400, the DAT signal is based on DS, not CLK.
716 * Therefore, use only CMD status.
717 */
718 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
719 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
720 if (!smpcmp) {
721 return false; /* no error in CMD signal */
722 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) {
723 new_tap++;
724 error_tap--;
725 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) {
726 new_tap--;
727 error_tap++;
728 } else {
729 return true; /* need retune */
730 }
731
732 /*
733 * When new_tap is a bad tap, we cannot change. Then, we compare
734 * with the HS200 tuning result. When smpcmp[error_tap] is OK,
735 * we can at least retune.
736 */
737 if (bad_taps & BIT(new_tap % priv->tap_num))
738 return test_bit(error_tap % priv->tap_num, priv->smpcmp);
739 } else {
740 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
741 return true; /* need retune */
742 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
743 new_tap++;
744 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
745 new_tap--;
746 else
747 return false;
748 }
749
750 priv->tap_set = (new_tap % priv->tap_num);
751 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
752 priv->tap_set / (use_4tap ? 2 : 1));
753
754 return false;
755 }
756
757 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
758 {
759 struct renesas_sdhi *priv = host_to_priv(host);
760
761 /* Check SCC error */
762 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
763 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
764 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
765 return true;
766 }
767
768 return false;
769 }
770
771 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
772 {
773 struct renesas_sdhi *priv = host_to_priv(host);
774 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
775
776 /*
777 * Skip checking SCC errors when running on 4 taps in HS400 mode as
778 * any retuning would still result in the same 4 taps being used.
779 */
780 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
781 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
782 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
783 return false;
784
785 if (mmc_doing_tune(host->mmc))
786 return false;
787
788 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
789 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
790 return renesas_sdhi_auto_correction(host);
791
792 return renesas_sdhi_manual_correction(host, use_4tap);
793 }
794
795 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
796 {
797 int timeout = 1000;
798 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
799 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
800
801 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
802 & bit) == wait_state)
803 udelay(1);
804
805 if (!timeout) {
806 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
807 return -EBUSY;
808 }
809
810 return 0;
811 }
812
813 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
814 {
815 u32 bit = TMIO_STAT_SCLKDIVEN;
816
817 switch (addr) {
818 case CTL_SD_CMD:
819 case CTL_STOP_INTERNAL_ACTION:
820 case CTL_XFER_BLK_COUNT:
821 case CTL_SD_XFER_LEN:
822 case CTL_SD_MEM_CARD_OPT:
823 case CTL_TRANSACTION_CTL:
824 case CTL_DMA_ENABLE:
825 case CTL_HOST_MODE:
826 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
827 bit = TMIO_STAT_CMD_BUSY;
828 fallthrough;
829 case CTL_SD_CARD_CLK_CTL:
830 return renesas_sdhi_wait_idle(host, bit);
831 }
832
833 return 0;
834 }
835
836 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
837 unsigned int direction, int blk_size)
838 {
839 /*
840 * In Renesas controllers, when performing a
841 * multiple block read of one or two blocks,
842 * depending on the timing with which the
843 * response register is read, the response
844 * value may not be read properly.
845 * Use single block read for this HW bug
846 */
847 if ((direction == MMC_DATA_READ) &&
848 blk_size == 2)
849 return 1;
850
851 return blk_size;
852 }
853
854 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq)
855 {
856 struct renesas_sdhi *priv = host_to_priv(host);
857
858 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS)
859 renesas_sdhi_adjust_hs400_mode_enable(host);
860 }
861 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
862 {
863 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
864 int width = (host->bus_shift == 2) ? 64 : 32;
865
866 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
867 renesas_sdhi_sdbuf_width(host, enable ? width : 16);
868 }
869
870 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
871 .hs400_disabled = true,
872 .hs400_4taps = true,
873 };
874
875 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
876 .hs400_4taps = true,
877 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
878 };
879
880 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
881 .hs400_disabled = true,
882 };
883
884 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = {
885 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
886 };
887
888 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = {
889 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
890 };
891
892 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
893 .hs400_4taps = true,
894 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
895 .hs400_calib_table = r8a7796_es13_calib_table,
896 };
897
898 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
899 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
900 .hs400_calib_table = r8a77965_calib_table,
901 };
902
903 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = {
904 .hs400_calib_table = r8a77990_calib_table,
905 };
906
907 /*
908 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
909 * So, we want to treat them equally and only have a match for ES1.2 to enforce
910 * this if there ever will be a way to distinguish ES1.2.
911 */
912 static const struct soc_device_attribute sdhi_quirks_match[] = {
913 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
914 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 },
915 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
916 { .soc_id = "r8a7795", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps2367 },
917 { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
918 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 },
919 { .soc_id = "r8a7796", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps1357 },
920 { .soc_id = "r8a77965", .data = &sdhi_quirks_r8a77965 },
921 { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 },
922 { .soc_id = "r8a77990", .data = &sdhi_quirks_r8a77990 },
923 { /* Sentinel. */ },
924 };
925
926 int renesas_sdhi_probe(struct platform_device *pdev,
927 const struct tmio_mmc_dma_ops *dma_ops)
928 {
929 struct tmio_mmc_data *mmd = pdev->dev.platform_data;
930 const struct renesas_sdhi_quirks *quirks = NULL;
931 const struct renesas_sdhi_of_data *of_data;
932 const struct soc_device_attribute *attr;
933 struct tmio_mmc_data *mmc_data;
934 struct tmio_mmc_dma *dma_priv;
935 struct tmio_mmc_host *host;
936 struct renesas_sdhi *priv;
937 int num_irqs, irq, ret, i;
938 struct resource *res;
939 u16 ver;
940
941 of_data = of_device_get_match_data(&pdev->dev);
942
943 attr = soc_device_match(sdhi_quirks_match);
944 if (attr)
945 quirks = attr->data;
946
947 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
948 if (!res)
949 return -EINVAL;
950
951 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
952 GFP_KERNEL);
953 if (!priv)
954 return -ENOMEM;
955
956 priv->quirks = quirks;
957 mmc_data = &priv->mmc_data;
958 dma_priv = &priv->dma_priv;
959
960 priv->clk = devm_clk_get(&pdev->dev, NULL);
961 if (IS_ERR(priv->clk)) {
962 ret = PTR_ERR(priv->clk);
963 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
964 return ret;
965 }
966
967 /*
968 * Some controllers provide a 2nd clock just to run the internal card
969 * detection logic. Unfortunately, the existing driver architecture does
970 * not support a separation of clocks for runtime PM usage. When
971 * native hotplug is used, the tmio driver assumes that the core
972 * must continue to run for card detect to stay active, so we cannot
973 * disable it.
974 * Additionally, it is prohibited to supply a clock to the core but not
975 * to the card detect circuit. That leaves us with if separate clocks
976 * are presented, we must treat them both as virtually 1 clock.
977 */
978 priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
979 if (IS_ERR(priv->clk_cd))
980 priv->clk_cd = NULL;
981
982 priv->pinctrl = devm_pinctrl_get(&pdev->dev);
983 if (!IS_ERR(priv->pinctrl)) {
984 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
985 PINCTRL_STATE_DEFAULT);
986 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
987 "state_uhs");
988 }
989
990 host = tmio_mmc_host_alloc(pdev, mmc_data);
991 if (IS_ERR(host))
992 return PTR_ERR(host);
993
994 if (of_data) {
995 mmc_data->flags |= of_data->tmio_flags;
996 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
997 mmc_data->capabilities |= of_data->capabilities;
998 mmc_data->capabilities2 |= of_data->capabilities2;
999 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
1000 mmc_data->max_blk_count = of_data->max_blk_count;
1001 mmc_data->max_segs = of_data->max_segs;
1002 dma_priv->dma_buswidth = of_data->dma_buswidth;
1003 host->bus_shift = of_data->bus_shift;
1004 }
1005
1006 host->write16_hook = renesas_sdhi_write16_hook;
1007 host->clk_enable = renesas_sdhi_clk_enable;
1008 host->clk_disable = renesas_sdhi_clk_disable;
1009 host->set_clock = renesas_sdhi_set_clock;
1010 host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
1011 host->dma_ops = dma_ops;
1012
1013 if (quirks && quirks->hs400_disabled)
1014 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
1015
1016 /* For some SoC, we disable internal WP. GPIO may override this */
1017 if (mmc_can_gpio_ro(host->mmc))
1018 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
1019
1020 /* SDR speeds are only available on Gen2+ */
1021 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
1022 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
1023 host->ops.card_busy = renesas_sdhi_card_busy;
1024 host->ops.start_signal_voltage_switch =
1025 renesas_sdhi_start_signal_voltage_switch;
1026 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
1027 host->reset = renesas_sdhi_reset;
1028 }
1029
1030 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
1031 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
1032 host->bus_shift = 1;
1033
1034 if (mmd)
1035 *mmc_data = *mmd;
1036
1037 dma_priv->filter = shdma_chan_filter;
1038 dma_priv->enable = renesas_sdhi_enable_dma;
1039
1040 mmc_data->alignment_shift = 1; /* 2-byte alignment */
1041 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1042
1043 /*
1044 * All SDHI blocks support 2-byte and larger block sizes in 4-bit
1045 * bus width mode.
1046 */
1047 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
1048
1049 /*
1050 * All SDHI blocks support SDIO IRQ signalling.
1051 */
1052 mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
1053
1054 /* All SDHI have CMD12 control bit */
1055 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
1056
1057 /* All SDHI have SDIO status bits which must be 1 */
1058 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
1059
1060 /* All SDHI support HW busy detection */
1061 mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT;
1062
1063 dev_pm_domain_start(&pdev->dev);
1064
1065 ret = renesas_sdhi_clk_enable(host);
1066 if (ret)
1067 goto efree;
1068
1069 ver = sd_ctrl_read16(host, CTL_VERSION);
1070 /* GEN2_SDR104 is first known SDHI to use 32bit block count */
1071 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
1072 mmc_data->max_blk_count = U16_MAX;
1073
1074 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
1075 if (ver == SDHI_VER_GEN2_SDR50)
1076 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
1077
1078 if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) {
1079 host->fixup_request = renesas_sdhi_fixup_request;
1080 priv->adjust_hs400_calib_table = *(
1081 res->start == SDHI_GEN3_MMC0_ADDR ?
1082 quirks->hs400_calib_table :
1083 quirks->hs400_calib_table + 1);
1084 }
1085
1086 /* these have an EXTOP bit */
1087 if (ver >= SDHI_VER_GEN3_SD)
1088 host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles;
1089
1090 /* Enable tuning iff we have an SCC and a supported mode */
1091 if (of_data && of_data->scc_offset &&
1092 (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
1093 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
1094 MMC_CAP2_HS400_1_8V))) {
1095 const struct renesas_sdhi_scc *taps = of_data->taps;
1096 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
1097 bool hit = false;
1098
1099 for (i = 0; i < of_data->taps_num; i++) {
1100 if (taps[i].clk_rate == 0 ||
1101 taps[i].clk_rate == host->mmc->f_max) {
1102 priv->scc_tappos = taps->tap;
1103 priv->scc_tappos_hs400 = use_4tap ?
1104 taps->tap_hs400_4tap :
1105 taps->tap;
1106 hit = true;
1107 break;
1108 }
1109 }
1110
1111 if (!hit)
1112 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
1113
1114 priv->scc_ctl = host->ctl + of_data->scc_offset;
1115 host->check_retune = renesas_sdhi_check_scc_error;
1116 host->ops.execute_tuning = renesas_sdhi_execute_tuning;
1117 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
1118 host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
1119 host->ops.hs400_complete = renesas_sdhi_hs400_complete;
1120 }
1121
1122 ret = tmio_mmc_host_probe(host);
1123 if (ret < 0)
1124 goto edisclk;
1125
1126 num_irqs = platform_irq_count(pdev);
1127 if (num_irqs < 0) {
1128 ret = num_irqs;
1129 goto eirq;
1130 }
1131
1132 /* There must be at least one IRQ source */
1133 if (!num_irqs) {
1134 ret = -ENXIO;
1135 goto eirq;
1136 }
1137
1138 for (i = 0; i < num_irqs; i++) {
1139 irq = platform_get_irq(pdev, i);
1140 if (irq < 0) {
1141 ret = irq;
1142 goto eirq;
1143 }
1144
1145 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
1146 dev_name(&pdev->dev), host);
1147 if (ret)
1148 goto eirq;
1149 }
1150
1151 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
1152 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
1153
1154 return ret;
1155
1156 eirq:
1157 tmio_mmc_host_remove(host);
1158 edisclk:
1159 renesas_sdhi_clk_disable(host);
1160 efree:
1161 tmio_mmc_host_free(host);
1162
1163 return ret;
1164 }
1165 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
1166
1167 int renesas_sdhi_remove(struct platform_device *pdev)
1168 {
1169 struct tmio_mmc_host *host = platform_get_drvdata(pdev);
1170
1171 tmio_mmc_host_remove(host);
1172 renesas_sdhi_clk_disable(host);
1173 tmio_mmc_host_free(host);
1174
1175 return 0;
1176 }
1177 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
1178
1179 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support