drivers/pci/controller/pci-xgene.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /**
   3  * APM X-Gene PCIe Driver
   4  *
   5  * Copyright (c) 2014 Applied Micro Circuits Corporation.
   6  *
   7  * Author: Tanmay Inamdar <tinamdar@apm.com>.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/io.h>
  12 #include <linux/jiffies.h>
  13 #include <linux/memblock.h>
  14 #include <linux/init.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/of_pci.h>
  19 #include <linux/pci.h>
  20 #include <linux/pci-acpi.h>
  21 #include <linux/pci-ecam.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/slab.h>
  24
  25 #include "../pci.h"
  26
  27 #define PCIECORE_CTLANDSTATUS           0x50
  28 #define PIM1_1L                         0x80
  29 #define IBAR2                           0x98
  30 #define IR2MSK                          0x9c
  31 #define PIM2_1L                         0xa0
  32 #define IBAR3L                          0xb4
  33 #define IR3MSKL                         0xbc
  34 #define PIM3_1L                         0xc4
  35 #define OMR1BARL                        0x100
  36 #define OMR2BARL                        0x118
  37 #define OMR3BARL                        0x130
  38 #define CFGBARL                         0x154
  39 #define CFGBARH                         0x158
  40 #define CFGCTL                          0x15c
  41 #define RTDID                           0x160
  42 #define BRIDGE_CFG_0                    0x2000
  43 #define BRIDGE_CFG_4                    0x2010
  44 #define BRIDGE_STATUS_0                 0x2600
  45
  46 #define LINK_UP_MASK                    0x00000100
  47 #define AXI_EP_CFG_ACCESS               0x10000
  48 #define EN_COHERENCY                    0xF0000000
  49 #define EN_REG                          0x00000001
  50 #define OB_LO_IO                        0x00000002
  51 #define XGENE_PCIE_VENDORID             0x10E8
  52 #define XGENE_PCIE_DEVICEID             0xE004
  53 #define SZ_1T                           (SZ_1G*1024ULL)
  54 #define PIPE_PHY_RATE_RD(src)           ((0xc000 & (u32)(src)) >> 0xe)
  55
  56 #define XGENE_V1_PCI_EXP_CAP            0x40
  57
  58 /* PCIe IP version */
  59 #define XGENE_PCIE_IP_VER_UNKN          0
  60 #define XGENE_PCIE_IP_VER_1             1
  61 #define XGENE_PCIE_IP_VER_2             2
  62
  63 #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
  64 struct xgene_pcie_port {
  65         struct device_node      *node;
  66         struct device           *dev;
  67         struct clk              *clk;
  68         void __iomem            *csr_base;
  69         void __iomem            *cfg_base;
  70         unsigned long           cfg_addr;
  71         bool                    link_up;
  72         u32                     version;
  73 };
  74
  75 static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg)
  76 {
  77         return readl(port->csr_base + reg);
  78 }
  79
  80 static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val)
  81 {
  82         writel(val, port->csr_base + reg);
  83 }
  84
  85 static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
  86 {
  87         return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
  88 }
  89
  90 static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus)
  91 {
  92         struct pci_config_window *cfg;
  93
  94         if (acpi_disabled)
  95                 return (struct xgene_pcie_port *)(bus->sysdata);
  96
  97         cfg = bus->sysdata;
  98         return (struct xgene_pcie_port *)(cfg->priv);
  99 }
 100
 101 /*
 102  * When the address bit [17:16] is 2'b01, the Configuration access will be
 103  * treated as Type 1 and it will be forwarded to external PCIe device.
 104  */
 105 static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
 106 {
 107         struct xgene_pcie_port *port = pcie_bus_to_port(bus);
 108
 109         if (bus->number >= (bus->primary + 1))
 110                 return port->cfg_base + AXI_EP_CFG_ACCESS;
 111
 112         return port->cfg_base;
 113 }
 114
 115 /*
 116  * For Configuration request, RTDID register is used as Bus Number,
 117  * Device Number and Function number of the header fields.
 118  */
 119 static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
 120 {
 121         struct xgene_pcie_port *port = pcie_bus_to_port(bus);
 122         unsigned int b, d, f;
 123         u32 rtdid_val = 0;
 124
 125         b = bus->number;
 126         d = PCI_SLOT(devfn);
 127         f = PCI_FUNC(devfn);
 128
 129         if (!pci_is_root_bus(bus))
 130                 rtdid_val = (b << 8) | (d << 3) | f;
 131
 132         xgene_pcie_writel(port, RTDID, rtdid_val);
 133         /* read the register back to ensure flush */
 134         xgene_pcie_readl(port, RTDID);
 135 }
 136
 137 /*
 138  * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
 139  * the translation from PCI bus to native BUS.  Entire DDR region
 140  * is mapped into PCIe space using these registers, so it can be
 141  * reached by DMA from EP devices.  The BAR0/1 of bridge should be
 142  * hidden during enumeration to avoid the sizing and resource allocation
 143  * by PCIe core.
 144  */
 145 static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
 146 {
 147         if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
 148                                      (offset == PCI_BASE_ADDRESS_1)))
 149                 return true;
 150
 151         return false;
 152 }
 153
 154 static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
 155                                         int offset)
 156 {
 157         if ((pci_is_root_bus(bus) && devfn != 0) ||
 158             xgene_pcie_hide_rc_bars(bus, offset))
 159                 return NULL;
 160
 161         xgene_pcie_set_rtdid_reg(bus, devfn);
 162         return xgene_pcie_get_cfg_base(bus) + offset;
 163 }
 164
 165 static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
 166                                     int where, int size, u32 *val)
 167 {
 168         struct xgene_pcie_port *port = pcie_bus_to_port(bus);
 169
 170         if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
 171             PCIBIOS_SUCCESSFUL)
 172                 return PCIBIOS_DEVICE_NOT_FOUND;
 173
 174         /*
 175          * The v1 controller has a bug in its Configuration Request
 176          * Retry Status (CRS) logic: when CRS is enabled and we read the
 177          * Vendor and Device ID of a non-existent device, the controller
 178          * fabricates return data of 0xFFFF0001 ("device exists but is not
 179          * ready") instead of 0xFFFFFFFF ("device does not exist").  This
 180          * causes the PCI core to retry the read until it times out.
 181          * Avoid this by not claiming to support CRS.
 182          */
 183         if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
 184             ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))
 185                 *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
 186
 187         if (size <= 2)
 188                 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
 189
 190         return PCIBIOS_SUCCESSFUL;
 191 }
 192 #endif
 193
 194 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
 195 static int xgene_get_csr_resource(struct acpi_device *adev,
 196                                   struct resource *res)
 197 {
 198         struct device *dev = &adev->dev;
 199         struct resource_entry *entry;
 200         struct list_head list;
 201         unsigned long flags;
 202         int ret;
 203
 204         INIT_LIST_HEAD(&list);
 205         flags = IORESOURCE_MEM;
 206         ret = acpi_dev_get_resources(adev, &list,
 207                                      acpi_dev_filter_resource_type_cb,
 208                                      (void *) flags);
 209         if (ret < 0) {
 210                 dev_err(dev, "failed to parse _CRS method, error code %d\n",
 211                         ret);
 212                 return ret;
 213         }
 214
 215         if (ret == 0) {
 216                 dev_err(dev, "no IO and memory resources present in _CRS\n");
 217                 return -EINVAL;
 218         }
 219
 220         entry = list_first_entry(&list, struct resource_entry, node);
 221         *res = *entry->res;
 222         acpi_dev_free_resource_list(&list);
 223         return 0;
 224 }
 225
 226 static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)
 227 {
 228         struct device *dev = cfg->parent;
 229         struct acpi_device *adev = to_acpi_device(dev);
 230         struct xgene_pcie_port *port;
 231         struct resource csr;
 232         int ret;
 233
 234         port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
 235         if (!port)
 236                 return -ENOMEM;
 237
 238         ret = xgene_get_csr_resource(adev, &csr);
 239         if (ret) {
 240                 dev_err(dev, "can't get CSR resource\n");
 241                 return ret;
 242         }
 243         port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);
 244         if (IS_ERR(port->csr_base))
 245                 return PTR_ERR(port->csr_base);
 246
 247         port->cfg_base = cfg->win;
 248         port->version = ipversion;
 249
 250         cfg->priv = port;
 251         return 0;
 252 }
 253
 254 static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
 255 {
 256         return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1);
 257 }
 258
 259 const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
 260         .init           = xgene_v1_pcie_ecam_init,
 261         .pci_ops        = {
 262                 .map_bus        = xgene_pcie_map_bus,
 263                 .read           = xgene_pcie_config_read32,
 264                 .write          = pci_generic_config_write,
 265         }
 266 };
 267
 268 static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg)
 269 {
 270         return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2);
 271 }
 272
 273 const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {
 274         .init           = xgene_v2_pcie_ecam_init,
 275         .pci_ops        = {
 276                 .map_bus        = xgene_pcie_map_bus,
 277                 .read           = xgene_pcie_config_read32,
 278                 .write          = pci_generic_config_write,
 279         }
 280 };
 281 #endif
 282
 283 #if defined(CONFIG_PCI_XGENE)
 284 static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
 285                                   u32 flags, u64 size)
 286 {
 287         u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
 288         u32 val32 = 0;
 289         u32 val;
 290
 291         val32 = xgene_pcie_readl(port, addr);
 292         val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
 293         xgene_pcie_writel(port, addr, val);
 294
 295         val32 = xgene_pcie_readl(port, addr + 0x04);
 296         val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
 297         xgene_pcie_writel(port, addr + 0x04, val);
 298
 299         val32 = xgene_pcie_readl(port, addr + 0x04);
 300         val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
 301         xgene_pcie_writel(port, addr + 0x04, val);
 302
 303         val32 = xgene_pcie_readl(port, addr + 0x08);
 304         val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
 305         xgene_pcie_writel(port, addr + 0x08, val);
 306
 307         return mask;
 308 }
 309
 310 static void xgene_pcie_linkup(struct xgene_pcie_port *port,
 311                               u32 *lanes, u32 *speed)
 312 {
 313         u32 val32;
 314
 315         port->link_up = false;
 316         val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);
 317         if (val32 & LINK_UP_MASK) {
 318                 port->link_up = true;
 319                 *speed = PIPE_PHY_RATE_RD(val32);
 320                 val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);
 321                 *lanes = val32 >> 26;
 322         }
 323 }
 324
 325 static int xgene_pcie_init_port(struct xgene_pcie_port *port)
 326 {
 327         struct device *dev = port->dev;
 328         int rc;
 329
 330         port->clk = clk_get(dev, NULL);
 331         if (IS_ERR(port->clk)) {
 332                 dev_err(dev, "clock not available\n");
 333                 return -ENODEV;
 334         }
 335
 336         rc = clk_prepare_enable(port->clk);
 337         if (rc) {
 338                 dev_err(dev, "clock enable failed\n");
 339                 return rc;
 340         }
 341
 342         return 0;
 343 }
 344
 345 static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
 346                               struct platform_device *pdev)
 347 {
 348         struct device *dev = port->dev;
 349         struct resource *res;
 350
 351         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
 352         port->csr_base = devm_pci_remap_cfg_resource(dev, res);
 353         if (IS_ERR(port->csr_base))
 354                 return PTR_ERR(port->csr_base);
 355
 356         port->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
 357         if (IS_ERR(port->cfg_base))
 358                 return PTR_ERR(port->cfg_base);
 359         port->cfg_addr = res->start;
 360
 361         return 0;
 362 }
 363
 364 static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
 365                                     struct resource *res, u32 offset,
 366                                     u64 cpu_addr, u64 pci_addr)
 367 {
 368         struct device *dev = port->dev;
 369         resource_size_t size = resource_size(res);
 370         u64 restype = resource_type(res);
 371         u64 mask = 0;
 372         u32 min_size;
 373         u32 flag = EN_REG;
 374
 375         if (restype == IORESOURCE_MEM) {
 376                 min_size = SZ_128M;
 377         } else {
 378                 min_size = 128;
 379                 flag |= OB_LO_IO;
 380         }
 381
 382         if (size >= min_size)
 383                 mask = ~(size - 1) | flag;
 384         else
 385                 dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",
 386                          (u64)size, min_size);
 387
 388         xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));
 389         xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));
 390         xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));
 391         xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));
 392         xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));
 393         xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
 394 }
 395
 396 static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)
 397 {
 398         u64 addr = port->cfg_addr;
 399
 400         xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));
 401         xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));
 402         xgene_pcie_writel(port, CFGCTL, EN_REG);
 403 }
 404
 405 static int xgene_pcie_map_ranges(struct xgene_pcie_port *port)
 406 {
 407         struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
 408         struct resource_entry *window;
 409         struct device *dev = port->dev;
 410
 411         resource_list_for_each_entry(window, &bridge->windows) {
 412                 struct resource *res = window->res;
 413                 u64 restype = resource_type(res);
 414
 415                 dev_dbg(dev, "%pR\n", res);
 416
 417                 switch (restype) {
 418                 case IORESOURCE_IO:
 419                         xgene_pcie_setup_ob_reg(port, res, OMR3BARL,
 420                                                 pci_pio_to_address(res->start),
 421                                                 res->start - window->offset);
 422                         break;
 423                 case IORESOURCE_MEM:
 424                         if (res->flags & IORESOURCE_PREFETCH)
 425                                 xgene_pcie_setup_ob_reg(port, res, OMR2BARL,
 426                                                         res->start,
 427                                                         res->start -
 428                                                         window->offset);
 429                         else
 430                                 xgene_pcie_setup_ob_reg(port, res, OMR1BARL,
 431                                                         res->start,
 432                                                         res->start -
 433                                                         window->offset);
 434                         break;
 435                 case IORESOURCE_BUS:
 436                         break;
 437                 default:
 438                         dev_err(dev, "invalid resource %pR\n", res);
 439                         return -EINVAL;
 440                 }
 441         }
 442         xgene_pcie_setup_cfg_reg(port);
 443         return 0;
 444 }
 445
 446 static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg,
 447                                   u64 pim, u64 size)
 448 {
 449         xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
 450         xgene_pcie_writel(port, pim_reg + 0x04,
 451                           upper_32_bits(pim) | EN_COHERENCY);
 452         xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));
 453         xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));
 454 }
 455
 456 /*
 457  * X-Gene PCIe support maximum 3 inbound memory regions
 458  * This function helps to select a region based on size of region
 459  */
 460 static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
 461 {
 462         if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
 463                 *ib_reg_mask |= (1 << 1);
 464                 return 1;
 465         }
 466
 467         if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
 468                 *ib_reg_mask |= (1 << 0);
 469                 return 0;
 470         }
 471
 472         if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
 473                 *ib_reg_mask |= (1 << 2);
 474                 return 2;
 475         }
 476
 477         return -EINVAL;
 478 }
 479
 480 static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
 481                                     struct resource_entry *entry,
 482                                     u8 *ib_reg_mask)
 483 {
 484         void __iomem *cfg_base = port->cfg_base;
 485         struct device *dev = port->dev;
 486         void *bar_addr;
 487         u32 pim_reg;
 488         u64 cpu_addr = entry->res->start;
 489         u64 pci_addr = cpu_addr - entry->offset;
 490         u64 size = resource_size(entry->res);
 491         u64 mask = ~(size - 1) | EN_REG;
 492         u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
 493         u32 bar_low;
 494         int region;
 495
 496         region = xgene_pcie_select_ib_reg(ib_reg_mask, size);
 497         if (region < 0) {
 498                 dev_warn(dev, "invalid pcie dma-range config\n");
 499                 return;
 500         }
 501
 502         if (entry->res->flags & IORESOURCE_PREFETCH)
 503                 flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
 504
 505         bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
 506         switch (region) {
 507         case 0:
 508                 xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size);
 509                 bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
 510                 writel(bar_low, bar_addr);
 511                 writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
 512                 pim_reg = PIM1_1L;
 513                 break;
 514         case 1:
 515                 xgene_pcie_writel(port, IBAR2, bar_low);
 516                 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));
 517                 pim_reg = PIM2_1L;
 518                 break;
 519         case 2:
 520                 xgene_pcie_writel(port, IBAR3L, bar_low);
 521                 xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));
 522                 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));
 523                 xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));
 524                 pim_reg = PIM3_1L;
 525                 break;
 526         }
 527
 528         xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
 529 }
 530
 531 static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
 532 {
 533         struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
 534         struct resource_entry *entry;
 535         u8 ib_reg_mask = 0;
 536
 537         resource_list_for_each_entry(entry, &bridge->dma_ranges)
 538                 xgene_pcie_setup_ib_reg(port, entry, &ib_reg_mask);
 539
 540         return 0;
 541 }
 542
 543 /* clear BAR configuration which was done by firmware */
 544 static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
 545 {
 546         int i;
 547
 548         for (i = PIM1_1L; i <= CFGCTL; i += 4)
 549                 xgene_pcie_writel(port, i, 0);
 550 }
 551
 552 static int xgene_pcie_setup(struct xgene_pcie_port *port)
 553 {
 554         struct device *dev = port->dev;
 555         u32 val, lanes = 0, speed = 0;
 556         int ret;
 557
 558         xgene_pcie_clear_config(port);
 559
 560         /* setup the vendor and device IDs correctly */
 561         val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
 562         xgene_pcie_writel(port, BRIDGE_CFG_0, val);
 563
 564         ret = xgene_pcie_map_ranges(port);
 565         if (ret)
 566                 return ret;
 567
 568         ret = xgene_pcie_parse_map_dma_ranges(port);
 569         if (ret)
 570                 return ret;
 571
 572         xgene_pcie_linkup(port, &lanes, &speed);
 573         if (!port->link_up)
 574                 dev_info(dev, "(rc) link down\n");
 575         else
 576                 dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1);
 577         return 0;
 578 }
 579
 580 static struct pci_ops xgene_pcie_ops = {
 581         .map_bus = xgene_pcie_map_bus,
 582         .read = xgene_pcie_config_read32,
 583         .write = pci_generic_config_write32,
 584 };
 585
 586 static int xgene_pcie_probe(struct platform_device *pdev)
 587 {
 588         struct device *dev = &pdev->dev;
 589         struct device_node *dn = dev->of_node;
 590         struct xgene_pcie_port *port;
 591         struct pci_host_bridge *bridge;
 592         int ret;
 593
 594         bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
 595         if (!bridge)
 596                 return -ENOMEM;
 597
 598         port = pci_host_bridge_priv(bridge);
 599
 600         port->node = of_node_get(dn);
 601         port->dev = dev;
 602
 603         port->version = XGENE_PCIE_IP_VER_UNKN;
 604         if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
 605                 port->version = XGENE_PCIE_IP_VER_1;
 606
 607         ret = xgene_pcie_map_reg(port, pdev);
 608         if (ret)
 609                 return ret;
 610
 611         ret = xgene_pcie_init_port(port);
 612         if (ret)
 613                 return ret;
 614
 615         ret = xgene_pcie_setup(port);
 616         if (ret)
 617                 return ret;
 618
 619         bridge->sysdata = port;
 620         bridge->ops = &xgene_pcie_ops;
 621
 622         return pci_host_probe(bridge);
 623 }
 624
 625 static const struct of_device_id xgene_pcie_match_table[] = {
 626         {.compatible = "apm,xgene-pcie",},
 627         {},
 628 };
 629
 630 static struct platform_driver xgene_pcie_driver = {
 631         .driver = {
 632                 .name = "xgene-pcie",
 633                 .of_match_table = of_match_ptr(xgene_pcie_match_table),
 634                 .suppress_bind_attrs = true,
 635         },
 636         .probe = xgene_pcie_probe,
 637 };
 638 builtin_platform_driver(xgene_pcie_driver);
 639 #endif