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Merge tag 'regmap-fix-v5.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / pinctrl / qcom / pinctrl-sc7280.c
blob8daccd530285400fac736ccf0735b45fa6881491
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9 #include <linux/pinctrl/pinctrl.h>
10
11 #include "pinctrl-msm.h"
12
13 #define FUNCTION(fname) \
14 [msm_mux_##fname] = { \
15 .name = #fname, \
16 .groups = fname##_groups, \
17 .ngroups = ARRAY_SIZE(fname##_groups), \
18 }
19
20 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
21 { \
22 .name = "gpio" #id, \
23 .pins = gpio##id##_pins, \
24 .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
25 .funcs = (int[]){ \
26 msm_mux_gpio, /* gpio mode */ \
27 msm_mux_##f1, \
28 msm_mux_##f2, \
29 msm_mux_##f3, \
30 msm_mux_##f4, \
31 msm_mux_##f5, \
32 msm_mux_##f6, \
33 msm_mux_##f7, \
34 msm_mux_##f8, \
35 msm_mux_##f9 \
36 }, \
37 .nfuncs = 10, \
38 .ctl_reg = 0x1000 * id, \
39 .io_reg = 0x1000 * id + 0x4, \
40 .intr_cfg_reg = 0x1000 * id + 0x8, \
41 .intr_status_reg = 0x1000 * id + 0xc, \
42 .intr_target_reg = 0x1000 * id + 0x8, \
43 .mux_bit = 2, \
44 .pull_bit = 0, \
45 .drv_bit = 6, \
46 .oe_bit = 9, \
47 .in_bit = 0, \
48 .out_bit = 1, \
49 .intr_enable_bit = 0, \
50 .intr_status_bit = 0, \
51 .intr_target_bit = 5, \
52 .intr_target_kpss_val = 3, \
53 .intr_raw_status_bit = 4, \
54 .intr_polarity_bit = 1, \
55 .intr_detection_bit = 2, \
56 .intr_detection_width = 2, \
57 }
58
59 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
60 { \
61 .name = #pg_name, \
62 .pins = pg_name##_pins, \
63 .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
64 .ctl_reg = ctl, \
65 .io_reg = 0, \
66 .intr_cfg_reg = 0, \
67 .intr_status_reg = 0, \
68 .intr_target_reg = 0, \
69 .mux_bit = -1, \
70 .pull_bit = pull, \
71 .drv_bit = drv, \
72 .oe_bit = -1, \
73 .in_bit = -1, \
74 .out_bit = -1, \
75 .intr_enable_bit = -1, \
76 .intr_status_bit = -1, \
77 .intr_target_bit = -1, \
78 .intr_raw_status_bit = -1, \
79 .intr_polarity_bit = -1, \
80 .intr_detection_bit = -1, \
81 .intr_detection_width = -1, \
82 }
83
84 #define UFS_RESET(pg_name, offset) \
85 { \
86 .name = #pg_name, \
87 .pins = pg_name##_pins, \
88 .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
89 .ctl_reg = offset, \
90 .io_reg = offset + 0x4, \
91 .intr_cfg_reg = 0, \
92 .intr_status_reg = 0, \
93 .intr_target_reg = 0, \
94 .mux_bit = -1, \
95 .pull_bit = 3, \
96 .drv_bit = 0, \
97 .oe_bit = -1, \
98 .in_bit = -1, \
99 .out_bit = 0, \
100 .intr_enable_bit = -1, \
101 .intr_status_bit = -1, \
102 .intr_target_bit = -1, \
103 .intr_raw_status_bit = -1, \
104 .intr_polarity_bit = -1, \
105 .intr_detection_bit = -1, \
106 .intr_detection_width = -1, \
107 }
108
109 static const struct pinctrl_pin_desc sc7280_pins[] = {
110 PINCTRL_PIN(0, "GPIO_0"),
111 PINCTRL_PIN(1, "GPIO_1"),
112 PINCTRL_PIN(2, "GPIO_2"),
113 PINCTRL_PIN(3, "GPIO_3"),
114 PINCTRL_PIN(4, "GPIO_4"),
115 PINCTRL_PIN(5, "GPIO_5"),
116 PINCTRL_PIN(6, "GPIO_6"),
117 PINCTRL_PIN(7, "GPIO_7"),
118 PINCTRL_PIN(8, "GPIO_8"),
119 PINCTRL_PIN(9, "GPIO_9"),
120 PINCTRL_PIN(10, "GPIO_10"),
121 PINCTRL_PIN(11, "GPIO_11"),
122 PINCTRL_PIN(12, "GPIO_12"),
123 PINCTRL_PIN(13, "GPIO_13"),
124 PINCTRL_PIN(14, "GPIO_14"),
125 PINCTRL_PIN(15, "GPIO_15"),
126 PINCTRL_PIN(16, "GPIO_16"),
127 PINCTRL_PIN(17, "GPIO_17"),
128 PINCTRL_PIN(18, "GPIO_18"),
129 PINCTRL_PIN(19, "GPIO_19"),
130 PINCTRL_PIN(20, "GPIO_20"),
131 PINCTRL_PIN(21, "GPIO_21"),
132 PINCTRL_PIN(22, "GPIO_22"),
133 PINCTRL_PIN(23, "GPIO_23"),
134 PINCTRL_PIN(24, "GPIO_24"),
135 PINCTRL_PIN(25, "GPIO_25"),
136 PINCTRL_PIN(26, "GPIO_26"),
137 PINCTRL_PIN(27, "GPIO_27"),
138 PINCTRL_PIN(28, "GPIO_28"),
139 PINCTRL_PIN(29, "GPIO_29"),
140 PINCTRL_PIN(30, "GPIO_30"),
141 PINCTRL_PIN(31, "GPIO_31"),
142 PINCTRL_PIN(32, "GPIO_32"),
143 PINCTRL_PIN(33, "GPIO_33"),
144 PINCTRL_PIN(34, "GPIO_34"),
145 PINCTRL_PIN(35, "GPIO_35"),
146 PINCTRL_PIN(36, "GPIO_36"),
147 PINCTRL_PIN(37, "GPIO_37"),
148 PINCTRL_PIN(38, "GPIO_38"),
149 PINCTRL_PIN(39, "GPIO_39"),
150 PINCTRL_PIN(40, "GPIO_40"),
151 PINCTRL_PIN(41, "GPIO_41"),
152 PINCTRL_PIN(42, "GPIO_42"),
153 PINCTRL_PIN(43, "GPIO_43"),
154 PINCTRL_PIN(44, "GPIO_44"),
155 PINCTRL_PIN(45, "GPIO_45"),
156 PINCTRL_PIN(46, "GPIO_46"),
157 PINCTRL_PIN(47, "GPIO_47"),
158 PINCTRL_PIN(48, "GPIO_48"),
159 PINCTRL_PIN(49, "GPIO_49"),
160 PINCTRL_PIN(50, "GPIO_50"),
161 PINCTRL_PIN(51, "GPIO_51"),
162 PINCTRL_PIN(52, "GPIO_52"),
163 PINCTRL_PIN(53, "GPIO_53"),
164 PINCTRL_PIN(54, "GPIO_54"),
165 PINCTRL_PIN(55, "GPIO_55"),
166 PINCTRL_PIN(56, "GPIO_56"),
167 PINCTRL_PIN(57, "GPIO_57"),
168 PINCTRL_PIN(58, "GPIO_58"),
169 PINCTRL_PIN(59, "GPIO_59"),
170 PINCTRL_PIN(60, "GPIO_60"),
171 PINCTRL_PIN(61, "GPIO_61"),
172 PINCTRL_PIN(62, "GPIO_62"),
173 PINCTRL_PIN(63, "GPIO_63"),
174 PINCTRL_PIN(64, "GPIO_64"),
175 PINCTRL_PIN(65, "GPIO_65"),
176 PINCTRL_PIN(66, "GPIO_66"),
177 PINCTRL_PIN(67, "GPIO_67"),
178 PINCTRL_PIN(68, "GPIO_68"),
179 PINCTRL_PIN(69, "GPIO_69"),
180 PINCTRL_PIN(70, "GPIO_70"),
181 PINCTRL_PIN(71, "GPIO_71"),
182 PINCTRL_PIN(72, "GPIO_72"),
183 PINCTRL_PIN(73, "GPIO_73"),
184 PINCTRL_PIN(74, "GPIO_74"),
185 PINCTRL_PIN(75, "GPIO_75"),
186 PINCTRL_PIN(76, "GPIO_76"),
187 PINCTRL_PIN(77, "GPIO_77"),
188 PINCTRL_PIN(78, "GPIO_78"),
189 PINCTRL_PIN(79, "GPIO_79"),
190 PINCTRL_PIN(80, "GPIO_80"),
191 PINCTRL_PIN(81, "GPIO_81"),
192 PINCTRL_PIN(82, "GPIO_82"),
193 PINCTRL_PIN(83, "GPIO_83"),
194 PINCTRL_PIN(84, "GPIO_84"),
195 PINCTRL_PIN(85, "GPIO_85"),
196 PINCTRL_PIN(86, "GPIO_86"),
197 PINCTRL_PIN(87, "GPIO_87"),
198 PINCTRL_PIN(88, "GPIO_88"),
199 PINCTRL_PIN(89, "GPIO_89"),
200 PINCTRL_PIN(90, "GPIO_90"),
201 PINCTRL_PIN(91, "GPIO_91"),
202 PINCTRL_PIN(92, "GPIO_92"),
203 PINCTRL_PIN(93, "GPIO_93"),
204 PINCTRL_PIN(94, "GPIO_94"),
205 PINCTRL_PIN(95, "GPIO_95"),
206 PINCTRL_PIN(96, "GPIO_96"),
207 PINCTRL_PIN(97, "GPIO_97"),
208 PINCTRL_PIN(98, "GPIO_98"),
209 PINCTRL_PIN(99, "GPIO_99"),
210 PINCTRL_PIN(100, "GPIO_100"),
211 PINCTRL_PIN(101, "GPIO_101"),
212 PINCTRL_PIN(102, "GPIO_102"),
213 PINCTRL_PIN(103, "GPIO_103"),
214 PINCTRL_PIN(104, "GPIO_104"),
215 PINCTRL_PIN(105, "GPIO_105"),
216 PINCTRL_PIN(106, "GPIO_106"),
217 PINCTRL_PIN(107, "GPIO_107"),
218 PINCTRL_PIN(108, "GPIO_108"),
219 PINCTRL_PIN(109, "GPIO_109"),
220 PINCTRL_PIN(110, "GPIO_110"),
221 PINCTRL_PIN(111, "GPIO_111"),
222 PINCTRL_PIN(112, "GPIO_112"),
223 PINCTRL_PIN(113, "GPIO_113"),
224 PINCTRL_PIN(114, "GPIO_114"),
225 PINCTRL_PIN(115, "GPIO_115"),
226 PINCTRL_PIN(116, "GPIO_116"),
227 PINCTRL_PIN(117, "GPIO_117"),
228 PINCTRL_PIN(118, "GPIO_118"),
229 PINCTRL_PIN(119, "GPIO_119"),
230 PINCTRL_PIN(120, "GPIO_120"),
231 PINCTRL_PIN(121, "GPIO_121"),
232 PINCTRL_PIN(122, "GPIO_122"),
233 PINCTRL_PIN(123, "GPIO_123"),
234 PINCTRL_PIN(124, "GPIO_124"),
235 PINCTRL_PIN(125, "GPIO_125"),
236 PINCTRL_PIN(126, "GPIO_126"),
237 PINCTRL_PIN(127, "GPIO_127"),
238 PINCTRL_PIN(128, "GPIO_128"),
239 PINCTRL_PIN(129, "GPIO_129"),
240 PINCTRL_PIN(130, "GPIO_130"),
241 PINCTRL_PIN(131, "GPIO_131"),
242 PINCTRL_PIN(132, "GPIO_132"),
243 PINCTRL_PIN(133, "GPIO_133"),
244 PINCTRL_PIN(134, "GPIO_134"),
245 PINCTRL_PIN(135, "GPIO_135"),
246 PINCTRL_PIN(136, "GPIO_136"),
247 PINCTRL_PIN(137, "GPIO_137"),
248 PINCTRL_PIN(138, "GPIO_138"),
249 PINCTRL_PIN(139, "GPIO_139"),
250 PINCTRL_PIN(140, "GPIO_140"),
251 PINCTRL_PIN(141, "GPIO_141"),
252 PINCTRL_PIN(142, "GPIO_142"),
253 PINCTRL_PIN(143, "GPIO_143"),
254 PINCTRL_PIN(144, "GPIO_144"),
255 PINCTRL_PIN(145, "GPIO_145"),
256 PINCTRL_PIN(146, "GPIO_146"),
257 PINCTRL_PIN(147, "GPIO_147"),
258 PINCTRL_PIN(148, "GPIO_148"),
259 PINCTRL_PIN(149, "GPIO_149"),
260 PINCTRL_PIN(150, "GPIO_150"),
261 PINCTRL_PIN(151, "GPIO_151"),
262 PINCTRL_PIN(152, "GPIO_152"),
263 PINCTRL_PIN(153, "GPIO_153"),
264 PINCTRL_PIN(154, "GPIO_154"),
265 PINCTRL_PIN(155, "GPIO_155"),
266 PINCTRL_PIN(156, "GPIO_156"),
267 PINCTRL_PIN(157, "GPIO_157"),
268 PINCTRL_PIN(158, "GPIO_158"),
269 PINCTRL_PIN(159, "GPIO_159"),
270 PINCTRL_PIN(160, "GPIO_160"),
271 PINCTRL_PIN(161, "GPIO_161"),
272 PINCTRL_PIN(162, "GPIO_162"),
273 PINCTRL_PIN(163, "GPIO_163"),
274 PINCTRL_PIN(164, "GPIO_164"),
275 PINCTRL_PIN(165, "GPIO_165"),
276 PINCTRL_PIN(166, "GPIO_166"),
277 PINCTRL_PIN(167, "GPIO_167"),
278 PINCTRL_PIN(168, "GPIO_168"),
279 PINCTRL_PIN(169, "GPIO_169"),
280 PINCTRL_PIN(170, "GPIO_170"),
281 PINCTRL_PIN(171, "GPIO_171"),
282 PINCTRL_PIN(172, "GPIO_172"),
283 PINCTRL_PIN(173, "GPIO_173"),
284 PINCTRL_PIN(174, "GPIO_174"),
285 PINCTRL_PIN(175, "UFS_RESET"),
286 PINCTRL_PIN(176, "SDC1_RCLK"),
287 PINCTRL_PIN(177, "SDC1_CLK"),
288 PINCTRL_PIN(178, "SDC1_CMD"),
289 PINCTRL_PIN(179, "SDC1_DATA"),
290 PINCTRL_PIN(180, "SDC2_CLK"),
291 PINCTRL_PIN(181, "SDC2_CMD"),
292 PINCTRL_PIN(182, "SDC2_DATA"),
293 };
294
295 #define DECLARE_MSM_GPIO_PINS(pin) \
296 static const unsigned int gpio##pin##_pins[] = { pin }
297 DECLARE_MSM_GPIO_PINS(0);
298 DECLARE_MSM_GPIO_PINS(1);
299 DECLARE_MSM_GPIO_PINS(2);
300 DECLARE_MSM_GPIO_PINS(3);
301 DECLARE_MSM_GPIO_PINS(4);
302 DECLARE_MSM_GPIO_PINS(5);
303 DECLARE_MSM_GPIO_PINS(6);
304 DECLARE_MSM_GPIO_PINS(7);
305 DECLARE_MSM_GPIO_PINS(8);
306 DECLARE_MSM_GPIO_PINS(9);
307 DECLARE_MSM_GPIO_PINS(10);
308 DECLARE_MSM_GPIO_PINS(11);
309 DECLARE_MSM_GPIO_PINS(12);
310 DECLARE_MSM_GPIO_PINS(13);
311 DECLARE_MSM_GPIO_PINS(14);
312 DECLARE_MSM_GPIO_PINS(15);
313 DECLARE_MSM_GPIO_PINS(16);
314 DECLARE_MSM_GPIO_PINS(17);
315 DECLARE_MSM_GPIO_PINS(18);
316 DECLARE_MSM_GPIO_PINS(19);
317 DECLARE_MSM_GPIO_PINS(20);
318 DECLARE_MSM_GPIO_PINS(21);
319 DECLARE_MSM_GPIO_PINS(22);
320 DECLARE_MSM_GPIO_PINS(23);
321 DECLARE_MSM_GPIO_PINS(24);
322 DECLARE_MSM_GPIO_PINS(25);
323 DECLARE_MSM_GPIO_PINS(26);
324 DECLARE_MSM_GPIO_PINS(27);
325 DECLARE_MSM_GPIO_PINS(28);
326 DECLARE_MSM_GPIO_PINS(29);
327 DECLARE_MSM_GPIO_PINS(30);
328 DECLARE_MSM_GPIO_PINS(31);
329 DECLARE_MSM_GPIO_PINS(32);
330 DECLARE_MSM_GPIO_PINS(33);
331 DECLARE_MSM_GPIO_PINS(34);
332 DECLARE_MSM_GPIO_PINS(35);
333 DECLARE_MSM_GPIO_PINS(36);
334 DECLARE_MSM_GPIO_PINS(37);
335 DECLARE_MSM_GPIO_PINS(38);
336 DECLARE_MSM_GPIO_PINS(39);
337 DECLARE_MSM_GPIO_PINS(40);
338 DECLARE_MSM_GPIO_PINS(41);
339 DECLARE_MSM_GPIO_PINS(42);
340 DECLARE_MSM_GPIO_PINS(43);
341 DECLARE_MSM_GPIO_PINS(44);
342 DECLARE_MSM_GPIO_PINS(45);
343 DECLARE_MSM_GPIO_PINS(46);
344 DECLARE_MSM_GPIO_PINS(47);
345 DECLARE_MSM_GPIO_PINS(48);
346 DECLARE_MSM_GPIO_PINS(49);
347 DECLARE_MSM_GPIO_PINS(50);
348 DECLARE_MSM_GPIO_PINS(51);
349 DECLARE_MSM_GPIO_PINS(52);
350 DECLARE_MSM_GPIO_PINS(53);
351 DECLARE_MSM_GPIO_PINS(54);
352 DECLARE_MSM_GPIO_PINS(55);
353 DECLARE_MSM_GPIO_PINS(56);
354 DECLARE_MSM_GPIO_PINS(57);
355 DECLARE_MSM_GPIO_PINS(58);
356 DECLARE_MSM_GPIO_PINS(59);
357 DECLARE_MSM_GPIO_PINS(60);
358 DECLARE_MSM_GPIO_PINS(61);
359 DECLARE_MSM_GPIO_PINS(62);
360 DECLARE_MSM_GPIO_PINS(63);
361 DECLARE_MSM_GPIO_PINS(64);
362 DECLARE_MSM_GPIO_PINS(65);
363 DECLARE_MSM_GPIO_PINS(66);
364 DECLARE_MSM_GPIO_PINS(67);
365 DECLARE_MSM_GPIO_PINS(68);
366 DECLARE_MSM_GPIO_PINS(69);
367 DECLARE_MSM_GPIO_PINS(70);
368 DECLARE_MSM_GPIO_PINS(71);
369 DECLARE_MSM_GPIO_PINS(72);
370 DECLARE_MSM_GPIO_PINS(73);
371 DECLARE_MSM_GPIO_PINS(74);
372 DECLARE_MSM_GPIO_PINS(75);
373 DECLARE_MSM_GPIO_PINS(76);
374 DECLARE_MSM_GPIO_PINS(77);
375 DECLARE_MSM_GPIO_PINS(78);
376 DECLARE_MSM_GPIO_PINS(79);
377 DECLARE_MSM_GPIO_PINS(80);
378 DECLARE_MSM_GPIO_PINS(81);
379 DECLARE_MSM_GPIO_PINS(82);
380 DECLARE_MSM_GPIO_PINS(83);
381 DECLARE_MSM_GPIO_PINS(84);
382 DECLARE_MSM_GPIO_PINS(85);
383 DECLARE_MSM_GPIO_PINS(86);
384 DECLARE_MSM_GPIO_PINS(87);
385 DECLARE_MSM_GPIO_PINS(88);
386 DECLARE_MSM_GPIO_PINS(89);
387 DECLARE_MSM_GPIO_PINS(90);
388 DECLARE_MSM_GPIO_PINS(91);
389 DECLARE_MSM_GPIO_PINS(92);
390 DECLARE_MSM_GPIO_PINS(93);
391 DECLARE_MSM_GPIO_PINS(94);
392 DECLARE_MSM_GPIO_PINS(95);
393 DECLARE_MSM_GPIO_PINS(96);
394 DECLARE_MSM_GPIO_PINS(97);
395 DECLARE_MSM_GPIO_PINS(98);
396 DECLARE_MSM_GPIO_PINS(99);
397 DECLARE_MSM_GPIO_PINS(100);
398 DECLARE_MSM_GPIO_PINS(101);
399 DECLARE_MSM_GPIO_PINS(102);
400 DECLARE_MSM_GPIO_PINS(103);
401 DECLARE_MSM_GPIO_PINS(104);
402 DECLARE_MSM_GPIO_PINS(105);
403 DECLARE_MSM_GPIO_PINS(106);
404 DECLARE_MSM_GPIO_PINS(107);
405 DECLARE_MSM_GPIO_PINS(108);
406 DECLARE_MSM_GPIO_PINS(109);
407 DECLARE_MSM_GPIO_PINS(110);
408 DECLARE_MSM_GPIO_PINS(111);
409 DECLARE_MSM_GPIO_PINS(112);
410 DECLARE_MSM_GPIO_PINS(113);
411 DECLARE_MSM_GPIO_PINS(114);
412 DECLARE_MSM_GPIO_PINS(115);
413 DECLARE_MSM_GPIO_PINS(116);
414 DECLARE_MSM_GPIO_PINS(117);
415 DECLARE_MSM_GPIO_PINS(118);
416 DECLARE_MSM_GPIO_PINS(119);
417 DECLARE_MSM_GPIO_PINS(120);
418 DECLARE_MSM_GPIO_PINS(121);
419 DECLARE_MSM_GPIO_PINS(122);
420 DECLARE_MSM_GPIO_PINS(123);
421 DECLARE_MSM_GPIO_PINS(124);
422 DECLARE_MSM_GPIO_PINS(125);
423 DECLARE_MSM_GPIO_PINS(126);
424 DECLARE_MSM_GPIO_PINS(127);
425 DECLARE_MSM_GPIO_PINS(128);
426 DECLARE_MSM_GPIO_PINS(129);
427 DECLARE_MSM_GPIO_PINS(130);
428 DECLARE_MSM_GPIO_PINS(131);
429 DECLARE_MSM_GPIO_PINS(132);
430 DECLARE_MSM_GPIO_PINS(133);
431 DECLARE_MSM_GPIO_PINS(134);
432 DECLARE_MSM_GPIO_PINS(135);
433 DECLARE_MSM_GPIO_PINS(136);
434 DECLARE_MSM_GPIO_PINS(137);
435 DECLARE_MSM_GPIO_PINS(138);
436 DECLARE_MSM_GPIO_PINS(139);
437 DECLARE_MSM_GPIO_PINS(140);
438 DECLARE_MSM_GPIO_PINS(141);
439 DECLARE_MSM_GPIO_PINS(142);
440 DECLARE_MSM_GPIO_PINS(143);
441 DECLARE_MSM_GPIO_PINS(144);
442 DECLARE_MSM_GPIO_PINS(145);
443 DECLARE_MSM_GPIO_PINS(146);
444 DECLARE_MSM_GPIO_PINS(147);
445 DECLARE_MSM_GPIO_PINS(148);
446 DECLARE_MSM_GPIO_PINS(149);
447 DECLARE_MSM_GPIO_PINS(150);
448 DECLARE_MSM_GPIO_PINS(151);
449 DECLARE_MSM_GPIO_PINS(152);
450 DECLARE_MSM_GPIO_PINS(153);
451 DECLARE_MSM_GPIO_PINS(154);
452 DECLARE_MSM_GPIO_PINS(155);
453 DECLARE_MSM_GPIO_PINS(156);
454 DECLARE_MSM_GPIO_PINS(157);
455 DECLARE_MSM_GPIO_PINS(158);
456 DECLARE_MSM_GPIO_PINS(159);
457 DECLARE_MSM_GPIO_PINS(160);
458 DECLARE_MSM_GPIO_PINS(161);
459 DECLARE_MSM_GPIO_PINS(162);
460 DECLARE_MSM_GPIO_PINS(163);
461 DECLARE_MSM_GPIO_PINS(164);
462 DECLARE_MSM_GPIO_PINS(165);
463 DECLARE_MSM_GPIO_PINS(166);
464 DECLARE_MSM_GPIO_PINS(167);
465 DECLARE_MSM_GPIO_PINS(168);
466 DECLARE_MSM_GPIO_PINS(169);
467 DECLARE_MSM_GPIO_PINS(170);
468 DECLARE_MSM_GPIO_PINS(171);
469 DECLARE_MSM_GPIO_PINS(172);
470 DECLARE_MSM_GPIO_PINS(173);
471 DECLARE_MSM_GPIO_PINS(174);
472
473 static const unsigned int ufs_reset_pins[] = { 175 };
474 static const unsigned int sdc1_rclk_pins[] = { 176 };
475 static const unsigned int sdc1_clk_pins[] = { 177 };
476 static const unsigned int sdc1_cmd_pins[] = { 178 };
477 static const unsigned int sdc1_data_pins[] = { 179 };
478 static const unsigned int sdc2_clk_pins[] = { 180 };
479 static const unsigned int sdc2_cmd_pins[] = { 181 };
480 static const unsigned int sdc2_data_pins[] = { 182 };
481
482 enum sc7280_functions {
483 msm_mux_atest_char,
484 msm_mux_atest_char0,
485 msm_mux_atest_char1,
486 msm_mux_atest_char2,
487 msm_mux_atest_char3,
488 msm_mux_atest_usb0,
489 msm_mux_atest_usb00,
490 msm_mux_atest_usb01,
491 msm_mux_atest_usb02,
492 msm_mux_atest_usb03,
493 msm_mux_atest_usb1,
494 msm_mux_atest_usb10,
495 msm_mux_atest_usb11,
496 msm_mux_atest_usb12,
497 msm_mux_atest_usb13,
498 msm_mux_audio_ref,
499 msm_mux_cam_mclk,
500 msm_mux_cci_async,
501 msm_mux_cci_i2c,
502 msm_mux_cci_timer0,
503 msm_mux_cci_timer1,
504 msm_mux_cci_timer2,
505 msm_mux_cci_timer3,
506 msm_mux_cci_timer4,
507 msm_mux_cmu_rng0,
508 msm_mux_cmu_rng1,
509 msm_mux_cmu_rng2,
510 msm_mux_cmu_rng3,
511 msm_mux_coex_uart1,
512 msm_mux_cri_trng,
513 msm_mux_cri_trng0,
514 msm_mux_cri_trng1,
515 msm_mux_dbg_out,
516 msm_mux_ddr_bist,
517 msm_mux_ddr_pxi0,
518 msm_mux_ddr_pxi1,
519 msm_mux_dp_hot,
520 msm_mux_dp_lcd,
521 msm_mux_edp_hot,
522 msm_mux_edp_lcd,
523 msm_mux_gcc_gp1,
524 msm_mux_gcc_gp2,
525 msm_mux_gcc_gp3,
526 msm_mux_gpio,
527 msm_mux_host2wlan_sol,
528 msm_mux_ibi_i3c,
529 msm_mux_jitter_bist,
530 msm_mux_lpass_slimbus,
531 msm_mux_mdp_vsync,
532 msm_mux_mdp_vsync0,
533 msm_mux_mdp_vsync1,
534 msm_mux_mdp_vsync2,
535 msm_mux_mdp_vsync3,
536 msm_mux_mdp_vsync4,
537 msm_mux_mdp_vsync5,
538 msm_mux_mi2s0_data0,
539 msm_mux_mi2s0_data1,
540 msm_mux_mi2s0_sck,
541 msm_mux_mi2s0_ws,
542 msm_mux_mi2s1_data0,
543 msm_mux_mi2s1_data1,
544 msm_mux_mi2s1_sck,
545 msm_mux_mi2s1_ws,
546 msm_mux_mi2s2_data0,
547 msm_mux_mi2s2_data1,
548 msm_mux_mi2s2_sck,
549 msm_mux_mi2s2_ws,
550 msm_mux_mss_grfc0,
551 msm_mux_mss_grfc1,
552 msm_mux_mss_grfc10,
553 msm_mux_mss_grfc11,
554 msm_mux_mss_grfc12,
555 msm_mux_mss_grfc2,
556 msm_mux_mss_grfc3,
557 msm_mux_mss_grfc4,
558 msm_mux_mss_grfc5,
559 msm_mux_mss_grfc6,
560 msm_mux_mss_grfc7,
561 msm_mux_mss_grfc8,
562 msm_mux_mss_grfc9,
563 msm_mux_nav_gpio0,
564 msm_mux_nav_gpio1,
565 msm_mux_nav_gpio2,
566 msm_mux_pa_indicator,
567 msm_mux_pcie0_clkreqn,
568 msm_mux_pcie1_clkreqn,
569 msm_mux_phase_flag,
570 msm_mux_pll_bist,
571 msm_mux_pll_bypassnl,
572 msm_mux_pll_clk,
573 msm_mux_pll_reset,
574 msm_mux_pri_mi2s,
575 msm_mux_prng_rosc,
576 msm_mux_qdss,
577 msm_mux_qdss_cti,
578 msm_mux_qlink0_enable,
579 msm_mux_qlink0_request,
580 msm_mux_qlink0_wmss,
581 msm_mux_qlink1_enable,
582 msm_mux_qlink1_request,
583 msm_mux_qlink1_wmss,
584 msm_mux_qspi_clk,
585 msm_mux_qspi_cs,
586 msm_mux_qspi_data,
587 msm_mux_qup00,
588 msm_mux_qup01,
589 msm_mux_qup02,
590 msm_mux_qup03,
591 msm_mux_qup04,
592 msm_mux_qup05,
593 msm_mux_qup06,
594 msm_mux_qup07,
595 msm_mux_qup10,
596 msm_mux_qup11,
597 msm_mux_qup12,
598 msm_mux_qup13,
599 msm_mux_qup14,
600 msm_mux_qup15,
601 msm_mux_qup16,
602 msm_mux_qup17,
603 msm_mux_sd_write,
604 msm_mux_sdc40,
605 msm_mux_sdc41,
606 msm_mux_sdc42,
607 msm_mux_sdc43,
608 msm_mux_sdc4_clk,
609 msm_mux_sdc4_cmd,
610 msm_mux_sec_mi2s,
611 msm_mux_tb_trig,
612 msm_mux_tgu_ch0,
613 msm_mux_tgu_ch1,
614 msm_mux_tsense_pwm1,
615 msm_mux_tsense_pwm2,
616 msm_mux_uim0_clk,
617 msm_mux_uim0_data,
618 msm_mux_uim0_present,
619 msm_mux_uim0_reset,
620 msm_mux_uim1_clk,
621 msm_mux_uim1_data,
622 msm_mux_uim1_present,
623 msm_mux_uim1_reset,
624 msm_mux_usb2phy_ac,
625 msm_mux_usb_phy,
626 msm_mux_vfr_0,
627 msm_mux_vfr_1,
628 msm_mux_vsense_trigger,
629 msm_mux__,
630 };
631
632 static const char * const gpio_groups[] = {
633 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
634 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
635 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
636 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
637 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
638 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
639 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
640 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
641 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
642 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
643 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
644 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
645 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
646 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
647 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
648 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
649 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
650 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
651 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
652 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
653 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
654 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
655 "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
656 "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
657 "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
658 "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
659 "gpio171", "gpio172", "gpio173", "gpio174",
660 };
661 static const char * const atest_char_groups[] = {
662 "gpio81",
663 };
664 static const char * const atest_char0_groups[] = {
665 "gpio77",
666 };
667 static const char * const atest_char1_groups[] = {
668 "gpio78",
669 };
670 static const char * const atest_char2_groups[] = {
671 "gpio79",
672 };
673 static const char * const atest_char3_groups[] = {
674 "gpio80",
675 };
676 static const char * const atest_usb0_groups[] = {
677 "gpio107",
678 };
679 static const char * const atest_usb00_groups[] = {
680 "gpio106",
681 };
682 static const char * const atest_usb01_groups[] = {
683 "gpio105",
684 };
685 static const char * const atest_usb02_groups[] = {
686 "gpio104",
687 };
688 static const char * const atest_usb03_groups[] = {
689 "gpio103",
690 };
691 static const char * const atest_usb1_groups[] = {
692 "gpio81",
693 };
694 static const char * const atest_usb10_groups[] = {
695 "gpio80",
696 };
697 static const char * const atest_usb11_groups[] = {
698 "gpio79",
699 };
700 static const char * const atest_usb12_groups[] = {
701 "gpio78",
702 };
703 static const char * const atest_usb13_groups[] = {
704 "gpio77",
705 };
706 static const char * const audio_ref_groups[] = {
707 "gpio105",
708 };
709 static const char * const cam_mclk_groups[] = {
710 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio93",
711 };
712 static const char * const cci_async_groups[] = {
713 "gpio78", "gpio79", "gpio93",
714 };
715 static const char * const cci_i2c_groups[] = {
716 "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75",
717 "gpio76",
718 };
719 static const char * const cci_timer0_groups[] = {
720 "gpio20",
721 };
722 static const char * const cci_timer1_groups[] = {
723 "gpio21",
724 };
725 static const char * const cci_timer2_groups[] = {
726 "gpio77",
727 };
728 static const char * const cci_timer3_groups[] = {
729 "gpio78",
730 };
731 static const char * const cci_timer4_groups[] = {
732 "gpio79",
733 };
734 static const char * const cmu_rng0_groups[] = {
735 "gpio120",
736 };
737 static const char * const cmu_rng1_groups[] = {
738 "gpio119",
739 };
740 static const char * const cmu_rng2_groups[] = {
741 "gpio118",
742 };
743 static const char * const cmu_rng3_groups[] = {
744 "gpio117",
745 };
746 static const char * const coex_uart1_groups[] = {
747 "gpio127", "gpio128",
748 };
749 static const char * const cri_trng_groups[] = {
750 "gpio124",
751 };
752 static const char * const cri_trng0_groups[] = {
753 "gpio121",
754 };
755 static const char * const cri_trng1_groups[] = {
756 "gpio122",
757 };
758 static const char * const dbg_out_groups[] = {
759 "gpio38",
760 };
761 static const char * const ddr_bist_groups[] = {
762 "gpio56", "gpio57", "gpio58", "gpio59",
763 };
764 static const char * const ddr_pxi0_groups[] = {
765 "gpio14", "gpio15",
766 };
767 static const char * const ddr_pxi1_groups[] = {
768 "gpio12", "gpio13",
769 };
770 static const char * const dp_hot_groups[] = {
771 "gpio47",
772 };
773 static const char * const dp_lcd_groups[] = {
774 "gpio81",
775 };
776 static const char * const edp_hot_groups[] = {
777 "gpio60",
778 };
779 static const char * const edp_lcd_groups[] = {
780 "gpio46",
781 };
782 static const char * const gcc_gp1_groups[] = {
783 "gpio76", "gpio105",
784 };
785 static const char * const gcc_gp2_groups[] = {
786 "gpio77", "gpio106",
787 };
788 static const char * const gcc_gp3_groups[] = {
789 "gpio78", "gpio107",
790 };
791 static const char * const host2wlan_sol_groups[] = {
792 "gpio26",
793 };
794 static const char * const ibi_i3c_groups[] = {
795 "gpio0", "gpio1", "gpio4", "gpio5", "gpio36", "gpio37",
796 };
797 static const char * const jitter_bist_groups[] = {
798 "gpio79",
799 };
800 static const char * const lpass_slimbus_groups[] = {
801 "gpio94", "gpio95",
802 };
803 static const char * const mdp_vsync_groups[] = {
804 "gpio14", "gpio16", "gpio79", "gpio80", "gpio81",
805 };
806 static const char * const mdp_vsync0_groups[] = {
807 "gpio80",
808 };
809 static const char * const mdp_vsync1_groups[] = {
810 "gpio80",
811 };
812 static const char * const mdp_vsync2_groups[] = {
813 "gpio81",
814 };
815 static const char * const mdp_vsync3_groups[] = {
816 "gpio81",
817 };
818 static const char * const mdp_vsync4_groups[] = {
819 "gpio80",
820 };
821 static const char * const mdp_vsync5_groups[] = {
822 "gpio81",
823 };
824 static const char * const mi2s0_data0_groups[] = {
825 "gpio98",
826 };
827 static const char * const mi2s0_data1_groups[] = {
828 "gpio99",
829 };
830 static const char * const mi2s0_sck_groups[] = {
831 "gpio97",
832 };
833 static const char * const mi2s0_ws_groups[] = {
834 "gpio100",
835 };
836 static const char * const mi2s1_data0_groups[] = {
837 "gpio107",
838 };
839 static const char * const mi2s1_data1_groups[] = {
840 "gpio105",
841 };
842 static const char * const mi2s1_sck_groups[] = {
843 "gpio106",
844 };
845 static const char * const mi2s1_ws_groups[] = {
846 "gpio108",
847 };
848 static const char * const mi2s2_data0_groups[] = {
849 "gpio102",
850 };
851 static const char * const mi2s2_data1_groups[] = {
852 "gpio104",
853 };
854 static const char * const mi2s2_sck_groups[] = {
855 "gpio101",
856 };
857 static const char * const mi2s2_ws_groups[] = {
858 "gpio103",
859 };
860 static const char * const mss_grfc0_groups[] = {
861 "gpio117", "gpio132",
862 };
863 static const char * const mss_grfc1_groups[] = {
864 "gpio118",
865 };
866 static const char * const mss_grfc10_groups[] = {
867 "gpio127",
868 };
869 static const char * const mss_grfc11_groups[] = {
870 "gpio128",
871 };
872 static const char * const mss_grfc12_groups[] = {
873 "gpio131",
874 };
875 static const char * const mss_grfc2_groups[] = {
876 "gpio119",
877 };
878 static const char * const mss_grfc3_groups[] = {
879 "gpio120",
880 };
881 static const char * const mss_grfc4_groups[] = {
882 "gpio121",
883 };
884 static const char * const mss_grfc5_groups[] = {
885 "gpio122",
886 };
887 static const char * const mss_grfc6_groups[] = {
888 "gpio123",
889 };
890 static const char * const mss_grfc7_groups[] = {
891 "gpio124",
892 };
893 static const char * const mss_grfc8_groups[] = {
894 "gpio125",
895 };
896 static const char * const mss_grfc9_groups[] = {
897 "gpio126",
898 };
899 static const char * const nav_gpio0_groups[] = {
900 "gpio129",
901 };
902 static const char * const nav_gpio1_groups[] = {
903 "gpio130",
904 };
905 static const char * const nav_gpio2_groups[] = {
906 "gpio131",
907 };
908 static const char * const pa_indicator_groups[] = {
909 "gpio131",
910 };
911 static const char * const pcie0_clkreqn_groups[] = {
912 "gpio88",
913 };
914 static const char * const pcie1_clkreqn_groups[] = {
915 "gpio79",
916 };
917 static const char * const phase_flag_groups[] = {
918 "gpio12", "gpio13", "gpio14", "gpio15", "gpio16",
919 "gpio17", "gpio18", "gpio19", "gpio56", "gpio57",
920 "gpio58", "gpio59", "gpio60", "gpio61", "gpio62",
921 "gpio63", "gpio117", "gpio118", "gpio119", "gpio120",
922 "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
923 "gpio126", "gpio127", "gpio128", "gpio129", "gpio130",
924 "gpio131", "gpio132",
925 };
926 static const char * const pll_bist_groups[] = {
927 "gpio80",
928 };
929 static const char * const pll_bypassnl_groups[] = {
930 "gpio66",
931 };
932 static const char * const pll_clk_groups[] = {
933 "gpio140",
934 };
935 static const char * const pll_reset_groups[] = {
936 "gpio67",
937 };
938 static const char * const pri_mi2s_groups[] = {
939 "gpio96",
940 };
941 static const char * const prng_rosc_groups[] = {
942 "gpio123",
943 };
944 static const char * const qdss_groups[] = {
945 "gpio2", "gpio3", "gpio8", "gpio9", "gpio10",
946 "gpio11", "gpio12", "gpio13", "gpio20", "gpio21",
947 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
948 "gpio27", "gpio28", "gpio29", "gpio58", "gpio59",
949 "gpio101", "gpio102", "gpio103", "gpio104", "gpio105",
950 "gpio106", "gpio107", "gpio108", "gpio150", "gpio151",
951 "gpio152", "gpio153", "gpio171", "gpio172", "gpio173",
952 "gpio174",
953 };
954 static const char * const qdss_cti_groups[] = {
955 "gpio15", "gpio16", "gpio18", "gpio19", "gpio156", "gpio157",
956 "gpio165", "gpio166",
957 };
958 static const char * const qlink0_enable_groups[] = {
959 "gpio134",
960 };
961 static const char * const qlink0_request_groups[] = {
962 "gpio133",
963 };
964 static const char * const qlink0_wmss_groups[] = {
965 "gpio135",
966 };
967 static const char * const qlink1_enable_groups[] = {
968 "gpio137",
969 };
970 static const char * const qlink1_request_groups[] = {
971 "gpio136",
972 };
973 static const char * const qlink1_wmss_groups[] = {
974 "gpio138",
975 };
976 static const char * const qspi_clk_groups[] = {
977 "gpio14",
978 };
979 static const char * const qspi_cs_groups[] = {
980 "gpio15", "gpio19",
981 };
982 static const char * const qspi_data_groups[] = {
983 "gpio12", "gpio13", "gpio16", "gpio17",
984 };
985 static const char * const qup00_groups[] = {
986 "gpio0", "gpio1", "gpio2", "gpio3",
987 };
988 static const char * const qup01_groups[] = {
989 "gpio4", "gpio5", "gpio6", "gpio7",
990 };
991 static const char * const qup02_groups[] = {
992 "gpio8", "gpio9", "gpio10", "gpio11",
993 };
994 static const char * const qup03_groups[] = {
995 "gpio12", "gpio13", "gpio14", "gpio15",
996 };
997 static const char * const qup04_groups[] = {
998 "gpio16", "gpio17", "gpio18", "gpio19",
999 };
1000 static const char * const qup05_groups[] = {
1001 "gpio20", "gpio21", "gpio22", "gpio23",
1002 };
1003 static const char * const qup06_groups[] = {
1004 "gpio24", "gpio25", "gpio26", "gpio27",
1005 };
1006 static const char * const qup07_groups[] = {
1007 "gpio2", "gpio3", "gpio6", "gpio28", "gpio29", "gpio30", "gpio31",
1008 };
1009 static const char * const qup10_groups[] = {
1010 "gpio32", "gpio33", "gpio34", "gpio35",
1011 };
1012 static const char * const qup11_groups[] = {
1013 "gpio36", "gpio37", "gpio38", "gpio39",
1014 };
1015 static const char * const qup12_groups[] = {
1016 "gpio40", "gpio41", "gpio42", "gpio43",
1017 };
1018 static const char * const qup13_groups[] = {
1019 "gpio44", "gpio45", "gpio46", "gpio47",
1020 };
1021 static const char * const qup14_groups[] = {
1022 "gpio38", "gpio48", "gpio49", "gpio50", "gpio51", "gpio54", "gpio55",
1023 };
1024 static const char * const qup15_groups[] = {
1025 "gpio52", "gpio53", "gpio54", "gpio55",
1026 };
1027 static const char * const qup16_groups[] = {
1028 "gpio50", "gpio56", "gpio57", "gpio58", "gpio59", "gpio62", "gpio63",
1029 };
1030 static const char * const qup17_groups[] = {
1031 "gpio60", "gpio61", "gpio62", "gpio63",
1032 };
1033 static const char * const sd_write_groups[] = {
1034 "gpio61",
1035 };
1036 static const char * const sdc40_groups[] = {
1037 "gpio12",
1038 };
1039 static const char * const sdc41_groups[] = {
1040 "gpio13",
1041 };
1042 static const char * const sdc42_groups[] = {
1043 "gpio16",
1044 };
1045 static const char * const sdc43_groups[] = {
1046 "gpio17",
1047 };
1048 static const char * const sdc4_clk_groups[] = {
1049 "gpio14",
1050 };
1051 static const char * const sdc4_cmd_groups[] = {
1052 "gpio19",
1053 };
1054 static const char * const sec_mi2s_groups[] = {
1055 "gpio105",
1056 };
1057 static const char * const tb_trig_groups[] = {
1058 "gpio12", "gpio13", "gpio15",
1059 };
1060 static const char * const tgu_ch0_groups[] = {
1061 "gpio65",
1062 };
1063 static const char * const tgu_ch1_groups[] = {
1064 "gpio66",
1065 };
1066 static const char * const tsense_pwm1_groups[] = {
1067 "gpio61",
1068 };
1069 static const char * const tsense_pwm2_groups[] = {
1070 "gpio61",
1071 };
1072 static const char * const uim0_clk_groups[] = {
1073 "gpio114",
1074 };
1075 static const char * const uim0_data_groups[] = {
1076 "gpio113",
1077 };
1078 static const char * const uim0_present_groups[] = {
1079 "gpio116",
1080 };
1081 static const char * const uim0_reset_groups[] = {
1082 "gpio115",
1083 };
1084 static const char * const uim1_clk_groups[] = {
1085 "gpio110",
1086 };
1087 static const char * const uim1_data_groups[] = {
1088 "gpio109",
1089 };
1090 static const char * const uim1_present_groups[] = {
1091 "gpio112",
1092 };
1093 static const char * const uim1_reset_groups[] = {
1094 "gpio111",
1095 };
1096 static const char * const usb2phy_ac_groups[] = {
1097 "gpio84", "gpio85",
1098 };
1099 static const char * const usb_phy_groups[] = {
1100 "gpio140",
1101 };
1102 static const char * const vfr_0_groups[] = {
1103 "gpio80",
1104 };
1105 static const char * const vfr_1_groups[] = {
1106 "gpio103",
1107 };
1108 static const char * const vsense_trigger_groups[] = {
1109 "gpio100",
1110 };
1111
1112 static const struct msm_function sc7280_functions[] = {
1113 FUNCTION(atest_char),
1114 FUNCTION(atest_char0),
1115 FUNCTION(atest_char1),
1116 FUNCTION(atest_char2),
1117 FUNCTION(atest_char3),
1118 FUNCTION(atest_usb0),
1119 FUNCTION(atest_usb00),
1120 FUNCTION(atest_usb01),
1121 FUNCTION(atest_usb02),
1122 FUNCTION(atest_usb03),
1123 FUNCTION(atest_usb1),
1124 FUNCTION(atest_usb10),
1125 FUNCTION(atest_usb11),
1126 FUNCTION(atest_usb12),
1127 FUNCTION(atest_usb13),
1128 FUNCTION(audio_ref),
1129 FUNCTION(cam_mclk),
1130 FUNCTION(cci_async),
1131 FUNCTION(cci_i2c),
1132 FUNCTION(cci_timer0),
1133 FUNCTION(cci_timer1),
1134 FUNCTION(cci_timer2),
1135 FUNCTION(cci_timer3),
1136 FUNCTION(cci_timer4),
1137 FUNCTION(cmu_rng0),
1138 FUNCTION(cmu_rng1),
1139 FUNCTION(cmu_rng2),
1140 FUNCTION(cmu_rng3),
1141 FUNCTION(coex_uart1),
1142 FUNCTION(cri_trng),
1143 FUNCTION(cri_trng0),
1144 FUNCTION(cri_trng1),
1145 FUNCTION(dbg_out),
1146 FUNCTION(ddr_bist),
1147 FUNCTION(ddr_pxi0),
1148 FUNCTION(ddr_pxi1),
1149 FUNCTION(dp_hot),
1150 FUNCTION(dp_lcd),
1151 FUNCTION(edp_hot),
1152 FUNCTION(edp_lcd),
1153 FUNCTION(gcc_gp1),
1154 FUNCTION(gcc_gp2),
1155 FUNCTION(gcc_gp3),
1156 FUNCTION(gpio),
1157 FUNCTION(host2wlan_sol),
1158 FUNCTION(ibi_i3c),
1159 FUNCTION(jitter_bist),
1160 FUNCTION(lpass_slimbus),
1161 FUNCTION(mdp_vsync),
1162 FUNCTION(mdp_vsync0),
1163 FUNCTION(mdp_vsync1),
1164 FUNCTION(mdp_vsync2),
1165 FUNCTION(mdp_vsync3),
1166 FUNCTION(mdp_vsync4),
1167 FUNCTION(mdp_vsync5),
1168 FUNCTION(mi2s0_data0),
1169 FUNCTION(mi2s0_data1),
1170 FUNCTION(mi2s0_sck),
1171 FUNCTION(mi2s0_ws),
1172 FUNCTION(mi2s1_data0),
1173 FUNCTION(mi2s1_data1),
1174 FUNCTION(mi2s1_sck),
1175 FUNCTION(mi2s1_ws),
1176 FUNCTION(mi2s2_data0),
1177 FUNCTION(mi2s2_data1),
1178 FUNCTION(mi2s2_sck),
1179 FUNCTION(mi2s2_ws),
1180 FUNCTION(mss_grfc0),
1181 FUNCTION(mss_grfc1),
1182 FUNCTION(mss_grfc10),
1183 FUNCTION(mss_grfc11),
1184 FUNCTION(mss_grfc12),
1185 FUNCTION(mss_grfc2),
1186 FUNCTION(mss_grfc3),
1187 FUNCTION(mss_grfc4),
1188 FUNCTION(mss_grfc5),
1189 FUNCTION(mss_grfc6),
1190 FUNCTION(mss_grfc7),
1191 FUNCTION(mss_grfc8),
1192 FUNCTION(mss_grfc9),
1193 FUNCTION(nav_gpio0),
1194 FUNCTION(nav_gpio1),
1195 FUNCTION(nav_gpio2),
1196 FUNCTION(pa_indicator),
1197 FUNCTION(pcie0_clkreqn),
1198 FUNCTION(pcie1_clkreqn),
1199 FUNCTION(phase_flag),
1200 FUNCTION(pll_bist),
1201 FUNCTION(pll_bypassnl),
1202 FUNCTION(pll_clk),
1203 FUNCTION(pll_reset),
1204 FUNCTION(pri_mi2s),
1205 FUNCTION(prng_rosc),
1206 FUNCTION(qdss),
1207 FUNCTION(qdss_cti),
1208 FUNCTION(qlink0_enable),
1209 FUNCTION(qlink0_request),
1210 FUNCTION(qlink0_wmss),
1211 FUNCTION(qlink1_enable),
1212 FUNCTION(qlink1_request),
1213 FUNCTION(qlink1_wmss),
1214 FUNCTION(qspi_clk),
1215 FUNCTION(qspi_cs),
1216 FUNCTION(qspi_data),
1217 FUNCTION(qup00),
1218 FUNCTION(qup01),
1219 FUNCTION(qup02),
1220 FUNCTION(qup03),
1221 FUNCTION(qup04),
1222 FUNCTION(qup05),
1223 FUNCTION(qup06),
1224 FUNCTION(qup07),
1225 FUNCTION(qup10),
1226 FUNCTION(qup11),
1227 FUNCTION(qup12),
1228 FUNCTION(qup13),
1229 FUNCTION(qup14),
1230 FUNCTION(qup15),
1231 FUNCTION(qup16),
1232 FUNCTION(qup17),
1233 FUNCTION(sdc40),
1234 FUNCTION(sdc41),
1235 FUNCTION(sdc42),
1236 FUNCTION(sdc43),
1237 FUNCTION(sdc4_clk),
1238 FUNCTION(sdc4_cmd),
1239 FUNCTION(sd_write),
1240 FUNCTION(sec_mi2s),
1241 FUNCTION(tb_trig),
1242 FUNCTION(tgu_ch0),
1243 FUNCTION(tgu_ch1),
1244 FUNCTION(tsense_pwm1),
1245 FUNCTION(tsense_pwm2),
1246 FUNCTION(uim0_clk),
1247 FUNCTION(uim0_data),
1248 FUNCTION(uim0_present),
1249 FUNCTION(uim0_reset),
1250 FUNCTION(uim1_clk),
1251 FUNCTION(uim1_data),
1252 FUNCTION(uim1_present),
1253 FUNCTION(uim1_reset),
1254 FUNCTION(usb2phy_ac),
1255 FUNCTION(usb_phy),
1256 FUNCTION(vfr_0),
1257 FUNCTION(vfr_1),
1258 FUNCTION(vsense_trigger),
1259 };
1260
1261 /* Every pin is maintained as a single group, and missing or non-existing pin
1262 * would be maintained as dummy group to synchronize pin group index with
1263 * pin descriptor registered with pinctrl core.
1264 * Clients would not be able to request these dummy pin groups.
1265 */
1266 static const struct msm_pingroup sc7280_groups[] = {
1267 [0] = PINGROUP(0, qup00, ibi_i3c, _, _, _, _, _, _, _),
1268 [1] = PINGROUP(1, qup00, ibi_i3c, _, _, _, _, _, _, _),
1269 [2] = PINGROUP(2, qup00, qup07, _, qdss, _, _, _, _, _),
1270 [3] = PINGROUP(3, qup00, qup07, _, qdss, _, _, _, _, _),
1271 [4] = PINGROUP(4, qup01, ibi_i3c, _, _, _, _, _, _, _),
1272 [5] = PINGROUP(5, qup01, ibi_i3c, _, _, _, _, _, _, _),
1273 [6] = PINGROUP(6, qup01, qup07, _, _, _, _, _, _, _),
1274 [7] = PINGROUP(7, qup01, _, _, _, _, _, _, _, _),
1275 [8] = PINGROUP(8, qup02, _, qdss, _, _, _, _, _, _),
1276 [9] = PINGROUP(9, qup02, _, qdss, _, _, _, _, _, _),
1277 [10] = PINGROUP(10, qup02, _, qdss, _, _, _, _, _, _),
1278 [11] = PINGROUP(11, qup02, _, qdss, _, _, _, _, _, _),
1279 [12] = PINGROUP(12, qup03, qspi_data, sdc40, tb_trig, phase_flag, qdss, ddr_pxi1, _, _),
1280 [13] = PINGROUP(13, qup03, qspi_data, sdc41, tb_trig, phase_flag, qdss, ddr_pxi1, _, _),
1281 [14] = PINGROUP(14, qup03, qspi_clk, sdc4_clk, mdp_vsync, phase_flag, ddr_pxi0, _, _, _),
1282 [15] = PINGROUP(15, qup03, qspi_cs, tb_trig, phase_flag, qdss_cti, ddr_pxi0, _, _, _),
1283 [16] = PINGROUP(16, qup04, qspi_data, sdc42, mdp_vsync, phase_flag, qdss_cti, _, _, _),
1284 [17] = PINGROUP(17, qup04, qspi_data, sdc43, _, phase_flag, _, _, _, _),
1285 [18] = PINGROUP(18, qup04, _, phase_flag, qdss_cti, _, _, _, _, _),
1286 [19] = PINGROUP(19, qup04, qspi_cs, sdc4_cmd, _, phase_flag, qdss_cti, _, _, _),
1287 [20] = PINGROUP(20, qup05, cci_timer0, _, qdss, _, _, _, _, _),
1288 [21] = PINGROUP(21, qup05, cci_timer1, _, qdss, _, _, _, _, _),
1289 [22] = PINGROUP(22, qup05, _, qdss, _, _, _, _, _, _),
1290 [23] = PINGROUP(23, qup05, _, qdss, _, _, _, _, _, _),
1291 [24] = PINGROUP(24, qup06, _, qdss, _, _, _, _, _, _),
1292 [25] = PINGROUP(25, qup06, _, qdss, _, _, _, _, _, _),
1293 [26] = PINGROUP(26, qup06, host2wlan_sol, _, qdss, _, _, _, _, _),
1294 [27] = PINGROUP(27, qup06, _, qdss, _, _, _, _, _, _),
1295 [28] = PINGROUP(28, qup07, _, qdss, _, _, _, _, _, _),
1296 [29] = PINGROUP(29, qup07, qdss, _, _, _, _, _, _, _),
1297 [30] = PINGROUP(30, qup07, _, _, _, _, _, _, _, _),
1298 [31] = PINGROUP(31, qup07, _, _, _, _, _, _, _, _),
1299 [32] = PINGROUP(32, qup10, _, _, _, _, _, _, _, _),
1300 [33] = PINGROUP(33, qup10, _, _, _, _, _, _, _, _),
1301 [34] = PINGROUP(34, qup10, _, _, _, _, _, _, _, _),
1302 [35] = PINGROUP(35, qup10, _, _, _, _, _, _, _, _),
1303 [36] = PINGROUP(36, qup11, ibi_i3c, _, _, _, _, _, _, _),
1304 [37] = PINGROUP(37, qup11, ibi_i3c, _, _, _, _, _, _, _),
1305 [38] = PINGROUP(38, qup11, qup14, dbg_out, _, _, _, _, _, _),
1306 [39] = PINGROUP(39, qup11, _, _, _, _, _, _, _, _),
1307 [40] = PINGROUP(40, qup12, _, _, _, _, _, _, _, _),
1308 [41] = PINGROUP(41, qup12, _, _, _, _, _, _, _, _),
1309 [42] = PINGROUP(42, qup12, _, _, _, _, _, _, _, _),
1310 [43] = PINGROUP(43, qup12, _, _, _, _, _, _, _, _),
1311 [44] = PINGROUP(44, qup13, _, _, _, _, _, _, _, _),
1312 [45] = PINGROUP(45, qup13, _, _, _, _, _, _, _, _),
1313 [46] = PINGROUP(46, qup13, edp_lcd, _, _, _, _, _, _, _),
1314 [47] = PINGROUP(47, qup13, dp_hot, _, _, _, _, _, _, _),
1315 [48] = PINGROUP(48, qup14, _, _, _, _, _, _, _, _),
1316 [49] = PINGROUP(49, qup14, _, _, _, _, _, _, _, _),
1317 [50] = PINGROUP(50, qup14, qup16, _, _, _, _, _, _, _),
1318 [51] = PINGROUP(51, qup14, _, _, _, _, _, _, _, _),
1319 [52] = PINGROUP(52, qup15, _, _, _, _, _, _, _, _),
1320 [53] = PINGROUP(53, qup15, _, _, _, _, _, _, _, _),
1321 [54] = PINGROUP(54, qup15, qup14, _, _, _, _, _, _, _),
1322 [55] = PINGROUP(55, qup15, qup14, _, _, _, _, _, _, _),
1323 [56] = PINGROUP(56, qup16, ddr_bist, phase_flag, _, _, _, _, _, _),
1324 [57] = PINGROUP(57, qup16, ddr_bist, phase_flag, _, _, _, _, _, _),
1325 [58] = PINGROUP(58, qup16, ddr_bist, phase_flag, qdss, _, _, _, _, _),
1326 [59] = PINGROUP(59, qup16, ddr_bist, phase_flag, qdss, _, _, _, _, _),
1327 [60] = PINGROUP(60, qup17, edp_hot, _, phase_flag, _, _, _, _, _),
1328 [61] = PINGROUP(61, qup17, sd_write, phase_flag, tsense_pwm1, tsense_pwm2, _, _, _, _),
1329 [62] = PINGROUP(62, qup17, qup16, phase_flag, _, _, _, _, _, _),
1330 [63] = PINGROUP(63, qup17, qup16, phase_flag, _, _, _, _, _, _),
1331 [64] = PINGROUP(64, cam_mclk, _, _, _, _, _, _, _, _),
1332 [65] = PINGROUP(65, cam_mclk, tgu_ch0, _, _, _, _, _, _, _),
1333 [66] = PINGROUP(66, cam_mclk, pll_bypassnl, tgu_ch1, _, _, _, _, _, _),
1334 [67] = PINGROUP(67, cam_mclk, pll_reset, _, _, _, _, _, _, _),
1335 [68] = PINGROUP(68, cam_mclk, _, _, _, _, _, _, _, _),
1336 [69] = PINGROUP(69, cci_i2c, _, _, _, _, _, _, _, _),
1337 [70] = PINGROUP(70, cci_i2c, _, _, _, _, _, _, _, _),
1338 [71] = PINGROUP(71, cci_i2c, _, _, _, _, _, _, _, _),
1339 [72] = PINGROUP(72, cci_i2c, _, _, _, _, _, _, _, _),
1340 [73] = PINGROUP(73, cci_i2c, _, _, _, _, _, _, _, _),
1341 [74] = PINGROUP(74, cci_i2c, _, _, _, _, _, _, _, _),
1342 [75] = PINGROUP(75, cci_i2c, _, _, _, _, _, _, _, _),
1343 [76] = PINGROUP(76, cci_i2c, gcc_gp1, _, _, _, _, _, _, _),
1344 [77] = PINGROUP(77, cci_timer2, gcc_gp2, _, atest_usb13, atest_char0, _, _, _, _),
1345 [78] = PINGROUP(78, cci_timer3, cci_async, gcc_gp3, _, atest_usb12, atest_char1, _, _, _),
1346 [79] = PINGROUP(79, cci_timer4, cci_async, pcie1_clkreqn, mdp_vsync, jitter_bist, atest_usb11, atest_char2, _, _),
1347 [80] = PINGROUP(80, mdp_vsync, vfr_0, mdp_vsync0, mdp_vsync1, mdp_vsync4, pll_bist, atest_usb10, atest_char3, _),
1348 [81] = PINGROUP(81, mdp_vsync, dp_lcd, mdp_vsync2, mdp_vsync3, mdp_vsync5, atest_usb1, atest_char, _, _),
1349 [82] = PINGROUP(82, _, _, _, _, _, _, _, _, _),
1350 [83] = PINGROUP(83, _, _, _, _, _, _, _, _, _),
1351 [84] = PINGROUP(84, usb2phy_ac, _, _, _, _, _, _, _, _),
1352 [85] = PINGROUP(85, usb2phy_ac, _, _, _, _, _, _, _, _),
1353 [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _),
1354 [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _),
1355 [88] = PINGROUP(88, pcie0_clkreqn, _, _, _, _, _, _, _, _),
1356 [89] = PINGROUP(89, _, _, _, _, _, _, _, _, _),
1357 [90] = PINGROUP(90, _, _, _, _, _, _, _, _, _),
1358 [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _),
1359 [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _),
1360 [93] = PINGROUP(93, cam_mclk, cci_async, _, _, _, _, _, _, _),
1361 [94] = PINGROUP(94, lpass_slimbus, _, _, _, _, _, _, _, _),
1362 [95] = PINGROUP(95, lpass_slimbus, _, _, _, _, _, _, _, _),
1363 [96] = PINGROUP(96, pri_mi2s, _, _, _, _, _, _, _, _),
1364 [97] = PINGROUP(97, mi2s0_sck, _, _, _, _, _, _, _, _),
1365 [98] = PINGROUP(98, mi2s0_data0, _, _, _, _, _, _, _, _),
1366 [99] = PINGROUP(99, mi2s0_data1, _, _, _, _, _, _, _, _),
1367 [100] = PINGROUP(100, mi2s0_ws, _, vsense_trigger, _, _, _, _, _, _),
1368 [101] = PINGROUP(101, mi2s2_sck, _, qdss, _, _, _, _, _, _),
1369 [102] = PINGROUP(102, mi2s2_data0, _, _, qdss, _, _, _, _, _),
1370 [103] = PINGROUP(103, mi2s2_ws, vfr_1, _, _, qdss, _, atest_usb03, _, _),
1371 [104] = PINGROUP(104, mi2s2_data1, _, _, qdss, _, atest_usb02, _, _, _),
1372 [105] = PINGROUP(105, sec_mi2s, mi2s1_data1, audio_ref, gcc_gp1, _, qdss, atest_usb01, _, _),
1373 [106] = PINGROUP(106, mi2s1_sck, gcc_gp2, _, qdss, atest_usb00, _, _, _, _),
1374 [107] = PINGROUP(107, mi2s1_data0, gcc_gp3, _, qdss, atest_usb0, _, _, _, _),
1375 [108] = PINGROUP(108, mi2s1_ws, _, qdss, _, _, _, _, _, _),
1376 [109] = PINGROUP(109, uim1_data, _, _, _, _, _, _, _, _),
1377 [110] = PINGROUP(110, uim1_clk, _, _, _, _, _, _, _, _),
1378 [111] = PINGROUP(111, uim1_reset, _, _, _, _, _, _, _, _),
1379 [112] = PINGROUP(112, uim1_present, _, _, _, _, _, _, _, _),
1380 [113] = PINGROUP(113, uim0_data, _, _, _, _, _, _, _, _),
1381 [114] = PINGROUP(114, uim0_clk, _, _, _, _, _, _, _, _),
1382 [115] = PINGROUP(115, uim0_reset, _, _, _, _, _, _, _, _),
1383 [116] = PINGROUP(116, uim0_present, _, _, _, _, _, _, _, _),
1384 [117] = PINGROUP(117, _, mss_grfc0, cmu_rng3, phase_flag, _, _, _, _, _),
1385 [118] = PINGROUP(118, _, mss_grfc1, cmu_rng2, phase_flag, _, _, _, _, _),
1386 [119] = PINGROUP(119, _, mss_grfc2, cmu_rng1, phase_flag, _, _, _, _, _),
1387 [120] = PINGROUP(120, _, mss_grfc3, cmu_rng0, phase_flag, _, _, _, _, _),
1388 [121] = PINGROUP(121, _, mss_grfc4, cri_trng0, phase_flag, _, _, _, _, _),
1389 [122] = PINGROUP(122, _, mss_grfc5, cri_trng1, phase_flag, _, _, _, _, _),
1390 [123] = PINGROUP(123, _, mss_grfc6, prng_rosc, phase_flag, _, _, _, _, _),
1391 [124] = PINGROUP(124, _, mss_grfc7, cri_trng, phase_flag, _, _, _, _, _),
1392 [125] = PINGROUP(125, _, mss_grfc8, phase_flag, _, _, _, _, _, _),
1393 [126] = PINGROUP(126, _, mss_grfc9, phase_flag, _, _, _, _, _, _),
1394 [127] = PINGROUP(127, coex_uart1, mss_grfc10, phase_flag, _, _, _, _, _, _),
1395 [128] = PINGROUP(128, coex_uart1, mss_grfc11, phase_flag, _, _, _, _, _, _),
1396 [129] = PINGROUP(129, nav_gpio0, phase_flag, _, _, _, _, _, _, _),
1397 [130] = PINGROUP(130, nav_gpio1, phase_flag, _, _, _, _, _, _, _),
1398 [131] = PINGROUP(131, mss_grfc12, nav_gpio2, pa_indicator, phase_flag, _, _, _, _, _),
1399 [132] = PINGROUP(132, mss_grfc0, phase_flag, _, _, _, _, _, _, _),
1400 [133] = PINGROUP(133, qlink0_request, _, _, _, _, _, _, _, _),
1401 [134] = PINGROUP(134, qlink0_enable, _, _, _, _, _, _, _, _),
1402 [135] = PINGROUP(135, qlink0_wmss, _, _, _, _, _, _, _, _),
1403 [136] = PINGROUP(136, qlink1_request, _, _, _, _, _, _, _, _),
1404 [137] = PINGROUP(137, qlink1_enable, _, _, _, _, _, _, _, _),
1405 [138] = PINGROUP(138, qlink1_wmss, _, _, _, _, _, _, _, _),
1406 [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _),
1407 [140] = PINGROUP(140, usb_phy, pll_clk, _, _, _, _, _, _, _),
1408 [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _),
1409 [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _),
1410 [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _),
1411 [144] = PINGROUP(144, _, _, _, _, _, _, _, _, _),
1412 [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _),
1413 [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _),
1414 [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _),
1415 [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _),
1416 [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _),
1417 [150] = PINGROUP(150, qdss, _, _, _, _, _, _, _, _),
1418 [151] = PINGROUP(151, qdss, _, _, _, _, _, _, _, _),
1419 [152] = PINGROUP(152, qdss, _, _, _, _, _, _, _, _),
1420 [153] = PINGROUP(153, qdss, _, _, _, _, _, _, _, _),
1421 [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _),
1422 [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _),
1423 [156] = PINGROUP(156, qdss_cti, _, _, _, _, _, _, _, _),
1424 [157] = PINGROUP(157, qdss_cti, _, _, _, _, _, _, _, _),
1425 [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _),
1426 [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _),
1427 [160] = PINGROUP(160, _, _, _, _, _, _, _, _, _),
1428 [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _),
1429 [162] = PINGROUP(162, _, _, _, _, _, _, _, _, _),
1430 [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _),
1431 [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _),
1432 [165] = PINGROUP(165, qdss_cti, _, _, _, _, _, _, _, _),
1433 [166] = PINGROUP(166, qdss_cti, _, _, _, _, _, _, _, _),
1434 [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _),
1435 [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _),
1436 [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _),
1437 [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _),
1438 [171] = PINGROUP(171, qdss, _, _, _, _, _, _, _, _),
1439 [172] = PINGROUP(172, qdss, _, _, _, _, _, _, _, _),
1440 [173] = PINGROUP(173, qdss, _, _, _, _, _, _, _, _),
1441 [174] = PINGROUP(174, qdss, _, _, _, _, _, _, _, _),
1442 [175] = UFS_RESET(ufs_reset, 0x1be000),
1443 [176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x1b3000, 15, 0),
1444 [177] = SDC_QDSD_PINGROUP(sdc1_clk, 0x1b3000, 13, 6),
1445 [178] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x1b3000, 11, 3),
1446 [179] = SDC_QDSD_PINGROUP(sdc1_data, 0x1b3000, 9, 0),
1447 [180] = SDC_QDSD_PINGROUP(sdc2_clk, 0x1b4000, 14, 6),
1448 [181] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x1b4000, 11, 3),
1449 [182] = SDC_QDSD_PINGROUP(sdc2_data, 0x1b4000, 9, 0),
1450 };
1451
1452 static const struct msm_pinctrl_soc_data sc7280_pinctrl = {
1453 .pins = sc7280_pins,
1454 .npins = ARRAY_SIZE(sc7280_pins),
1455 .functions = sc7280_functions,
1456 .nfunctions = ARRAY_SIZE(sc7280_functions),
1457 .groups = sc7280_groups,
1458 .ngroups = ARRAY_SIZE(sc7280_groups),
1459 .ngpios = 176,
1460 };
1461
1462 static int sc7280_pinctrl_probe(struct platform_device *pdev)
1463 {
1464 return msm_pinctrl_probe(pdev, &sc7280_pinctrl);
1465 }
1466
1467 static const struct of_device_id sc7280_pinctrl_of_match[] = {
1468 { .compatible = "qcom,sc7280-pinctrl", },
1469 { },
1470 };
1471
1472 static struct platform_driver sc7280_pinctrl_driver = {
1473 .driver = {
1474 .name = "sc7280-pinctrl",
1475 .of_match_table = sc7280_pinctrl_of_match,
1476 },
1477 .probe = sc7280_pinctrl_probe,
1478 .remove = msm_pinctrl_remove,
1479 };
1480
1481 static int __init sc7280_pinctrl_init(void)
1482 {
1483 return platform_driver_register(&sc7280_pinctrl_driver);
1484 }
1485 arch_initcall(sc7280_pinctrl_init);
1486
1487 static void __exit sc7280_pinctrl_exit(void)
1488 {
1489 platform_driver_unregister(&sc7280_pinctrl_driver);
1490 }
1491 module_exit(sc7280_pinctrl_exit);
1492
1493 MODULE_DESCRIPTION("QTI sc7280 pinctrl driver");
1494 MODULE_LICENSE("GPL v2");
1495 MODULE_DEVICE_TABLE(of, sc7280_pinctrl_of_match);
Linux with added FPC-III support