drivers/platform/x86/intel_mid_powerbtn.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Power button driver for Intel MID platforms.
   4  *
   5  * Copyright (C) 2010,2017 Intel Corp
   6  *
   7  * Author: Hong Liu <hong.liu@intel.com>
   8  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   9  */
  10
  11 #include <linux/input.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/mfd/intel_msic.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_wakeirq.h>
  17 #include <linux/slab.h>
  18
  19 #include <asm/cpu_device_id.h>
  20 #include <asm/intel-family.h>
  21 #include <asm/intel_scu_ipc.h>
  22
  23 #define DRIVER_NAME "msic_power_btn"
  24
  25 #define MSIC_PB_LEVEL   (1 << 3) /* 1 - release, 0 - press */
  26
  27 /*
  28  * MSIC document ti_datasheet defines the 1st bit reg 0x21 is used to mask
  29  * power button interrupt
  30  */
  31 #define MSIC_PWRBTNM    (1 << 0)
  32
  33 /* Intel Tangier */
  34 #define BCOVE_PB_LEVEL          (1 << 4)        /* 1 - release, 0 - press */
  35
  36 /* Basin Cove PMIC */
  37 #define BCOVE_PBIRQ             0x02
  38 #define BCOVE_IRQLVL1MSK        0x0c
  39 #define BCOVE_PBIRQMASK         0x0d
  40 #define BCOVE_PBSTATUS          0x27
  41
  42 struct mid_pb_ddata {
  43         struct device *dev;
  44         int irq;
  45         struct input_dev *input;
  46         unsigned short mirqlvl1_addr;
  47         unsigned short pbstat_addr;
  48         u8 pbstat_mask;
  49         struct intel_scu_ipc_dev *scu;
  50         int (*setup)(struct mid_pb_ddata *ddata);
  51 };
  52
  53 static int mid_pbstat(struct mid_pb_ddata *ddata, int *value)
  54 {
  55         struct input_dev *input = ddata->input;
  56         int ret;
  57         u8 pbstat;
  58
  59         ret = intel_scu_ipc_dev_ioread8(ddata->scu, ddata->pbstat_addr,
  60                                         &pbstat);
  61         if (ret)
  62                 return ret;
  63
  64         dev_dbg(input->dev.parent, "PB_INT status= %d\n", pbstat);
  65
  66         *value = !(pbstat & ddata->pbstat_mask);
  67         return 0;
  68 }
  69
  70 static int mid_irq_ack(struct mid_pb_ddata *ddata)
  71 {
  72         return intel_scu_ipc_dev_update(ddata->scu, ddata->mirqlvl1_addr, 0,
  73                                         MSIC_PWRBTNM);
  74 }
  75
  76 static int mrfld_setup(struct mid_pb_ddata *ddata)
  77 {
  78         /* Unmask the PBIRQ and MPBIRQ on Tangier */
  79         intel_scu_ipc_dev_update(ddata->scu, BCOVE_PBIRQ, 0, MSIC_PWRBTNM);
  80         intel_scu_ipc_dev_update(ddata->scu, BCOVE_PBIRQMASK, 0, MSIC_PWRBTNM);
  81
  82         return 0;
  83 }
  84
  85 static irqreturn_t mid_pb_isr(int irq, void *dev_id)
  86 {
  87         struct mid_pb_ddata *ddata = dev_id;
  88         struct input_dev *input = ddata->input;
  89         int value = 0;
  90         int ret;
  91
  92         ret = mid_pbstat(ddata, &value);
  93         if (ret < 0) {
  94                 dev_err(input->dev.parent,
  95                         "Read error %d while reading MSIC_PB_STATUS\n", ret);
  96         } else {
  97                 input_event(input, EV_KEY, KEY_POWER, value);
  98                 input_sync(input);
  99         }
 100
 101         mid_irq_ack(ddata);
 102         return IRQ_HANDLED;
 103 }
 104
 105 static const struct mid_pb_ddata mfld_ddata = {
 106         .mirqlvl1_addr  = INTEL_MSIC_IRQLVL1MSK,
 107         .pbstat_addr    = INTEL_MSIC_PBSTATUS,
 108         .pbstat_mask    = MSIC_PB_LEVEL,
 109 };
 110
 111 static const struct mid_pb_ddata mrfld_ddata = {
 112         .mirqlvl1_addr  = BCOVE_IRQLVL1MSK,
 113         .pbstat_addr    = BCOVE_PBSTATUS,
 114         .pbstat_mask    = BCOVE_PB_LEVEL,
 115         .setup  = mrfld_setup,
 116 };
 117
 118 static const struct x86_cpu_id mid_pb_cpu_ids[] = {
 119         X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_MID,   &mfld_ddata),
 120         X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &mrfld_ddata),
 121         {}
 122 };
 123
 124 static int mid_pb_probe(struct platform_device *pdev)
 125 {
 126         const struct x86_cpu_id *id;
 127         struct mid_pb_ddata *ddata;
 128         struct input_dev *input;
 129         int irq = platform_get_irq(pdev, 0);
 130         int error;
 131
 132         id = x86_match_cpu(mid_pb_cpu_ids);
 133         if (!id)
 134                 return -ENODEV;
 135
 136         if (irq < 0) {
 137                 dev_err(&pdev->dev, "Failed to get IRQ: %d\n", irq);
 138                 return irq;
 139         }
 140
 141         input = devm_input_allocate_device(&pdev->dev);
 142         if (!input)
 143                 return -ENOMEM;
 144
 145         input->name = pdev->name;
 146         input->phys = "power-button/input0";
 147         input->id.bustype = BUS_HOST;
 148         input->dev.parent = &pdev->dev;
 149
 150         input_set_capability(input, EV_KEY, KEY_POWER);
 151
 152         ddata = devm_kmemdup(&pdev->dev, (void *)id->driver_data,
 153                              sizeof(*ddata), GFP_KERNEL);
 154         if (!ddata)
 155                 return -ENOMEM;
 156
 157         ddata->dev = &pdev->dev;
 158         ddata->irq = irq;
 159         ddata->input = input;
 160
 161         if (ddata->setup) {
 162                 error = ddata->setup(ddata);
 163                 if (error)
 164                         return error;
 165         }
 166
 167         ddata->scu = devm_intel_scu_ipc_dev_get(&pdev->dev);
 168         if (!ddata->scu)
 169                 return -EPROBE_DEFER;
 170
 171         error = devm_request_threaded_irq(&pdev->dev, irq, NULL, mid_pb_isr,
 172                                           IRQF_ONESHOT, DRIVER_NAME, ddata);
 173         if (error) {
 174                 dev_err(&pdev->dev,
 175                         "Unable to request irq %d for MID power button\n", irq);
 176                 return error;
 177         }
 178
 179         error = input_register_device(input);
 180         if (error) {
 181                 dev_err(&pdev->dev,
 182                         "Unable to register input dev, error %d\n", error);
 183                 return error;
 184         }
 185
 186         platform_set_drvdata(pdev, ddata);
 187
 188         /*
 189          * SCU firmware might send power button interrupts to IA core before
 190          * kernel boots and doesn't get EOI from IA core. The first bit of
 191          * MSIC reg 0x21 is kept masked, and SCU firmware doesn't send new
 192          * power interrupt to Android kernel. Unmask the bit when probing
 193          * power button in kernel.
 194          * There is a very narrow race between irq handler and power button
 195          * initialization. The race happens rarely. So we needn't worry
 196          * about it.
 197          */
 198         error = mid_irq_ack(ddata);
 199         if (error) {
 200                 dev_err(&pdev->dev,
 201                         "Unable to clear power button interrupt, error: %d\n",
 202                         error);
 203                 return error;
 204         }
 205
 206         device_init_wakeup(&pdev->dev, true);
 207         dev_pm_set_wake_irq(&pdev->dev, irq);
 208
 209         return 0;
 210 }
 211
 212 static int mid_pb_remove(struct platform_device *pdev)
 213 {
 214         dev_pm_clear_wake_irq(&pdev->dev);
 215         device_init_wakeup(&pdev->dev, false);
 216
 217         return 0;
 218 }
 219
 220 static struct platform_driver mid_pb_driver = {
 221         .driver = {
 222                 .name = DRIVER_NAME,
 223         },
 224         .probe  = mid_pb_probe,
 225         .remove = mid_pb_remove,
 226 };
 227
 228 module_platform_driver(mid_pb_driver);
 229
 230 MODULE_AUTHOR("Hong Liu <hong.liu@intel.com>");
 231 MODULE_DESCRIPTION("Intel MID Power Button Driver");
 232 MODULE_LICENSE("GPL v2");
 233 MODULE_ALIAS("platform:" DRIVER_NAME);