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Merge tag 'regmap-fix-v5.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_nx2.c
blob68a16c95dcb77a4551f6d03187700f93f064e576
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6
7 #include <linux/vmalloc.h>
8 #include <linux/delay.h>
9
10 #include "qla_def.h"
11 #include "qla_gbl.h"
12
13 #define TIMEOUT_100_MS 100
14
15 static const uint32_t qla8044_reg_tbl[] = {
16 QLA8044_PEG_HALT_STATUS1,
17 QLA8044_PEG_HALT_STATUS2,
18 QLA8044_PEG_ALIVE_COUNTER,
19 QLA8044_CRB_DRV_ACTIVE,
20 QLA8044_CRB_DEV_STATE,
21 QLA8044_CRB_DRV_STATE,
22 QLA8044_CRB_DRV_SCRATCH,
23 QLA8044_CRB_DEV_PART_INFO1,
24 QLA8044_CRB_IDC_VER_MAJOR,
25 QLA8044_FW_VER_MAJOR,
26 QLA8044_FW_VER_MINOR,
27 QLA8044_FW_VER_SUB,
28 QLA8044_CMDPEG_STATE,
29 QLA8044_ASIC_TEMP,
30 };
31
32 /* 8044 Flash Read/Write functions */
33 uint32_t
34 qla8044_rd_reg(struct qla_hw_data *ha, ulong addr)
35 {
36 return readl((void __iomem *) (ha->nx_pcibase + addr));
37 }
38
39 void
40 qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val)
41 {
42 writel(val, (void __iomem *)((ha)->nx_pcibase + addr));
43 }
44
45 int
46 qla8044_rd_direct(struct scsi_qla_host *vha,
47 const uint32_t crb_reg)
48 {
49 struct qla_hw_data *ha = vha->hw;
50
51 if (crb_reg < CRB_REG_INDEX_MAX)
52 return qla8044_rd_reg(ha, qla8044_reg_tbl[crb_reg]);
53 else
54 return QLA_FUNCTION_FAILED;
55 }
56
57 void
58 qla8044_wr_direct(struct scsi_qla_host *vha,
59 const uint32_t crb_reg,
60 const uint32_t value)
61 {
62 struct qla_hw_data *ha = vha->hw;
63
64 if (crb_reg < CRB_REG_INDEX_MAX)
65 qla8044_wr_reg(ha, qla8044_reg_tbl[crb_reg], value);
66 }
67
68 static int
69 qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr)
70 {
71 uint32_t val;
72 int ret_val = QLA_SUCCESS;
73 struct qla_hw_data *ha = vha->hw;
74
75 qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr);
76 val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum));
77
78 if (val != addr) {
79 ql_log(ql_log_warn, vha, 0xb087,
80 "%s: Failed to set register window : "
81 "addr written 0x%x, read 0x%x!\n",
82 __func__, addr, val);
83 ret_val = QLA_FUNCTION_FAILED;
84 }
85 return ret_val;
86 }
87
88 static int
89 qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
90 {
91 int ret_val = QLA_SUCCESS;
92 struct qla_hw_data *ha = vha->hw;
93
94 ret_val = qla8044_set_win_base(vha, addr);
95 if (!ret_val)
96 *data = qla8044_rd_reg(ha, QLA8044_WILDCARD);
97 else
98 ql_log(ql_log_warn, vha, 0xb088,
99 "%s: failed read of addr 0x%x!\n", __func__, addr);
100 return ret_val;
101 }
102
103 static int
104 qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
105 {
106 int ret_val = QLA_SUCCESS;
107 struct qla_hw_data *ha = vha->hw;
108
109 ret_val = qla8044_set_win_base(vha, addr);
110 if (!ret_val)
111 qla8044_wr_reg(ha, QLA8044_WILDCARD, data);
112 else
113 ql_log(ql_log_warn, vha, 0xb089,
114 "%s: failed wrt to addr 0x%x, data 0x%x\n",
115 __func__, addr, data);
116 return ret_val;
117 }
118
119 /*
120 * qla8044_read_write_crb_reg - Read from raddr and write value to waddr.
121 *
122 * @ha : Pointer to adapter structure
123 * @raddr : CRB address to read from
124 * @waddr : CRB address to write to
125 *
126 */
127 static void
128 qla8044_read_write_crb_reg(struct scsi_qla_host *vha,
129 uint32_t raddr, uint32_t waddr)
130 {
131 uint32_t value;
132
133 qla8044_rd_reg_indirect(vha, raddr, &value);
134 qla8044_wr_reg_indirect(vha, waddr, value);
135 }
136
137 static int
138 qla8044_poll_wait_for_ready(struct scsi_qla_host *vha, uint32_t addr1,
139 uint32_t mask)
140 {
141 unsigned long timeout;
142 uint32_t temp = 0;
143
144 /* jiffies after 100ms */
145 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
146 do {
147 qla8044_rd_reg_indirect(vha, addr1, &temp);
148 if ((temp & mask) != 0)
149 break;
150 if (time_after_eq(jiffies, timeout)) {
151 ql_log(ql_log_warn, vha, 0xb151,
152 "Error in processing rdmdio entry\n");
153 return -1;
154 }
155 } while (1);
156
157 return 0;
158 }
159
160 static uint32_t
161 qla8044_ipmdio_rd_reg(struct scsi_qla_host *vha,
162 uint32_t addr1, uint32_t addr3, uint32_t mask, uint32_t addr)
163 {
164 uint32_t temp;
165 int ret = 0;
166
167 ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
168 if (ret == -1)
169 return -1;
170
171 temp = (0x40000000 | addr);
172 qla8044_wr_reg_indirect(vha, addr1, temp);
173
174 ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
175 if (ret == -1)
176 return 0;
177
178 qla8044_rd_reg_indirect(vha, addr3, &ret);
179
180 return ret;
181 }
182
183
184 static int
185 qla8044_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *vha,
186 uint32_t addr1, uint32_t addr2, uint32_t addr3, uint32_t mask)
187 {
188 unsigned long timeout;
189 uint32_t temp;
190
191 /* jiffies after 100 msecs */
192 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
193 do {
194 temp = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr2);
195 if ((temp & 0x1) != 1)
196 break;
197 if (time_after_eq(jiffies, timeout)) {
198 ql_log(ql_log_warn, vha, 0xb152,
199 "Error in processing mdiobus idle\n");
200 return -1;
201 }
202 } while (1);
203
204 return 0;
205 }
206
207 static int
208 qla8044_ipmdio_wr_reg(struct scsi_qla_host *vha, uint32_t addr1,
209 uint32_t addr3, uint32_t mask, uint32_t addr, uint32_t value)
210 {
211 int ret = 0;
212
213 ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
214 if (ret == -1)
215 return -1;
216
217 qla8044_wr_reg_indirect(vha, addr3, value);
218 qla8044_wr_reg_indirect(vha, addr1, addr);
219
220 ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
221 if (ret == -1)
222 return -1;
223
224 return 0;
225 }
226 /*
227 * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask,
228 * Shift Left,Right/OR/XOR with values RMW header and write value to waddr.
229 *
230 * @vha : Pointer to adapter structure
231 * @raddr : CRB address to read from
232 * @waddr : CRB address to write to
233 * @p_rmw_hdr : header with shift/or/xor values.
234 *
235 */
236 static void
237 qla8044_rmw_crb_reg(struct scsi_qla_host *vha,
238 uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr)
239 {
240 uint32_t value;
241
242 if (p_rmw_hdr->index_a)
243 value = vha->reset_tmplt.array[p_rmw_hdr->index_a];
244 else
245 qla8044_rd_reg_indirect(vha, raddr, &value);
246 value &= p_rmw_hdr->test_mask;
247 value <<= p_rmw_hdr->shl;
248 value >>= p_rmw_hdr->shr;
249 value |= p_rmw_hdr->or_value;
250 value ^= p_rmw_hdr->xor_value;
251 qla8044_wr_reg_indirect(vha, waddr, value);
252 return;
253 }
254
255 static inline void
256 qla8044_set_qsnt_ready(struct scsi_qla_host *vha)
257 {
258 uint32_t qsnt_state;
259 struct qla_hw_data *ha = vha->hw;
260
261 qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
262 qsnt_state |= (1 << ha->portnum);
263 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
264 ql_log(ql_log_info, vha, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n",
265 __func__, vha->host_no, qsnt_state);
266 }
267
268 void
269 qla8044_clear_qsnt_ready(struct scsi_qla_host *vha)
270 {
271 uint32_t qsnt_state;
272 struct qla_hw_data *ha = vha->hw;
273
274 qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
275 qsnt_state &= ~(1 << ha->portnum);
276 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
277 ql_log(ql_log_info, vha, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n",
278 __func__, vha->host_no, qsnt_state);
279 }
280
281 /**
282 * qla8044_lock_recovery - Recovers the idc_lock.
283 * @vha : Pointer to adapter structure
284 *
285 * Lock Recovery Register
286 * 5-2 Lock recovery owner: Function ID of driver doing lock recovery,
287 * valid if bits 1..0 are set by driver doing lock recovery.
288 * 1-0 1 - Driver intends to force unlock the IDC lock.
289 * 2 - Driver is moving forward to unlock the IDC lock. Driver clears
290 * this field after force unlocking the IDC lock.
291 *
292 * Lock Recovery process
293 * a. Read the IDC_LOCK_RECOVERY register. If the value in bits 1..0 is
294 * greater than 0, then wait for the other driver to unlock otherwise
295 * move to the next step.
296 * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY
297 * register bits 1..0 and also set the function# in bits 5..2.
298 * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms.
299 * Wait for the other driver to perform lock recovery if the function
300 * number in bits 5..2 has changed, otherwise move to the next step.
301 * d. Write a value of 2h to the IDC_LOCK_RECOVERY register bits 1..0
302 * leaving your function# in bits 5..2.
303 * e. Force unlock using the DRIVER_UNLOCK register and immediately clear
304 * the IDC_LOCK_RECOVERY bits 5..0 by writing 0.
305 **/
306 static int
307 qla8044_lock_recovery(struct scsi_qla_host *vha)
308 {
309 uint32_t lock = 0, lockid;
310 struct qla_hw_data *ha = vha->hw;
311
312 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
313
314 /* Check for other Recovery in progress, go wait */
315 if ((lockid & IDC_LOCK_RECOVERY_STATE_MASK) != 0)
316 return QLA_FUNCTION_FAILED;
317
318 /* Intent to Recover */
319 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
320 (ha->portnum <<
321 IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | INTENT_TO_RECOVER);
322 msleep(200);
323
324 /* Check Intent to Recover is advertised */
325 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
326 if ((lockid & IDC_LOCK_RECOVERY_OWNER_MASK) != (ha->portnum <<
327 IDC_LOCK_RECOVERY_STATE_SHIFT_BITS))
328 return QLA_FUNCTION_FAILED;
329
330 ql_dbg(ql_dbg_p3p, vha, 0xb08B, "%s:%d: IDC Lock recovery initiated\n"
331 , __func__, ha->portnum);
332
333 /* Proceed to Recover */
334 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
335 (ha->portnum << IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) |
336 PROCEED_TO_RECOVER);
337
338 /* Force Unlock() */
339 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, 0xFF);
340 qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
341
342 /* Clear bits 0-5 in IDC_RECOVERY register*/
343 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 0);
344
345 /* Get lock() */
346 lock = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
347 if (lock) {
348 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
349 lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->portnum;
350 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lockid);
351 return QLA_SUCCESS;
352 } else
353 return QLA_FUNCTION_FAILED;
354 }
355
356 int
357 qla8044_idc_lock(struct qla_hw_data *ha)
358 {
359 uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0;
360 uint32_t lock_id, lock_cnt, func_num, tmo_owner = 0, first_owner = 0;
361 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
362
363 while (status == 0) {
364 /* acquire semaphore5 from PCI HW block */
365 status = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
366
367 if (status) {
368 /* Increment Counter (8-31) and update func_num (0-7) on
369 * getting a successful lock */
370 lock_id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
371 lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->portnum;
372 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lock_id);
373 break;
374 }
375
376 if (timeout == 0)
377 first_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
378
379 if (++timeout >=
380 (QLA8044_DRV_LOCK_TIMEOUT / QLA8044_DRV_LOCK_MSLEEP)) {
381 tmo_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
382 func_num = tmo_owner & 0xFF;
383 lock_cnt = tmo_owner >> 8;
384 ql_log(ql_log_warn, vha, 0xb114,
385 "%s: Lock by func %d failed after 2s, lock held "
386 "by func %d, lock count %d, first_owner %d\n",
387 __func__, ha->portnum, func_num, lock_cnt,
388 (first_owner & 0xFF));
389 if (first_owner != tmo_owner) {
390 /* Some other driver got lock,
391 * OR same driver got lock again (counter
392 * value changed), when we were waiting for
393 * lock. Retry for another 2 sec */
394 ql_dbg(ql_dbg_p3p, vha, 0xb115,
395 "%s: %d: IDC lock failed\n",
396 __func__, ha->portnum);
397 timeout = 0;
398 } else {
399 /* Same driver holding lock > 2sec.
400 * Force Recovery */
401 if (qla8044_lock_recovery(vha) == QLA_SUCCESS) {
402 /* Recovered and got lock */
403 ret_val = QLA_SUCCESS;
404 ql_dbg(ql_dbg_p3p, vha, 0xb116,
405 "%s:IDC lock Recovery by %d"
406 "successful...\n", __func__,
407 ha->portnum);
408 }
409 /* Recovery Failed, some other function
410 * has the lock, wait for 2secs
411 * and retry
412 */
413 ql_dbg(ql_dbg_p3p, vha, 0xb08a,
414 "%s: IDC lock Recovery by %d "
415 "failed, Retrying timeout\n", __func__,
416 ha->portnum);
417 timeout = 0;
418 }
419 }
420 msleep(QLA8044_DRV_LOCK_MSLEEP);
421 }
422 return ret_val;
423 }
424
425 void
426 qla8044_idc_unlock(struct qla_hw_data *ha)
427 {
428 int id;
429 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
430
431 id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
432
433 if ((id & 0xFF) != ha->portnum) {
434 ql_log(ql_log_warn, vha, 0xb118,
435 "%s: IDC Unlock by %d failed, lock owner is %d!\n",
436 __func__, ha->portnum, (id & 0xFF));
437 return;
438 }
439
440 /* Keep lock counter value, update the ha->func_num to 0xFF */
441 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, (id | 0xFF));
442 qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
443 }
444
445 /* 8044 Flash Lock/Unlock functions */
446 static int
447 qla8044_flash_lock(scsi_qla_host_t *vha)
448 {
449 int lock_owner;
450 int timeout = 0;
451 uint32_t lock_status = 0;
452 int ret_val = QLA_SUCCESS;
453 struct qla_hw_data *ha = vha->hw;
454
455 while (lock_status == 0) {
456 lock_status = qla8044_rd_reg(ha, QLA8044_FLASH_LOCK);
457 if (lock_status)
458 break;
459
460 if (++timeout >= QLA8044_FLASH_LOCK_TIMEOUT / 20) {
461 lock_owner = qla8044_rd_reg(ha,
462 QLA8044_FLASH_LOCK_ID);
463 ql_log(ql_log_warn, vha, 0xb113,
464 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
465 __func__, ha->portnum, lock_owner);
466 ret_val = QLA_FUNCTION_FAILED;
467 break;
468 }
469 msleep(20);
470 }
471 qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, ha->portnum);
472 return ret_val;
473 }
474
475 static void
476 qla8044_flash_unlock(scsi_qla_host_t *vha)
477 {
478 struct qla_hw_data *ha = vha->hw;
479
480 /* Reading FLASH_UNLOCK register unlocks the Flash */
481 qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, 0xFF);
482 qla8044_rd_reg(ha, QLA8044_FLASH_UNLOCK);
483 }
484
485
486 static
487 void qla8044_flash_lock_recovery(struct scsi_qla_host *vha)
488 {
489
490 if (qla8044_flash_lock(vha)) {
491 /* Someone else is holding the lock. */
492 ql_log(ql_log_warn, vha, 0xb120, "Resetting flash_lock\n");
493 }
494
495 /*
496 * Either we got the lock, or someone
497 * else died while holding it.
498 * In either case, unlock.
499 */
500 qla8044_flash_unlock(vha);
501 }
502
503 /*
504 * Address and length are byte address
505 */
506 static int
507 qla8044_read_flash_data(scsi_qla_host_t *vha, uint8_t *p_data,
508 uint32_t flash_addr, int u32_word_count)
509 {
510 int i, ret_val = QLA_SUCCESS;
511 uint32_t u32_word;
512
513 if (qla8044_flash_lock(vha) != QLA_SUCCESS) {
514 ret_val = QLA_FUNCTION_FAILED;
515 goto exit_lock_error;
516 }
517
518 if (flash_addr & 0x03) {
519 ql_log(ql_log_warn, vha, 0xb117,
520 "%s: Illegal addr = 0x%x\n", __func__, flash_addr);
521 ret_val = QLA_FUNCTION_FAILED;
522 goto exit_flash_read;
523 }
524
525 for (i = 0; i < u32_word_count; i++) {
526 if (qla8044_wr_reg_indirect(vha, QLA8044_FLASH_DIRECT_WINDOW,
527 (flash_addr & 0xFFFF0000))) {
528 ql_log(ql_log_warn, vha, 0xb119,
529 "%s: failed to write addr 0x%x to "
530 "FLASH_DIRECT_WINDOW\n! ",
531 __func__, flash_addr);
532 ret_val = QLA_FUNCTION_FAILED;
533 goto exit_flash_read;
534 }
535
536 ret_val = qla8044_rd_reg_indirect(vha,
537 QLA8044_FLASH_DIRECT_DATA(flash_addr),
538 &u32_word);
539 if (ret_val != QLA_SUCCESS) {
540 ql_log(ql_log_warn, vha, 0xb08c,
541 "%s: failed to read addr 0x%x!\n",
542 __func__, flash_addr);
543 goto exit_flash_read;
544 }
545
546 *(uint32_t *)p_data = u32_word;
547 p_data = p_data + 4;
548 flash_addr = flash_addr + 4;
549 }
550
551 exit_flash_read:
552 qla8044_flash_unlock(vha);
553
554 exit_lock_error:
555 return ret_val;
556 }
557
558 /*
559 * Address and length are byte address
560 */
561 void *
562 qla8044_read_optrom_data(struct scsi_qla_host *vha, void *buf,
563 uint32_t offset, uint32_t length)
564 {
565 scsi_block_requests(vha->host);
566 if (qla8044_read_flash_data(vha, buf, offset, length / 4)
567 != QLA_SUCCESS) {
568 ql_log(ql_log_warn, vha, 0xb08d,
569 "%s: Failed to read from flash\n",
570 __func__);
571 }
572 scsi_unblock_requests(vha->host);
573 return buf;
574 }
575
576 static inline int
577 qla8044_need_reset(struct scsi_qla_host *vha)
578 {
579 uint32_t drv_state, drv_active;
580 int rval;
581 struct qla_hw_data *ha = vha->hw;
582
583 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
584 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
585
586 rval = drv_state & (1 << ha->portnum);
587
588 if (ha->flags.eeh_busy && drv_active)
589 rval = 1;
590 return rval;
591 }
592
593 /*
594 * qla8044_write_list - Write the value (p_entry->arg2) to address specified
595 * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between
596 * entries.
597 *
598 * @vha : Pointer to adapter structure
599 * @p_hdr : reset_entry header for WRITE_LIST opcode.
600 *
601 */
602 static void
603 qla8044_write_list(struct scsi_qla_host *vha,
604 struct qla8044_reset_entry_hdr *p_hdr)
605 {
606 struct qla8044_entry *p_entry;
607 uint32_t i;
608
609 p_entry = (struct qla8044_entry *)((char *)p_hdr +
610 sizeof(struct qla8044_reset_entry_hdr));
611
612 for (i = 0; i < p_hdr->count; i++, p_entry++) {
613 qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2);
614 if (p_hdr->delay)
615 udelay((uint32_t)(p_hdr->delay));
616 }
617 }
618
619 /*
620 * qla8044_read_write_list - Read from address specified by p_entry->arg1,
621 * write value read to address specified by p_entry->arg2, for all entries in
622 * header with delay of p_hdr->delay between entries.
623 *
624 * @vha : Pointer to adapter structure
625 * @p_hdr : reset_entry header for READ_WRITE_LIST opcode.
626 *
627 */
628 static void
629 qla8044_read_write_list(struct scsi_qla_host *vha,
630 struct qla8044_reset_entry_hdr *p_hdr)
631 {
632 struct qla8044_entry *p_entry;
633 uint32_t i;
634
635 p_entry = (struct qla8044_entry *)((char *)p_hdr +
636 sizeof(struct qla8044_reset_entry_hdr));
637
638 for (i = 0; i < p_hdr->count; i++, p_entry++) {
639 qla8044_read_write_crb_reg(vha, p_entry->arg1,
640 p_entry->arg2);
641 if (p_hdr->delay)
642 udelay((uint32_t)(p_hdr->delay));
643 }
644 }
645
646 /*
647 * qla8044_poll_reg - Poll the given CRB addr for duration msecs till
648 * value read ANDed with test_mask is equal to test_result.
649 *
650 * @ha : Pointer to adapter structure
651 * @addr : CRB register address
652 * @duration : Poll for total of "duration" msecs
653 * @test_mask : Mask value read with "test_mask"
654 * @test_result : Compare (value&test_mask) with test_result.
655 *
656 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
657 */
658 static int
659 qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr,
660 int duration, uint32_t test_mask, uint32_t test_result)
661 {
662 uint32_t value = 0;
663 int timeout_error;
664 uint8_t retries;
665 int ret_val = QLA_SUCCESS;
666
667 ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
668 if (ret_val == QLA_FUNCTION_FAILED) {
669 timeout_error = 1;
670 goto exit_poll_reg;
671 }
672
673 /* poll every 1/10 of the total duration */
674 retries = duration/10;
675
676 do {
677 if ((value & test_mask) != test_result) {
678 timeout_error = 1;
679 msleep(duration/10);
680 ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
681 if (ret_val == QLA_FUNCTION_FAILED) {
682 timeout_error = 1;
683 goto exit_poll_reg;
684 }
685 } else {
686 timeout_error = 0;
687 break;
688 }
689 } while (retries--);
690
691 exit_poll_reg:
692 if (timeout_error) {
693 vha->reset_tmplt.seq_error++;
694 ql_log(ql_log_fatal, vha, 0xb090,
695 "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n",
696 __func__, value, test_mask, test_result);
697 }
698
699 return timeout_error;
700 }
701
702 /*
703 * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB
704 * register specified by p_entry->arg1 and compare (value AND test_mask) with
705 * test_result to validate it. Wait for p_hdr->delay between processing entries.
706 *
707 * @ha : Pointer to adapter structure
708 * @p_hdr : reset_entry header for POLL_LIST opcode.
709 *
710 */
711 static void
712 qla8044_poll_list(struct scsi_qla_host *vha,
713 struct qla8044_reset_entry_hdr *p_hdr)
714 {
715 long delay;
716 struct qla8044_entry *p_entry;
717 struct qla8044_poll *p_poll;
718 uint32_t i;
719 uint32_t value;
720
721 p_poll = (struct qla8044_poll *)
722 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
723
724 /* Entries start after 8 byte qla8044_poll, poll header contains
725 * the test_mask, test_value.
726 */
727 p_entry = (struct qla8044_entry *)((char *)p_poll +
728 sizeof(struct qla8044_poll));
729
730 delay = (long)p_hdr->delay;
731
732 if (!delay) {
733 for (i = 0; i < p_hdr->count; i++, p_entry++)
734 qla8044_poll_reg(vha, p_entry->arg1,
735 delay, p_poll->test_mask, p_poll->test_value);
736 } else {
737 for (i = 0; i < p_hdr->count; i++, p_entry++) {
738 if (delay) {
739 if (qla8044_poll_reg(vha,
740 p_entry->arg1, delay,
741 p_poll->test_mask,
742 p_poll->test_value)) {
743 /*If
744 * (data_read&test_mask != test_value)
745 * read TIMEOUT_ADDR (arg1) and
746 * ADDR (arg2) registers
747 */
748 qla8044_rd_reg_indirect(vha,
749 p_entry->arg1, &value);
750 qla8044_rd_reg_indirect(vha,
751 p_entry->arg2, &value);
752 }
753 }
754 }
755 }
756 }
757
758 /*
759 * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr,
760 * read ar_addr, if (value& test_mask != test_mask) re-read till timeout
761 * expires.
762 *
763 * @vha : Pointer to adapter structure
764 * @p_hdr : reset entry header for POLL_WRITE_LIST opcode.
765 *
766 */
767 static void
768 qla8044_poll_write_list(struct scsi_qla_host *vha,
769 struct qla8044_reset_entry_hdr *p_hdr)
770 {
771 long delay;
772 struct qla8044_quad_entry *p_entry;
773 struct qla8044_poll *p_poll;
774 uint32_t i;
775
776 p_poll = (struct qla8044_poll *)((char *)p_hdr +
777 sizeof(struct qla8044_reset_entry_hdr));
778
779 p_entry = (struct qla8044_quad_entry *)((char *)p_poll +
780 sizeof(struct qla8044_poll));
781
782 delay = (long)p_hdr->delay;
783
784 for (i = 0; i < p_hdr->count; i++, p_entry++) {
785 qla8044_wr_reg_indirect(vha,
786 p_entry->dr_addr, p_entry->dr_value);
787 qla8044_wr_reg_indirect(vha,
788 p_entry->ar_addr, p_entry->ar_value);
789 if (delay) {
790 if (qla8044_poll_reg(vha,
791 p_entry->ar_addr, delay,
792 p_poll->test_mask,
793 p_poll->test_value)) {
794 ql_dbg(ql_dbg_p3p, vha, 0xb091,
795 "%s: Timeout Error: poll list, ",
796 __func__);
797 ql_dbg(ql_dbg_p3p, vha, 0xb092,
798 "item_num %d, entry_num %d\n", i,
799 vha->reset_tmplt.seq_index);
800 }
801 }
802 }
803 }
804
805 /*
806 * qla8044_read_modify_write - Read value from p_entry->arg1, modify the
807 * value, write value to p_entry->arg2. Process entries with p_hdr->delay
808 * between entries.
809 *
810 * @vha : Pointer to adapter structure
811 * @p_hdr : header with shift/or/xor values.
812 *
813 */
814 static void
815 qla8044_read_modify_write(struct scsi_qla_host *vha,
816 struct qla8044_reset_entry_hdr *p_hdr)
817 {
818 struct qla8044_entry *p_entry;
819 struct qla8044_rmw *p_rmw_hdr;
820 uint32_t i;
821
822 p_rmw_hdr = (struct qla8044_rmw *)((char *)p_hdr +
823 sizeof(struct qla8044_reset_entry_hdr));
824
825 p_entry = (struct qla8044_entry *)((char *)p_rmw_hdr +
826 sizeof(struct qla8044_rmw));
827
828 for (i = 0; i < p_hdr->count; i++, p_entry++) {
829 qla8044_rmw_crb_reg(vha, p_entry->arg1,
830 p_entry->arg2, p_rmw_hdr);
831 if (p_hdr->delay)
832 udelay((uint32_t)(p_hdr->delay));
833 }
834 }
835
836 /*
837 * qla8044_pause - Wait for p_hdr->delay msecs, called between processing
838 * two entries of a sequence.
839 *
840 * @vha : Pointer to adapter structure
841 * @p_hdr : Common reset entry header.
842 *
843 */
844 static
845 void qla8044_pause(struct scsi_qla_host *vha,
846 struct qla8044_reset_entry_hdr *p_hdr)
847 {
848 if (p_hdr->delay)
849 mdelay((uint32_t)((long)p_hdr->delay));
850 }
851
852 /*
853 * qla8044_template_end - Indicates end of reset sequence processing.
854 *
855 * @vha : Pointer to adapter structure
856 * @p_hdr : Common reset entry header.
857 *
858 */
859 static void
860 qla8044_template_end(struct scsi_qla_host *vha,
861 struct qla8044_reset_entry_hdr *p_hdr)
862 {
863 vha->reset_tmplt.template_end = 1;
864
865 if (vha->reset_tmplt.seq_error == 0) {
866 ql_dbg(ql_dbg_p3p, vha, 0xb093,
867 "%s: Reset sequence completed SUCCESSFULLY.\n", __func__);
868 } else {
869 ql_log(ql_log_fatal, vha, 0xb094,
870 "%s: Reset sequence completed with some timeout "
871 "errors.\n", __func__);
872 }
873 }
874
875 /*
876 * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr,
877 * if (value & test_mask != test_value) re-read till timeout value expires,
878 * read dr_addr register and assign to reset_tmplt.array.
879 *
880 * @vha : Pointer to adapter structure
881 * @p_hdr : Common reset entry header.
882 *
883 */
884 static void
885 qla8044_poll_read_list(struct scsi_qla_host *vha,
886 struct qla8044_reset_entry_hdr *p_hdr)
887 {
888 long delay;
889 int index;
890 struct qla8044_quad_entry *p_entry;
891 struct qla8044_poll *p_poll;
892 uint32_t i;
893 uint32_t value;
894
895 p_poll = (struct qla8044_poll *)
896 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
897
898 p_entry = (struct qla8044_quad_entry *)
899 ((char *)p_poll + sizeof(struct qla8044_poll));
900
901 delay = (long)p_hdr->delay;
902
903 for (i = 0; i < p_hdr->count; i++, p_entry++) {
904 qla8044_wr_reg_indirect(vha, p_entry->ar_addr,
905 p_entry->ar_value);
906 if (delay) {
907 if (qla8044_poll_reg(vha, p_entry->ar_addr, delay,
908 p_poll->test_mask, p_poll->test_value)) {
909 ql_dbg(ql_dbg_p3p, vha, 0xb095,
910 "%s: Timeout Error: poll "
911 "list, ", __func__);
912 ql_dbg(ql_dbg_p3p, vha, 0xb096,
913 "Item_num %d, "
914 "entry_num %d\n", i,
915 vha->reset_tmplt.seq_index);
916 } else {
917 index = vha->reset_tmplt.array_index;
918 qla8044_rd_reg_indirect(vha,
919 p_entry->dr_addr, &value);
920 vha->reset_tmplt.array[index++] = value;
921 if (index == QLA8044_MAX_RESET_SEQ_ENTRIES)
922 vha->reset_tmplt.array_index = 1;
923 }
924 }
925 }
926 }
927
928 /*
929 * qla8031_process_reset_template - Process all entries in reset template
930 * till entry with SEQ_END opcode, which indicates end of the reset template
931 * processing. Each entry has a Reset Entry header, entry opcode/command, with
932 * size of the entry, number of entries in sub-sequence and delay in microsecs
933 * or timeout in millisecs.
934 *
935 * @ha : Pointer to adapter structure
936 * @p_buff : Common reset entry header.
937 *
938 */
939 static void
940 qla8044_process_reset_template(struct scsi_qla_host *vha,
941 char *p_buff)
942 {
943 int index, entries;
944 struct qla8044_reset_entry_hdr *p_hdr;
945 char *p_entry = p_buff;
946
947 vha->reset_tmplt.seq_end = 0;
948 vha->reset_tmplt.template_end = 0;
949 entries = vha->reset_tmplt.hdr->entries;
950 index = vha->reset_tmplt.seq_index;
951
952 for (; (!vha->reset_tmplt.seq_end) && (index < entries); index++) {
953 p_hdr = (struct qla8044_reset_entry_hdr *)p_entry;
954 switch (p_hdr->cmd) {
955 case OPCODE_NOP:
956 break;
957 case OPCODE_WRITE_LIST:
958 qla8044_write_list(vha, p_hdr);
959 break;
960 case OPCODE_READ_WRITE_LIST:
961 qla8044_read_write_list(vha, p_hdr);
962 break;
963 case OPCODE_POLL_LIST:
964 qla8044_poll_list(vha, p_hdr);
965 break;
966 case OPCODE_POLL_WRITE_LIST:
967 qla8044_poll_write_list(vha, p_hdr);
968 break;
969 case OPCODE_READ_MODIFY_WRITE:
970 qla8044_read_modify_write(vha, p_hdr);
971 break;
972 case OPCODE_SEQ_PAUSE:
973 qla8044_pause(vha, p_hdr);
974 break;
975 case OPCODE_SEQ_END:
976 vha->reset_tmplt.seq_end = 1;
977 break;
978 case OPCODE_TMPL_END:
979 qla8044_template_end(vha, p_hdr);
980 break;
981 case OPCODE_POLL_READ_LIST:
982 qla8044_poll_read_list(vha, p_hdr);
983 break;
984 default:
985 ql_log(ql_log_fatal, vha, 0xb097,
986 "%s: Unknown command ==> 0x%04x on "
987 "entry = %d\n", __func__, p_hdr->cmd, index);
988 break;
989 }
990 /*
991 *Set pointer to next entry in the sequence.
992 */
993 p_entry += p_hdr->size;
994 }
995 vha->reset_tmplt.seq_index = index;
996 }
997
998 static void
999 qla8044_process_init_seq(struct scsi_qla_host *vha)
1000 {
1001 qla8044_process_reset_template(vha,
1002 vha->reset_tmplt.init_offset);
1003 if (vha->reset_tmplt.seq_end != 1)
1004 ql_log(ql_log_fatal, vha, 0xb098,
1005 "%s: Abrupt INIT Sub-Sequence end.\n",
1006 __func__);
1007 }
1008
1009 static void
1010 qla8044_process_stop_seq(struct scsi_qla_host *vha)
1011 {
1012 vha->reset_tmplt.seq_index = 0;
1013 qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset);
1014 if (vha->reset_tmplt.seq_end != 1)
1015 ql_log(ql_log_fatal, vha, 0xb099,
1016 "%s: Abrupt STOP Sub-Sequence end.\n", __func__);
1017 }
1018
1019 static void
1020 qla8044_process_start_seq(struct scsi_qla_host *vha)
1021 {
1022 qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset);
1023 if (vha->reset_tmplt.template_end != 1)
1024 ql_log(ql_log_fatal, vha, 0xb09a,
1025 "%s: Abrupt START Sub-Sequence end.\n",
1026 __func__);
1027 }
1028
1029 static int
1030 qla8044_lockless_flash_read_u32(struct scsi_qla_host *vha,
1031 uint32_t flash_addr, uint8_t *p_data, int u32_word_count)
1032 {
1033 uint32_t i;
1034 uint32_t u32_word;
1035 uint32_t flash_offset;
1036 uint32_t addr = flash_addr;
1037 int ret_val = QLA_SUCCESS;
1038
1039 flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1);
1040
1041 if (addr & 0x3) {
1042 ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n",
1043 __func__, addr);
1044 ret_val = QLA_FUNCTION_FAILED;
1045 goto exit_lockless_read;
1046 }
1047
1048 ret_val = qla8044_wr_reg_indirect(vha,
1049 QLA8044_FLASH_DIRECT_WINDOW, (addr));
1050
1051 if (ret_val != QLA_SUCCESS) {
1052 ql_log(ql_log_fatal, vha, 0xb09c,
1053 "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
1054 __func__, addr);
1055 goto exit_lockless_read;
1056 }
1057
1058 /* Check if data is spread across multiple sectors */
1059 if ((flash_offset + (u32_word_count * sizeof(uint32_t))) >
1060 (QLA8044_FLASH_SECTOR_SIZE - 1)) {
1061 /* Multi sector read */
1062 for (i = 0; i < u32_word_count; i++) {
1063 ret_val = qla8044_rd_reg_indirect(vha,
1064 QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
1065 if (ret_val != QLA_SUCCESS) {
1066 ql_log(ql_log_fatal, vha, 0xb09d,
1067 "%s: failed to read addr 0x%x!\n",
1068 __func__, addr);
1069 goto exit_lockless_read;
1070 }
1071 *(uint32_t *)p_data = u32_word;
1072 p_data = p_data + 4;
1073 addr = addr + 4;
1074 flash_offset = flash_offset + 4;
1075 if (flash_offset > (QLA8044_FLASH_SECTOR_SIZE - 1)) {
1076 /* This write is needed once for each sector */
1077 ret_val = qla8044_wr_reg_indirect(vha,
1078 QLA8044_FLASH_DIRECT_WINDOW, (addr));
1079 if (ret_val != QLA_SUCCESS) {
1080 ql_log(ql_log_fatal, vha, 0xb09f,
1081 "%s: failed to write addr "
1082 "0x%x to FLASH_DIRECT_WINDOW!\n",
1083 __func__, addr);
1084 goto exit_lockless_read;
1085 }
1086 flash_offset = 0;
1087 }
1088 }
1089 } else {
1090 /* Single sector read */
1091 for (i = 0; i < u32_word_count; i++) {
1092 ret_val = qla8044_rd_reg_indirect(vha,
1093 QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
1094 if (ret_val != QLA_SUCCESS) {
1095 ql_log(ql_log_fatal, vha, 0xb0a0,
1096 "%s: failed to read addr 0x%x!\n",
1097 __func__, addr);
1098 goto exit_lockless_read;
1099 }
1100 *(uint32_t *)p_data = u32_word;
1101 p_data = p_data + 4;
1102 addr = addr + 4;
1103 }
1104 }
1105
1106 exit_lockless_read:
1107 return ret_val;
1108 }
1109
1110 /*
1111 * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory
1112 *
1113 * @vha : Pointer to adapter structure
1114 * addr : Flash address to write to
1115 * data : Data to be written
1116 * count : word_count to be written
1117 *
1118 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1119 */
1120 static int
1121 qla8044_ms_mem_write_128b(struct scsi_qla_host *vha,
1122 uint64_t addr, uint32_t *data, uint32_t count)
1123 {
1124 int i, j, ret_val = QLA_SUCCESS;
1125 uint32_t agt_ctrl;
1126 unsigned long flags;
1127 struct qla_hw_data *ha = vha->hw;
1128
1129 /* Only 128-bit aligned access */
1130 if (addr & 0xF) {
1131 ret_val = QLA_FUNCTION_FAILED;
1132 goto exit_ms_mem_write;
1133 }
1134 write_lock_irqsave(&ha->hw_lock, flags);
1135
1136 /* Write address */
1137 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, 0);
1138 if (ret_val == QLA_FUNCTION_FAILED) {
1139 ql_log(ql_log_fatal, vha, 0xb0a1,
1140 "%s: write to AGT_ADDR_HI failed!\n", __func__);
1141 goto exit_ms_mem_write_unlock;
1142 }
1143
1144 for (i = 0; i < count; i++, addr += 16) {
1145 if (!((addr_in_range(addr, QLA8044_ADDR_QDR_NET,
1146 QLA8044_ADDR_QDR_NET_MAX)) ||
1147 (addr_in_range(addr, QLA8044_ADDR_DDR_NET,
1148 QLA8044_ADDR_DDR_NET_MAX)))) {
1149 ret_val = QLA_FUNCTION_FAILED;
1150 goto exit_ms_mem_write_unlock;
1151 }
1152
1153 ret_val = qla8044_wr_reg_indirect(vha,
1154 MD_MIU_TEST_AGT_ADDR_LO, addr);
1155
1156 /* Write data */
1157 ret_val += qla8044_wr_reg_indirect(vha,
1158 MD_MIU_TEST_AGT_WRDATA_LO, *data++);
1159 ret_val += qla8044_wr_reg_indirect(vha,
1160 MD_MIU_TEST_AGT_WRDATA_HI, *data++);
1161 ret_val += qla8044_wr_reg_indirect(vha,
1162 MD_MIU_TEST_AGT_WRDATA_ULO, *data++);
1163 ret_val += qla8044_wr_reg_indirect(vha,
1164 MD_MIU_TEST_AGT_WRDATA_UHI, *data++);
1165 if (ret_val == QLA_FUNCTION_FAILED) {
1166 ql_log(ql_log_fatal, vha, 0xb0a2,
1167 "%s: write to AGT_WRDATA failed!\n",
1168 __func__);
1169 goto exit_ms_mem_write_unlock;
1170 }
1171
1172 /* Check write status */
1173 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1174 MIU_TA_CTL_WRITE_ENABLE);
1175 ret_val += qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1176 MIU_TA_CTL_WRITE_START);
1177 if (ret_val == QLA_FUNCTION_FAILED) {
1178 ql_log(ql_log_fatal, vha, 0xb0a3,
1179 "%s: write to AGT_CTRL failed!\n", __func__);
1180 goto exit_ms_mem_write_unlock;
1181 }
1182
1183 for (j = 0; j < MAX_CTL_CHECK; j++) {
1184 ret_val = qla8044_rd_reg_indirect(vha,
1185 MD_MIU_TEST_AGT_CTRL, &agt_ctrl);
1186 if (ret_val == QLA_FUNCTION_FAILED) {
1187 ql_log(ql_log_fatal, vha, 0xb0a4,
1188 "%s: failed to read "
1189 "MD_MIU_TEST_AGT_CTRL!\n", __func__);
1190 goto exit_ms_mem_write_unlock;
1191 }
1192 if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
1193 break;
1194 }
1195
1196 /* Status check failed */
1197 if (j >= MAX_CTL_CHECK) {
1198 ql_log(ql_log_fatal, vha, 0xb0a5,
1199 "%s: MS memory write failed!\n",
1200 __func__);
1201 ret_val = QLA_FUNCTION_FAILED;
1202 goto exit_ms_mem_write_unlock;
1203 }
1204 }
1205
1206 exit_ms_mem_write_unlock:
1207 write_unlock_irqrestore(&ha->hw_lock, flags);
1208
1209 exit_ms_mem_write:
1210 return ret_val;
1211 }
1212
1213 static int
1214 qla8044_copy_bootloader(struct scsi_qla_host *vha)
1215 {
1216 uint8_t *p_cache;
1217 uint32_t src, count, size;
1218 uint64_t dest;
1219 int ret_val = QLA_SUCCESS;
1220 struct qla_hw_data *ha = vha->hw;
1221
1222 src = QLA8044_BOOTLOADER_FLASH_ADDR;
1223 dest = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_ADDR);
1224 size = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_SIZE);
1225
1226 /* 128 bit alignment check */
1227 if (size & 0xF)
1228 size = (size + 16) & ~0xF;
1229
1230 /* 16 byte count */
1231 count = size/16;
1232
1233 p_cache = vmalloc(size);
1234 if (p_cache == NULL) {
1235 ql_log(ql_log_fatal, vha, 0xb0a6,
1236 "%s: Failed to allocate memory for "
1237 "boot loader cache\n", __func__);
1238 ret_val = QLA_FUNCTION_FAILED;
1239 goto exit_copy_bootloader;
1240 }
1241
1242 ret_val = qla8044_lockless_flash_read_u32(vha, src,
1243 p_cache, size/sizeof(uint32_t));
1244 if (ret_val == QLA_FUNCTION_FAILED) {
1245 ql_log(ql_log_fatal, vha, 0xb0a7,
1246 "%s: Error reading F/W from flash!!!\n", __func__);
1247 goto exit_copy_error;
1248 }
1249 ql_dbg(ql_dbg_p3p, vha, 0xb0a8, "%s: Read F/W from flash!\n",
1250 __func__);
1251
1252 /* 128 bit/16 byte write to MS memory */
1253 ret_val = qla8044_ms_mem_write_128b(vha, dest,
1254 (uint32_t *)p_cache, count);
1255 if (ret_val == QLA_FUNCTION_FAILED) {
1256 ql_log(ql_log_fatal, vha, 0xb0a9,
1257 "%s: Error writing F/W to MS !!!\n", __func__);
1258 goto exit_copy_error;
1259 }
1260 ql_dbg(ql_dbg_p3p, vha, 0xb0aa,
1261 "%s: Wrote F/W (size %d) to MS !!!\n",
1262 __func__, size);
1263
1264 exit_copy_error:
1265 vfree(p_cache);
1266
1267 exit_copy_bootloader:
1268 return ret_val;
1269 }
1270
1271 static int
1272 qla8044_restart(struct scsi_qla_host *vha)
1273 {
1274 int ret_val = QLA_SUCCESS;
1275 struct qla_hw_data *ha = vha->hw;
1276
1277 qla8044_process_stop_seq(vha);
1278
1279 /* Collect minidump */
1280 if (ql2xmdenable)
1281 qla8044_get_minidump(vha);
1282 else
1283 ql_log(ql_log_fatal, vha, 0xb14c,
1284 "Minidump disabled.\n");
1285
1286 qla8044_process_init_seq(vha);
1287
1288 if (qla8044_copy_bootloader(vha)) {
1289 ql_log(ql_log_fatal, vha, 0xb0ab,
1290 "%s: Copy bootloader, firmware restart failed!\n",
1291 __func__);
1292 ret_val = QLA_FUNCTION_FAILED;
1293 goto exit_restart;
1294 }
1295
1296 /*
1297 * Loads F/W from flash
1298 */
1299 qla8044_wr_reg(ha, QLA8044_FW_IMAGE_VALID, QLA8044_BOOT_FROM_FLASH);
1300
1301 qla8044_process_start_seq(vha);
1302
1303 exit_restart:
1304 return ret_val;
1305 }
1306
1307 /*
1308 * qla8044_check_cmd_peg_status - Check peg status to see if Peg is
1309 * initialized.
1310 *
1311 * @ha : Pointer to adapter structure
1312 *
1313 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1314 */
1315 static int
1316 qla8044_check_cmd_peg_status(struct scsi_qla_host *vha)
1317 {
1318 uint32_t val, ret_val = QLA_FUNCTION_FAILED;
1319 int retries = CRB_CMDPEG_CHECK_RETRY_COUNT;
1320 struct qla_hw_data *ha = vha->hw;
1321
1322 do {
1323 val = qla8044_rd_reg(ha, QLA8044_CMDPEG_STATE);
1324 if (val == PHAN_INITIALIZE_COMPLETE) {
1325 ql_dbg(ql_dbg_p3p, vha, 0xb0ac,
1326 "%s: Command Peg initialization "
1327 "complete! state=0x%x\n", __func__, val);
1328 ret_val = QLA_SUCCESS;
1329 break;
1330 }
1331 msleep(CRB_CMDPEG_CHECK_DELAY);
1332 } while (--retries);
1333
1334 return ret_val;
1335 }
1336
1337 static int
1338 qla8044_start_firmware(struct scsi_qla_host *vha)
1339 {
1340 int ret_val = QLA_SUCCESS;
1341
1342 if (qla8044_restart(vha)) {
1343 ql_log(ql_log_fatal, vha, 0xb0ad,
1344 "%s: Restart Error!!!, Need Reset!!!\n",
1345 __func__);
1346 ret_val = QLA_FUNCTION_FAILED;
1347 goto exit_start_fw;
1348 } else
1349 ql_dbg(ql_dbg_p3p, vha, 0xb0af,
1350 "%s: Restart done!\n", __func__);
1351
1352 ret_val = qla8044_check_cmd_peg_status(vha);
1353 if (ret_val) {
1354 ql_log(ql_log_fatal, vha, 0xb0b0,
1355 "%s: Peg not initialized!\n", __func__);
1356 ret_val = QLA_FUNCTION_FAILED;
1357 }
1358
1359 exit_start_fw:
1360 return ret_val;
1361 }
1362
1363 void
1364 qla8044_clear_drv_active(struct qla_hw_data *ha)
1365 {
1366 uint32_t drv_active;
1367 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
1368
1369 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1370 drv_active &= ~(1 << (ha->portnum));
1371
1372 ql_log(ql_log_info, vha, 0xb0b1,
1373 "%s(%ld): drv_active: 0x%08x\n",
1374 __func__, vha->host_no, drv_active);
1375
1376 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1377 }
1378
1379 /*
1380 * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw
1381 * @ha: pointer to adapter structure
1382 *
1383 * Note: IDC lock must be held upon entry
1384 **/
1385 static int
1386 qla8044_device_bootstrap(struct scsi_qla_host *vha)
1387 {
1388 int rval = QLA_FUNCTION_FAILED;
1389 int i;
1390 uint32_t old_count = 0, count = 0;
1391 int need_reset = 0;
1392 uint32_t idc_ctrl;
1393 struct qla_hw_data *ha = vha->hw;
1394
1395 need_reset = qla8044_need_reset(vha);
1396
1397 if (!need_reset) {
1398 old_count = qla8044_rd_direct(vha,
1399 QLA8044_PEG_ALIVE_COUNTER_INDEX);
1400
1401 for (i = 0; i < 10; i++) {
1402 msleep(200);
1403
1404 count = qla8044_rd_direct(vha,
1405 QLA8044_PEG_ALIVE_COUNTER_INDEX);
1406 if (count != old_count) {
1407 rval = QLA_SUCCESS;
1408 goto dev_ready;
1409 }
1410 }
1411 qla8044_flash_lock_recovery(vha);
1412 } else {
1413 /* We are trying to perform a recovery here. */
1414 if (ha->flags.isp82xx_fw_hung)
1415 qla8044_flash_lock_recovery(vha);
1416 }
1417
1418 /* set to DEV_INITIALIZING */
1419 ql_log(ql_log_info, vha, 0xb0b2,
1420 "%s: HW State: INITIALIZING\n", __func__);
1421 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1422 QLA8XXX_DEV_INITIALIZING);
1423
1424 qla8044_idc_unlock(ha);
1425 rval = qla8044_start_firmware(vha);
1426 qla8044_idc_lock(ha);
1427
1428 if (rval != QLA_SUCCESS) {
1429 ql_log(ql_log_info, vha, 0xb0b3,
1430 "%s: HW State: FAILED\n", __func__);
1431 qla8044_clear_drv_active(ha);
1432 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1433 QLA8XXX_DEV_FAILED);
1434 return rval;
1435 }
1436
1437 /* For ISP8044, If IDC_CTRL GRACEFUL_RESET_BIT1 is set , reset it after
1438 * device goes to INIT state. */
1439 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1440 if (idc_ctrl & GRACEFUL_RESET_BIT1) {
1441 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
1442 (idc_ctrl & ~GRACEFUL_RESET_BIT1));
1443 ha->fw_dumped = false;
1444 }
1445
1446 dev_ready:
1447 ql_log(ql_log_info, vha, 0xb0b4,
1448 "%s: HW State: READY\n", __func__);
1449 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, QLA8XXX_DEV_READY);
1450
1451 return rval;
1452 }
1453
1454 /*-------------------------Reset Sequence Functions-----------------------*/
1455 static void
1456 qla8044_dump_reset_seq_hdr(struct scsi_qla_host *vha)
1457 {
1458 u8 *phdr;
1459
1460 if (!vha->reset_tmplt.buff) {
1461 ql_log(ql_log_fatal, vha, 0xb0b5,
1462 "%s: Error Invalid reset_seq_template\n", __func__);
1463 return;
1464 }
1465
1466 phdr = vha->reset_tmplt.buff;
1467 ql_dbg(ql_dbg_p3p, vha, 0xb0b6,
1468 "Reset Template :\n\t0x%X 0x%X 0x%X 0x%X"
1469 "0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n"
1470 "\t0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n\n",
1471 *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4),
1472 *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8),
1473 *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12),
1474 *(phdr+13), *(phdr+14), *(phdr+15));
1475 }
1476
1477 /*
1478 * qla8044_reset_seq_checksum_test - Validate Reset Sequence template.
1479 *
1480 * @ha : Pointer to adapter structure
1481 *
1482 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1483 */
1484 static int
1485 qla8044_reset_seq_checksum_test(struct scsi_qla_host *vha)
1486 {
1487 uint32_t sum = 0;
1488 uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff;
1489 int u16_count = vha->reset_tmplt.hdr->size / sizeof(uint16_t);
1490
1491 while (u16_count-- > 0)
1492 sum += *buff++;
1493
1494 while (sum >> 16)
1495 sum = (sum & 0xFFFF) + (sum >> 16);
1496
1497 /* checksum of 0 indicates a valid template */
1498 if (~sum) {
1499 return QLA_SUCCESS;
1500 } else {
1501 ql_log(ql_log_fatal, vha, 0xb0b7,
1502 "%s: Reset seq checksum failed\n", __func__);
1503 return QLA_FUNCTION_FAILED;
1504 }
1505 }
1506
1507 /*
1508 * qla8044_read_reset_template - Read Reset Template from Flash, validate
1509 * the template and store offsets of stop/start/init offsets in ha->reset_tmplt.
1510 *
1511 * @ha : Pointer to adapter structure
1512 */
1513 void
1514 qla8044_read_reset_template(struct scsi_qla_host *vha)
1515 {
1516 uint8_t *p_buff;
1517 uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size;
1518
1519 vha->reset_tmplt.seq_error = 0;
1520 vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE);
1521 if (vha->reset_tmplt.buff == NULL) {
1522 ql_log(ql_log_fatal, vha, 0xb0b8,
1523 "%s: Failed to allocate reset template resources\n",
1524 __func__);
1525 goto exit_read_reset_template;
1526 }
1527
1528 p_buff = vha->reset_tmplt.buff;
1529 addr = QLA8044_RESET_TEMPLATE_ADDR;
1530
1531 tmplt_hdr_def_size =
1532 sizeof(struct qla8044_reset_template_hdr) / sizeof(uint32_t);
1533
1534 ql_dbg(ql_dbg_p3p, vha, 0xb0b9,
1535 "%s: Read template hdr size %d from Flash\n",
1536 __func__, tmplt_hdr_def_size);
1537
1538 /* Copy template header from flash */
1539 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1540 ql_log(ql_log_fatal, vha, 0xb0ba,
1541 "%s: Failed to read reset template\n", __func__);
1542 goto exit_read_template_error;
1543 }
1544
1545 vha->reset_tmplt.hdr =
1546 (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff;
1547
1548 /* Validate the template header size and signature */
1549 tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t);
1550 if ((tmplt_hdr_size != tmplt_hdr_def_size) ||
1551 (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) {
1552 ql_log(ql_log_fatal, vha, 0xb0bb,
1553 "%s: Template Header size invalid %d "
1554 "tmplt_hdr_def_size %d!!!\n", __func__,
1555 tmplt_hdr_size, tmplt_hdr_def_size);
1556 goto exit_read_template_error;
1557 }
1558
1559 addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size;
1560 p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size;
1561 tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size -
1562 vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t);
1563
1564 ql_dbg(ql_dbg_p3p, vha, 0xb0bc,
1565 "%s: Read rest of the template size %d\n",
1566 __func__, vha->reset_tmplt.hdr->size);
1567
1568 /* Copy rest of the template */
1569 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1570 ql_log(ql_log_fatal, vha, 0xb0bd,
1571 "%s: Failed to read reset template\n", __func__);
1572 goto exit_read_template_error;
1573 }
1574
1575 /* Integrity check */
1576 if (qla8044_reset_seq_checksum_test(vha)) {
1577 ql_log(ql_log_fatal, vha, 0xb0be,
1578 "%s: Reset Seq checksum failed!\n", __func__);
1579 goto exit_read_template_error;
1580 }
1581
1582 ql_dbg(ql_dbg_p3p, vha, 0xb0bf,
1583 "%s: Reset Seq checksum passed! Get stop, "
1584 "start and init seq offsets\n", __func__);
1585
1586 /* Get STOP, START, INIT sequence offsets */
1587 vha->reset_tmplt.init_offset = vha->reset_tmplt.buff +
1588 vha->reset_tmplt.hdr->init_seq_offset;
1589
1590 vha->reset_tmplt.start_offset = vha->reset_tmplt.buff +
1591 vha->reset_tmplt.hdr->start_seq_offset;
1592
1593 vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff +
1594 vha->reset_tmplt.hdr->hdr_size;
1595
1596 qla8044_dump_reset_seq_hdr(vha);
1597
1598 goto exit_read_reset_template;
1599
1600 exit_read_template_error:
1601 vfree(vha->reset_tmplt.buff);
1602
1603 exit_read_reset_template:
1604 return;
1605 }
1606
1607 void
1608 qla8044_set_idc_dontreset(struct scsi_qla_host *vha)
1609 {
1610 uint32_t idc_ctrl;
1611 struct qla_hw_data *ha = vha->hw;
1612
1613 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1614 idc_ctrl |= DONTRESET_BIT0;
1615 ql_dbg(ql_dbg_p3p, vha, 0xb0c0,
1616 "%s: idc_ctrl = %d\n", __func__, idc_ctrl);
1617 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
1618 }
1619
1620 static inline void
1621 qla8044_set_rst_ready(struct scsi_qla_host *vha)
1622 {
1623 uint32_t drv_state;
1624 struct qla_hw_data *ha = vha->hw;
1625
1626 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1627
1628 /* For ISP8044, drv_active register has 1 bit per function,
1629 * shift 1 by func_num to set a bit for the function.*/
1630 drv_state |= (1 << ha->portnum);
1631
1632 ql_log(ql_log_info, vha, 0xb0c1,
1633 "%s(%ld): drv_state: 0x%08x\n",
1634 __func__, vha->host_no, drv_state);
1635 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
1636 }
1637
1638 /**
1639 * qla8044_need_reset_handler - Code to start reset sequence
1640 * @vha: pointer to adapter structure
1641 *
1642 * Note: IDC lock must be held upon entry
1643 */
1644 static void
1645 qla8044_need_reset_handler(struct scsi_qla_host *vha)
1646 {
1647 uint32_t dev_state = 0, drv_state, drv_active;
1648 unsigned long reset_timeout;
1649 struct qla_hw_data *ha = vha->hw;
1650
1651 ql_log(ql_log_fatal, vha, 0xb0c2,
1652 "%s: Performing ISP error recovery\n", __func__);
1653
1654 if (vha->flags.online) {
1655 qla8044_idc_unlock(ha);
1656 qla2x00_abort_isp_cleanup(vha);
1657 ha->isp_ops->get_flash_version(vha, vha->req->ring);
1658 ha->isp_ops->nvram_config(vha);
1659 qla8044_idc_lock(ha);
1660 }
1661
1662 dev_state = qla8044_rd_direct(vha,
1663 QLA8044_CRB_DEV_STATE_INDEX);
1664 drv_state = qla8044_rd_direct(vha,
1665 QLA8044_CRB_DRV_STATE_INDEX);
1666 drv_active = qla8044_rd_direct(vha,
1667 QLA8044_CRB_DRV_ACTIVE_INDEX);
1668
1669 ql_log(ql_log_info, vha, 0xb0c5,
1670 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x dev_state = 0x%x\n",
1671 __func__, vha->host_no, drv_state, drv_active, dev_state);
1672
1673 qla8044_set_rst_ready(vha);
1674
1675 /* wait for 10 seconds for reset ack from all functions */
1676 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
1677
1678 do {
1679 if (time_after_eq(jiffies, reset_timeout)) {
1680 ql_log(ql_log_info, vha, 0xb0c4,
1681 "%s: Function %d: Reset Ack Timeout!, drv_state: 0x%08x, drv_active: 0x%08x\n",
1682 __func__, ha->portnum, drv_state, drv_active);
1683 break;
1684 }
1685
1686 qla8044_idc_unlock(ha);
1687 msleep(1000);
1688 qla8044_idc_lock(ha);
1689
1690 dev_state = qla8044_rd_direct(vha,
1691 QLA8044_CRB_DEV_STATE_INDEX);
1692 drv_state = qla8044_rd_direct(vha,
1693 QLA8044_CRB_DRV_STATE_INDEX);
1694 drv_active = qla8044_rd_direct(vha,
1695 QLA8044_CRB_DRV_ACTIVE_INDEX);
1696 } while (((drv_state & drv_active) != drv_active) &&
1697 (dev_state == QLA8XXX_DEV_NEED_RESET));
1698
1699 /* Remove IDC participation of functions not acknowledging */
1700 if (drv_state != drv_active) {
1701 ql_log(ql_log_info, vha, 0xb0c7,
1702 "%s(%ld): Function %d turning off drv_active of non-acking function 0x%x\n",
1703 __func__, vha->host_no, ha->portnum,
1704 (drv_active ^ drv_state));
1705 drv_active = drv_active & drv_state;
1706 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX,
1707 drv_active);
1708 } else {
1709 /*
1710 * Reset owner should execute reset recovery,
1711 * if all functions acknowledged
1712 */
1713 if ((ha->flags.nic_core_reset_owner) &&
1714 (dev_state == QLA8XXX_DEV_NEED_RESET)) {
1715 ha->flags.nic_core_reset_owner = 0;
1716 qla8044_device_bootstrap(vha);
1717 return;
1718 }
1719 }
1720
1721 /* Exit if non active function */
1722 if (!(drv_active & (1 << ha->portnum))) {
1723 ha->flags.nic_core_reset_owner = 0;
1724 return;
1725 }
1726
1727 /*
1728 * Execute Reset Recovery if Reset Owner or Function 7
1729 * is the only active function
1730 */
1731 if (ha->flags.nic_core_reset_owner ||
1732 ((drv_state & drv_active) == QLA8044_FUN7_ACTIVE_INDEX)) {
1733 ha->flags.nic_core_reset_owner = 0;
1734 qla8044_device_bootstrap(vha);
1735 }
1736 }
1737
1738 static void
1739 qla8044_set_drv_active(struct scsi_qla_host *vha)
1740 {
1741 uint32_t drv_active;
1742 struct qla_hw_data *ha = vha->hw;
1743
1744 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1745
1746 /* For ISP8044, drv_active register has 1 bit per function,
1747 * shift 1 by func_num to set a bit for the function.*/
1748 drv_active |= (1 << ha->portnum);
1749
1750 ql_log(ql_log_info, vha, 0xb0c8,
1751 "%s(%ld): drv_active: 0x%08x\n",
1752 __func__, vha->host_no, drv_active);
1753 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1754 }
1755
1756 static int
1757 qla8044_check_drv_active(struct scsi_qla_host *vha)
1758 {
1759 uint32_t drv_active;
1760 struct qla_hw_data *ha = vha->hw;
1761
1762 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1763 if (drv_active & (1 << ha->portnum))
1764 return QLA_SUCCESS;
1765 else
1766 return QLA_TEST_FAILED;
1767 }
1768
1769 static void
1770 qla8044_clear_idc_dontreset(struct scsi_qla_host *vha)
1771 {
1772 uint32_t idc_ctrl;
1773 struct qla_hw_data *ha = vha->hw;
1774
1775 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1776 idc_ctrl &= ~DONTRESET_BIT0;
1777 ql_log(ql_log_info, vha, 0xb0c9,
1778 "%s: idc_ctrl = %d\n", __func__,
1779 idc_ctrl);
1780 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
1781 }
1782
1783 static int
1784 qla8044_set_idc_ver(struct scsi_qla_host *vha)
1785 {
1786 int idc_ver;
1787 uint32_t drv_active;
1788 int rval = QLA_SUCCESS;
1789 struct qla_hw_data *ha = vha->hw;
1790
1791 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1792 if (drv_active == (1 << ha->portnum)) {
1793 idc_ver = qla8044_rd_direct(vha,
1794 QLA8044_CRB_DRV_IDC_VERSION_INDEX);
1795 idc_ver &= (~0xFF);
1796 idc_ver |= QLA8044_IDC_VER_MAJ_VALUE;
1797 qla8044_wr_direct(vha, QLA8044_CRB_DRV_IDC_VERSION_INDEX,
1798 idc_ver);
1799 ql_log(ql_log_info, vha, 0xb0ca,
1800 "%s: IDC version updated to %d\n",
1801 __func__, idc_ver);
1802 } else {
1803 idc_ver = qla8044_rd_direct(vha,
1804 QLA8044_CRB_DRV_IDC_VERSION_INDEX);
1805 idc_ver &= 0xFF;
1806 if (QLA8044_IDC_VER_MAJ_VALUE != idc_ver) {
1807 ql_log(ql_log_info, vha, 0xb0cb,
1808 "%s: qla4xxx driver IDC version %d "
1809 "is not compatible with IDC version %d "
1810 "of other drivers!\n",
1811 __func__, QLA8044_IDC_VER_MAJ_VALUE,
1812 idc_ver);
1813 rval = QLA_FUNCTION_FAILED;
1814 goto exit_set_idc_ver;
1815 }
1816 }
1817
1818 /* Update IDC_MINOR_VERSION */
1819 idc_ver = qla8044_rd_reg(ha, QLA8044_CRB_IDC_VER_MINOR);
1820 idc_ver &= ~(0x03 << (ha->portnum * 2));
1821 idc_ver |= (QLA8044_IDC_VER_MIN_VALUE << (ha->portnum * 2));
1822 qla8044_wr_reg(ha, QLA8044_CRB_IDC_VER_MINOR, idc_ver);
1823
1824 exit_set_idc_ver:
1825 return rval;
1826 }
1827
1828 static int
1829 qla8044_update_idc_reg(struct scsi_qla_host *vha)
1830 {
1831 uint32_t drv_active;
1832 int rval = QLA_SUCCESS;
1833 struct qla_hw_data *ha = vha->hw;
1834
1835 if (vha->flags.init_done)
1836 goto exit_update_idc_reg;
1837
1838 qla8044_idc_lock(ha);
1839 qla8044_set_drv_active(vha);
1840
1841 drv_active = qla8044_rd_direct(vha,
1842 QLA8044_CRB_DRV_ACTIVE_INDEX);
1843
1844 /* If we are the first driver to load and
1845 * ql2xdontresethba is not set, clear IDC_CTRL BIT0. */
1846 if ((drv_active == (1 << ha->portnum)) && !ql2xdontresethba)
1847 qla8044_clear_idc_dontreset(vha);
1848
1849 rval = qla8044_set_idc_ver(vha);
1850 if (rval == QLA_FUNCTION_FAILED)
1851 qla8044_clear_drv_active(ha);
1852 qla8044_idc_unlock(ha);
1853
1854 exit_update_idc_reg:
1855 return rval;
1856 }
1857
1858 /**
1859 * qla8044_need_qsnt_handler - Code to start qsnt
1860 * @vha: pointer to adapter structure
1861 */
1862 static void
1863 qla8044_need_qsnt_handler(struct scsi_qla_host *vha)
1864 {
1865 unsigned long qsnt_timeout;
1866 uint32_t drv_state, drv_active, dev_state;
1867 struct qla_hw_data *ha = vha->hw;
1868
1869 if (vha->flags.online)
1870 qla2x00_quiesce_io(vha);
1871 else
1872 return;
1873
1874 qla8044_set_qsnt_ready(vha);
1875
1876 /* Wait for 30 secs for all functions to ack qsnt mode */
1877 qsnt_timeout = jiffies + (QSNT_ACK_TOV * HZ);
1878 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1879 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1880
1881 /* Shift drv_active by 1 to match drv_state. As quiescent ready bit
1882 position is at bit 1 and drv active is at bit 0 */
1883 drv_active = drv_active << 1;
1884
1885 while (drv_state != drv_active) {
1886 if (time_after_eq(jiffies, qsnt_timeout)) {
1887 /* Other functions did not ack, changing state to
1888 * DEV_READY
1889 */
1890 clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
1891 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1892 QLA8XXX_DEV_READY);
1893 qla8044_clear_qsnt_ready(vha);
1894 ql_log(ql_log_info, vha, 0xb0cc,
1895 "Timeout waiting for quiescent ack!!!\n");
1896 return;
1897 }
1898 qla8044_idc_unlock(ha);
1899 msleep(1000);
1900 qla8044_idc_lock(ha);
1901
1902 drv_state = qla8044_rd_direct(vha,
1903 QLA8044_CRB_DRV_STATE_INDEX);
1904 drv_active = qla8044_rd_direct(vha,
1905 QLA8044_CRB_DRV_ACTIVE_INDEX);
1906 drv_active = drv_active << 1;
1907 }
1908
1909 /* All functions have Acked. Set quiescent state */
1910 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1911
1912 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
1913 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1914 QLA8XXX_DEV_QUIESCENT);
1915 ql_log(ql_log_info, vha, 0xb0cd,
1916 "%s: HW State: QUIESCENT\n", __func__);
1917 }
1918 }
1919
1920 /*
1921 * qla8044_device_state_handler - Adapter state machine
1922 * @ha: pointer to host adapter structure.
1923 *
1924 * Note: IDC lock must be UNLOCKED upon entry
1925 **/
1926 int
1927 qla8044_device_state_handler(struct scsi_qla_host *vha)
1928 {
1929 uint32_t dev_state;
1930 int rval = QLA_SUCCESS;
1931 unsigned long dev_init_timeout;
1932 struct qla_hw_data *ha = vha->hw;
1933
1934 rval = qla8044_update_idc_reg(vha);
1935 if (rval == QLA_FUNCTION_FAILED)
1936 goto exit_error;
1937
1938 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1939 ql_dbg(ql_dbg_p3p, vha, 0xb0ce,
1940 "Device state is 0x%x = %s\n",
1941 dev_state, dev_state < MAX_STATES ?
1942 qdev_state(dev_state) : "Unknown");
1943
1944 /* wait for 30 seconds for device to go ready */
1945 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
1946
1947 qla8044_idc_lock(ha);
1948
1949 while (1) {
1950 if (time_after_eq(jiffies, dev_init_timeout)) {
1951 if (qla8044_check_drv_active(vha) == QLA_SUCCESS) {
1952 ql_log(ql_log_warn, vha, 0xb0cf,
1953 "%s: Device Init Failed 0x%x = %s\n",
1954 QLA2XXX_DRIVER_NAME, dev_state,
1955 dev_state < MAX_STATES ?
1956 qdev_state(dev_state) : "Unknown");
1957 qla8044_wr_direct(vha,
1958 QLA8044_CRB_DEV_STATE_INDEX,
1959 QLA8XXX_DEV_FAILED);
1960 }
1961 }
1962
1963 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1964 ql_log(ql_log_info, vha, 0xb0d0,
1965 "Device state is 0x%x = %s\n",
1966 dev_state, dev_state < MAX_STATES ?
1967 qdev_state(dev_state) : "Unknown");
1968
1969 /* NOTE: Make sure idc unlocked upon exit of switch statement */
1970 switch (dev_state) {
1971 case QLA8XXX_DEV_READY:
1972 ha->flags.nic_core_reset_owner = 0;
1973 goto exit;
1974 case QLA8XXX_DEV_COLD:
1975 rval = qla8044_device_bootstrap(vha);
1976 break;
1977 case QLA8XXX_DEV_INITIALIZING:
1978 qla8044_idc_unlock(ha);
1979 msleep(1000);
1980 qla8044_idc_lock(ha);
1981 break;
1982 case QLA8XXX_DEV_NEED_RESET:
1983 /* For ISP8044, if NEED_RESET is set by any driver,
1984 * it should be honored, irrespective of IDC_CTRL
1985 * DONTRESET_BIT0 */
1986 qla8044_need_reset_handler(vha);
1987 break;
1988 case QLA8XXX_DEV_NEED_QUIESCENT:
1989 /* idc locked/unlocked in handler */
1990 qla8044_need_qsnt_handler(vha);
1991
1992 /* Reset the init timeout after qsnt handler */
1993 dev_init_timeout = jiffies +
1994 (ha->fcoe_reset_timeout * HZ);
1995 break;
1996 case QLA8XXX_DEV_QUIESCENT:
1997 ql_log(ql_log_info, vha, 0xb0d1,
1998 "HW State: QUIESCENT\n");
1999
2000 qla8044_idc_unlock(ha);
2001 msleep(1000);
2002 qla8044_idc_lock(ha);
2003
2004 /* Reset the init timeout after qsnt handler */
2005 dev_init_timeout = jiffies +
2006 (ha->fcoe_reset_timeout * HZ);
2007 break;
2008 case QLA8XXX_DEV_FAILED:
2009 ha->flags.nic_core_reset_owner = 0;
2010 qla8044_idc_unlock(ha);
2011 qla8xxx_dev_failed_handler(vha);
2012 rval = QLA_FUNCTION_FAILED;
2013 qla8044_idc_lock(ha);
2014 goto exit;
2015 default:
2016 qla8044_idc_unlock(ha);
2017 qla8xxx_dev_failed_handler(vha);
2018 rval = QLA_FUNCTION_FAILED;
2019 qla8044_idc_lock(ha);
2020 goto exit;
2021 }
2022 }
2023 exit:
2024 qla8044_idc_unlock(ha);
2025
2026 exit_error:
2027 return rval;
2028 }
2029
2030 /**
2031 * qla4_8xxx_check_temp - Check the ISP82XX temperature.
2032 * @vha: adapter block pointer.
2033 *
2034 * Note: The caller should not hold the idc lock.
2035 */
2036 static int
2037 qla8044_check_temp(struct scsi_qla_host *vha)
2038 {
2039 uint32_t temp, temp_state, temp_val;
2040 int status = QLA_SUCCESS;
2041
2042 temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
2043 temp_state = qla82xx_get_temp_state(temp);
2044 temp_val = qla82xx_get_temp_val(temp);
2045
2046 if (temp_state == QLA82XX_TEMP_PANIC) {
2047 ql_log(ql_log_warn, vha, 0xb0d2,
2048 "Device temperature %d degrees C"
2049 " exceeds maximum allowed. Hardware has been shut"
2050 " down\n", temp_val);
2051 status = QLA_FUNCTION_FAILED;
2052 return status;
2053 } else if (temp_state == QLA82XX_TEMP_WARN) {
2054 ql_log(ql_log_warn, vha, 0xb0d3,
2055 "Device temperature %d"
2056 " degrees C exceeds operating range."
2057 " Immediate action needed.\n", temp_val);
2058 }
2059 return 0;
2060 }
2061
2062 int qla8044_read_temperature(scsi_qla_host_t *vha)
2063 {
2064 uint32_t temp;
2065
2066 temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
2067 return qla82xx_get_temp_val(temp);
2068 }
2069
2070 /**
2071 * qla8044_check_fw_alive - Check firmware health
2072 * @vha: Pointer to host adapter structure.
2073 *
2074 * Context: Interrupt
2075 */
2076 int
2077 qla8044_check_fw_alive(struct scsi_qla_host *vha)
2078 {
2079 uint32_t fw_heartbeat_counter;
2080 uint32_t halt_status1, halt_status2;
2081 int status = QLA_SUCCESS;
2082
2083 fw_heartbeat_counter = qla8044_rd_direct(vha,
2084 QLA8044_PEG_ALIVE_COUNTER_INDEX);
2085
2086 /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */
2087 if (fw_heartbeat_counter == 0xffffffff) {
2088 ql_dbg(ql_dbg_p3p, vha, 0xb0d4,
2089 "scsi%ld: %s: Device in frozen "
2090 "state, QLA82XX_PEG_ALIVE_COUNTER is 0xffffffff\n",
2091 vha->host_no, __func__);
2092 return status;
2093 }
2094
2095 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
2096 vha->seconds_since_last_heartbeat++;
2097 /* FW not alive after 2 seconds */
2098 if (vha->seconds_since_last_heartbeat == 2) {
2099 vha->seconds_since_last_heartbeat = 0;
2100 halt_status1 = qla8044_rd_direct(vha,
2101 QLA8044_PEG_HALT_STATUS1_INDEX);
2102 halt_status2 = qla8044_rd_direct(vha,
2103 QLA8044_PEG_HALT_STATUS2_INDEX);
2104
2105 ql_log(ql_log_info, vha, 0xb0d5,
2106 "scsi(%ld): %s, ISP8044 "
2107 "Dumping hw/fw registers:\n"
2108 " PEG_HALT_STATUS1: 0x%x, "
2109 "PEG_HALT_STATUS2: 0x%x,\n",
2110 vha->host_no, __func__, halt_status1,
2111 halt_status2);
2112 status = QLA_FUNCTION_FAILED;
2113 }
2114 } else
2115 vha->seconds_since_last_heartbeat = 0;
2116
2117 vha->fw_heartbeat_counter = fw_heartbeat_counter;
2118 return status;
2119 }
2120
2121 void
2122 qla8044_watchdog(struct scsi_qla_host *vha)
2123 {
2124 uint32_t dev_state, halt_status;
2125 int halt_status_unrecoverable = 0;
2126 struct qla_hw_data *ha = vha->hw;
2127
2128 /* don't poll if reset is going on or FW hang in quiescent state */
2129 if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) ||
2130 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) {
2131 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
2132
2133 if (qla8044_check_fw_alive(vha)) {
2134 ha->flags.isp82xx_fw_hung = 1;
2135 ql_log(ql_log_warn, vha, 0xb10a,
2136 "Firmware hung.\n");
2137 qla82xx_clear_pending_mbx(vha);
2138 }
2139
2140 if (qla8044_check_temp(vha)) {
2141 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
2142 ha->flags.isp82xx_fw_hung = 1;
2143 qla2xxx_wake_dpc(vha);
2144 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
2145 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
2146 ql_log(ql_log_info, vha, 0xb0d6,
2147 "%s: HW State: NEED RESET!\n",
2148 __func__);
2149 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2150 qla2xxx_wake_dpc(vha);
2151 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
2152 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
2153 ql_log(ql_log_info, vha, 0xb0d7,
2154 "%s: HW State: NEED QUIES detected!\n",
2155 __func__);
2156 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
2157 qla2xxx_wake_dpc(vha);
2158 } else {
2159 /* Check firmware health */
2160 if (ha->flags.isp82xx_fw_hung) {
2161 halt_status = qla8044_rd_direct(vha,
2162 QLA8044_PEG_HALT_STATUS1_INDEX);
2163 if (halt_status &
2164 QLA8044_HALT_STATUS_FW_RESET) {
2165 ql_log(ql_log_fatal, vha,
2166 0xb0d8, "%s: Firmware "
2167 "error detected device "
2168 "is being reset\n",
2169 __func__);
2170 } else if (halt_status &
2171 QLA8044_HALT_STATUS_UNRECOVERABLE) {
2172 halt_status_unrecoverable = 1;
2173 }
2174
2175 /* Since we cannot change dev_state in interrupt
2176 * context, set appropriate DPC flag then wakeup
2177 * DPC */
2178 if (halt_status_unrecoverable) {
2179 set_bit(ISP_UNRECOVERABLE,
2180 &vha->dpc_flags);
2181 } else {
2182 if (dev_state ==
2183 QLA8XXX_DEV_QUIESCENT) {
2184 set_bit(FCOE_CTX_RESET_NEEDED,
2185 &vha->dpc_flags);
2186 ql_log(ql_log_info, vha, 0xb0d9,
2187 "%s: FW CONTEXT Reset "
2188 "needed!\n", __func__);
2189 } else {
2190 ql_log(ql_log_info, vha,
2191 0xb0da, "%s: "
2192 "detect abort needed\n",
2193 __func__);
2194 set_bit(ISP_ABORT_NEEDED,
2195 &vha->dpc_flags);
2196 }
2197 }
2198 qla2xxx_wake_dpc(vha);
2199 }
2200 }
2201
2202 }
2203 }
2204
2205 static int
2206 qla8044_minidump_process_control(struct scsi_qla_host *vha,
2207 struct qla8044_minidump_entry_hdr *entry_hdr)
2208 {
2209 struct qla8044_minidump_entry_crb *crb_entry;
2210 uint32_t read_value, opcode, poll_time, addr, index;
2211 uint32_t crb_addr, rval = QLA_SUCCESS;
2212 unsigned long wtime;
2213 struct qla8044_minidump_template_hdr *tmplt_hdr;
2214 int i;
2215 struct qla_hw_data *ha = vha->hw;
2216
2217 ql_dbg(ql_dbg_p3p, vha, 0xb0dd, "Entering fn: %s\n", __func__);
2218 tmplt_hdr = (struct qla8044_minidump_template_hdr *)
2219 ha->md_tmplt_hdr;
2220 crb_entry = (struct qla8044_minidump_entry_crb *)entry_hdr;
2221
2222 crb_addr = crb_entry->addr;
2223 for (i = 0; i < crb_entry->op_count; i++) {
2224 opcode = crb_entry->crb_ctrl.opcode;
2225
2226 if (opcode & QLA82XX_DBG_OPCODE_WR) {
2227 qla8044_wr_reg_indirect(vha, crb_addr,
2228 crb_entry->value_1);
2229 opcode &= ~QLA82XX_DBG_OPCODE_WR;
2230 }
2231
2232 if (opcode & QLA82XX_DBG_OPCODE_RW) {
2233 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2234 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2235 opcode &= ~QLA82XX_DBG_OPCODE_RW;
2236 }
2237
2238 if (opcode & QLA82XX_DBG_OPCODE_AND) {
2239 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2240 read_value &= crb_entry->value_2;
2241 opcode &= ~QLA82XX_DBG_OPCODE_AND;
2242 if (opcode & QLA82XX_DBG_OPCODE_OR) {
2243 read_value |= crb_entry->value_3;
2244 opcode &= ~QLA82XX_DBG_OPCODE_OR;
2245 }
2246 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2247 }
2248 if (opcode & QLA82XX_DBG_OPCODE_OR) {
2249 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2250 read_value |= crb_entry->value_3;
2251 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2252 opcode &= ~QLA82XX_DBG_OPCODE_OR;
2253 }
2254 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
2255 poll_time = crb_entry->crb_strd.poll_timeout;
2256 wtime = jiffies + poll_time;
2257 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2258
2259 do {
2260 if ((read_value & crb_entry->value_2) ==
2261 crb_entry->value_1) {
2262 break;
2263 } else if (time_after_eq(jiffies, wtime)) {
2264 /* capturing dump failed */
2265 rval = QLA_FUNCTION_FAILED;
2266 break;
2267 } else {
2268 qla8044_rd_reg_indirect(vha,
2269 crb_addr, &read_value);
2270 }
2271 } while (1);
2272 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
2273 }
2274
2275 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
2276 if (crb_entry->crb_strd.state_index_a) {
2277 index = crb_entry->crb_strd.state_index_a;
2278 addr = tmplt_hdr->saved_state_array[index];
2279 } else {
2280 addr = crb_addr;
2281 }
2282
2283 qla8044_rd_reg_indirect(vha, addr, &read_value);
2284 index = crb_entry->crb_ctrl.state_index_v;
2285 tmplt_hdr->saved_state_array[index] = read_value;
2286 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
2287 }
2288
2289 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
2290 if (crb_entry->crb_strd.state_index_a) {
2291 index = crb_entry->crb_strd.state_index_a;
2292 addr = tmplt_hdr->saved_state_array[index];
2293 } else {
2294 addr = crb_addr;
2295 }
2296
2297 if (crb_entry->crb_ctrl.state_index_v) {
2298 index = crb_entry->crb_ctrl.state_index_v;
2299 read_value =
2300 tmplt_hdr->saved_state_array[index];
2301 } else {
2302 read_value = crb_entry->value_1;
2303 }
2304
2305 qla8044_wr_reg_indirect(vha, addr, read_value);
2306 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
2307 }
2308
2309 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
2310 index = crb_entry->crb_ctrl.state_index_v;
2311 read_value = tmplt_hdr->saved_state_array[index];
2312 read_value <<= crb_entry->crb_ctrl.shl;
2313 read_value >>= crb_entry->crb_ctrl.shr;
2314 if (crb_entry->value_2)
2315 read_value &= crb_entry->value_2;
2316 read_value |= crb_entry->value_3;
2317 read_value += crb_entry->value_1;
2318 tmplt_hdr->saved_state_array[index] = read_value;
2319 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
2320 }
2321 crb_addr += crb_entry->crb_strd.addr_stride;
2322 }
2323 return rval;
2324 }
2325
2326 static void
2327 qla8044_minidump_process_rdcrb(struct scsi_qla_host *vha,
2328 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2329 {
2330 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2331 struct qla8044_minidump_entry_crb *crb_hdr;
2332 uint32_t *data_ptr = *d_ptr;
2333
2334 ql_dbg(ql_dbg_p3p, vha, 0xb0de, "Entering fn: %s\n", __func__);
2335 crb_hdr = (struct qla8044_minidump_entry_crb *)entry_hdr;
2336 r_addr = crb_hdr->addr;
2337 r_stride = crb_hdr->crb_strd.addr_stride;
2338 loop_cnt = crb_hdr->op_count;
2339
2340 for (i = 0; i < loop_cnt; i++) {
2341 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2342 *data_ptr++ = r_addr;
2343 *data_ptr++ = r_value;
2344 r_addr += r_stride;
2345 }
2346 *d_ptr = data_ptr;
2347 }
2348
2349 static int
2350 qla8044_minidump_process_rdmem(struct scsi_qla_host *vha,
2351 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2352 {
2353 uint32_t r_addr, r_value, r_data;
2354 uint32_t i, j, loop_cnt;
2355 struct qla8044_minidump_entry_rdmem *m_hdr;
2356 unsigned long flags;
2357 uint32_t *data_ptr = *d_ptr;
2358 struct qla_hw_data *ha = vha->hw;
2359
2360 ql_dbg(ql_dbg_p3p, vha, 0xb0df, "Entering fn: %s\n", __func__);
2361 m_hdr = (struct qla8044_minidump_entry_rdmem *)entry_hdr;
2362 r_addr = m_hdr->read_addr;
2363 loop_cnt = m_hdr->read_data_size/16;
2364
2365 ql_dbg(ql_dbg_p3p, vha, 0xb0f0,
2366 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2367 __func__, r_addr, m_hdr->read_data_size);
2368
2369 if (r_addr & 0xf) {
2370 ql_dbg(ql_dbg_p3p, vha, 0xb0f1,
2371 "[%s]: Read addr 0x%x not 16 bytes aligned\n",
2372 __func__, r_addr);
2373 return QLA_FUNCTION_FAILED;
2374 }
2375
2376 if (m_hdr->read_data_size % 16) {
2377 ql_dbg(ql_dbg_p3p, vha, 0xb0f2,
2378 "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2379 __func__, m_hdr->read_data_size);
2380 return QLA_FUNCTION_FAILED;
2381 }
2382
2383 ql_dbg(ql_dbg_p3p, vha, 0xb0f3,
2384 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2385 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
2386
2387 write_lock_irqsave(&ha->hw_lock, flags);
2388 for (i = 0; i < loop_cnt; i++) {
2389 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_LO, r_addr);
2390 r_value = 0;
2391 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, r_value);
2392 r_value = MIU_TA_CTL_ENABLE;
2393 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2394 r_value = MIU_TA_CTL_START_ENABLE;
2395 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2396
2397 for (j = 0; j < MAX_CTL_CHECK; j++) {
2398 qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
2399 &r_value);
2400 if ((r_value & MIU_TA_CTL_BUSY) == 0)
2401 break;
2402 }
2403
2404 if (j >= MAX_CTL_CHECK) {
2405 write_unlock_irqrestore(&ha->hw_lock, flags);
2406 return QLA_SUCCESS;
2407 }
2408
2409 for (j = 0; j < 4; j++) {
2410 qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_RDDATA[j],
2411 &r_data);
2412 *data_ptr++ = r_data;
2413 }
2414
2415 r_addr += 16;
2416 }
2417 write_unlock_irqrestore(&ha->hw_lock, flags);
2418
2419 ql_dbg(ql_dbg_p3p, vha, 0xb0f4,
2420 "Leaving fn: %s datacount: 0x%x\n",
2421 __func__, (loop_cnt * 16));
2422
2423 *d_ptr = data_ptr;
2424 return QLA_SUCCESS;
2425 }
2426
2427 /* ISP83xx flash read for _RDROM _BOARD */
2428 static uint32_t
2429 qla8044_minidump_process_rdrom(struct scsi_qla_host *vha,
2430 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2431 {
2432 uint32_t fl_addr, u32_count, rval;
2433 struct qla8044_minidump_entry_rdrom *rom_hdr;
2434 uint32_t *data_ptr = *d_ptr;
2435
2436 rom_hdr = (struct qla8044_minidump_entry_rdrom *)entry_hdr;
2437 fl_addr = rom_hdr->read_addr;
2438 u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t);
2439
2440 ql_dbg(ql_dbg_p3p, vha, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2441 __func__, fl_addr, u32_count);
2442
2443 rval = qla8044_lockless_flash_read_u32(vha, fl_addr,
2444 (u8 *)(data_ptr), u32_count);
2445
2446 if (rval != QLA_SUCCESS) {
2447 ql_log(ql_log_fatal, vha, 0xb0f6,
2448 "%s: Flash Read Error,Count=%d\n", __func__, u32_count);
2449 return QLA_FUNCTION_FAILED;
2450 } else {
2451 data_ptr += u32_count;
2452 *d_ptr = data_ptr;
2453 return QLA_SUCCESS;
2454 }
2455 }
2456
2457 static void
2458 qla8044_mark_entry_skipped(struct scsi_qla_host *vha,
2459 struct qla8044_minidump_entry_hdr *entry_hdr, int index)
2460 {
2461 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
2462
2463 ql_log(ql_log_info, vha, 0xb0f7,
2464 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2465 vha->host_no, index, entry_hdr->entry_type,
2466 entry_hdr->d_ctrl.entry_capture_mask);
2467 }
2468
2469 static int
2470 qla8044_minidump_process_l2tag(struct scsi_qla_host *vha,
2471 struct qla8044_minidump_entry_hdr *entry_hdr,
2472 uint32_t **d_ptr)
2473 {
2474 uint32_t addr, r_addr, c_addr, t_r_addr;
2475 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2476 unsigned long p_wait, w_time, p_mask;
2477 uint32_t c_value_w, c_value_r;
2478 struct qla8044_minidump_entry_cache *cache_hdr;
2479 int rval = QLA_FUNCTION_FAILED;
2480 uint32_t *data_ptr = *d_ptr;
2481
2482 ql_dbg(ql_dbg_p3p, vha, 0xb0f8, "Entering fn: %s\n", __func__);
2483 cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
2484
2485 loop_count = cache_hdr->op_count;
2486 r_addr = cache_hdr->read_addr;
2487 c_addr = cache_hdr->control_addr;
2488 c_value_w = cache_hdr->cache_ctrl.write_value;
2489
2490 t_r_addr = cache_hdr->tag_reg_addr;
2491 t_value = cache_hdr->addr_ctrl.init_tag_value;
2492 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2493 p_wait = cache_hdr->cache_ctrl.poll_wait;
2494 p_mask = cache_hdr->cache_ctrl.poll_mask;
2495
2496 for (i = 0; i < loop_count; i++) {
2497 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2498 if (c_value_w)
2499 qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2500
2501 if (p_mask) {
2502 w_time = jiffies + p_wait;
2503 do {
2504 qla8044_rd_reg_indirect(vha, c_addr,
2505 &c_value_r);
2506 if ((c_value_r & p_mask) == 0) {
2507 break;
2508 } else if (time_after_eq(jiffies, w_time)) {
2509 /* capturing dump failed */
2510 return rval;
2511 }
2512 } while (1);
2513 }
2514
2515 addr = r_addr;
2516 for (k = 0; k < r_cnt; k++) {
2517 qla8044_rd_reg_indirect(vha, addr, &r_value);
2518 *data_ptr++ = r_value;
2519 addr += cache_hdr->read_ctrl.read_addr_stride;
2520 }
2521 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2522 }
2523 *d_ptr = data_ptr;
2524 return QLA_SUCCESS;
2525 }
2526
2527 static void
2528 qla8044_minidump_process_l1cache(struct scsi_qla_host *vha,
2529 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2530 {
2531 uint32_t addr, r_addr, c_addr, t_r_addr;
2532 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2533 uint32_t c_value_w;
2534 struct qla8044_minidump_entry_cache *cache_hdr;
2535 uint32_t *data_ptr = *d_ptr;
2536
2537 cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
2538 loop_count = cache_hdr->op_count;
2539 r_addr = cache_hdr->read_addr;
2540 c_addr = cache_hdr->control_addr;
2541 c_value_w = cache_hdr->cache_ctrl.write_value;
2542
2543 t_r_addr = cache_hdr->tag_reg_addr;
2544 t_value = cache_hdr->addr_ctrl.init_tag_value;
2545 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2546
2547 for (i = 0; i < loop_count; i++) {
2548 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2549 qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2550 addr = r_addr;
2551 for (k = 0; k < r_cnt; k++) {
2552 qla8044_rd_reg_indirect(vha, addr, &r_value);
2553 *data_ptr++ = r_value;
2554 addr += cache_hdr->read_ctrl.read_addr_stride;
2555 }
2556 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2557 }
2558 *d_ptr = data_ptr;
2559 }
2560
2561 static void
2562 qla8044_minidump_process_rdocm(struct scsi_qla_host *vha,
2563 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2564 {
2565 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2566 struct qla8044_minidump_entry_rdocm *ocm_hdr;
2567 uint32_t *data_ptr = *d_ptr;
2568 struct qla_hw_data *ha = vha->hw;
2569
2570 ql_dbg(ql_dbg_p3p, vha, 0xb0f9, "Entering fn: %s\n", __func__);
2571
2572 ocm_hdr = (struct qla8044_minidump_entry_rdocm *)entry_hdr;
2573 r_addr = ocm_hdr->read_addr;
2574 r_stride = ocm_hdr->read_addr_stride;
2575 loop_cnt = ocm_hdr->op_count;
2576
2577 ql_dbg(ql_dbg_p3p, vha, 0xb0fa,
2578 "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
2579 __func__, r_addr, r_stride, loop_cnt);
2580
2581 for (i = 0; i < loop_cnt; i++) {
2582 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
2583 *data_ptr++ = r_value;
2584 r_addr += r_stride;
2585 }
2586 ql_dbg(ql_dbg_p3p, vha, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n",
2587 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)));
2588
2589 *d_ptr = data_ptr;
2590 }
2591
2592 static void
2593 qla8044_minidump_process_rdmux(struct scsi_qla_host *vha,
2594 struct qla8044_minidump_entry_hdr *entry_hdr,
2595 uint32_t **d_ptr)
2596 {
2597 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value = 0;
2598 struct qla8044_minidump_entry_mux *mux_hdr;
2599 uint32_t *data_ptr = *d_ptr;
2600
2601 ql_dbg(ql_dbg_p3p, vha, 0xb0fc, "Entering fn: %s\n", __func__);
2602
2603 mux_hdr = (struct qla8044_minidump_entry_mux *)entry_hdr;
2604 r_addr = mux_hdr->read_addr;
2605 s_addr = mux_hdr->select_addr;
2606 s_stride = mux_hdr->select_value_stride;
2607 s_value = mux_hdr->select_value;
2608 loop_cnt = mux_hdr->op_count;
2609
2610 for (i = 0; i < loop_cnt; i++) {
2611 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2612 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2613 *data_ptr++ = s_value;
2614 *data_ptr++ = r_value;
2615 s_value += s_stride;
2616 }
2617 *d_ptr = data_ptr;
2618 }
2619
2620 static void
2621 qla8044_minidump_process_queue(struct scsi_qla_host *vha,
2622 struct qla8044_minidump_entry_hdr *entry_hdr,
2623 uint32_t **d_ptr)
2624 {
2625 uint32_t s_addr, r_addr;
2626 uint32_t r_stride, r_value, r_cnt, qid = 0;
2627 uint32_t i, k, loop_cnt;
2628 struct qla8044_minidump_entry_queue *q_hdr;
2629 uint32_t *data_ptr = *d_ptr;
2630
2631 ql_dbg(ql_dbg_p3p, vha, 0xb0fd, "Entering fn: %s\n", __func__);
2632 q_hdr = (struct qla8044_minidump_entry_queue *)entry_hdr;
2633 s_addr = q_hdr->select_addr;
2634 r_cnt = q_hdr->rd_strd.read_addr_cnt;
2635 r_stride = q_hdr->rd_strd.read_addr_stride;
2636 loop_cnt = q_hdr->op_count;
2637
2638 for (i = 0; i < loop_cnt; i++) {
2639 qla8044_wr_reg_indirect(vha, s_addr, qid);
2640 r_addr = q_hdr->read_addr;
2641 for (k = 0; k < r_cnt; k++) {
2642 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2643 *data_ptr++ = r_value;
2644 r_addr += r_stride;
2645 }
2646 qid += q_hdr->q_strd.queue_id_stride;
2647 }
2648 *d_ptr = data_ptr;
2649 }
2650
2651 /* ISP83xx functions to process new minidump entries... */
2652 static uint32_t
2653 qla8044_minidump_process_pollrd(struct scsi_qla_host *vha,
2654 struct qla8044_minidump_entry_hdr *entry_hdr,
2655 uint32_t **d_ptr)
2656 {
2657 uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2658 uint16_t s_stride, i;
2659 struct qla8044_minidump_entry_pollrd *pollrd_hdr;
2660 uint32_t *data_ptr = *d_ptr;
2661
2662 pollrd_hdr = (struct qla8044_minidump_entry_pollrd *) entry_hdr;
2663 s_addr = pollrd_hdr->select_addr;
2664 r_addr = pollrd_hdr->read_addr;
2665 s_value = pollrd_hdr->select_value;
2666 s_stride = pollrd_hdr->select_value_stride;
2667
2668 poll_wait = pollrd_hdr->poll_wait;
2669 poll_mask = pollrd_hdr->poll_mask;
2670
2671 for (i = 0; i < pollrd_hdr->op_count; i++) {
2672 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2673 poll_wait = pollrd_hdr->poll_wait;
2674 while (1) {
2675 qla8044_rd_reg_indirect(vha, s_addr, &r_value);
2676 if ((r_value & poll_mask) != 0) {
2677 break;
2678 } else {
2679 usleep_range(1000, 1100);
2680 if (--poll_wait == 0) {
2681 ql_log(ql_log_fatal, vha, 0xb0fe,
2682 "%s: TIMEOUT\n", __func__);
2683 goto error;
2684 }
2685 }
2686 }
2687 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2688 *data_ptr++ = s_value;
2689 *data_ptr++ = r_value;
2690
2691 s_value += s_stride;
2692 }
2693 *d_ptr = data_ptr;
2694 return QLA_SUCCESS;
2695
2696 error:
2697 return QLA_FUNCTION_FAILED;
2698 }
2699
2700 static void
2701 qla8044_minidump_process_rdmux2(struct scsi_qla_host *vha,
2702 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2703 {
2704 uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2705 uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2706 struct qla8044_minidump_entry_rdmux2 *rdmux2_hdr;
2707 uint32_t *data_ptr = *d_ptr;
2708
2709 rdmux2_hdr = (struct qla8044_minidump_entry_rdmux2 *) entry_hdr;
2710 sel_val1 = rdmux2_hdr->select_value_1;
2711 sel_val2 = rdmux2_hdr->select_value_2;
2712 sel_addr1 = rdmux2_hdr->select_addr_1;
2713 sel_addr2 = rdmux2_hdr->select_addr_2;
2714 sel_val_mask = rdmux2_hdr->select_value_mask;
2715 read_addr = rdmux2_hdr->read_addr;
2716
2717 for (i = 0; i < rdmux2_hdr->op_count; i++) {
2718 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val1);
2719 t_sel_val = sel_val1 & sel_val_mask;
2720 *data_ptr++ = t_sel_val;
2721
2722 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2723 qla8044_rd_reg_indirect(vha, read_addr, &data);
2724
2725 *data_ptr++ = data;
2726
2727 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val2);
2728 t_sel_val = sel_val2 & sel_val_mask;
2729 *data_ptr++ = t_sel_val;
2730
2731 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2732 qla8044_rd_reg_indirect(vha, read_addr, &data);
2733
2734 *data_ptr++ = data;
2735
2736 sel_val1 += rdmux2_hdr->select_value_stride;
2737 sel_val2 += rdmux2_hdr->select_value_stride;
2738 }
2739
2740 *d_ptr = data_ptr;
2741 }
2742
2743 static uint32_t
2744 qla8044_minidump_process_pollrdmwr(struct scsi_qla_host *vha,
2745 struct qla8044_minidump_entry_hdr *entry_hdr,
2746 uint32_t **d_ptr)
2747 {
2748 uint32_t poll_wait, poll_mask, r_value, data;
2749 uint32_t addr_1, addr_2, value_1, value_2;
2750 struct qla8044_minidump_entry_pollrdmwr *poll_hdr;
2751 uint32_t *data_ptr = *d_ptr;
2752
2753 poll_hdr = (struct qla8044_minidump_entry_pollrdmwr *) entry_hdr;
2754 addr_1 = poll_hdr->addr_1;
2755 addr_2 = poll_hdr->addr_2;
2756 value_1 = poll_hdr->value_1;
2757 value_2 = poll_hdr->value_2;
2758 poll_mask = poll_hdr->poll_mask;
2759
2760 qla8044_wr_reg_indirect(vha, addr_1, value_1);
2761
2762 poll_wait = poll_hdr->poll_wait;
2763 while (1) {
2764 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2765
2766 if ((r_value & poll_mask) != 0) {
2767 break;
2768 } else {
2769 usleep_range(1000, 1100);
2770 if (--poll_wait == 0) {
2771 ql_log(ql_log_fatal, vha, 0xb0ff,
2772 "%s: TIMEOUT\n", __func__);
2773 goto error;
2774 }
2775 }
2776 }
2777
2778 qla8044_rd_reg_indirect(vha, addr_2, &data);
2779 data &= poll_hdr->modify_mask;
2780 qla8044_wr_reg_indirect(vha, addr_2, data);
2781 qla8044_wr_reg_indirect(vha, addr_1, value_2);
2782
2783 poll_wait = poll_hdr->poll_wait;
2784 while (1) {
2785 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2786
2787 if ((r_value & poll_mask) != 0) {
2788 break;
2789 } else {
2790 usleep_range(1000, 1100);
2791 if (--poll_wait == 0) {
2792 ql_log(ql_log_fatal, vha, 0xb100,
2793 "%s: TIMEOUT2\n", __func__);
2794 goto error;
2795 }
2796 }
2797 }
2798
2799 *data_ptr++ = addr_2;
2800 *data_ptr++ = data;
2801
2802 *d_ptr = data_ptr;
2803
2804 return QLA_SUCCESS;
2805
2806 error:
2807 return QLA_FUNCTION_FAILED;
2808 }
2809
2810 #define ISP8044_PEX_DMA_ENGINE_INDEX 8
2811 #define ISP8044_PEX_DMA_BASE_ADDRESS 0x77320000
2812 #define ISP8044_PEX_DMA_NUM_OFFSET 0x10000UL
2813 #define ISP8044_PEX_DMA_CMD_ADDR_LOW 0x0
2814 #define ISP8044_PEX_DMA_CMD_ADDR_HIGH 0x04
2815 #define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL 0x08
2816
2817 #define ISP8044_PEX_DMA_READ_SIZE (16 * 1024)
2818 #define ISP8044_PEX_DMA_MAX_WAIT (100 * 100) /* Max wait of 100 msecs */
2819
2820 static int
2821 qla8044_check_dma_engine_state(struct scsi_qla_host *vha)
2822 {
2823 struct qla_hw_data *ha = vha->hw;
2824 int rval = QLA_SUCCESS;
2825 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
2826 uint64_t dma_base_addr = 0;
2827 struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2828
2829 tmplt_hdr = ha->md_tmplt_hdr;
2830 dma_eng_num =
2831 tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2832 dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
2833 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
2834
2835 /* Read the pex-dma's command-status-and-control register. */
2836 rval = qla8044_rd_reg_indirect(vha,
2837 (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
2838 &cmd_sts_and_cntrl);
2839 if (rval)
2840 return QLA_FUNCTION_FAILED;
2841
2842 /* Check if requested pex-dma engine is available. */
2843 if (cmd_sts_and_cntrl & BIT_31)
2844 return QLA_SUCCESS;
2845
2846 return QLA_FUNCTION_FAILED;
2847 }
2848
2849 static int
2850 qla8044_start_pex_dma(struct scsi_qla_host *vha,
2851 struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr)
2852 {
2853 struct qla_hw_data *ha = vha->hw;
2854 int rval = QLA_SUCCESS, wait = 0;
2855 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
2856 uint64_t dma_base_addr = 0;
2857 struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2858
2859 tmplt_hdr = ha->md_tmplt_hdr;
2860 dma_eng_num =
2861 tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2862 dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
2863 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
2864
2865 rval = qla8044_wr_reg_indirect(vha,
2866 dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_LOW,
2867 m_hdr->desc_card_addr);
2868 if (rval)
2869 goto error_exit;
2870
2871 rval = qla8044_wr_reg_indirect(vha,
2872 dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_HIGH, 0);
2873 if (rval)
2874 goto error_exit;
2875
2876 rval = qla8044_wr_reg_indirect(vha,
2877 dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL,
2878 m_hdr->start_dma_cmd);
2879 if (rval)
2880 goto error_exit;
2881
2882 /* Wait for dma operation to complete. */
2883 for (wait = 0; wait < ISP8044_PEX_DMA_MAX_WAIT; wait++) {
2884 rval = qla8044_rd_reg_indirect(vha,
2885 (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
2886 &cmd_sts_and_cntrl);
2887 if (rval)
2888 goto error_exit;
2889
2890 if ((cmd_sts_and_cntrl & BIT_1) == 0)
2891 break;
2892
2893 udelay(10);
2894 }
2895
2896 /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
2897 if (wait >= ISP8044_PEX_DMA_MAX_WAIT) {
2898 rval = QLA_FUNCTION_FAILED;
2899 goto error_exit;
2900 }
2901
2902 error_exit:
2903 return rval;
2904 }
2905
2906 static int
2907 qla8044_minidump_pex_dma_read(struct scsi_qla_host *vha,
2908 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2909 {
2910 struct qla_hw_data *ha = vha->hw;
2911 int rval = QLA_SUCCESS;
2912 struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
2913 uint32_t chunk_size, read_size;
2914 uint8_t *data_ptr = (uint8_t *)*d_ptr;
2915 void *rdmem_buffer = NULL;
2916 dma_addr_t rdmem_dma;
2917 struct qla8044_pex_dma_descriptor dma_desc;
2918
2919 rval = qla8044_check_dma_engine_state(vha);
2920 if (rval != QLA_SUCCESS) {
2921 ql_dbg(ql_dbg_p3p, vha, 0xb147,
2922 "DMA engine not available. Fallback to rdmem-read.\n");
2923 return QLA_FUNCTION_FAILED;
2924 }
2925
2926 m_hdr = (void *)entry_hdr;
2927
2928 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
2929 ISP8044_PEX_DMA_READ_SIZE, &rdmem_dma, GFP_KERNEL);
2930 if (!rdmem_buffer) {
2931 ql_dbg(ql_dbg_p3p, vha, 0xb148,
2932 "Unable to allocate rdmem dma buffer\n");
2933 return QLA_FUNCTION_FAILED;
2934 }
2935
2936 /* Prepare pex-dma descriptor to be written to MS memory. */
2937 /* dma-desc-cmd layout:
2938 * 0-3: dma-desc-cmd 0-3
2939 * 4-7: pcid function number
2940 * 8-15: dma-desc-cmd 8-15
2941 * dma_bus_addr: dma buffer address
2942 * cmd.read_data_size: amount of data-chunk to be read.
2943 */
2944 dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
2945 dma_desc.cmd.dma_desc_cmd |=
2946 ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
2947
2948 dma_desc.dma_bus_addr = rdmem_dma;
2949 dma_desc.cmd.read_data_size = chunk_size = ISP8044_PEX_DMA_READ_SIZE;
2950 read_size = 0;
2951
2952 /*
2953 * Perform rdmem operation using pex-dma.
2954 * Prepare dma in chunks of ISP8044_PEX_DMA_READ_SIZE.
2955 */
2956 while (read_size < m_hdr->read_data_size) {
2957 if (m_hdr->read_data_size - read_size <
2958 ISP8044_PEX_DMA_READ_SIZE) {
2959 chunk_size = (m_hdr->read_data_size - read_size);
2960 dma_desc.cmd.read_data_size = chunk_size;
2961 }
2962
2963 dma_desc.src_addr = m_hdr->read_addr + read_size;
2964
2965 /* Prepare: Write pex-dma descriptor to MS memory. */
2966 rval = qla8044_ms_mem_write_128b(vha,
2967 m_hdr->desc_card_addr, (uint32_t *)&dma_desc,
2968 (sizeof(struct qla8044_pex_dma_descriptor)/16));
2969 if (rval) {
2970 ql_log(ql_log_warn, vha, 0xb14a,
2971 "%s: Error writing rdmem-dma-init to MS !!!\n",
2972 __func__);
2973 goto error_exit;
2974 }
2975 ql_dbg(ql_dbg_p3p, vha, 0xb14b,
2976 "%s: Dma-descriptor: Instruct for rdmem dma "
2977 "(chunk_size 0x%x).\n", __func__, chunk_size);
2978
2979 /* Execute: Start pex-dma operation. */
2980 rval = qla8044_start_pex_dma(vha, m_hdr);
2981 if (rval)
2982 goto error_exit;
2983
2984 memcpy(data_ptr, rdmem_buffer, chunk_size);
2985 data_ptr += chunk_size;
2986 read_size += chunk_size;
2987 }
2988
2989 *d_ptr = (uint32_t *)data_ptr;
2990
2991 error_exit:
2992 if (rdmem_buffer)
2993 dma_free_coherent(&ha->pdev->dev, ISP8044_PEX_DMA_READ_SIZE,
2994 rdmem_buffer, rdmem_dma);
2995
2996 return rval;
2997 }
2998
2999 static uint32_t
3000 qla8044_minidump_process_rddfe(struct scsi_qla_host *vha,
3001 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
3002 {
3003 int loop_cnt;
3004 uint32_t addr1, addr2, value, data, temp, wrVal;
3005 uint8_t stride, stride2;
3006 uint16_t count;
3007 uint32_t poll, mask, modify_mask;
3008 uint32_t wait_count = 0;
3009 uint32_t *data_ptr = *d_ptr;
3010 struct qla8044_minidump_entry_rddfe *rddfe;
3011
3012 rddfe = (struct qla8044_minidump_entry_rddfe *) entry_hdr;
3013
3014 addr1 = rddfe->addr_1;
3015 value = rddfe->value;
3016 stride = rddfe->stride;
3017 stride2 = rddfe->stride2;
3018 count = rddfe->count;
3019
3020 poll = rddfe->poll;
3021 mask = rddfe->mask;
3022 modify_mask = rddfe->modify_mask;
3023
3024 addr2 = addr1 + stride;
3025
3026 for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) {
3027 qla8044_wr_reg_indirect(vha, addr1, (0x40000000 | value));
3028
3029 wait_count = 0;
3030 while (wait_count < poll) {
3031 qla8044_rd_reg_indirect(vha, addr1, &temp);
3032 if ((temp & mask) != 0)
3033 break;
3034 wait_count++;
3035 }
3036
3037 if (wait_count == poll) {
3038 ql_log(ql_log_warn, vha, 0xb153,
3039 "%s: TIMEOUT\n", __func__);
3040 goto error;
3041 } else {
3042 qla8044_rd_reg_indirect(vha, addr2, &temp);
3043 temp = temp & modify_mask;
3044 temp = (temp | ((loop_cnt << 16) | loop_cnt));
3045 wrVal = ((temp << 16) | temp);
3046
3047 qla8044_wr_reg_indirect(vha, addr2, wrVal);
3048 qla8044_wr_reg_indirect(vha, addr1, value);
3049
3050 wait_count = 0;
3051 while (wait_count < poll) {
3052 qla8044_rd_reg_indirect(vha, addr1, &temp);
3053 if ((temp & mask) != 0)
3054 break;
3055 wait_count++;
3056 }
3057 if (wait_count == poll) {
3058 ql_log(ql_log_warn, vha, 0xb154,
3059 "%s: TIMEOUT\n", __func__);
3060 goto error;
3061 }
3062
3063 qla8044_wr_reg_indirect(vha, addr1,
3064 ((0x40000000 | value) + stride2));
3065 wait_count = 0;
3066 while (wait_count < poll) {
3067 qla8044_rd_reg_indirect(vha, addr1, &temp);
3068 if ((temp & mask) != 0)
3069 break;
3070 wait_count++;
3071 }
3072
3073 if (wait_count == poll) {
3074 ql_log(ql_log_warn, vha, 0xb155,
3075 "%s: TIMEOUT\n", __func__);
3076 goto error;
3077 }
3078
3079 qla8044_rd_reg_indirect(vha, addr2, &data);
3080
3081 *data_ptr++ = wrVal;
3082 *data_ptr++ = data;
3083 }
3084
3085 }
3086
3087 *d_ptr = data_ptr;
3088 return QLA_SUCCESS;
3089
3090 error:
3091 return -1;
3092
3093 }
3094
3095 static uint32_t
3096 qla8044_minidump_process_rdmdio(struct scsi_qla_host *vha,
3097 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
3098 {
3099 int ret = 0;
3100 uint32_t addr1, addr2, value1, value2, data, selVal;
3101 uint8_t stride1, stride2;
3102 uint32_t addr3, addr4, addr5, addr6, addr7;
3103 uint16_t count, loop_cnt;
3104 uint32_t mask;
3105 uint32_t *data_ptr = *d_ptr;
3106
3107 struct qla8044_minidump_entry_rdmdio *rdmdio;
3108
3109 rdmdio = (struct qla8044_minidump_entry_rdmdio *) entry_hdr;
3110
3111 addr1 = rdmdio->addr_1;
3112 addr2 = rdmdio->addr_2;
3113 value1 = rdmdio->value_1;
3114 stride1 = rdmdio->stride_1;
3115 stride2 = rdmdio->stride_2;
3116 count = rdmdio->count;
3117
3118 mask = rdmdio->mask;
3119 value2 = rdmdio->value_2;
3120
3121 addr3 = addr1 + stride1;
3122
3123 for (loop_cnt = 0; loop_cnt < count; loop_cnt++) {
3124 ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2,
3125 addr3, mask);
3126 if (ret == -1)
3127 goto error;
3128
3129 addr4 = addr2 - stride1;
3130 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr4,
3131 value2);
3132 if (ret == -1)
3133 goto error;
3134
3135 addr5 = addr2 - (2 * stride1);
3136 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr5,
3137 value1);
3138 if (ret == -1)
3139 goto error;
3140
3141 addr6 = addr2 - (3 * stride1);
3142 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask,
3143 addr6, 0x2);
3144 if (ret == -1)
3145 goto error;
3146
3147 ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2,
3148 addr3, mask);
3149 if (ret == -1)
3150 goto error;
3151
3152 addr7 = addr2 - (4 * stride1);
3153 data = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr7);
3154 if (data == -1)
3155 goto error;
3156
3157 selVal = (value2 << 18) | (value1 << 2) | 2;
3158
3159 stride2 = rdmdio->stride_2;
3160 *data_ptr++ = selVal;
3161 *data_ptr++ = data;
3162
3163 value1 = value1 + stride2;
3164 *d_ptr = data_ptr;
3165 }
3166
3167 return 0;
3168
3169 error:
3170 return -1;
3171 }
3172
3173 static uint32_t qla8044_minidump_process_pollwr(struct scsi_qla_host *vha,
3174 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
3175 {
3176 uint32_t addr1, addr2, value1, value2, poll, r_value;
3177 uint32_t wait_count = 0;
3178 struct qla8044_minidump_entry_pollwr *pollwr_hdr;
3179
3180 pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr;
3181 addr1 = pollwr_hdr->addr_1;
3182 addr2 = pollwr_hdr->addr_2;
3183 value1 = pollwr_hdr->value_1;
3184 value2 = pollwr_hdr->value_2;
3185
3186 poll = pollwr_hdr->poll;
3187
3188 while (wait_count < poll) {
3189 qla8044_rd_reg_indirect(vha, addr1, &r_value);
3190
3191 if ((r_value & poll) != 0)
3192 break;
3193 wait_count++;
3194 }
3195
3196 if (wait_count == poll) {
3197 ql_log(ql_log_warn, vha, 0xb156, "%s: TIMEOUT\n", __func__);
3198 goto error;
3199 }
3200
3201 qla8044_wr_reg_indirect(vha, addr2, value2);
3202 qla8044_wr_reg_indirect(vha, addr1, value1);
3203
3204 wait_count = 0;
3205 while (wait_count < poll) {
3206 qla8044_rd_reg_indirect(vha, addr1, &r_value);
3207
3208 if ((r_value & poll) != 0)
3209 break;
3210 wait_count++;
3211 }
3212
3213 return QLA_SUCCESS;
3214
3215 error:
3216 return -1;
3217 }
3218
3219 /*
3220 *
3221 * qla8044_collect_md_data - Retrieve firmware minidump data.
3222 * @ha: pointer to adapter structure
3223 **/
3224 int
3225 qla8044_collect_md_data(struct scsi_qla_host *vha)
3226 {
3227 int num_entry_hdr = 0;
3228 struct qla8044_minidump_entry_hdr *entry_hdr;
3229 struct qla8044_minidump_template_hdr *tmplt_hdr;
3230 uint32_t *data_ptr;
3231 uint32_t data_collected = 0, f_capture_mask;
3232 int i, rval = QLA_FUNCTION_FAILED;
3233 uint64_t now;
3234 uint32_t timestamp, idc_control;
3235 struct qla_hw_data *ha = vha->hw;
3236
3237 if (!ha->md_dump) {
3238 ql_log(ql_log_info, vha, 0xb101,
3239 "%s(%ld) No buffer to dump\n",
3240 __func__, vha->host_no);
3241 return rval;
3242 }
3243
3244 if (ha->fw_dumped) {
3245 ql_log(ql_log_warn, vha, 0xb10d,
3246 "Firmware has been previously dumped (%p) "
3247 "-- ignoring request.\n", ha->fw_dump);
3248 goto md_failed;
3249 }
3250
3251 ha->fw_dumped = false;
3252
3253 if (!ha->md_tmplt_hdr || !ha->md_dump) {
3254 ql_log(ql_log_warn, vha, 0xb10e,
3255 "Memory not allocated for minidump capture\n");
3256 goto md_failed;
3257 }
3258
3259 qla8044_idc_lock(ha);
3260 idc_control = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
3261 if (idc_control & GRACEFUL_RESET_BIT1) {
3262 ql_log(ql_log_warn, vha, 0xb112,
3263 "Forced reset from application, "
3264 "ignore minidump capture\n");
3265 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
3266 (idc_control & ~GRACEFUL_RESET_BIT1));
3267 qla8044_idc_unlock(ha);
3268
3269 goto md_failed;
3270 }
3271 qla8044_idc_unlock(ha);
3272
3273 if (qla82xx_validate_template_chksum(vha)) {
3274 ql_log(ql_log_info, vha, 0xb109,
3275 "Template checksum validation error\n");
3276 goto md_failed;
3277 }
3278
3279 tmplt_hdr = (struct qla8044_minidump_template_hdr *)
3280 ha->md_tmplt_hdr;
3281 data_ptr = (uint32_t *)((uint8_t *)ha->md_dump);
3282 num_entry_hdr = tmplt_hdr->num_of_entries;
3283
3284 ql_dbg(ql_dbg_p3p, vha, 0xb11a,
3285 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
3286
3287 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
3288
3289 /* Validate whether required debug level is set */
3290 if ((f_capture_mask & 0x3) != 0x3) {
3291 ql_log(ql_log_warn, vha, 0xb10f,
3292 "Minimum required capture mask[0x%x] level not set\n",
3293 f_capture_mask);
3294
3295 }
3296 tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
3297 ql_log(ql_log_info, vha, 0xb102,
3298 "[%s]: starting data ptr: %p\n",
3299 __func__, data_ptr);
3300 ql_log(ql_log_info, vha, 0xb10b,
3301 "[%s]: no of entry headers in Template: 0x%x\n",
3302 __func__, num_entry_hdr);
3303 ql_log(ql_log_info, vha, 0xb10c,
3304 "[%s]: Total_data_size 0x%x, %d obtained\n",
3305 __func__, ha->md_dump_size, ha->md_dump_size);
3306
3307 /* Update current timestamp before taking dump */
3308 now = get_jiffies_64();
3309 timestamp = (u32)(jiffies_to_msecs(now) / 1000);
3310 tmplt_hdr->driver_timestamp = timestamp;
3311
3312 entry_hdr = (struct qla8044_minidump_entry_hdr *)
3313 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
3314 tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] =
3315 tmplt_hdr->ocm_window_reg[ha->portnum];
3316
3317 /* Walk through the entry headers - validate/perform required action */
3318 for (i = 0; i < num_entry_hdr; i++) {
3319 if (data_collected > ha->md_dump_size) {
3320 ql_log(ql_log_info, vha, 0xb103,
3321 "Data collected: [0x%x], "
3322 "Total Dump size: [0x%x]\n",
3323 data_collected, ha->md_dump_size);
3324 return rval;
3325 }
3326
3327 if (!(entry_hdr->d_ctrl.entry_capture_mask &
3328 ql2xmdcapmask)) {
3329 entry_hdr->d_ctrl.driver_flags |=
3330 QLA82XX_DBG_SKIPPED_FLAG;
3331 goto skip_nxt_entry;
3332 }
3333
3334 ql_dbg(ql_dbg_p3p, vha, 0xb104,
3335 "Data collected: [0x%x], Dump size left:[0x%x]\n",
3336 data_collected,
3337 (ha->md_dump_size - data_collected));
3338
3339 /* Decode the entry type and take required action to capture
3340 * debug data
3341 */
3342 switch (entry_hdr->entry_type) {
3343 case QLA82XX_RDEND:
3344 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3345 break;
3346 case QLA82XX_CNTRL:
3347 rval = qla8044_minidump_process_control(vha,
3348 entry_hdr);
3349 if (rval != QLA_SUCCESS) {
3350 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3351 goto md_failed;
3352 }
3353 break;
3354 case QLA82XX_RDCRB:
3355 qla8044_minidump_process_rdcrb(vha,
3356 entry_hdr, &data_ptr);
3357 break;
3358 case QLA82XX_RDMEM:
3359 rval = qla8044_minidump_pex_dma_read(vha,
3360 entry_hdr, &data_ptr);
3361 if (rval != QLA_SUCCESS) {
3362 rval = qla8044_minidump_process_rdmem(vha,
3363 entry_hdr, &data_ptr);
3364 if (rval != QLA_SUCCESS) {
3365 qla8044_mark_entry_skipped(vha,
3366 entry_hdr, i);
3367 goto md_failed;
3368 }
3369 }
3370 break;
3371 case QLA82XX_BOARD:
3372 case QLA82XX_RDROM:
3373 rval = qla8044_minidump_process_rdrom(vha,
3374 entry_hdr, &data_ptr);
3375 if (rval != QLA_SUCCESS) {
3376 qla8044_mark_entry_skipped(vha,
3377 entry_hdr, i);
3378 }
3379 break;
3380 case QLA82XX_L2DTG:
3381 case QLA82XX_L2ITG:
3382 case QLA82XX_L2DAT:
3383 case QLA82XX_L2INS:
3384 rval = qla8044_minidump_process_l2tag(vha,
3385 entry_hdr, &data_ptr);
3386 if (rval != QLA_SUCCESS) {
3387 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3388 goto md_failed;
3389 }
3390 break;
3391 case QLA8044_L1DTG:
3392 case QLA8044_L1ITG:
3393 case QLA82XX_L1DAT:
3394 case QLA82XX_L1INS:
3395 qla8044_minidump_process_l1cache(vha,
3396 entry_hdr, &data_ptr);
3397 break;
3398 case QLA82XX_RDOCM:
3399 qla8044_minidump_process_rdocm(vha,
3400 entry_hdr, &data_ptr);
3401 break;
3402 case QLA82XX_RDMUX:
3403 qla8044_minidump_process_rdmux(vha,
3404 entry_hdr, &data_ptr);
3405 break;
3406 case QLA82XX_QUEUE:
3407 qla8044_minidump_process_queue(vha,
3408 entry_hdr, &data_ptr);
3409 break;
3410 case QLA8044_POLLRD:
3411 rval = qla8044_minidump_process_pollrd(vha,
3412 entry_hdr, &data_ptr);
3413 if (rval != QLA_SUCCESS)
3414 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3415 break;
3416 case QLA8044_RDMUX2:
3417 qla8044_minidump_process_rdmux2(vha,
3418 entry_hdr, &data_ptr);
3419 break;
3420 case QLA8044_POLLRDMWR:
3421 rval = qla8044_minidump_process_pollrdmwr(vha,
3422 entry_hdr, &data_ptr);
3423 if (rval != QLA_SUCCESS)
3424 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3425 break;
3426 case QLA8044_RDDFE:
3427 rval = qla8044_minidump_process_rddfe(vha, entry_hdr,
3428 &data_ptr);
3429 if (rval != QLA_SUCCESS)
3430 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3431 break;
3432 case QLA8044_RDMDIO:
3433 rval = qla8044_minidump_process_rdmdio(vha, entry_hdr,
3434 &data_ptr);
3435 if (rval != QLA_SUCCESS)
3436 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3437 break;
3438 case QLA8044_POLLWR:
3439 rval = qla8044_minidump_process_pollwr(vha, entry_hdr,
3440 &data_ptr);
3441 if (rval != QLA_SUCCESS)
3442 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3443 break;
3444 case QLA82XX_RDNOP:
3445 default:
3446 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3447 break;
3448 }
3449
3450 data_collected = (uint8_t *)data_ptr -
3451 (uint8_t *)((uint8_t *)ha->md_dump);
3452 skip_nxt_entry:
3453 /*
3454 * next entry in the template
3455 */
3456 entry_hdr = (struct qla8044_minidump_entry_hdr *)
3457 (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
3458 }
3459
3460 if (data_collected != ha->md_dump_size) {
3461 ql_log(ql_log_info, vha, 0xb105,
3462 "Dump data mismatch: Data collected: "
3463 "[0x%x], total_data_size:[0x%x]\n",
3464 data_collected, ha->md_dump_size);
3465 rval = QLA_FUNCTION_FAILED;
3466 goto md_failed;
3467 }
3468
3469 ql_log(ql_log_info, vha, 0xb110,
3470 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
3471 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
3472 ha->fw_dumped = true;
3473 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
3474
3475
3476 ql_log(ql_log_info, vha, 0xb106,
3477 "Leaving fn: %s Last entry: 0x%x\n",
3478 __func__, i);
3479 md_failed:
3480 return rval;
3481 }
3482
3483 void
3484 qla8044_get_minidump(struct scsi_qla_host *vha)
3485 {
3486 struct qla_hw_data *ha = vha->hw;
3487
3488 if (!qla8044_collect_md_data(vha)) {
3489 ha->fw_dumped = true;
3490 ha->prev_minidump_failed = 0;
3491 } else {
3492 ql_log(ql_log_fatal, vha, 0xb0db,
3493 "%s: Unable to collect minidump\n",
3494 __func__);
3495 ha->prev_minidump_failed = 1;
3496 }
3497 }
3498
3499 static int
3500 qla8044_poll_flash_status_reg(struct scsi_qla_host *vha)
3501 {
3502 uint32_t flash_status;
3503 int retries = QLA8044_FLASH_READ_RETRY_COUNT;
3504 int ret_val = QLA_SUCCESS;
3505
3506 while (retries--) {
3507 ret_val = qla8044_rd_reg_indirect(vha, QLA8044_FLASH_STATUS,
3508 &flash_status);
3509 if (ret_val) {
3510 ql_log(ql_log_warn, vha, 0xb13c,
3511 "%s: Failed to read FLASH_STATUS reg.\n",
3512 __func__);
3513 break;
3514 }
3515 if ((flash_status & QLA8044_FLASH_STATUS_READY) ==
3516 QLA8044_FLASH_STATUS_READY)
3517 break;
3518 msleep(QLA8044_FLASH_STATUS_REG_POLL_DELAY);
3519 }
3520
3521 if (!retries)
3522 ret_val = QLA_FUNCTION_FAILED;
3523
3524 return ret_val;
3525 }
3526
3527 static int
3528 qla8044_write_flash_status_reg(struct scsi_qla_host *vha,
3529 uint32_t data)
3530 {
3531 int ret_val = QLA_SUCCESS;
3532 uint32_t cmd;
3533
3534 cmd = vha->hw->fdt_wrt_sts_reg_cmd;
3535
3536 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3537 QLA8044_FLASH_STATUS_WRITE_DEF_SIG | cmd);
3538 if (ret_val) {
3539 ql_log(ql_log_warn, vha, 0xb125,
3540 "%s: Failed to write to FLASH_ADDR.\n", __func__);
3541 goto exit_func;
3542 }
3543
3544 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, data);
3545 if (ret_val) {
3546 ql_log(ql_log_warn, vha, 0xb126,
3547 "%s: Failed to write to FLASH_WRDATA.\n", __func__);
3548 goto exit_func;
3549 }
3550
3551 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3552 QLA8044_FLASH_SECOND_ERASE_MS_VAL);
3553 if (ret_val) {
3554 ql_log(ql_log_warn, vha, 0xb127,
3555 "%s: Failed to write to FLASH_CONTROL.\n", __func__);
3556 goto exit_func;
3557 }
3558
3559 ret_val = qla8044_poll_flash_status_reg(vha);
3560 if (ret_val)
3561 ql_log(ql_log_warn, vha, 0xb128,
3562 "%s: Error polling flash status reg.\n", __func__);
3563
3564 exit_func:
3565 return ret_val;
3566 }
3567
3568 /*
3569 * This function assumes that the flash lock is held.
3570 */
3571 static int
3572 qla8044_unprotect_flash(scsi_qla_host_t *vha)
3573 {
3574 int ret_val;
3575 struct qla_hw_data *ha = vha->hw;
3576
3577 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable);
3578 if (ret_val)
3579 ql_log(ql_log_warn, vha, 0xb139,
3580 "%s: Write flash status failed.\n", __func__);
3581
3582 return ret_val;
3583 }
3584
3585 /*
3586 * This function assumes that the flash lock is held.
3587 */
3588 static int
3589 qla8044_protect_flash(scsi_qla_host_t *vha)
3590 {
3591 int ret_val;
3592 struct qla_hw_data *ha = vha->hw;
3593
3594 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable);
3595 if (ret_val)
3596 ql_log(ql_log_warn, vha, 0xb13b,
3597 "%s: Write flash status failed.\n", __func__);
3598
3599 return ret_val;
3600 }
3601
3602
3603 static int
3604 qla8044_erase_flash_sector(struct scsi_qla_host *vha,
3605 uint32_t sector_start_addr)
3606 {
3607 uint32_t reversed_addr;
3608 int ret_val = QLA_SUCCESS;
3609
3610 ret_val = qla8044_poll_flash_status_reg(vha);
3611 if (ret_val) {
3612 ql_log(ql_log_warn, vha, 0xb12e,
3613 "%s: Poll flash status after erase failed..\n", __func__);
3614 }
3615
3616 reversed_addr = (((sector_start_addr & 0xFF) << 16) |
3617 (sector_start_addr & 0xFF00) |
3618 ((sector_start_addr & 0xFF0000) >> 16));
3619
3620 ret_val = qla8044_wr_reg_indirect(vha,
3621 QLA8044_FLASH_WRDATA, reversed_addr);
3622 if (ret_val) {
3623 ql_log(ql_log_warn, vha, 0xb12f,
3624 "%s: Failed to write to FLASH_WRDATA.\n", __func__);
3625 }
3626 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3627 QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd);
3628 if (ret_val) {
3629 ql_log(ql_log_warn, vha, 0xb130,
3630 "%s: Failed to write to FLASH_ADDR.\n", __func__);
3631 }
3632 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3633 QLA8044_FLASH_LAST_ERASE_MS_VAL);
3634 if (ret_val) {
3635 ql_log(ql_log_warn, vha, 0xb131,
3636 "%s: Failed write to FLASH_CONTROL.\n", __func__);
3637 }
3638 ret_val = qla8044_poll_flash_status_reg(vha);
3639 if (ret_val) {
3640 ql_log(ql_log_warn, vha, 0xb132,
3641 "%s: Poll flash status failed.\n", __func__);
3642 }
3643
3644
3645 return ret_val;
3646 }
3647
3648 /*
3649 * qla8044_flash_write_u32 - Write data to flash
3650 *
3651 * @ha : Pointer to adapter structure
3652 * addr : Flash address to write to
3653 * p_data : Data to be written
3654 *
3655 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
3656 *
3657 * NOTE: Lock should be held on entry
3658 */
3659 static int
3660 qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr,
3661 uint32_t *p_data)
3662 {
3663 int ret_val = QLA_SUCCESS;
3664
3665 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3666 0x00800000 | (addr >> 2));
3667 if (ret_val) {
3668 ql_log(ql_log_warn, vha, 0xb134,
3669 "%s: Failed write to FLASH_ADDR.\n", __func__);
3670 goto exit_func;
3671 }
3672 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *p_data);
3673 if (ret_val) {
3674 ql_log(ql_log_warn, vha, 0xb135,
3675 "%s: Failed write to FLASH_WRDATA.\n", __func__);
3676 goto exit_func;
3677 }
3678 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 0x3D);
3679 if (ret_val) {
3680 ql_log(ql_log_warn, vha, 0xb136,
3681 "%s: Failed write to FLASH_CONTROL.\n", __func__);
3682 goto exit_func;
3683 }
3684 ret_val = qla8044_poll_flash_status_reg(vha);
3685 if (ret_val) {
3686 ql_log(ql_log_warn, vha, 0xb137,
3687 "%s: Poll flash status failed.\n", __func__);
3688 }
3689
3690 exit_func:
3691 return ret_val;
3692 }
3693
3694 static int
3695 qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3696 uint32_t faddr, uint32_t dwords)
3697 {
3698 int ret = QLA_FUNCTION_FAILED;
3699 uint32_t spi_val;
3700
3701 if (dwords < QLA8044_MIN_OPTROM_BURST_DWORDS ||
3702 dwords > QLA8044_MAX_OPTROM_BURST_DWORDS) {
3703 ql_dbg(ql_dbg_user, vha, 0xb123,
3704 "Got unsupported dwords = 0x%x.\n",
3705 dwords);
3706 return QLA_FUNCTION_FAILED;
3707 }
3708
3709 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, &spi_val);
3710 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3711 spi_val | QLA8044_FLASH_SPI_CTL);
3712 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3713 QLA8044_FLASH_FIRST_TEMP_VAL);
3714
3715 /* First DWORD write to FLASH_WRDATA */
3716 ret = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA,
3717 *dwptr++);
3718 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3719 QLA8044_FLASH_FIRST_MS_PATTERN);
3720
3721 ret = qla8044_poll_flash_status_reg(vha);
3722 if (ret) {
3723 ql_log(ql_log_warn, vha, 0xb124,
3724 "%s: Failed.\n", __func__);
3725 goto exit_func;
3726 }
3727
3728 dwords--;
3729
3730 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3731 QLA8044_FLASH_SECOND_TEMP_VAL);
3732
3733
3734 /* Second to N-1 DWORDS writes */
3735 while (dwords != 1) {
3736 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3737 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3738 QLA8044_FLASH_SECOND_MS_PATTERN);
3739 ret = qla8044_poll_flash_status_reg(vha);
3740 if (ret) {
3741 ql_log(ql_log_warn, vha, 0xb129,
3742 "%s: Failed.\n", __func__);
3743 goto exit_func;
3744 }
3745 dwords--;
3746 }
3747
3748 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3749 QLA8044_FLASH_FIRST_TEMP_VAL | (faddr >> 2));
3750
3751 /* Last DWORD write */
3752 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3753 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3754 QLA8044_FLASH_LAST_MS_PATTERN);
3755 ret = qla8044_poll_flash_status_reg(vha);
3756 if (ret) {
3757 ql_log(ql_log_warn, vha, 0xb12a,
3758 "%s: Failed.\n", __func__);
3759 goto exit_func;
3760 }
3761 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_STATUS, &spi_val);
3762
3763 if ((spi_val & QLA8044_FLASH_SPI_CTL) == QLA8044_FLASH_SPI_CTL) {
3764 ql_log(ql_log_warn, vha, 0xb12b,
3765 "%s: Failed.\n", __func__);
3766 spi_val = 0;
3767 /* Operation failed, clear error bit. */
3768 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3769 &spi_val);
3770 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3771 spi_val | QLA8044_FLASH_SPI_CTL);
3772 }
3773 exit_func:
3774 return ret;
3775 }
3776
3777 static int
3778 qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3779 uint32_t faddr, uint32_t dwords)
3780 {
3781 int ret = QLA_FUNCTION_FAILED;
3782 uint32_t liter;
3783
3784 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
3785 ret = qla8044_flash_write_u32(vha, faddr, dwptr);
3786 if (ret) {
3787 ql_dbg(ql_dbg_p3p, vha, 0xb141,
3788 "%s: flash address=%x data=%x.\n", __func__,
3789 faddr, *dwptr);
3790 break;
3791 }
3792 }
3793
3794 return ret;
3795 }
3796
3797 int
3798 qla8044_write_optrom_data(struct scsi_qla_host *vha, void *buf,
3799 uint32_t offset, uint32_t length)
3800 {
3801 int rval = QLA_FUNCTION_FAILED, i, burst_iter_count;
3802 int dword_count, erase_sec_count;
3803 uint32_t erase_offset;
3804 uint8_t *p_cache, *p_src;
3805
3806 erase_offset = offset;
3807
3808 p_cache = kcalloc(length, sizeof(uint8_t), GFP_KERNEL);
3809 if (!p_cache)
3810 return QLA_FUNCTION_FAILED;
3811
3812 memcpy(p_cache, buf, length);
3813 p_src = p_cache;
3814 dword_count = length / sizeof(uint32_t);
3815 /* Since the offset and legth are sector aligned, it will be always
3816 * multiple of burst_iter_count (64)
3817 */
3818 burst_iter_count = dword_count / QLA8044_MAX_OPTROM_BURST_DWORDS;
3819 erase_sec_count = length / QLA8044_SECTOR_SIZE;
3820
3821 /* Suspend HBA. */
3822 scsi_block_requests(vha->host);
3823 /* Lock and enable write for whole operation. */
3824 qla8044_flash_lock(vha);
3825 qla8044_unprotect_flash(vha);
3826
3827 /* Erasing the sectors */
3828 for (i = 0; i < erase_sec_count; i++) {
3829 rval = qla8044_erase_flash_sector(vha, erase_offset);
3830 ql_dbg(ql_dbg_user, vha, 0xb138,
3831 "Done erase of sector=0x%x.\n",
3832 erase_offset);
3833 if (rval) {
3834 ql_log(ql_log_warn, vha, 0xb121,
3835 "Failed to erase the sector having address: "
3836 "0x%x.\n", erase_offset);
3837 goto out;
3838 }
3839 erase_offset += QLA8044_SECTOR_SIZE;
3840 }
3841 ql_dbg(ql_dbg_user, vha, 0xb13f,
3842 "Got write for addr = 0x%x length=0x%x.\n",
3843 offset, length);
3844
3845 for (i = 0; i < burst_iter_count; i++) {
3846
3847 /* Go with write. */
3848 rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src,
3849 offset, QLA8044_MAX_OPTROM_BURST_DWORDS);
3850 if (rval) {
3851 /* Buffer Mode failed skip to dword mode */
3852 ql_log(ql_log_warn, vha, 0xb122,
3853 "Failed to write flash in buffer mode, "
3854 "Reverting to slow-write.\n");
3855 rval = qla8044_write_flash_dword_mode(vha,
3856 (uint32_t *)p_src, offset,
3857 QLA8044_MAX_OPTROM_BURST_DWORDS);
3858 }
3859 p_src += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
3860 offset += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
3861 }
3862 ql_dbg(ql_dbg_user, vha, 0xb133,
3863 "Done writing.\n");
3864
3865 out:
3866 qla8044_protect_flash(vha);
3867 qla8044_flash_unlock(vha);
3868 scsi_unblock_requests(vha->host);
3869 kfree(p_cache);
3870
3871 return rval;
3872 }
3873
3874 #define LEG_INT_PTR_B31 (1 << 31)
3875 #define LEG_INT_PTR_B30 (1 << 30)
3876 #define PF_BITS_MASK (0xF << 16)
3877 /**
3878 * qla8044_intr_handler() - Process interrupts for the ISP8044
3879 * @irq: interrupt number
3880 * @dev_id: SCSI driver HA context
3881 *
3882 * Called by system whenever the host adapter generates an interrupt.
3883 *
3884 * Returns handled flag.
3885 */
3886 irqreturn_t
3887 qla8044_intr_handler(int irq, void *dev_id)
3888 {
3889 scsi_qla_host_t *vha;
3890 struct qla_hw_data *ha;
3891 struct rsp_que *rsp;
3892 struct device_reg_82xx __iomem *reg;
3893 int status = 0;
3894 unsigned long flags;
3895 unsigned long iter;
3896 uint32_t stat;
3897 uint16_t mb[8];
3898 uint32_t leg_int_ptr = 0, pf_bit;
3899
3900 rsp = (struct rsp_que *) dev_id;
3901 if (!rsp) {
3902 ql_log(ql_log_info, NULL, 0xb143,
3903 "%s(): NULL response queue pointer\n", __func__);
3904 return IRQ_NONE;
3905 }
3906 ha = rsp->hw;
3907 vha = pci_get_drvdata(ha->pdev);
3908
3909 if (unlikely(pci_channel_offline(ha->pdev)))
3910 return IRQ_HANDLED;
3911
3912 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
3913
3914 /* Legacy interrupt is valid if bit31 of leg_int_ptr is set */
3915 if (!(leg_int_ptr & (LEG_INT_PTR_B31))) {
3916 ql_dbg(ql_dbg_p3p, vha, 0xb144,
3917 "%s: Legacy Interrupt Bit 31 not set, "
3918 "spurious interrupt!\n", __func__);
3919 return IRQ_NONE;
3920 }
3921
3922 pf_bit = ha->portnum << 16;
3923 /* Validate the PCIE function ID set in leg_int_ptr bits [19..16] */
3924 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) {
3925 ql_dbg(ql_dbg_p3p, vha, 0xb145,
3926 "%s: Incorrect function ID 0x%x in "
3927 "legacy interrupt register, "
3928 "ha->pf_bit = 0x%x\n", __func__,
3929 (leg_int_ptr & (PF_BITS_MASK)), pf_bit);
3930 return IRQ_NONE;
3931 }
3932
3933 /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger
3934 * Control register and poll till Legacy Interrupt Pointer register
3935 * bit32 is 0.
3936 */
3937 qla8044_wr_reg(ha, LEG_INTR_TRIG_OFFSET, 0);
3938 do {
3939 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
3940 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit)
3941 break;
3942 } while (leg_int_ptr & (LEG_INT_PTR_B30));
3943
3944 reg = &ha->iobase->isp82;
3945 spin_lock_irqsave(&ha->hardware_lock, flags);
3946 for (iter = 1; iter--; ) {
3947
3948 if (rd_reg_dword(&reg->host_int)) {
3949 stat = rd_reg_dword(&reg->host_status);
3950 if ((stat & HSRX_RISC_INT) == 0)
3951 break;
3952
3953 switch (stat & 0xff) {
3954 case 0x1:
3955 case 0x2:
3956 case 0x10:
3957 case 0x11:
3958 qla82xx_mbx_completion(vha, MSW(stat));
3959 status |= MBX_INTERRUPT;
3960 break;
3961 case 0x12:
3962 mb[0] = MSW(stat);
3963 mb[1] = rd_reg_word(&reg->mailbox_out[1]);
3964 mb[2] = rd_reg_word(&reg->mailbox_out[2]);
3965 mb[3] = rd_reg_word(&reg->mailbox_out[3]);
3966 qla2x00_async_event(vha, rsp, mb);
3967 break;
3968 case 0x13:
3969 qla24xx_process_response_queue(vha, rsp);
3970 break;
3971 default:
3972 ql_dbg(ql_dbg_p3p, vha, 0xb146,
3973 "Unrecognized interrupt type "
3974 "(%d).\n", stat & 0xff);
3975 break;
3976 }
3977 }
3978 wrt_reg_dword(&reg->host_int, 0);
3979 }
3980
3981 qla2x00_handle_mbx_completion(ha, status);
3982 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3983
3984 return IRQ_HANDLED;
3985 }
3986
3987 static int
3988 qla8044_idc_dontreset(struct qla_hw_data *ha)
3989 {
3990 uint32_t idc_ctrl;
3991
3992 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
3993 return idc_ctrl & DONTRESET_BIT0;
3994 }
3995
3996 static void
3997 qla8044_clear_rst_ready(scsi_qla_host_t *vha)
3998 {
3999 uint32_t drv_state;
4000
4001 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
4002
4003 /*
4004 * For ISP8044, drv_active register has 1 bit per function,
4005 * shift 1 by func_num to set a bit for the function.
4006 * For ISP82xx, drv_active has 4 bits per function
4007 */
4008 drv_state &= ~(1 << vha->hw->portnum);
4009
4010 ql_dbg(ql_dbg_p3p, vha, 0xb13d,
4011 "drv_state: 0x%08x\n", drv_state);
4012 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
4013 }
4014
4015 int
4016 qla8044_abort_isp(scsi_qla_host_t *vha)
4017 {
4018 int rval;
4019 uint32_t dev_state;
4020 struct qla_hw_data *ha = vha->hw;
4021
4022 qla8044_idc_lock(ha);
4023 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
4024
4025 if (ql2xdontresethba)
4026 qla8044_set_idc_dontreset(vha);
4027
4028 /* If device_state is NEED_RESET, go ahead with
4029 * Reset,irrespective of ql2xdontresethba. This is to allow a
4030 * non-reset-owner to force a reset. Non-reset-owner sets
4031 * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset
4032 * and then forces a Reset by setting device_state to
4033 * NEED_RESET. */
4034 if (dev_state == QLA8XXX_DEV_READY) {
4035 /* If IDC_CTRL DONTRESETHBA_BIT0 is set don't do reset
4036 * recovery */
4037 if (qla8044_idc_dontreset(ha) == DONTRESET_BIT0) {
4038 ql_dbg(ql_dbg_p3p, vha, 0xb13e,
4039 "Reset recovery disabled\n");
4040 rval = QLA_FUNCTION_FAILED;
4041 goto exit_isp_reset;
4042 }
4043
4044 ql_dbg(ql_dbg_p3p, vha, 0xb140,
4045 "HW State: NEED RESET\n");
4046 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
4047 QLA8XXX_DEV_NEED_RESET);
4048 }
4049
4050 /* For ISP8044, Reset owner is NIC, iSCSI or FCOE based on priority
4051 * and which drivers are present. Unlike ISP82XX, the function setting
4052 * NEED_RESET, may not be the Reset owner. */
4053 qla83xx_reset_ownership(vha);
4054
4055 qla8044_idc_unlock(ha);
4056 rval = qla8044_device_state_handler(vha);
4057 qla8044_idc_lock(ha);
4058 qla8044_clear_rst_ready(vha);
4059
4060 exit_isp_reset:
4061 qla8044_idc_unlock(ha);
4062 if (rval == QLA_SUCCESS) {
4063 ha->flags.isp82xx_fw_hung = 0;
4064 ha->flags.nic_core_reset_hdlr_active = 0;
4065 rval = qla82xx_restart_isp(vha);
4066 }
4067
4068 return rval;
4069 }
4070
4071 void
4072 qla8044_fw_dump(scsi_qla_host_t *vha)
4073 {
4074 struct qla_hw_data *ha = vha->hw;
4075
4076 if (!ha->allow_cna_fw_dump)
4077 return;
4078
4079 scsi_block_requests(vha->host);
4080 ha->flags.isp82xx_no_md_cap = 1;
4081 qla8044_idc_lock(ha);
4082 qla82xx_set_reset_owner(vha);
4083 qla8044_idc_unlock(ha);
4084 qla2x00_wait_for_chip_reset(vha);
4085 scsi_unblock_requests(vha->host);
4086 }
Linux with added FPC-III support