1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt control channel messages
5 * Copyright (C) 2014 Andreas Noever <andreas.noever@gmail.com>
6 * Copyright (C) 2017, Intel Corporation
12 #include <linux/types.h>
13 #include <linux/uuid.h>
23 TB_CFG_ERROR_PORT_NOT_CONNECTED
= 0,
24 TB_CFG_ERROR_LINK_ERROR
= 1,
25 TB_CFG_ERROR_INVALID_CONFIG_SPACE
= 2,
26 TB_CFG_ERROR_NO_SUCH_PORT
= 4,
27 TB_CFG_ERROR_ACK_PLUG_EVENT
= 7, /* send as reply to TB_CFG_PKG_EVENT */
28 TB_CFG_ERROR_LOOP
= 8,
29 TB_CFG_ERROR_HEC_ERROR_DETECTED
= 12,
30 TB_CFG_ERROR_FLOW_CONTROL_ERROR
= 13,
31 TB_CFG_ERROR_LOCK
= 15,
35 struct tb_cfg_header
{
37 u32 unknown
:10; /* highest order bit is set on replies */
41 /* additional header for read/write packets */
42 struct tb_cfg_address
{
43 u32 offset
:13; /* in dwords */
44 u32 length
:6; /* in dwords */
46 enum tb_cfg_space space
:2;
47 u32 seq
:2; /* sequence number */
51 /* TB_CFG_PKG_READ, response for TB_CFG_PKG_WRITE */
53 struct tb_cfg_header header
;
54 struct tb_cfg_address addr
;
57 /* TB_CFG_PKG_WRITE, response for TB_CFG_PKG_READ */
58 struct cfg_write_pkg
{
59 struct tb_cfg_header header
;
60 struct tb_cfg_address addr
;
61 u32 data
[64]; /* maximum size, tb_cfg_address.length has 6 bits */
64 /* TB_CFG_PKG_ERROR */
65 struct cfg_error_pkg
{
66 struct tb_cfg_header header
;
67 enum tb_cfg_error error
:4;
70 u32 zero2
:2; /* Both should be zero, still they are different fields. */
75 #define TB_CFG_ERROR_PG_HOT_PLUG 0x2
76 #define TB_CFG_ERROR_PG_HOT_UNPLUG 0x3
78 /* TB_CFG_PKG_EVENT */
79 struct cfg_event_pkg
{
80 struct tb_cfg_header header
;
86 /* TB_CFG_PKG_RESET */
87 struct cfg_reset_pkg
{
88 struct tb_cfg_header header
;
91 /* TB_CFG_PKG_PREPARE_TO_SLEEP */
93 struct tb_cfg_header header
;
100 ICM_GET_TOPOLOGY
= 0x1,
101 ICM_DRIVER_READY
= 0x3,
102 ICM_APPROVE_DEVICE
= 0x4,
103 ICM_CHALLENGE_DEVICE
= 0x5,
104 ICM_ADD_DEVICE_KEY
= 0x6,
106 ICM_APPROVE_XDOMAIN
= 0x10,
107 ICM_DISCONNECT_XDOMAIN
= 0x11,
108 ICM_PREBOOT_ACL
= 0x18,
109 ICM_USB4_SWITCH_OP
= 0x20,
112 enum icm_event_code
{
113 ICM_EVENT_DEVICE_CONNECTED
= 0x3,
114 ICM_EVENT_DEVICE_DISCONNECTED
= 0x4,
115 ICM_EVENT_XDOMAIN_CONNECTED
= 0x6,
116 ICM_EVENT_XDOMAIN_DISCONNECTED
= 0x7,
117 ICM_EVENT_RTD3_VETO
= 0xa,
120 struct icm_pkg_header
{
127 #define ICM_FLAGS_ERROR BIT(0)
128 #define ICM_FLAGS_NO_KEY BIT(1)
129 #define ICM_FLAGS_SLEVEL_SHIFT 3
130 #define ICM_FLAGS_SLEVEL_MASK GENMASK(4, 3)
131 #define ICM_FLAGS_DUAL_LANE BIT(5)
132 #define ICM_FLAGS_SPEED_GEN3 BIT(7)
133 #define ICM_FLAGS_WRITE BIT(7)
135 struct icm_pkg_driver_ready
{
136 struct icm_pkg_header hdr
;
139 /* Falcon Ridge only messages */
141 struct icm_fr_pkg_driver_ready_response
{
142 struct icm_pkg_header hdr
;
148 #define ICM_FR_SLEVEL_MASK 0xf
150 /* Falcon Ridge & Alpine Ridge common messages */
152 struct icm_fr_pkg_get_topology
{
153 struct icm_pkg_header hdr
;
156 #define ICM_GET_TOPOLOGY_PACKETS 14
158 struct icm_fr_pkg_get_topology_response
{
159 struct icm_pkg_header hdr
;
164 u8 drom_i2c_address_index
;
168 u32 port_hop_info
[16];
171 #define ICM_SWITCH_USED BIT(0)
172 #define ICM_SWITCH_UPSTREAM_PORT_MASK GENMASK(7, 1)
173 #define ICM_SWITCH_UPSTREAM_PORT_SHIFT 1
175 #define ICM_PORT_TYPE_MASK GENMASK(23, 0)
176 #define ICM_PORT_INDEX_SHIFT 24
177 #define ICM_PORT_INDEX_MASK GENMASK(31, 24)
179 struct icm_fr_event_device_connected
{
180 struct icm_pkg_header hdr
;
188 #define ICM_LINK_INFO_LINK_MASK 0x7
189 #define ICM_LINK_INFO_DEPTH_SHIFT 4
190 #define ICM_LINK_INFO_DEPTH_MASK GENMASK(7, 4)
191 #define ICM_LINK_INFO_APPROVED BIT(8)
192 #define ICM_LINK_INFO_REJECTED BIT(9)
193 #define ICM_LINK_INFO_BOOT BIT(10)
195 struct icm_fr_pkg_approve_device
{
196 struct icm_pkg_header hdr
;
203 struct icm_fr_event_device_disconnected
{
204 struct icm_pkg_header hdr
;
209 struct icm_fr_event_xdomain_connected
{
210 struct icm_pkg_header hdr
;
221 struct icm_fr_event_xdomain_disconnected
{
222 struct icm_pkg_header hdr
;
228 struct icm_fr_pkg_add_device_key
{
229 struct icm_pkg_header hdr
;
237 struct icm_fr_pkg_add_device_key_response
{
238 struct icm_pkg_header hdr
;
245 struct icm_fr_pkg_challenge_device
{
246 struct icm_pkg_header hdr
;
254 struct icm_fr_pkg_challenge_device_response
{
255 struct icm_pkg_header hdr
;
264 struct icm_fr_pkg_approve_xdomain
{
265 struct icm_pkg_header hdr
;
275 struct icm_fr_pkg_approve_xdomain_response
{
276 struct icm_pkg_header hdr
;
286 /* Alpine Ridge only messages */
288 struct icm_ar_pkg_driver_ready_response
{
289 struct icm_pkg_header hdr
;
295 #define ICM_AR_FLAGS_RTD3 BIT(6)
297 #define ICM_AR_INFO_SLEVEL_MASK GENMASK(3, 0)
298 #define ICM_AR_INFO_BOOT_ACL_SHIFT 7
299 #define ICM_AR_INFO_BOOT_ACL_MASK GENMASK(11, 7)
300 #define ICM_AR_INFO_BOOT_ACL_SUPPORTED BIT(13)
302 struct icm_ar_pkg_get_route
{
303 struct icm_pkg_header hdr
;
308 struct icm_ar_pkg_get_route_response
{
309 struct icm_pkg_header hdr
;
316 struct icm_ar_boot_acl_entry
{
321 #define ICM_AR_PREBOOT_ACL_ENTRIES 16
323 struct icm_ar_pkg_preboot_acl
{
324 struct icm_pkg_header hdr
;
325 struct icm_ar_boot_acl_entry acl
[ICM_AR_PREBOOT_ACL_ENTRIES
];
328 struct icm_ar_pkg_preboot_acl_response
{
329 struct icm_pkg_header hdr
;
330 struct icm_ar_boot_acl_entry acl
[ICM_AR_PREBOOT_ACL_ENTRIES
];
333 /* Titan Ridge messages */
335 struct icm_tr_pkg_driver_ready_response
{
336 struct icm_pkg_header hdr
;
344 #define ICM_TR_FLAGS_RTD3 BIT(6)
346 #define ICM_TR_INFO_SLEVEL_MASK GENMASK(2, 0)
347 #define ICM_TR_INFO_PROTO_VERSION_MASK GENMASK(6, 4)
348 #define ICM_TR_INFO_PROTO_VERSION_SHIFT 4
349 #define ICM_TR_INFO_BOOT_ACL_SHIFT 7
350 #define ICM_TR_INFO_BOOT_ACL_MASK GENMASK(12, 7)
352 struct icm_tr_event_device_connected
{
353 struct icm_pkg_header hdr
;
363 struct icm_tr_event_device_disconnected
{
364 struct icm_pkg_header hdr
;
369 struct icm_tr_event_xdomain_connected
{
370 struct icm_pkg_header hdr
;
381 struct icm_tr_event_xdomain_disconnected
{
382 struct icm_pkg_header hdr
;
388 struct icm_tr_pkg_approve_device
{
389 struct icm_pkg_header hdr
;
397 struct icm_tr_pkg_add_device_key
{
398 struct icm_pkg_header hdr
;
407 struct icm_tr_pkg_challenge_device
{
408 struct icm_pkg_header hdr
;
417 struct icm_tr_pkg_approve_xdomain
{
418 struct icm_pkg_header hdr
;
428 struct icm_tr_pkg_disconnect_xdomain
{
429 struct icm_pkg_header hdr
;
437 struct icm_tr_pkg_challenge_device_response
{
438 struct icm_pkg_header hdr
;
448 struct icm_tr_pkg_add_device_key_response
{
449 struct icm_pkg_header hdr
;
457 struct icm_tr_pkg_approve_xdomain_response
{
458 struct icm_pkg_header hdr
;
468 struct icm_tr_pkg_disconnect_xdomain_response
{
469 struct icm_pkg_header hdr
;
477 /* Ice Lake messages */
479 struct icm_icl_event_rtd3_veto
{
480 struct icm_pkg_header hdr
;
484 /* USB4 ICM messages */
486 struct icm_usb4_switch_op
{
487 struct icm_pkg_header hdr
;
496 #define ICM_USB4_SWITCH_DATA_LEN_MASK GENMASK(3, 0)
497 #define ICM_USB4_SWITCH_DATA_VALID BIT(4)
499 struct icm_usb4_switch_op_response
{
500 struct icm_pkg_header hdr
;
509 /* XDomain messages */
511 struct tb_xdomain_header
{
517 #define TB_XDOMAIN_LENGTH_MASK GENMASK(5, 0)
518 #define TB_XDOMAIN_SN_MASK GENMASK(28, 27)
519 #define TB_XDOMAIN_SN_SHIFT 27
522 UUID_REQUEST_OLD
= 1,
526 PROPERTIES_CHANGED_REQUEST
,
527 PROPERTIES_CHANGED_RESPONSE
,
532 struct tb_xdp_header
{
533 struct tb_xdomain_header xd_hdr
;
539 struct tb_xdp_header hdr
;
542 struct tb_xdp_uuid_response
{
543 struct tb_xdp_header hdr
;
549 struct tb_xdp_properties
{
550 struct tb_xdp_header hdr
;
557 struct tb_xdp_properties_response
{
558 struct tb_xdp_header hdr
;
568 * Max length of data array single XDomain property response is allowed
571 #define TB_XDP_PROPERTIES_MAX_DATA_LENGTH \
572 (((256 - 4 - sizeof(struct tb_xdp_properties_response))) / 4)
574 /* Maximum size of the total property block in dwords we allow */
575 #define TB_XDP_PROPERTIES_MAX_LENGTH 500
577 struct tb_xdp_properties_changed
{
578 struct tb_xdp_header hdr
;
582 struct tb_xdp_properties_changed_response
{
583 struct tb_xdp_header hdr
;
588 ERROR_UNKNOWN_PACKET
,
589 ERROR_UNKNOWN_DOMAIN
,
594 struct tb_xdp_error_response
{
595 struct tb_xdp_header hdr
;