?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
KVM: PPC: Book3S HV: Flush link stack on guest exit to host kernel
[linux/fpc-iii.git] / drivers / spi / spi-tegra20-slink.c
blob111fffc91435c1a85ca0785ef91280ba776ede5f
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
4 *
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmapool.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/kthread.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/reset.h>
25 #include <linux/spi/spi.h>
26
27 #define SLINK_COMMAND 0x000
28 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
29 #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
30 #define SLINK_BOTH_EN (1 << 10)
31 #define SLINK_CS_SW (1 << 11)
32 #define SLINK_CS_VALUE (1 << 12)
33 #define SLINK_CS_POLARITY (1 << 13)
34 #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
35 #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
36 #define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
37 #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
38 #define SLINK_IDLE_SDA_MASK (3 << 16)
39 #define SLINK_CS_POLARITY1 (1 << 20)
40 #define SLINK_CK_SDA (1 << 21)
41 #define SLINK_CS_POLARITY2 (1 << 22)
42 #define SLINK_CS_POLARITY3 (1 << 23)
43 #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
44 #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
45 #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
46 #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
47 #define SLINK_IDLE_SCLK_MASK (3 << 24)
48 #define SLINK_M_S (1 << 28)
49 #define SLINK_WAIT (1 << 29)
50 #define SLINK_GO (1 << 30)
51 #define SLINK_ENB (1 << 31)
52
53 #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA)
54
55 #define SLINK_COMMAND2 0x004
56 #define SLINK_LSBFE (1 << 0)
57 #define SLINK_SSOE (1 << 1)
58 #define SLINK_SPIE (1 << 4)
59 #define SLINK_BIDIROE (1 << 6)
60 #define SLINK_MODFEN (1 << 7)
61 #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
62 #define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
63 #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
64 #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
65 #define SLINK_FIFO_REFILLS_0 (0 << 22)
66 #define SLINK_FIFO_REFILLS_1 (1 << 22)
67 #define SLINK_FIFO_REFILLS_2 (2 << 22)
68 #define SLINK_FIFO_REFILLS_3 (3 << 22)
69 #define SLINK_FIFO_REFILLS_MASK (3 << 22)
70 #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
71 #define SLINK_SPC0 (1 << 29)
72 #define SLINK_TXEN (1 << 30)
73 #define SLINK_RXEN (1 << 31)
74
75 #define SLINK_STATUS 0x008
76 #define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
77 #define SLINK_WORD(val) (((val) >> 5) & 0x1f)
78 #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
79 #define SLINK_MODF (1 << 16)
80 #define SLINK_RX_UNF (1 << 18)
81 #define SLINK_TX_OVF (1 << 19)
82 #define SLINK_TX_FULL (1 << 20)
83 #define SLINK_TX_EMPTY (1 << 21)
84 #define SLINK_RX_FULL (1 << 22)
85 #define SLINK_RX_EMPTY (1 << 23)
86 #define SLINK_TX_UNF (1 << 24)
87 #define SLINK_RX_OVF (1 << 25)
88 #define SLINK_TX_FLUSH (1 << 26)
89 #define SLINK_RX_FLUSH (1 << 27)
90 #define SLINK_SCLK (1 << 28)
91 #define SLINK_ERR (1 << 29)
92 #define SLINK_RDY (1 << 30)
93 #define SLINK_BSY (1 << 31)
94 #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \
95 SLINK_TX_UNF | SLINK_RX_OVF)
96
97 #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY)
98
99 #define SLINK_MAS_DATA 0x010
100 #define SLINK_SLAVE_DATA 0x014
101
102 #define SLINK_DMA_CTL 0x018
103 #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
104 #define SLINK_TX_TRIG_1 (0 << 16)
105 #define SLINK_TX_TRIG_4 (1 << 16)
106 #define SLINK_TX_TRIG_8 (2 << 16)
107 #define SLINK_TX_TRIG_16 (3 << 16)
108 #define SLINK_TX_TRIG_MASK (3 << 16)
109 #define SLINK_RX_TRIG_1 (0 << 18)
110 #define SLINK_RX_TRIG_4 (1 << 18)
111 #define SLINK_RX_TRIG_8 (2 << 18)
112 #define SLINK_RX_TRIG_16 (3 << 18)
113 #define SLINK_RX_TRIG_MASK (3 << 18)
114 #define SLINK_PACKED (1 << 20)
115 #define SLINK_PACK_SIZE_4 (0 << 21)
116 #define SLINK_PACK_SIZE_8 (1 << 21)
117 #define SLINK_PACK_SIZE_16 (2 << 21)
118 #define SLINK_PACK_SIZE_32 (3 << 21)
119 #define SLINK_PACK_SIZE_MASK (3 << 21)
120 #define SLINK_IE_TXC (1 << 26)
121 #define SLINK_IE_RXC (1 << 27)
122 #define SLINK_DMA_EN (1 << 31)
123
124 #define SLINK_STATUS2 0x01c
125 #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
126 #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16)
127 #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6)
128
129 #define SLINK_TX_FIFO 0x100
130 #define SLINK_RX_FIFO 0x180
131
132 #define DATA_DIR_TX (1 << 0)
133 #define DATA_DIR_RX (1 << 1)
134
135 #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000))
136
137 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
138 #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20)
139 #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0)
140
141 #define SLINK_STATUS2_RESET \
142 (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16)
143
144 #define MAX_CHIP_SELECT 4
145 #define SLINK_FIFO_DEPTH 32
146
147 struct tegra_slink_chip_data {
148 bool cs_hold_time;
149 };
150
151 struct tegra_slink_data {
152 struct device *dev;
153 struct spi_master *master;
154 const struct tegra_slink_chip_data *chip_data;
155 spinlock_t lock;
156
157 struct clk *clk;
158 struct reset_control *rst;
159 void __iomem *base;
160 phys_addr_t phys;
161 unsigned irq;
162 u32 cur_speed;
163
164 struct spi_device *cur_spi;
165 unsigned cur_pos;
166 unsigned cur_len;
167 unsigned words_per_32bit;
168 unsigned bytes_per_word;
169 unsigned curr_dma_words;
170 unsigned cur_direction;
171
172 unsigned cur_rx_pos;
173 unsigned cur_tx_pos;
174
175 unsigned dma_buf_size;
176 unsigned max_buf_size;
177 bool is_curr_dma_xfer;
178
179 struct completion rx_dma_complete;
180 struct completion tx_dma_complete;
181
182 u32 tx_status;
183 u32 rx_status;
184 u32 status_reg;
185 bool is_packed;
186 u32 packed_size;
187
188 u32 command_reg;
189 u32 command2_reg;
190 u32 dma_control_reg;
191 u32 def_command_reg;
192 u32 def_command2_reg;
193
194 struct completion xfer_completion;
195 struct spi_transfer *curr_xfer;
196 struct dma_chan *rx_dma_chan;
197 u32 *rx_dma_buf;
198 dma_addr_t rx_dma_phys;
199 struct dma_async_tx_descriptor *rx_dma_desc;
200
201 struct dma_chan *tx_dma_chan;
202 u32 *tx_dma_buf;
203 dma_addr_t tx_dma_phys;
204 struct dma_async_tx_descriptor *tx_dma_desc;
205 };
206
207 static int tegra_slink_runtime_suspend(struct device *dev);
208 static int tegra_slink_runtime_resume(struct device *dev);
209
210 static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi,
211 unsigned long reg)
212 {
213 return readl(tspi->base + reg);
214 }
215
216 static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
217 u32 val, unsigned long reg)
218 {
219 writel(val, tspi->base + reg);
220
221 /* Read back register to make sure that register writes completed */
222 if (reg != SLINK_TX_FIFO)
223 readl(tspi->base + SLINK_MAS_DATA);
224 }
225
226 static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
227 {
228 u32 val_write;
229
230 tegra_slink_readl(tspi, SLINK_STATUS);
231
232 /* Write 1 to clear status register */
233 val_write = SLINK_RDY | SLINK_FIFO_ERROR;
234 tegra_slink_writel(tspi, val_write, SLINK_STATUS);
235 }
236
237 static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
238 struct spi_transfer *t)
239 {
240 switch (tspi->bytes_per_word) {
241 case 0:
242 return SLINK_PACK_SIZE_4;
243 case 1:
244 return SLINK_PACK_SIZE_8;
245 case 2:
246 return SLINK_PACK_SIZE_16;
247 case 4:
248 return SLINK_PACK_SIZE_32;
249 default:
250 return 0;
251 }
252 }
253
254 static unsigned tegra_slink_calculate_curr_xfer_param(
255 struct spi_device *spi, struct tegra_slink_data *tspi,
256 struct spi_transfer *t)
257 {
258 unsigned remain_len = t->len - tspi->cur_pos;
259 unsigned max_word;
260 unsigned bits_per_word;
261 unsigned max_len;
262 unsigned total_fifo_words;
263
264 bits_per_word = t->bits_per_word;
265 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
266
267 if (bits_per_word == 8 || bits_per_word == 16) {
268 tspi->is_packed = true;
269 tspi->words_per_32bit = 32/bits_per_word;
270 } else {
271 tspi->is_packed = false;
272 tspi->words_per_32bit = 1;
273 }
274 tspi->packed_size = tegra_slink_get_packed_size(tspi, t);
275
276 if (tspi->is_packed) {
277 max_len = min(remain_len, tspi->max_buf_size);
278 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
279 total_fifo_words = max_len/4;
280 } else {
281 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
282 max_word = min(max_word, tspi->max_buf_size/4);
283 tspi->curr_dma_words = max_word;
284 total_fifo_words = max_word;
285 }
286 return total_fifo_words;
287 }
288
289 static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
290 struct tegra_slink_data *tspi, struct spi_transfer *t)
291 {
292 unsigned nbytes;
293 unsigned tx_empty_count;
294 u32 fifo_status;
295 unsigned max_n_32bit;
296 unsigned i, count;
297 unsigned int written_words;
298 unsigned fifo_words_left;
299 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
300
301 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
302 tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
303
304 if (tspi->is_packed) {
305 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
306 written_words = min(fifo_words_left, tspi->curr_dma_words);
307 nbytes = written_words * tspi->bytes_per_word;
308 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
309 for (count = 0; count < max_n_32bit; count++) {
310 u32 x = 0;
311 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
312 x |= (u32)(*tx_buf++) << (i * 8);
313 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
314 }
315 } else {
316 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
317 written_words = max_n_32bit;
318 nbytes = written_words * tspi->bytes_per_word;
319 for (count = 0; count < max_n_32bit; count++) {
320 u32 x = 0;
321 for (i = 0; nbytes && (i < tspi->bytes_per_word);
322 i++, nbytes--)
323 x |= (u32)(*tx_buf++) << (i * 8);
324 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
325 }
326 }
327 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
328 return written_words;
329 }
330
331 static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
332 struct tegra_slink_data *tspi, struct spi_transfer *t)
333 {
334 unsigned rx_full_count;
335 u32 fifo_status;
336 unsigned i, count;
337 unsigned int read_words = 0;
338 unsigned len;
339 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
340
341 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
342 rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
343 if (tspi->is_packed) {
344 len = tspi->curr_dma_words * tspi->bytes_per_word;
345 for (count = 0; count < rx_full_count; count++) {
346 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
347 for (i = 0; len && (i < 4); i++, len--)
348 *rx_buf++ = (x >> i*8) & 0xFF;
349 }
350 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
351 read_words += tspi->curr_dma_words;
352 } else {
353 for (count = 0; count < rx_full_count; count++) {
354 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
355 for (i = 0; (i < tspi->bytes_per_word); i++)
356 *rx_buf++ = (x >> (i*8)) & 0xFF;
357 }
358 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
359 read_words += rx_full_count;
360 }
361 return read_words;
362 }
363
364 static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
365 struct tegra_slink_data *tspi, struct spi_transfer *t)
366 {
367 /* Make the dma buffer to read by cpu */
368 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
369 tspi->dma_buf_size, DMA_TO_DEVICE);
370
371 if (tspi->is_packed) {
372 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
373 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
374 } else {
375 unsigned int i;
376 unsigned int count;
377 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
378 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
379
380 for (count = 0; count < tspi->curr_dma_words; count++) {
381 u32 x = 0;
382 for (i = 0; consume && (i < tspi->bytes_per_word);
383 i++, consume--)
384 x |= (u32)(*tx_buf++) << (i * 8);
385 tspi->tx_dma_buf[count] = x;
386 }
387 }
388 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
389
390 /* Make the dma buffer to read by dma */
391 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
392 tspi->dma_buf_size, DMA_TO_DEVICE);
393 }
394
395 static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
396 struct tegra_slink_data *tspi, struct spi_transfer *t)
397 {
398 unsigned len;
399
400 /* Make the dma buffer to read by cpu */
401 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
402 tspi->dma_buf_size, DMA_FROM_DEVICE);
403
404 if (tspi->is_packed) {
405 len = tspi->curr_dma_words * tspi->bytes_per_word;
406 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
407 } else {
408 unsigned int i;
409 unsigned int count;
410 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
411 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
412
413 for (count = 0; count < tspi->curr_dma_words; count++) {
414 u32 x = tspi->rx_dma_buf[count] & rx_mask;
415 for (i = 0; (i < tspi->bytes_per_word); i++)
416 *rx_buf++ = (x >> (i*8)) & 0xFF;
417 }
418 }
419 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
420
421 /* Make the dma buffer to read by dma */
422 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
423 tspi->dma_buf_size, DMA_FROM_DEVICE);
424 }
425
426 static void tegra_slink_dma_complete(void *args)
427 {
428 struct completion *dma_complete = args;
429
430 complete(dma_complete);
431 }
432
433 static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len)
434 {
435 reinit_completion(&tspi->tx_dma_complete);
436 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
437 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
438 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
439 if (!tspi->tx_dma_desc) {
440 dev_err(tspi->dev, "Not able to get desc for Tx\n");
441 return -EIO;
442 }
443
444 tspi->tx_dma_desc->callback = tegra_slink_dma_complete;
445 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
446
447 dmaengine_submit(tspi->tx_dma_desc);
448 dma_async_issue_pending(tspi->tx_dma_chan);
449 return 0;
450 }
451
452 static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len)
453 {
454 reinit_completion(&tspi->rx_dma_complete);
455 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
456 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
457 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
458 if (!tspi->rx_dma_desc) {
459 dev_err(tspi->dev, "Not able to get desc for Rx\n");
460 return -EIO;
461 }
462
463 tspi->rx_dma_desc->callback = tegra_slink_dma_complete;
464 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
465
466 dmaengine_submit(tspi->rx_dma_desc);
467 dma_async_issue_pending(tspi->rx_dma_chan);
468 return 0;
469 }
470
471 static int tegra_slink_start_dma_based_transfer(
472 struct tegra_slink_data *tspi, struct spi_transfer *t)
473 {
474 u32 val;
475 unsigned int len;
476 int ret = 0;
477 u32 status;
478
479 /* Make sure that Rx and Tx fifo are empty */
480 status = tegra_slink_readl(tspi, SLINK_STATUS);
481 if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) {
482 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
483 (unsigned)status);
484 return -EIO;
485 }
486
487 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
488 val |= tspi->packed_size;
489 if (tspi->is_packed)
490 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
491 4) * 4;
492 else
493 len = tspi->curr_dma_words * 4;
494
495 /* Set attention level based on length of transfer */
496 if (len & 0xF)
497 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
498 else if (((len) >> 4) & 0x1)
499 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
500 else
501 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
502
503 if (tspi->cur_direction & DATA_DIR_TX)
504 val |= SLINK_IE_TXC;
505
506 if (tspi->cur_direction & DATA_DIR_RX)
507 val |= SLINK_IE_RXC;
508
509 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
510 tspi->dma_control_reg = val;
511
512 if (tspi->cur_direction & DATA_DIR_TX) {
513 tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t);
514 wmb();
515 ret = tegra_slink_start_tx_dma(tspi, len);
516 if (ret < 0) {
517 dev_err(tspi->dev,
518 "Starting tx dma failed, err %d\n", ret);
519 return ret;
520 }
521
522 /* Wait for tx fifo to be fill before starting slink */
523 status = tegra_slink_readl(tspi, SLINK_STATUS);
524 while (!(status & SLINK_TX_FULL))
525 status = tegra_slink_readl(tspi, SLINK_STATUS);
526 }
527
528 if (tspi->cur_direction & DATA_DIR_RX) {
529 /* Make the dma buffer to read by dma */
530 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
531 tspi->dma_buf_size, DMA_FROM_DEVICE);
532
533 ret = tegra_slink_start_rx_dma(tspi, len);
534 if (ret < 0) {
535 dev_err(tspi->dev,
536 "Starting rx dma failed, err %d\n", ret);
537 if (tspi->cur_direction & DATA_DIR_TX)
538 dmaengine_terminate_all(tspi->tx_dma_chan);
539 return ret;
540 }
541 }
542 tspi->is_curr_dma_xfer = true;
543 if (tspi->is_packed) {
544 val |= SLINK_PACKED;
545 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
546 /* HW need small delay after settign Packed mode */
547 udelay(1);
548 }
549 tspi->dma_control_reg = val;
550
551 val |= SLINK_DMA_EN;
552 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
553 return ret;
554 }
555
556 static int tegra_slink_start_cpu_based_transfer(
557 struct tegra_slink_data *tspi, struct spi_transfer *t)
558 {
559 u32 val;
560 unsigned cur_words;
561
562 val = tspi->packed_size;
563 if (tspi->cur_direction & DATA_DIR_TX)
564 val |= SLINK_IE_TXC;
565
566 if (tspi->cur_direction & DATA_DIR_RX)
567 val |= SLINK_IE_RXC;
568
569 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
570 tspi->dma_control_reg = val;
571
572 if (tspi->cur_direction & DATA_DIR_TX)
573 cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t);
574 else
575 cur_words = tspi->curr_dma_words;
576 val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1);
577 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
578 tspi->dma_control_reg = val;
579
580 tspi->is_curr_dma_xfer = false;
581 if (tspi->is_packed) {
582 val |= SLINK_PACKED;
583 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
584 udelay(1);
585 wmb();
586 }
587 tspi->dma_control_reg = val;
588 val |= SLINK_DMA_EN;
589 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
590 return 0;
591 }
592
593 static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
594 bool dma_to_memory)
595 {
596 struct dma_chan *dma_chan;
597 u32 *dma_buf;
598 dma_addr_t dma_phys;
599 int ret;
600 struct dma_slave_config dma_sconfig;
601
602 dma_chan = dma_request_slave_channel_reason(tspi->dev,
603 dma_to_memory ? "rx" : "tx");
604 if (IS_ERR(dma_chan)) {
605 ret = PTR_ERR(dma_chan);
606 if (ret != -EPROBE_DEFER)
607 dev_err(tspi->dev,
608 "Dma channel is not available: %d\n", ret);
609 return ret;
610 }
611
612 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
613 &dma_phys, GFP_KERNEL);
614 if (!dma_buf) {
615 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
616 dma_release_channel(dma_chan);
617 return -ENOMEM;
618 }
619
620 if (dma_to_memory) {
621 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
622 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
623 dma_sconfig.src_maxburst = 0;
624 } else {
625 dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO;
626 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
627 dma_sconfig.dst_maxburst = 0;
628 }
629
630 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
631 if (ret)
632 goto scrub;
633 if (dma_to_memory) {
634 tspi->rx_dma_chan = dma_chan;
635 tspi->rx_dma_buf = dma_buf;
636 tspi->rx_dma_phys = dma_phys;
637 } else {
638 tspi->tx_dma_chan = dma_chan;
639 tspi->tx_dma_buf = dma_buf;
640 tspi->tx_dma_phys = dma_phys;
641 }
642 return 0;
643
644 scrub:
645 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
646 dma_release_channel(dma_chan);
647 return ret;
648 }
649
650 static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi,
651 bool dma_to_memory)
652 {
653 u32 *dma_buf;
654 dma_addr_t dma_phys;
655 struct dma_chan *dma_chan;
656
657 if (dma_to_memory) {
658 dma_buf = tspi->rx_dma_buf;
659 dma_chan = tspi->rx_dma_chan;
660 dma_phys = tspi->rx_dma_phys;
661 tspi->rx_dma_chan = NULL;
662 tspi->rx_dma_buf = NULL;
663 } else {
664 dma_buf = tspi->tx_dma_buf;
665 dma_chan = tspi->tx_dma_chan;
666 dma_phys = tspi->tx_dma_phys;
667 tspi->tx_dma_buf = NULL;
668 tspi->tx_dma_chan = NULL;
669 }
670 if (!dma_chan)
671 return;
672
673 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
674 dma_release_channel(dma_chan);
675 }
676
677 static int tegra_slink_start_transfer_one(struct spi_device *spi,
678 struct spi_transfer *t)
679 {
680 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
681 u32 speed;
682 u8 bits_per_word;
683 unsigned total_fifo_words;
684 int ret;
685 u32 command;
686 u32 command2;
687
688 bits_per_word = t->bits_per_word;
689 speed = t->speed_hz;
690 if (speed != tspi->cur_speed) {
691 clk_set_rate(tspi->clk, speed * 4);
692 tspi->cur_speed = speed;
693 }
694
695 tspi->cur_spi = spi;
696 tspi->cur_pos = 0;
697 tspi->cur_rx_pos = 0;
698 tspi->cur_tx_pos = 0;
699 tspi->curr_xfer = t;
700 total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t);
701
702 command = tspi->command_reg;
703 command &= ~SLINK_BIT_LENGTH(~0);
704 command |= SLINK_BIT_LENGTH(bits_per_word - 1);
705
706 command2 = tspi->command2_reg;
707 command2 &= ~(SLINK_RXEN | SLINK_TXEN);
708
709 tspi->cur_direction = 0;
710 if (t->rx_buf) {
711 command2 |= SLINK_RXEN;
712 tspi->cur_direction |= DATA_DIR_RX;
713 }
714 if (t->tx_buf) {
715 command2 |= SLINK_TXEN;
716 tspi->cur_direction |= DATA_DIR_TX;
717 }
718
719 /*
720 * Writing to the command2 register bevore the command register prevents
721 * a spike in chip_select line 0. This selects the chip_select line
722 * before changing the chip_select value.
723 */
724 tegra_slink_writel(tspi, command2, SLINK_COMMAND2);
725 tspi->command2_reg = command2;
726
727 tegra_slink_writel(tspi, command, SLINK_COMMAND);
728 tspi->command_reg = command;
729
730 if (total_fifo_words > SLINK_FIFO_DEPTH)
731 ret = tegra_slink_start_dma_based_transfer(tspi, t);
732 else
733 ret = tegra_slink_start_cpu_based_transfer(tspi, t);
734 return ret;
735 }
736
737 static int tegra_slink_setup(struct spi_device *spi)
738 {
739 static const u32 cs_pol_bit[MAX_CHIP_SELECT] = {
740 SLINK_CS_POLARITY,
741 SLINK_CS_POLARITY1,
742 SLINK_CS_POLARITY2,
743 SLINK_CS_POLARITY3,
744 };
745
746 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
747 u32 val;
748 unsigned long flags;
749 int ret;
750
751 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
752 spi->bits_per_word,
753 spi->mode & SPI_CPOL ? "" : "~",
754 spi->mode & SPI_CPHA ? "" : "~",
755 spi->max_speed_hz);
756
757 ret = pm_runtime_get_sync(tspi->dev);
758 if (ret < 0) {
759 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
760 return ret;
761 }
762
763 spin_lock_irqsave(&tspi->lock, flags);
764 val = tspi->def_command_reg;
765 if (spi->mode & SPI_CS_HIGH)
766 val |= cs_pol_bit[spi->chip_select];
767 else
768 val &= ~cs_pol_bit[spi->chip_select];
769 tspi->def_command_reg = val;
770 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
771 spin_unlock_irqrestore(&tspi->lock, flags);
772
773 pm_runtime_put(tspi->dev);
774 return 0;
775 }
776
777 static int tegra_slink_prepare_message(struct spi_master *master,
778 struct spi_message *msg)
779 {
780 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
781 struct spi_device *spi = msg->spi;
782
783 tegra_slink_clear_status(tspi);
784
785 tspi->command_reg = tspi->def_command_reg;
786 tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE;
787
788 tspi->command2_reg = tspi->def_command2_reg;
789 tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select);
790
791 tspi->command_reg &= ~SLINK_MODES;
792 if (spi->mode & SPI_CPHA)
793 tspi->command_reg |= SLINK_CK_SDA;
794
795 if (spi->mode & SPI_CPOL)
796 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH;
797 else
798 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW;
799
800 return 0;
801 }
802
803 static int tegra_slink_transfer_one(struct spi_master *master,
804 struct spi_device *spi,
805 struct spi_transfer *xfer)
806 {
807 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
808 int ret;
809
810 reinit_completion(&tspi->xfer_completion);
811 ret = tegra_slink_start_transfer_one(spi, xfer);
812 if (ret < 0) {
813 dev_err(tspi->dev,
814 "spi can not start transfer, err %d\n", ret);
815 return ret;
816 }
817
818 ret = wait_for_completion_timeout(&tspi->xfer_completion,
819 SLINK_DMA_TIMEOUT);
820 if (WARN_ON(ret == 0)) {
821 dev_err(tspi->dev,
822 "spi transfer timeout, err %d\n", ret);
823 return -EIO;
824 }
825
826 if (tspi->tx_status)
827 return tspi->tx_status;
828 if (tspi->rx_status)
829 return tspi->rx_status;
830
831 return 0;
832 }
833
834 static int tegra_slink_unprepare_message(struct spi_master *master,
835 struct spi_message *msg)
836 {
837 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
838
839 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
840 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
841
842 return 0;
843 }
844
845 static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
846 {
847 struct spi_transfer *t = tspi->curr_xfer;
848 unsigned long flags;
849
850 spin_lock_irqsave(&tspi->lock, flags);
851 if (tspi->tx_status || tspi->rx_status ||
852 (tspi->status_reg & SLINK_BSY)) {
853 dev_err(tspi->dev,
854 "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg);
855 dev_err(tspi->dev,
856 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
857 tspi->command2_reg, tspi->dma_control_reg);
858 reset_control_assert(tspi->rst);
859 udelay(2);
860 reset_control_deassert(tspi->rst);
861 complete(&tspi->xfer_completion);
862 goto exit;
863 }
864
865 if (tspi->cur_direction & DATA_DIR_RX)
866 tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t);
867
868 if (tspi->cur_direction & DATA_DIR_TX)
869 tspi->cur_pos = tspi->cur_tx_pos;
870 else
871 tspi->cur_pos = tspi->cur_rx_pos;
872
873 if (tspi->cur_pos == t->len) {
874 complete(&tspi->xfer_completion);
875 goto exit;
876 }
877
878 tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
879 tegra_slink_start_cpu_based_transfer(tspi, t);
880 exit:
881 spin_unlock_irqrestore(&tspi->lock, flags);
882 return IRQ_HANDLED;
883 }
884
885 static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
886 {
887 struct spi_transfer *t = tspi->curr_xfer;
888 long wait_status;
889 int err = 0;
890 unsigned total_fifo_words;
891 unsigned long flags;
892
893 /* Abort dmas if any error */
894 if (tspi->cur_direction & DATA_DIR_TX) {
895 if (tspi->tx_status) {
896 dmaengine_terminate_all(tspi->tx_dma_chan);
897 err += 1;
898 } else {
899 wait_status = wait_for_completion_interruptible_timeout(
900 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
901 if (wait_status <= 0) {
902 dmaengine_terminate_all(tspi->tx_dma_chan);
903 dev_err(tspi->dev, "TxDma Xfer failed\n");
904 err += 1;
905 }
906 }
907 }
908
909 if (tspi->cur_direction & DATA_DIR_RX) {
910 if (tspi->rx_status) {
911 dmaengine_terminate_all(tspi->rx_dma_chan);
912 err += 2;
913 } else {
914 wait_status = wait_for_completion_interruptible_timeout(
915 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
916 if (wait_status <= 0) {
917 dmaengine_terminate_all(tspi->rx_dma_chan);
918 dev_err(tspi->dev, "RxDma Xfer failed\n");
919 err += 2;
920 }
921 }
922 }
923
924 spin_lock_irqsave(&tspi->lock, flags);
925 if (err) {
926 dev_err(tspi->dev,
927 "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg);
928 dev_err(tspi->dev,
929 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
930 tspi->command2_reg, tspi->dma_control_reg);
931 reset_control_assert(tspi->rst);
932 udelay(2);
933 reset_control_assert(tspi->rst);
934 complete(&tspi->xfer_completion);
935 spin_unlock_irqrestore(&tspi->lock, flags);
936 return IRQ_HANDLED;
937 }
938
939 if (tspi->cur_direction & DATA_DIR_RX)
940 tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
941
942 if (tspi->cur_direction & DATA_DIR_TX)
943 tspi->cur_pos = tspi->cur_tx_pos;
944 else
945 tspi->cur_pos = tspi->cur_rx_pos;
946
947 if (tspi->cur_pos == t->len) {
948 complete(&tspi->xfer_completion);
949 goto exit;
950 }
951
952 /* Continue transfer in current message */
953 total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi,
954 tspi, t);
955 if (total_fifo_words > SLINK_FIFO_DEPTH)
956 err = tegra_slink_start_dma_based_transfer(tspi, t);
957 else
958 err = tegra_slink_start_cpu_based_transfer(tspi, t);
959
960 exit:
961 spin_unlock_irqrestore(&tspi->lock, flags);
962 return IRQ_HANDLED;
963 }
964
965 static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data)
966 {
967 struct tegra_slink_data *tspi = context_data;
968
969 if (!tspi->is_curr_dma_xfer)
970 return handle_cpu_based_xfer(tspi);
971 return handle_dma_based_xfer(tspi);
972 }
973
974 static irqreturn_t tegra_slink_isr(int irq, void *context_data)
975 {
976 struct tegra_slink_data *tspi = context_data;
977
978 tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS);
979 if (tspi->cur_direction & DATA_DIR_TX)
980 tspi->tx_status = tspi->status_reg &
981 (SLINK_TX_OVF | SLINK_TX_UNF);
982
983 if (tspi->cur_direction & DATA_DIR_RX)
984 tspi->rx_status = tspi->status_reg &
985 (SLINK_RX_OVF | SLINK_RX_UNF);
986 tegra_slink_clear_status(tspi);
987
988 return IRQ_WAKE_THREAD;
989 }
990
991 static const struct tegra_slink_chip_data tegra30_spi_cdata = {
992 .cs_hold_time = true,
993 };
994
995 static const struct tegra_slink_chip_data tegra20_spi_cdata = {
996 .cs_hold_time = false,
997 };
998
999 static const struct of_device_id tegra_slink_of_match[] = {
1000 { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, },
1001 { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, },
1002 {}
1003 };
1004 MODULE_DEVICE_TABLE(of, tegra_slink_of_match);
1005
1006 static int tegra_slink_probe(struct platform_device *pdev)
1007 {
1008 struct spi_master *master;
1009 struct tegra_slink_data *tspi;
1010 struct resource *r;
1011 int ret, spi_irq;
1012 const struct tegra_slink_chip_data *cdata = NULL;
1013 const struct of_device_id *match;
1014
1015 match = of_match_device(tegra_slink_of_match, &pdev->dev);
1016 if (!match) {
1017 dev_err(&pdev->dev, "Error: No device match found\n");
1018 return -ENODEV;
1019 }
1020 cdata = match->data;
1021
1022 master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1023 if (!master) {
1024 dev_err(&pdev->dev, "master allocation failed\n");
1025 return -ENOMEM;
1026 }
1027
1028 /* the spi->mode bits understood by this driver: */
1029 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1030 master->setup = tegra_slink_setup;
1031 master->prepare_message = tegra_slink_prepare_message;
1032 master->transfer_one = tegra_slink_transfer_one;
1033 master->unprepare_message = tegra_slink_unprepare_message;
1034 master->auto_runtime_pm = true;
1035 master->num_chipselect = MAX_CHIP_SELECT;
1036
1037 platform_set_drvdata(pdev, master);
1038 tspi = spi_master_get_devdata(master);
1039 tspi->master = master;
1040 tspi->dev = &pdev->dev;
1041 tspi->chip_data = cdata;
1042 spin_lock_init(&tspi->lock);
1043
1044 if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency",
1045 &master->max_speed_hz))
1046 master->max_speed_hz = 25000000; /* 25MHz */
1047
1048 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1049 if (!r) {
1050 dev_err(&pdev->dev, "No IO memory resource\n");
1051 ret = -ENODEV;
1052 goto exit_free_master;
1053 }
1054 tspi->phys = r->start;
1055 tspi->base = devm_ioremap_resource(&pdev->dev, r);
1056 if (IS_ERR(tspi->base)) {
1057 ret = PTR_ERR(tspi->base);
1058 goto exit_free_master;
1059 }
1060
1061 /* disabled clock may cause interrupt storm upon request */
1062 tspi->clk = devm_clk_get(&pdev->dev, NULL);
1063 if (IS_ERR(tspi->clk)) {
1064 ret = PTR_ERR(tspi->clk);
1065 dev_err(&pdev->dev, "Can not get clock %d\n", ret);
1066 goto exit_free_master;
1067 }
1068 ret = clk_prepare(tspi->clk);
1069 if (ret < 0) {
1070 dev_err(&pdev->dev, "Clock prepare failed %d\n", ret);
1071 goto exit_free_master;
1072 }
1073 ret = clk_enable(tspi->clk);
1074 if (ret < 0) {
1075 dev_err(&pdev->dev, "Clock enable failed %d\n", ret);
1076 goto exit_free_master;
1077 }
1078
1079 spi_irq = platform_get_irq(pdev, 0);
1080 tspi->irq = spi_irq;
1081 ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
1082 tegra_slink_isr_thread, IRQF_ONESHOT,
1083 dev_name(&pdev->dev), tspi);
1084 if (ret < 0) {
1085 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1086 tspi->irq);
1087 goto exit_clk_disable;
1088 }
1089
1090 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
1091 if (IS_ERR(tspi->rst)) {
1092 dev_err(&pdev->dev, "can not get reset\n");
1093 ret = PTR_ERR(tspi->rst);
1094 goto exit_free_irq;
1095 }
1096
1097 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1098 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1099
1100 ret = tegra_slink_init_dma_param(tspi, true);
1101 if (ret < 0)
1102 goto exit_free_irq;
1103 ret = tegra_slink_init_dma_param(tspi, false);
1104 if (ret < 0)
1105 goto exit_rx_dma_free;
1106 tspi->max_buf_size = tspi->dma_buf_size;
1107 init_completion(&tspi->tx_dma_complete);
1108 init_completion(&tspi->rx_dma_complete);
1109
1110 init_completion(&tspi->xfer_completion);
1111
1112 pm_runtime_enable(&pdev->dev);
1113 if (!pm_runtime_enabled(&pdev->dev)) {
1114 ret = tegra_slink_runtime_resume(&pdev->dev);
1115 if (ret)
1116 goto exit_pm_disable;
1117 }
1118
1119 ret = pm_runtime_get_sync(&pdev->dev);
1120 if (ret < 0) {
1121 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1122 goto exit_pm_disable;
1123 }
1124 tspi->def_command_reg = SLINK_M_S;
1125 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
1126 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
1127 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
1128 pm_runtime_put(&pdev->dev);
1129
1130 master->dev.of_node = pdev->dev.of_node;
1131 ret = devm_spi_register_master(&pdev->dev, master);
1132 if (ret < 0) {
1133 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1134 goto exit_pm_disable;
1135 }
1136 return ret;
1137
1138 exit_pm_disable:
1139 pm_runtime_disable(&pdev->dev);
1140 if (!pm_runtime_status_suspended(&pdev->dev))
1141 tegra_slink_runtime_suspend(&pdev->dev);
1142 tegra_slink_deinit_dma_param(tspi, false);
1143 exit_rx_dma_free:
1144 tegra_slink_deinit_dma_param(tspi, true);
1145 exit_free_irq:
1146 free_irq(spi_irq, tspi);
1147 exit_clk_disable:
1148 clk_disable(tspi->clk);
1149 exit_free_master:
1150 spi_master_put(master);
1151 return ret;
1152 }
1153
1154 static int tegra_slink_remove(struct platform_device *pdev)
1155 {
1156 struct spi_master *master = platform_get_drvdata(pdev);
1157 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1158
1159 free_irq(tspi->irq, tspi);
1160
1161 clk_disable(tspi->clk);
1162
1163 if (tspi->tx_dma_chan)
1164 tegra_slink_deinit_dma_param(tspi, false);
1165
1166 if (tspi->rx_dma_chan)
1167 tegra_slink_deinit_dma_param(tspi, true);
1168
1169 pm_runtime_disable(&pdev->dev);
1170 if (!pm_runtime_status_suspended(&pdev->dev))
1171 tegra_slink_runtime_suspend(&pdev->dev);
1172
1173 return 0;
1174 }
1175
1176 #ifdef CONFIG_PM_SLEEP
1177 static int tegra_slink_suspend(struct device *dev)
1178 {
1179 struct spi_master *master = dev_get_drvdata(dev);
1180
1181 return spi_master_suspend(master);
1182 }
1183
1184 static int tegra_slink_resume(struct device *dev)
1185 {
1186 struct spi_master *master = dev_get_drvdata(dev);
1187 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1188 int ret;
1189
1190 ret = pm_runtime_get_sync(dev);
1191 if (ret < 0) {
1192 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1193 return ret;
1194 }
1195 tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND);
1196 tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2);
1197 pm_runtime_put(dev);
1198
1199 return spi_master_resume(master);
1200 }
1201 #endif
1202
1203 static int tegra_slink_runtime_suspend(struct device *dev)
1204 {
1205 struct spi_master *master = dev_get_drvdata(dev);
1206 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1207
1208 /* Flush all write which are in PPSB queue by reading back */
1209 tegra_slink_readl(tspi, SLINK_MAS_DATA);
1210
1211 clk_disable_unprepare(tspi->clk);
1212 return 0;
1213 }
1214
1215 static int tegra_slink_runtime_resume(struct device *dev)
1216 {
1217 struct spi_master *master = dev_get_drvdata(dev);
1218 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1219 int ret;
1220
1221 ret = clk_prepare_enable(tspi->clk);
1222 if (ret < 0) {
1223 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1224 return ret;
1225 }
1226 return 0;
1227 }
1228
1229 static const struct dev_pm_ops slink_pm_ops = {
1230 SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend,
1231 tegra_slink_runtime_resume, NULL)
1232 SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume)
1233 };
1234 static struct platform_driver tegra_slink_driver = {
1235 .driver = {
1236 .name = "spi-tegra-slink",
1237 .pm = &slink_pm_ops,
1238 .of_match_table = tegra_slink_of_match,
1239 },
1240 .probe = tegra_slink_probe,
1241 .remove = tegra_slink_remove,
1242 };
1243 module_platform_driver(tegra_slink_driver);
1244
1245 MODULE_ALIAS("platform:spi-tegra-slink");
1246 MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");
1247 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1248 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support