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sfc: Workaround flush failures on Falcon B0
[linux/fpc-iii.git] / drivers / net / sfc / falcon.c
blob8558865ff380a1e1cf2de6a0ffde31981e21a584
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2009 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/mii.h>
18 #include <linux/slab.h>
19 #include "net_driver.h"
20 #include "bitfield.h"
21 #include "efx.h"
22 #include "mac.h"
23 #include "spi.h"
24 #include "nic.h"
25 #include "regs.h"
26 #include "io.h"
27 #include "mdio_10g.h"
28 #include "phy.h"
29 #include "workarounds.h"
30
31 /* Hardware control for SFC4000 (aka Falcon). */
32
33 static const unsigned int
34 /* "Large" EEPROM device: Atmel AT25640 or similar
35 * 8 KB, 16-bit address, 32 B write block */
36 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
37 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
38 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
39 /* Default flash device: Atmel AT25F1024
40 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
41 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
42 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
43 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
44 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
45 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
46
47 /**************************************************************************
48 *
49 * I2C bus - this is a bit-bashing interface using GPIO pins
50 * Note that it uses the output enables to tristate the outputs
51 * SDA is the data pin and SCL is the clock
52 *
53 **************************************************************************
54 */
55 static void falcon_setsda(void *data, int state)
56 {
57 struct efx_nic *efx = (struct efx_nic *)data;
58 efx_oword_t reg;
59
60 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
61 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
62 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
63 }
64
65 static void falcon_setscl(void *data, int state)
66 {
67 struct efx_nic *efx = (struct efx_nic *)data;
68 efx_oword_t reg;
69
70 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
71 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
72 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
73 }
74
75 static int falcon_getsda(void *data)
76 {
77 struct efx_nic *efx = (struct efx_nic *)data;
78 efx_oword_t reg;
79
80 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
81 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
82 }
83
84 static int falcon_getscl(void *data)
85 {
86 struct efx_nic *efx = (struct efx_nic *)data;
87 efx_oword_t reg;
88
89 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
90 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
91 }
92
93 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
94 .setsda = falcon_setsda,
95 .setscl = falcon_setscl,
96 .getsda = falcon_getsda,
97 .getscl = falcon_getscl,
98 .udelay = 5,
99 /* Wait up to 50 ms for slave to let us pull SCL high */
100 .timeout = DIV_ROUND_UP(HZ, 20),
101 };
102
103 static void falcon_push_irq_moderation(struct efx_channel *channel)
104 {
105 efx_dword_t timer_cmd;
106 struct efx_nic *efx = channel->efx;
107
108 /* Set timer register */
109 if (channel->irq_moderation) {
110 EFX_POPULATE_DWORD_2(timer_cmd,
111 FRF_AB_TC_TIMER_MODE,
112 FFE_BB_TIMER_MODE_INT_HLDOFF,
113 FRF_AB_TC_TIMER_VAL,
114 channel->irq_moderation - 1);
115 } else {
116 EFX_POPULATE_DWORD_2(timer_cmd,
117 FRF_AB_TC_TIMER_MODE,
118 FFE_BB_TIMER_MODE_DIS,
119 FRF_AB_TC_TIMER_VAL, 0);
120 }
121 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
122 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
123 channel->channel);
124 }
125
126 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
127
128 static void falcon_prepare_flush(struct efx_nic *efx)
129 {
130 falcon_deconfigure_mac_wrapper(efx);
131
132 /* Wait for the tx and rx fifo's to get to the next packet boundary
133 * (~1ms without back-pressure), then to drain the remainder of the
134 * fifo's at data path speeds (negligible), with a healthy margin. */
135 msleep(10);
136 }
137
138 /* Acknowledge a legacy interrupt from Falcon
139 *
140 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
141 *
142 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
143 * BIU. Interrupt acknowledge is read sensitive so must write instead
144 * (then read to ensure the BIU collector is flushed)
145 *
146 * NB most hardware supports MSI interrupts
147 */
148 inline void falcon_irq_ack_a1(struct efx_nic *efx)
149 {
150 efx_dword_t reg;
151
152 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
153 efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
154 efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
155 }
156
157
158 irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
159 {
160 struct efx_nic *efx = dev_id;
161 efx_oword_t *int_ker = efx->irq_status.addr;
162 struct efx_channel *channel;
163 int syserr;
164 int queues;
165
166 /* Check to see if this is our interrupt. If it isn't, we
167 * exit without having touched the hardware.
168 */
169 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
170 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
171 raw_smp_processor_id());
172 return IRQ_NONE;
173 }
174 efx->last_irq_cpu = raw_smp_processor_id();
175 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
176 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
177
178 /* Determine interrupting queues, clear interrupt status
179 * register and acknowledge the device interrupt.
180 */
181 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
182 queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
183
184 /* Check to see if we have a serious error condition */
185 if (queues & (1U << efx->fatal_irq_level)) {
186 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
187 if (unlikely(syserr))
188 return efx_nic_fatal_interrupt(efx);
189 }
190
191 EFX_ZERO_OWORD(*int_ker);
192 wmb(); /* Ensure the vector is cleared before interrupt ack */
193 falcon_irq_ack_a1(efx);
194
195 /* Schedule processing of any interrupting queues */
196 channel = &efx->channel[0];
197 while (queues) {
198 if (queues & 0x01)
199 efx_schedule_channel(channel);
200 channel++;
201 queues >>= 1;
202 }
203
204 return IRQ_HANDLED;
205 }
206 /**************************************************************************
207 *
208 * EEPROM/flash
209 *
210 **************************************************************************
211 */
212
213 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
214
215 static int falcon_spi_poll(struct efx_nic *efx)
216 {
217 efx_oword_t reg;
218 efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
219 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
220 }
221
222 /* Wait for SPI command completion */
223 static int falcon_spi_wait(struct efx_nic *efx)
224 {
225 /* Most commands will finish quickly, so we start polling at
226 * very short intervals. Sometimes the command may have to
227 * wait for VPD or expansion ROM access outside of our
228 * control, so we allow up to 100 ms. */
229 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
230 int i;
231
232 for (i = 0; i < 10; i++) {
233 if (!falcon_spi_poll(efx))
234 return 0;
235 udelay(10);
236 }
237
238 for (;;) {
239 if (!falcon_spi_poll(efx))
240 return 0;
241 if (time_after_eq(jiffies, timeout)) {
242 EFX_ERR(efx, "timed out waiting for SPI\n");
243 return -ETIMEDOUT;
244 }
245 schedule_timeout_uninterruptible(1);
246 }
247 }
248
249 int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi,
250 unsigned int command, int address,
251 const void *in, void *out, size_t len)
252 {
253 bool addressed = (address >= 0);
254 bool reading = (out != NULL);
255 efx_oword_t reg;
256 int rc;
257
258 /* Input validation */
259 if (len > FALCON_SPI_MAX_LEN)
260 return -EINVAL;
261 BUG_ON(!mutex_is_locked(&efx->spi_lock));
262
263 /* Check that previous command is not still running */
264 rc = falcon_spi_poll(efx);
265 if (rc)
266 return rc;
267
268 /* Program address register, if we have an address */
269 if (addressed) {
270 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
271 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
272 }
273
274 /* Program data register, if we have data */
275 if (in != NULL) {
276 memcpy(&reg, in, len);
277 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
278 }
279
280 /* Issue read/write command */
281 EFX_POPULATE_OWORD_7(reg,
282 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
283 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
284 FRF_AB_EE_SPI_HCMD_DABCNT, len,
285 FRF_AB_EE_SPI_HCMD_READ, reading,
286 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
287 FRF_AB_EE_SPI_HCMD_ADBCNT,
288 (addressed ? spi->addr_len : 0),
289 FRF_AB_EE_SPI_HCMD_ENC, command);
290 efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
291
292 /* Wait for read/write to complete */
293 rc = falcon_spi_wait(efx);
294 if (rc)
295 return rc;
296
297 /* Read data */
298 if (out != NULL) {
299 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
300 memcpy(out, &reg, len);
301 }
302
303 return 0;
304 }
305
306 static size_t
307 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
308 {
309 return min(FALCON_SPI_MAX_LEN,
310 (spi->block_size - (start & (spi->block_size - 1))));
311 }
312
313 static inline u8
314 efx_spi_munge_command(const struct efx_spi_device *spi,
315 const u8 command, const unsigned int address)
316 {
317 return command | (((address >> 8) & spi->munge_address) << 3);
318 }
319
320 /* Wait up to 10 ms for buffered write completion */
321 int
322 falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi)
323 {
324 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
325 u8 status;
326 int rc;
327
328 for (;;) {
329 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
330 &status, sizeof(status));
331 if (rc)
332 return rc;
333 if (!(status & SPI_STATUS_NRDY))
334 return 0;
335 if (time_after_eq(jiffies, timeout)) {
336 EFX_ERR(efx, "SPI write timeout on device %d"
337 " last status=0x%02x\n",
338 spi->device_id, status);
339 return -ETIMEDOUT;
340 }
341 schedule_timeout_uninterruptible(1);
342 }
343 }
344
345 int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi,
346 loff_t start, size_t len, size_t *retlen, u8 *buffer)
347 {
348 size_t block_len, pos = 0;
349 unsigned int command;
350 int rc = 0;
351
352 while (pos < len) {
353 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
354
355 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
356 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
357 buffer + pos, block_len);
358 if (rc)
359 break;
360 pos += block_len;
361
362 /* Avoid locking up the system */
363 cond_resched();
364 if (signal_pending(current)) {
365 rc = -EINTR;
366 break;
367 }
368 }
369
370 if (retlen)
371 *retlen = pos;
372 return rc;
373 }
374
375 int
376 falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
377 loff_t start, size_t len, size_t *retlen, const u8 *buffer)
378 {
379 u8 verify_buffer[FALCON_SPI_MAX_LEN];
380 size_t block_len, pos = 0;
381 unsigned int command;
382 int rc = 0;
383
384 while (pos < len) {
385 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
386 if (rc)
387 break;
388
389 block_len = min(len - pos,
390 falcon_spi_write_limit(spi, start + pos));
391 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
392 rc = falcon_spi_cmd(efx, spi, command, start + pos,
393 buffer + pos, NULL, block_len);
394 if (rc)
395 break;
396
397 rc = falcon_spi_wait_write(efx, spi);
398 if (rc)
399 break;
400
401 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
402 rc = falcon_spi_cmd(efx, spi, command, start + pos,
403 NULL, verify_buffer, block_len);
404 if (memcmp(verify_buffer, buffer + pos, block_len)) {
405 rc = -EIO;
406 break;
407 }
408
409 pos += block_len;
410
411 /* Avoid locking up the system */
412 cond_resched();
413 if (signal_pending(current)) {
414 rc = -EINTR;
415 break;
416 }
417 }
418
419 if (retlen)
420 *retlen = pos;
421 return rc;
422 }
423
424 /**************************************************************************
425 *
426 * MAC wrapper
427 *
428 **************************************************************************
429 */
430
431 static void falcon_push_multicast_hash(struct efx_nic *efx)
432 {
433 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
434
435 WARN_ON(!mutex_is_locked(&efx->mac_lock));
436
437 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
438 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
439 }
440
441 static void falcon_reset_macs(struct efx_nic *efx)
442 {
443 struct falcon_nic_data *nic_data = efx->nic_data;
444 efx_oword_t reg, mac_ctrl;
445 int count;
446
447 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
448 /* It's not safe to use GLB_CTL_REG to reset the
449 * macs, so instead use the internal MAC resets
450 */
451 if (!EFX_IS10G(efx)) {
452 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
453 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
454 udelay(1000);
455
456 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
457 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
458 udelay(1000);
459 return;
460 } else {
461 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
462 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
463
464 for (count = 0; count < 10000; count++) {
465 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
466 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
467 0)
468 return;
469 udelay(10);
470 }
471
472 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
473 }
474 }
475
476 /* Mac stats will fail whist the TX fifo is draining */
477 WARN_ON(nic_data->stats_disable_count == 0);
478
479 efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
480 EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
481 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
482
483 efx_reado(efx, &reg, FR_AB_GLB_CTL);
484 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
485 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
486 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
487 efx_writeo(efx, &reg, FR_AB_GLB_CTL);
488
489 count = 0;
490 while (1) {
491 efx_reado(efx, &reg, FR_AB_GLB_CTL);
492 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
493 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
494 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
495 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
496 count);
497 break;
498 }
499 if (count > 20) {
500 EFX_ERR(efx, "MAC reset failed\n");
501 break;
502 }
503 count++;
504 udelay(10);
505 }
506
507 /* Ensure the correct MAC is selected before statistics
508 * are re-enabled by the caller */
509 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
510
511 /* This can run even when the GMAC is selected */
512 falcon_setup_xaui(efx);
513 }
514
515 void falcon_drain_tx_fifo(struct efx_nic *efx)
516 {
517 efx_oword_t reg;
518
519 if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
520 (efx->loopback_mode != LOOPBACK_NONE))
521 return;
522
523 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
524 /* There is no point in draining more than once */
525 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
526 return;
527
528 falcon_reset_macs(efx);
529 }
530
531 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
532 {
533 efx_oword_t reg;
534
535 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
536 return;
537
538 /* Isolate the MAC -> RX */
539 efx_reado(efx, &reg, FR_AZ_RX_CFG);
540 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
541 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
542
543 /* Isolate TX -> MAC */
544 falcon_drain_tx_fifo(efx);
545 }
546
547 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
548 {
549 struct efx_link_state *link_state = &efx->link_state;
550 efx_oword_t reg;
551 int link_speed, isolate;
552
553 isolate = (efx->reset_pending != RESET_TYPE_NONE);
554
555 switch (link_state->speed) {
556 case 10000: link_speed = 3; break;
557 case 1000: link_speed = 2; break;
558 case 100: link_speed = 1; break;
559 default: link_speed = 0; break;
560 }
561 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
562 * as advertised. Disable to ensure packets are not
563 * indefinitely held and TX queue can be flushed at any point
564 * while the link is down. */
565 EFX_POPULATE_OWORD_5(reg,
566 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
567 FRF_AB_MAC_BCAD_ACPT, 1,
568 FRF_AB_MAC_UC_PROM, efx->promiscuous,
569 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
570 FRF_AB_MAC_SPEED, link_speed);
571 /* On B0, MAC backpressure can be disabled and packets get
572 * discarded. */
573 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
574 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
575 !link_state->up || isolate);
576 }
577
578 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
579
580 /* Restore the multicast hash registers. */
581 falcon_push_multicast_hash(efx);
582
583 efx_reado(efx, &reg, FR_AZ_RX_CFG);
584 /* Enable XOFF signal from RX FIFO (we enabled it during NIC
585 * initialisation but it may read back as 0) */
586 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
587 /* Unisolate the MAC -> RX */
588 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
589 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);
590 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
591 }
592
593 static void falcon_stats_request(struct efx_nic *efx)
594 {
595 struct falcon_nic_data *nic_data = efx->nic_data;
596 efx_oword_t reg;
597
598 WARN_ON(nic_data->stats_pending);
599 WARN_ON(nic_data->stats_disable_count);
600
601 if (nic_data->stats_dma_done == NULL)
602 return; /* no mac selected */
603
604 *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE;
605 nic_data->stats_pending = true;
606 wmb(); /* ensure done flag is clear */
607
608 /* Initiate DMA transfer of stats */
609 EFX_POPULATE_OWORD_2(reg,
610 FRF_AB_MAC_STAT_DMA_CMD, 1,
611 FRF_AB_MAC_STAT_DMA_ADR,
612 efx->stats_buffer.dma_addr);
613 efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
614
615 mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
616 }
617
618 static void falcon_stats_complete(struct efx_nic *efx)
619 {
620 struct falcon_nic_data *nic_data = efx->nic_data;
621
622 if (!nic_data->stats_pending)
623 return;
624
625 nic_data->stats_pending = 0;
626 if (*nic_data->stats_dma_done == FALCON_STATS_DONE) {
627 rmb(); /* read the done flag before the stats */
628 efx->mac_op->update_stats(efx);
629 } else {
630 EFX_ERR(efx, "timed out waiting for statistics\n");
631 }
632 }
633
634 static void falcon_stats_timer_func(unsigned long context)
635 {
636 struct efx_nic *efx = (struct efx_nic *)context;
637 struct falcon_nic_data *nic_data = efx->nic_data;
638
639 spin_lock(&efx->stats_lock);
640
641 falcon_stats_complete(efx);
642 if (nic_data->stats_disable_count == 0)
643 falcon_stats_request(efx);
644
645 spin_unlock(&efx->stats_lock);
646 }
647
648 static void falcon_switch_mac(struct efx_nic *efx);
649
650 static bool falcon_loopback_link_poll(struct efx_nic *efx)
651 {
652 struct efx_link_state old_state = efx->link_state;
653
654 WARN_ON(!mutex_is_locked(&efx->mac_lock));
655 WARN_ON(!LOOPBACK_INTERNAL(efx));
656
657 efx->link_state.fd = true;
658 efx->link_state.fc = efx->wanted_fc;
659 efx->link_state.up = true;
660
661 if (efx->loopback_mode == LOOPBACK_GMAC)
662 efx->link_state.speed = 1000;
663 else
664 efx->link_state.speed = 10000;
665
666 return !efx_link_state_equal(&efx->link_state, &old_state);
667 }
668
669 static int falcon_reconfigure_port(struct efx_nic *efx)
670 {
671 int rc;
672
673 WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
674
675 /* Poll the PHY link state *before* reconfiguring it. This means we
676 * will pick up the correct speed (in loopback) to select the correct
677 * MAC.
678 */
679 if (LOOPBACK_INTERNAL(efx))
680 falcon_loopback_link_poll(efx);
681 else
682 efx->phy_op->poll(efx);
683
684 falcon_stop_nic_stats(efx);
685 falcon_deconfigure_mac_wrapper(efx);
686
687 falcon_switch_mac(efx);
688
689 efx->phy_op->reconfigure(efx);
690 rc = efx->mac_op->reconfigure(efx);
691 BUG_ON(rc);
692
693 falcon_start_nic_stats(efx);
694
695 /* Synchronise efx->link_state with the kernel */
696 efx_link_status_changed(efx);
697
698 return 0;
699 }
700
701 /**************************************************************************
702 *
703 * PHY access via GMII
704 *
705 **************************************************************************
706 */
707
708 /* Wait for GMII access to complete */
709 static int falcon_gmii_wait(struct efx_nic *efx)
710 {
711 efx_oword_t md_stat;
712 int count;
713
714 /* wait upto 50ms - taken max from datasheet */
715 for (count = 0; count < 5000; count++) {
716 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
717 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
718 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
719 EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
720 EFX_ERR(efx, "error from GMII access "
721 EFX_OWORD_FMT"\n",
722 EFX_OWORD_VAL(md_stat));
723 return -EIO;
724 }
725 return 0;
726 }
727 udelay(10);
728 }
729 EFX_ERR(efx, "timed out waiting for GMII\n");
730 return -ETIMEDOUT;
731 }
732
733 /* Write an MDIO register of a PHY connected to Falcon. */
734 static int falcon_mdio_write(struct net_device *net_dev,
735 int prtad, int devad, u16 addr, u16 value)
736 {
737 struct efx_nic *efx = netdev_priv(net_dev);
738 efx_oword_t reg;
739 int rc;
740
741 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
742 prtad, devad, addr, value);
743
744 mutex_lock(&efx->mdio_lock);
745
746 /* Check MDIO not currently being accessed */
747 rc = falcon_gmii_wait(efx);
748 if (rc)
749 goto out;
750
751 /* Write the address/ID register */
752 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
753 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
754
755 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
756 FRF_AB_MD_DEV_ADR, devad);
757 efx_writeo(efx, &reg, FR_AB_MD_ID);
758
759 /* Write data */
760 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
761 efx_writeo(efx, &reg, FR_AB_MD_TXD);
762
763 EFX_POPULATE_OWORD_2(reg,
764 FRF_AB_MD_WRC, 1,
765 FRF_AB_MD_GC, 0);
766 efx_writeo(efx, &reg, FR_AB_MD_CS);
767
768 /* Wait for data to be written */
769 rc = falcon_gmii_wait(efx);
770 if (rc) {
771 /* Abort the write operation */
772 EFX_POPULATE_OWORD_2(reg,
773 FRF_AB_MD_WRC, 0,
774 FRF_AB_MD_GC, 1);
775 efx_writeo(efx, &reg, FR_AB_MD_CS);
776 udelay(10);
777 }
778
779 out:
780 mutex_unlock(&efx->mdio_lock);
781 return rc;
782 }
783
784 /* Read an MDIO register of a PHY connected to Falcon. */
785 static int falcon_mdio_read(struct net_device *net_dev,
786 int prtad, int devad, u16 addr)
787 {
788 struct efx_nic *efx = netdev_priv(net_dev);
789 efx_oword_t reg;
790 int rc;
791
792 mutex_lock(&efx->mdio_lock);
793
794 /* Check MDIO not currently being accessed */
795 rc = falcon_gmii_wait(efx);
796 if (rc)
797 goto out;
798
799 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
800 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
801
802 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
803 FRF_AB_MD_DEV_ADR, devad);
804 efx_writeo(efx, &reg, FR_AB_MD_ID);
805
806 /* Request data to be read */
807 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
808 efx_writeo(efx, &reg, FR_AB_MD_CS);
809
810 /* Wait for data to become available */
811 rc = falcon_gmii_wait(efx);
812 if (rc == 0) {
813 efx_reado(efx, &reg, FR_AB_MD_RXD);
814 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
815 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
816 prtad, devad, addr, rc);
817 } else {
818 /* Abort the read operation */
819 EFX_POPULATE_OWORD_2(reg,
820 FRF_AB_MD_RIC, 0,
821 FRF_AB_MD_GC, 1);
822 efx_writeo(efx, &reg, FR_AB_MD_CS);
823
824 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
825 prtad, devad, addr, rc);
826 }
827
828 out:
829 mutex_unlock(&efx->mdio_lock);
830 return rc;
831 }
832
833 static void falcon_clock_mac(struct efx_nic *efx)
834 {
835 unsigned strap_val;
836 efx_oword_t nic_stat;
837
838 /* Configure the NIC generated MAC clock correctly */
839 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
840 strap_val = EFX_IS10G(efx) ? 5 : 3;
841 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
842 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
843 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
844 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
845 } else {
846 /* Falcon A1 does not support 1G/10G speed switching
847 * and must not be used with a PHY that does. */
848 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
849 strap_val);
850 }
851 }
852
853 static void falcon_switch_mac(struct efx_nic *efx)
854 {
855 struct efx_mac_operations *old_mac_op = efx->mac_op;
856 struct falcon_nic_data *nic_data = efx->nic_data;
857 unsigned int stats_done_offset;
858
859 WARN_ON(!mutex_is_locked(&efx->mac_lock));
860 WARN_ON(nic_data->stats_disable_count == 0);
861
862 efx->mac_op = (EFX_IS10G(efx) ?
863 &falcon_xmac_operations : &falcon_gmac_operations);
864
865 if (EFX_IS10G(efx))
866 stats_done_offset = XgDmaDone_offset;
867 else
868 stats_done_offset = GDmaDone_offset;
869 nic_data->stats_dma_done = efx->stats_buffer.addr + stats_done_offset;
870
871 if (old_mac_op == efx->mac_op)
872 return;
873
874 falcon_clock_mac(efx);
875
876 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
877 /* Not all macs support a mac-level link state */
878 efx->xmac_poll_required = false;
879 falcon_reset_macs(efx);
880 }
881
882 /* This call is responsible for hooking in the MAC and PHY operations */
883 static int falcon_probe_port(struct efx_nic *efx)
884 {
885 int rc;
886
887 switch (efx->phy_type) {
888 case PHY_TYPE_SFX7101:
889 efx->phy_op = &falcon_sfx7101_phy_ops;
890 break;
891 case PHY_TYPE_SFT9001A:
892 case PHY_TYPE_SFT9001B:
893 efx->phy_op = &falcon_sft9001_phy_ops;
894 break;
895 case PHY_TYPE_QT2022C2:
896 case PHY_TYPE_QT2025C:
897 efx->phy_op = &falcon_qt202x_phy_ops;
898 break;
899 default:
900 EFX_ERR(efx, "Unknown PHY type %d\n",
901 efx->phy_type);
902 return -ENODEV;
903 }
904
905 /* Fill out MDIO structure and loopback modes */
906 efx->mdio.mdio_read = falcon_mdio_read;
907 efx->mdio.mdio_write = falcon_mdio_write;
908 rc = efx->phy_op->probe(efx);
909 if (rc != 0)
910 return rc;
911
912 /* Initial assumption */
913 efx->link_state.speed = 10000;
914 efx->link_state.fd = true;
915
916 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
917 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
918 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
919 else
920 efx->wanted_fc = EFX_FC_RX;
921 if (efx->mdio.mmds & MDIO_DEVS_AN)
922 efx->wanted_fc |= EFX_FC_AUTO;
923
924 /* Allocate buffer for stats */
925 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
926 FALCON_MAC_STATS_SIZE);
927 if (rc)
928 return rc;
929 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
930 (u64)efx->stats_buffer.dma_addr,
931 efx->stats_buffer.addr,
932 (u64)virt_to_phys(efx->stats_buffer.addr));
933
934 return 0;
935 }
936
937 static void falcon_remove_port(struct efx_nic *efx)
938 {
939 efx->phy_op->remove(efx);
940 efx_nic_free_buffer(efx, &efx->stats_buffer);
941 }
942
943 /**************************************************************************
944 *
945 * Falcon test code
946 *
947 **************************************************************************/
948
949 static int
950 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
951 {
952 struct falcon_nvconfig *nvconfig;
953 struct efx_spi_device *spi;
954 void *region;
955 int rc, magic_num, struct_ver;
956 __le16 *word, *limit;
957 u32 csum;
958
959 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
960 if (!spi)
961 return -EINVAL;
962
963 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
964 if (!region)
965 return -ENOMEM;
966 nvconfig = region + FALCON_NVCONFIG_OFFSET;
967
968 mutex_lock(&efx->spi_lock);
969 rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
970 mutex_unlock(&efx->spi_lock);
971 if (rc) {
972 EFX_ERR(efx, "Failed to read %s\n",
973 efx->spi_flash ? "flash" : "EEPROM");
974 rc = -EIO;
975 goto out;
976 }
977
978 magic_num = le16_to_cpu(nvconfig->board_magic_num);
979 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
980
981 rc = -EINVAL;
982 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
983 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
984 goto out;
985 }
986 if (struct_ver < 2) {
987 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
988 goto out;
989 } else if (struct_ver < 4) {
990 word = &nvconfig->board_magic_num;
991 limit = (__le16 *) (nvconfig + 1);
992 } else {
993 word = region;
994 limit = region + FALCON_NVCONFIG_END;
995 }
996 for (csum = 0; word < limit; ++word)
997 csum += le16_to_cpu(*word);
998
999 if (~csum & 0xffff) {
1000 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
1001 goto out;
1002 }
1003
1004 rc = 0;
1005 if (nvconfig_out)
1006 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
1007
1008 out:
1009 kfree(region);
1010 return rc;
1011 }
1012
1013 static int falcon_test_nvram(struct efx_nic *efx)
1014 {
1015 return falcon_read_nvram(efx, NULL);
1016 }
1017
1018 static const struct efx_nic_register_test falcon_b0_register_tests[] = {
1019 { FR_AZ_ADR_REGION,
1020 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1021 { FR_AZ_RX_CFG,
1022 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1023 { FR_AZ_TX_CFG,
1024 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1025 { FR_AZ_TX_RESERVED,
1026 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1027 { FR_AB_MAC_CTRL,
1028 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1029 { FR_AZ_SRM_TX_DC_CFG,
1030 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1031 { FR_AZ_RX_DC_CFG,
1032 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1033 { FR_AZ_RX_DC_PF_WM,
1034 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1035 { FR_BZ_DP_CTRL,
1036 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1037 { FR_AB_GM_CFG2,
1038 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1039 { FR_AB_GMF_CFG0,
1040 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1041 { FR_AB_XM_GLB_CFG,
1042 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1043 { FR_AB_XM_TX_CFG,
1044 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1045 { FR_AB_XM_RX_CFG,
1046 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1047 { FR_AB_XM_RX_PARAM,
1048 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1049 { FR_AB_XM_FC,
1050 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1051 { FR_AB_XM_ADR_LO,
1052 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1053 { FR_AB_XX_SD_CTL,
1054 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1055 };
1056
1057 static int falcon_b0_test_registers(struct efx_nic *efx)
1058 {
1059 return efx_nic_test_registers(efx, falcon_b0_register_tests,
1060 ARRAY_SIZE(falcon_b0_register_tests));
1061 }
1062
1063 /**************************************************************************
1064 *
1065 * Device reset
1066 *
1067 **************************************************************************
1068 */
1069
1070 /* Resets NIC to known state. This routine must be called in process
1071 * context and is allowed to sleep. */
1072 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1073 {
1074 struct falcon_nic_data *nic_data = efx->nic_data;
1075 efx_oword_t glb_ctl_reg_ker;
1076 int rc;
1077
1078 EFX_LOG(efx, "performing %s hardware reset\n", RESET_TYPE(method));
1079
1080 /* Initiate device reset */
1081 if (method == RESET_TYPE_WORLD) {
1082 rc = pci_save_state(efx->pci_dev);
1083 if (rc) {
1084 EFX_ERR(efx, "failed to backup PCI state of primary "
1085 "function prior to hardware reset\n");
1086 goto fail1;
1087 }
1088 if (efx_nic_is_dual_func(efx)) {
1089 rc = pci_save_state(nic_data->pci_dev2);
1090 if (rc) {
1091 EFX_ERR(efx, "failed to backup PCI state of "
1092 "secondary function prior to "
1093 "hardware reset\n");
1094 goto fail2;
1095 }
1096 }
1097
1098 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1099 FRF_AB_EXT_PHY_RST_DUR,
1100 FFE_AB_EXT_PHY_RST_DUR_10240US,
1101 FRF_AB_SWRST, 1);
1102 } else {
1103 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1104 /* exclude PHY from "invisible" reset */
1105 FRF_AB_EXT_PHY_RST_CTL,
1106 method == RESET_TYPE_INVISIBLE,
1107 /* exclude EEPROM/flash and PCIe */
1108 FRF_AB_PCIE_CORE_RST_CTL, 1,
1109 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1110 FRF_AB_PCIE_SD_RST_CTL, 1,
1111 FRF_AB_EE_RST_CTL, 1,
1112 FRF_AB_EXT_PHY_RST_DUR,
1113 FFE_AB_EXT_PHY_RST_DUR_10240US,
1114 FRF_AB_SWRST, 1);
1115 }
1116 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1117
1118 EFX_LOG(efx, "waiting for hardware reset\n");
1119 schedule_timeout_uninterruptible(HZ / 20);
1120
1121 /* Restore PCI configuration if needed */
1122 if (method == RESET_TYPE_WORLD) {
1123 if (efx_nic_is_dual_func(efx)) {
1124 rc = pci_restore_state(nic_data->pci_dev2);
1125 if (rc) {
1126 EFX_ERR(efx, "failed to restore PCI config for "
1127 "the secondary function\n");
1128 goto fail3;
1129 }
1130 }
1131 rc = pci_restore_state(efx->pci_dev);
1132 if (rc) {
1133 EFX_ERR(efx, "failed to restore PCI config for the "
1134 "primary function\n");
1135 goto fail4;
1136 }
1137 EFX_LOG(efx, "successfully restored PCI config\n");
1138 }
1139
1140 /* Assert that reset complete */
1141 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1142 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
1143 rc = -ETIMEDOUT;
1144 EFX_ERR(efx, "timed out waiting for hardware reset\n");
1145 goto fail5;
1146 }
1147 EFX_LOG(efx, "hardware reset complete\n");
1148
1149 return 0;
1150
1151 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
1152 fail2:
1153 fail3:
1154 pci_restore_state(efx->pci_dev);
1155 fail1:
1156 fail4:
1157 fail5:
1158 return rc;
1159 }
1160
1161 static void falcon_monitor(struct efx_nic *efx)
1162 {
1163 bool link_changed;
1164 int rc;
1165
1166 BUG_ON(!mutex_is_locked(&efx->mac_lock));
1167
1168 rc = falcon_board(efx)->type->monitor(efx);
1169 if (rc) {
1170 EFX_ERR(efx, "Board sensor %s; shutting down PHY\n",
1171 (rc == -ERANGE) ? "reported fault" : "failed");
1172 efx->phy_mode |= PHY_MODE_LOW_POWER;
1173 rc = __efx_reconfigure_port(efx);
1174 WARN_ON(rc);
1175 }
1176
1177 if (LOOPBACK_INTERNAL(efx))
1178 link_changed = falcon_loopback_link_poll(efx);
1179 else
1180 link_changed = efx->phy_op->poll(efx);
1181
1182 if (link_changed) {
1183 falcon_stop_nic_stats(efx);
1184 falcon_deconfigure_mac_wrapper(efx);
1185
1186 falcon_switch_mac(efx);
1187 rc = efx->mac_op->reconfigure(efx);
1188 BUG_ON(rc);
1189
1190 falcon_start_nic_stats(efx);
1191
1192 efx_link_status_changed(efx);
1193 }
1194
1195 if (EFX_IS10G(efx))
1196 falcon_poll_xmac(efx);
1197 }
1198
1199 /* Zeroes out the SRAM contents. This routine must be called in
1200 * process context and is allowed to sleep.
1201 */
1202 static int falcon_reset_sram(struct efx_nic *efx)
1203 {
1204 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
1205 int count;
1206
1207 /* Set the SRAM wake/sleep GPIO appropriately. */
1208 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1209 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
1210 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
1211 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1212
1213 /* Initiate SRAM reset */
1214 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
1215 FRF_AZ_SRM_INIT_EN, 1,
1216 FRF_AZ_SRM_NB_SZ, 0);
1217 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1218
1219 /* Wait for SRAM reset to complete */
1220 count = 0;
1221 do {
1222 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
1223
1224 /* SRAM reset is slow; expect around 16ms */
1225 schedule_timeout_uninterruptible(HZ / 50);
1226
1227 /* Check for reset complete */
1228 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1229 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
1230 EFX_LOG(efx, "SRAM reset complete\n");
1231
1232 return 0;
1233 }
1234 } while (++count < 20); /* wait upto 0.4 sec */
1235
1236 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
1237 return -ETIMEDOUT;
1238 }
1239
1240 static int falcon_spi_device_init(struct efx_nic *efx,
1241 struct efx_spi_device **spi_device_ret,
1242 unsigned int device_id, u32 device_type)
1243 {
1244 struct efx_spi_device *spi_device;
1245
1246 if (device_type != 0) {
1247 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
1248 if (!spi_device)
1249 return -ENOMEM;
1250 spi_device->device_id = device_id;
1251 spi_device->size =
1252 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
1253 spi_device->addr_len =
1254 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
1255 spi_device->munge_address = (spi_device->size == 1 << 9 &&
1256 spi_device->addr_len == 1);
1257 spi_device->erase_command =
1258 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
1259 spi_device->erase_size =
1260 1 << SPI_DEV_TYPE_FIELD(device_type,
1261 SPI_DEV_TYPE_ERASE_SIZE);
1262 spi_device->block_size =
1263 1 << SPI_DEV_TYPE_FIELD(device_type,
1264 SPI_DEV_TYPE_BLOCK_SIZE);
1265 } else {
1266 spi_device = NULL;
1267 }
1268
1269 kfree(*spi_device_ret);
1270 *spi_device_ret = spi_device;
1271 return 0;
1272 }
1273
1274 static void falcon_remove_spi_devices(struct efx_nic *efx)
1275 {
1276 kfree(efx->spi_eeprom);
1277 efx->spi_eeprom = NULL;
1278 kfree(efx->spi_flash);
1279 efx->spi_flash = NULL;
1280 }
1281
1282 /* Extract non-volatile configuration */
1283 static int falcon_probe_nvconfig(struct efx_nic *efx)
1284 {
1285 struct falcon_nvconfig *nvconfig;
1286 int board_rev;
1287 int rc;
1288
1289 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
1290 if (!nvconfig)
1291 return -ENOMEM;
1292
1293 rc = falcon_read_nvram(efx, nvconfig);
1294 if (rc == -EINVAL) {
1295 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
1296 efx->phy_type = PHY_TYPE_NONE;
1297 efx->mdio.prtad = MDIO_PRTAD_NONE;
1298 board_rev = 0;
1299 rc = 0;
1300 } else if (rc) {
1301 goto fail1;
1302 } else {
1303 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
1304 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
1305
1306 efx->phy_type = v2->port0_phy_type;
1307 efx->mdio.prtad = v2->port0_phy_addr;
1308 board_rev = le16_to_cpu(v2->board_revision);
1309
1310 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
1311 rc = falcon_spi_device_init(
1312 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
1313 le32_to_cpu(v3->spi_device_type
1314 [FFE_AB_SPI_DEVICE_FLASH]));
1315 if (rc)
1316 goto fail2;
1317 rc = falcon_spi_device_init(
1318 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
1319 le32_to_cpu(v3->spi_device_type
1320 [FFE_AB_SPI_DEVICE_EEPROM]));
1321 if (rc)
1322 goto fail2;
1323 }
1324 }
1325
1326 /* Read the MAC addresses */
1327 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
1328
1329 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
1330
1331 rc = falcon_probe_board(efx, board_rev);
1332 if (rc)
1333 goto fail2;
1334
1335 kfree(nvconfig);
1336 return 0;
1337
1338 fail2:
1339 falcon_remove_spi_devices(efx);
1340 fail1:
1341 kfree(nvconfig);
1342 return rc;
1343 }
1344
1345 /* Probe all SPI devices on the NIC */
1346 static void falcon_probe_spi_devices(struct efx_nic *efx)
1347 {
1348 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
1349 int boot_dev;
1350
1351 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
1352 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1353 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1354
1355 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
1356 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
1357 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
1358 EFX_LOG(efx, "Booted from %s\n",
1359 boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
1360 } else {
1361 /* Disable VPD and set clock dividers to safe
1362 * values for initial programming. */
1363 boot_dev = -1;
1364 EFX_LOG(efx, "Booted from internal ASIC settings;"
1365 " setting SPI config\n");
1366 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
1367 /* 125 MHz / 7 ~= 20 MHz */
1368 FRF_AB_EE_SF_CLOCK_DIV, 7,
1369 /* 125 MHz / 63 ~= 2 MHz */
1370 FRF_AB_EE_EE_CLOCK_DIV, 63);
1371 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1372 }
1373
1374 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
1375 falcon_spi_device_init(efx, &efx->spi_flash,
1376 FFE_AB_SPI_DEVICE_FLASH,
1377 default_flash_type);
1378 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
1379 falcon_spi_device_init(efx, &efx->spi_eeprom,
1380 FFE_AB_SPI_DEVICE_EEPROM,
1381 large_eeprom_type);
1382 }
1383
1384 static int falcon_probe_nic(struct efx_nic *efx)
1385 {
1386 struct falcon_nic_data *nic_data;
1387 struct falcon_board *board;
1388 int rc;
1389
1390 /* Allocate storage for hardware specific data */
1391 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1392 if (!nic_data)
1393 return -ENOMEM;
1394 efx->nic_data = nic_data;
1395
1396 rc = -ENODEV;
1397
1398 if (efx_nic_fpga_ver(efx) != 0) {
1399 EFX_ERR(efx, "Falcon FPGA not supported\n");
1400 goto fail1;
1401 }
1402
1403 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1404 efx_oword_t nic_stat;
1405 struct pci_dev *dev;
1406 u8 pci_rev = efx->pci_dev->revision;
1407
1408 if ((pci_rev == 0xff) || (pci_rev == 0)) {
1409 EFX_ERR(efx, "Falcon rev A0 not supported\n");
1410 goto fail1;
1411 }
1412 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1413 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
1414 EFX_ERR(efx, "Falcon rev A1 1G not supported\n");
1415 goto fail1;
1416 }
1417 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
1418 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
1419 goto fail1;
1420 }
1421
1422 dev = pci_dev_get(efx->pci_dev);
1423 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
1424 dev))) {
1425 if (dev->bus == efx->pci_dev->bus &&
1426 dev->devfn == efx->pci_dev->devfn + 1) {
1427 nic_data->pci_dev2 = dev;
1428 break;
1429 }
1430 }
1431 if (!nic_data->pci_dev2) {
1432 EFX_ERR(efx, "failed to find secondary function\n");
1433 rc = -ENODEV;
1434 goto fail2;
1435 }
1436 }
1437
1438 /* Now we can reset the NIC */
1439 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
1440 if (rc) {
1441 EFX_ERR(efx, "failed to reset NIC\n");
1442 goto fail3;
1443 }
1444
1445 /* Allocate memory for INT_KER */
1446 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
1447 if (rc)
1448 goto fail4;
1449 BUG_ON(efx->irq_status.dma_addr & 0x0f);
1450
1451 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
1452 (u64)efx->irq_status.dma_addr,
1453 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
1454
1455 falcon_probe_spi_devices(efx);
1456
1457 /* Read in the non-volatile configuration */
1458 rc = falcon_probe_nvconfig(efx);
1459 if (rc)
1460 goto fail5;
1461
1462 /* Initialise I2C adapter */
1463 board = falcon_board(efx);
1464 board->i2c_adap.owner = THIS_MODULE;
1465 board->i2c_data = falcon_i2c_bit_operations;
1466 board->i2c_data.data = efx;
1467 board->i2c_adap.algo_data = &board->i2c_data;
1468 board->i2c_adap.dev.parent = &efx->pci_dev->dev;
1469 strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
1470 sizeof(board->i2c_adap.name));
1471 rc = i2c_bit_add_bus(&board->i2c_adap);
1472 if (rc)
1473 goto fail5;
1474
1475 rc = falcon_board(efx)->type->init(efx);
1476 if (rc) {
1477 EFX_ERR(efx, "failed to initialise board\n");
1478 goto fail6;
1479 }
1480
1481 nic_data->stats_disable_count = 1;
1482 setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
1483 (unsigned long)efx);
1484
1485 return 0;
1486
1487 fail6:
1488 BUG_ON(i2c_del_adapter(&board->i2c_adap));
1489 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1490 fail5:
1491 falcon_remove_spi_devices(efx);
1492 efx_nic_free_buffer(efx, &efx->irq_status);
1493 fail4:
1494 fail3:
1495 if (nic_data->pci_dev2) {
1496 pci_dev_put(nic_data->pci_dev2);
1497 nic_data->pci_dev2 = NULL;
1498 }
1499 fail2:
1500 fail1:
1501 kfree(efx->nic_data);
1502 return rc;
1503 }
1504
1505 static void falcon_init_rx_cfg(struct efx_nic *efx)
1506 {
1507 /* Prior to Siena the RX DMA engine will split each frame at
1508 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
1509 * be so large that that never happens. */
1510 const unsigned huge_buf_size = (3 * 4096) >> 5;
1511 /* RX control FIFO thresholds (32 entries) */
1512 const unsigned ctrl_xon_thr = 20;
1513 const unsigned ctrl_xoff_thr = 25;
1514 /* RX data FIFO thresholds (256-byte units; size varies) */
1515 int data_xon_thr = efx_nic_rx_xon_thresh >> 8;
1516 int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8;
1517 efx_oword_t reg;
1518
1519 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1520 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1521 /* Data FIFO size is 5.5K */
1522 if (data_xon_thr < 0)
1523 data_xon_thr = 512 >> 8;
1524 if (data_xoff_thr < 0)
1525 data_xoff_thr = 2048 >> 8;
1526 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
1527 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
1528 huge_buf_size);
1529 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
1530 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
1531 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
1532 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
1533 } else {
1534 /* Data FIFO size is 80K; register fields moved */
1535 if (data_xon_thr < 0)
1536 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
1537 if (data_xoff_thr < 0)
1538 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
1539 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
1540 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
1541 huge_buf_size);
1542 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
1543 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
1544 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
1545 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
1546 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1547 }
1548 /* Always enable XOFF signal from RX FIFO. We enable
1549 * or disable transmission of pause frames at the MAC. */
1550 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1551 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1552 }
1553
1554 /* This call performs hardware-specific global initialisation, such as
1555 * defining the descriptor cache sizes and number of RSS channels.
1556 * It does not set up any buffers, descriptor rings or event queues.
1557 */
1558 static int falcon_init_nic(struct efx_nic *efx)
1559 {
1560 efx_oword_t temp;
1561 int rc;
1562
1563 /* Use on-chip SRAM */
1564 efx_reado(efx, &temp, FR_AB_NIC_STAT);
1565 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
1566 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
1567
1568 /* Set the source of the GMAC clock */
1569 if (efx_nic_rev(efx) == EFX_REV_FALCON_B0) {
1570 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
1571 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
1572 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
1573 }
1574
1575 /* Select the correct MAC */
1576 falcon_clock_mac(efx);
1577
1578 rc = falcon_reset_sram(efx);
1579 if (rc)
1580 return rc;
1581
1582 /* Clear the parity enables on the TX data fifos as
1583 * they produce false parity errors because of timing issues
1584 */
1585 if (EFX_WORKAROUND_5129(efx)) {
1586 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
1587 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
1588 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
1589 }
1590
1591 if (EFX_WORKAROUND_7244(efx)) {
1592 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
1593 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
1594 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
1595 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
1596 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
1597 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
1598 }
1599
1600 /* XXX This is documented only for Falcon A0/A1 */
1601 /* Setup RX. Wait for descriptor is broken and must
1602 * be disabled. RXDP recovery shouldn't be needed, but is.
1603 */
1604 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
1605 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
1606 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
1607 if (EFX_WORKAROUND_5583(efx))
1608 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
1609 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
1610
1611 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
1612 * descriptors (which is bad).
1613 */
1614 efx_reado(efx, &temp, FR_AZ_TX_CFG);
1615 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
1616 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
1617
1618 falcon_init_rx_cfg(efx);
1619
1620 /* Set destination of both TX and RX Flush events */
1621 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1622 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
1623 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
1624 }
1625
1626 efx_nic_init_common(efx);
1627
1628 return 0;
1629 }
1630
1631 static void falcon_remove_nic(struct efx_nic *efx)
1632 {
1633 struct falcon_nic_data *nic_data = efx->nic_data;
1634 struct falcon_board *board = falcon_board(efx);
1635 int rc;
1636
1637 board->type->fini(efx);
1638
1639 /* Remove I2C adapter and clear it in preparation for a retry */
1640 rc = i2c_del_adapter(&board->i2c_adap);
1641 BUG_ON(rc);
1642 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1643
1644 falcon_remove_spi_devices(efx);
1645 efx_nic_free_buffer(efx, &efx->irq_status);
1646
1647 falcon_reset_hw(efx, RESET_TYPE_ALL);
1648
1649 /* Release the second function after the reset */
1650 if (nic_data->pci_dev2) {
1651 pci_dev_put(nic_data->pci_dev2);
1652 nic_data->pci_dev2 = NULL;
1653 }
1654
1655 /* Tear down the private nic state */
1656 kfree(efx->nic_data);
1657 efx->nic_data = NULL;
1658 }
1659
1660 static void falcon_update_nic_stats(struct efx_nic *efx)
1661 {
1662 struct falcon_nic_data *nic_data = efx->nic_data;
1663 efx_oword_t cnt;
1664
1665 if (nic_data->stats_disable_count)
1666 return;
1667
1668 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
1669 efx->n_rx_nodesc_drop_cnt +=
1670 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
1671
1672 if (nic_data->stats_pending &&
1673 *nic_data->stats_dma_done == FALCON_STATS_DONE) {
1674 nic_data->stats_pending = false;
1675 rmb(); /* read the done flag before the stats */
1676 efx->mac_op->update_stats(efx);
1677 }
1678 }
1679
1680 void falcon_start_nic_stats(struct efx_nic *efx)
1681 {
1682 struct falcon_nic_data *nic_data = efx->nic_data;
1683
1684 spin_lock_bh(&efx->stats_lock);
1685 if (--nic_data->stats_disable_count == 0)
1686 falcon_stats_request(efx);
1687 spin_unlock_bh(&efx->stats_lock);
1688 }
1689
1690 void falcon_stop_nic_stats(struct efx_nic *efx)
1691 {
1692 struct falcon_nic_data *nic_data = efx->nic_data;
1693 int i;
1694
1695 might_sleep();
1696
1697 spin_lock_bh(&efx->stats_lock);
1698 ++nic_data->stats_disable_count;
1699 spin_unlock_bh(&efx->stats_lock);
1700
1701 del_timer_sync(&nic_data->stats_timer);
1702
1703 /* Wait enough time for the most recent transfer to
1704 * complete. */
1705 for (i = 0; i < 4 && nic_data->stats_pending; i++) {
1706 if (*nic_data->stats_dma_done == FALCON_STATS_DONE)
1707 break;
1708 msleep(1);
1709 }
1710
1711 spin_lock_bh(&efx->stats_lock);
1712 falcon_stats_complete(efx);
1713 spin_unlock_bh(&efx->stats_lock);
1714 }
1715
1716 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1717 {
1718 falcon_board(efx)->type->set_id_led(efx, mode);
1719 }
1720
1721 /**************************************************************************
1722 *
1723 * Wake on LAN
1724 *
1725 **************************************************************************
1726 */
1727
1728 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1729 {
1730 wol->supported = 0;
1731 wol->wolopts = 0;
1732 memset(&wol->sopass, 0, sizeof(wol->sopass));
1733 }
1734
1735 static int falcon_set_wol(struct efx_nic *efx, u32 type)
1736 {
1737 if (type != 0)
1738 return -EINVAL;
1739 return 0;
1740 }
1741
1742 /**************************************************************************
1743 *
1744 * Revision-dependent attributes used by efx.c and nic.c
1745 *
1746 **************************************************************************
1747 */
1748
1749 struct efx_nic_type falcon_a1_nic_type = {
1750 .probe = falcon_probe_nic,
1751 .remove = falcon_remove_nic,
1752 .init = falcon_init_nic,
1753 .fini = efx_port_dummy_op_void,
1754 .monitor = falcon_monitor,
1755 .reset = falcon_reset_hw,
1756 .probe_port = falcon_probe_port,
1757 .remove_port = falcon_remove_port,
1758 .prepare_flush = falcon_prepare_flush,
1759 .update_stats = falcon_update_nic_stats,
1760 .start_stats = falcon_start_nic_stats,
1761 .stop_stats = falcon_stop_nic_stats,
1762 .set_id_led = falcon_set_id_led,
1763 .push_irq_moderation = falcon_push_irq_moderation,
1764 .push_multicast_hash = falcon_push_multicast_hash,
1765 .reconfigure_port = falcon_reconfigure_port,
1766 .get_wol = falcon_get_wol,
1767 .set_wol = falcon_set_wol,
1768 .resume_wol = efx_port_dummy_op_void,
1769 .test_nvram = falcon_test_nvram,
1770 .default_mac_ops = &falcon_xmac_operations,
1771
1772 .revision = EFX_REV_FALCON_A1,
1773 .mem_map_size = 0x20000,
1774 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
1775 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
1776 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
1777 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
1778 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
1779 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1780 .rx_buffer_padding = 0x24,
1781 .max_interrupt_mode = EFX_INT_MODE_MSI,
1782 .phys_addr_channels = 4,
1783 .tx_dc_base = 0x130000,
1784 .rx_dc_base = 0x100000,
1785 .offload_features = NETIF_F_IP_CSUM,
1786 .reset_world_flags = ETH_RESET_IRQ,
1787 };
1788
1789 struct efx_nic_type falcon_b0_nic_type = {
1790 .probe = falcon_probe_nic,
1791 .remove = falcon_remove_nic,
1792 .init = falcon_init_nic,
1793 .fini = efx_port_dummy_op_void,
1794 .monitor = falcon_monitor,
1795 .reset = falcon_reset_hw,
1796 .probe_port = falcon_probe_port,
1797 .remove_port = falcon_remove_port,
1798 .prepare_flush = falcon_prepare_flush,
1799 .update_stats = falcon_update_nic_stats,
1800 .start_stats = falcon_start_nic_stats,
1801 .stop_stats = falcon_stop_nic_stats,
1802 .set_id_led = falcon_set_id_led,
1803 .push_irq_moderation = falcon_push_irq_moderation,
1804 .push_multicast_hash = falcon_push_multicast_hash,
1805 .reconfigure_port = falcon_reconfigure_port,
1806 .get_wol = falcon_get_wol,
1807 .set_wol = falcon_set_wol,
1808 .resume_wol = efx_port_dummy_op_void,
1809 .test_registers = falcon_b0_test_registers,
1810 .test_nvram = falcon_test_nvram,
1811 .default_mac_ops = &falcon_xmac_operations,
1812
1813 .revision = EFX_REV_FALCON_B0,
1814 /* Map everything up to and including the RSS indirection
1815 * table. Don't map MSI-X table, MSI-X PBA since Linux
1816 * requires that they not be mapped. */
1817 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
1818 FR_BZ_RX_INDIRECTION_TBL_STEP *
1819 FR_BZ_RX_INDIRECTION_TBL_ROWS),
1820 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1821 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1822 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1823 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1824 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1825 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1826 .rx_buffer_padding = 0,
1827 .max_interrupt_mode = EFX_INT_MODE_MSIX,
1828 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
1829 * interrupt handler only supports 32
1830 * channels */
1831 .tx_dc_base = 0x130000,
1832 .rx_dc_base = 0x100000,
1833 .offload_features = NETIF_F_IP_CSUM,
1834 .reset_world_flags = ETH_RESET_IRQ,
1835 };
1836
Linux with added FPC-III support