include/linux/mtd/spi-nor.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LINUX_MTD_SPI_NOR_H
   7 #define __LINUX_MTD_SPI_NOR_H
   8
   9 #include <linux/bitops.h>
  10 #include <linux/mtd/cfi.h>
  11 #include <linux/mtd/mtd.h>
  12 #include <linux/spi/spi-mem.h>
  13
  14 /*
  15  * Manufacturer IDs
  16  *
  17  * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
  18  * Sometimes these are the same as CFI IDs, but sometimes they aren't.
  19  */
  20 #define SNOR_MFR_ATMEL          CFI_MFR_ATMEL
  21 #define SNOR_MFR_GIGADEVICE     0xc8
  22 #define SNOR_MFR_INTEL          CFI_MFR_INTEL
  23 #define SNOR_MFR_ST             CFI_MFR_ST      /* ST Micro */
  24 #define SNOR_MFR_MICRON         CFI_MFR_MICRON  /* Micron */
  25 #define SNOR_MFR_ISSI           CFI_MFR_PMC
  26 #define SNOR_MFR_MACRONIX       CFI_MFR_MACRONIX
  27 #define SNOR_MFR_SPANSION       CFI_MFR_AMD
  28 #define SNOR_MFR_SST            CFI_MFR_SST
  29 #define SNOR_MFR_WINBOND        0xef /* Also used by some Spansion */
  30
  31 /*
  32  * Note on opcode nomenclature: some opcodes have a format like
  33  * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
  34  * of I/O lines used for the opcode, address, and data (respectively). The
  35  * FUNCTION has an optional suffix of '4', to represent an opcode which
  36  * requires a 4-byte (32-bit) address.
  37  */
  38
  39 /* Flash opcodes. */
  40 #define SPINOR_OP_WREN          0x06    /* Write enable */
  41 #define SPINOR_OP_RDSR          0x05    /* Read status register */
  42 #define SPINOR_OP_WRSR          0x01    /* Write status register 1 byte */
  43 #define SPINOR_OP_RDSR2         0x3f    /* Read status register 2 */
  44 #define SPINOR_OP_WRSR2         0x3e    /* Write status register 2 */
  45 #define SPINOR_OP_READ          0x03    /* Read data bytes (low frequency) */
  46 #define SPINOR_OP_READ_FAST     0x0b    /* Read data bytes (high frequency) */
  47 #define SPINOR_OP_READ_1_1_2    0x3b    /* Read data bytes (Dual Output SPI) */
  48 #define SPINOR_OP_READ_1_2_2    0xbb    /* Read data bytes (Dual I/O SPI) */
  49 #define SPINOR_OP_READ_1_1_4    0x6b    /* Read data bytes (Quad Output SPI) */
  50 #define SPINOR_OP_READ_1_4_4    0xeb    /* Read data bytes (Quad I/O SPI) */
  51 #define SPINOR_OP_READ_1_1_8    0x8b    /* Read data bytes (Octal Output SPI) */
  52 #define SPINOR_OP_READ_1_8_8    0xcb    /* Read data bytes (Octal I/O SPI) */
  53 #define SPINOR_OP_PP            0x02    /* Page program (up to 256 bytes) */
  54 #define SPINOR_OP_PP_1_1_4      0x32    /* Quad page program */
  55 #define SPINOR_OP_PP_1_4_4      0x38    /* Quad page program */
  56 #define SPINOR_OP_PP_1_1_8      0x82    /* Octal page program */
  57 #define SPINOR_OP_PP_1_8_8      0xc2    /* Octal page program */
  58 #define SPINOR_OP_BE_4K         0x20    /* Erase 4KiB block */
  59 #define SPINOR_OP_BE_4K_PMC     0xd7    /* Erase 4KiB block on PMC chips */
  60 #define SPINOR_OP_BE_32K        0x52    /* Erase 32KiB block */
  61 #define SPINOR_OP_CHIP_ERASE    0xc7    /* Erase whole flash chip */
  62 #define SPINOR_OP_SE            0xd8    /* Sector erase (usually 64KiB) */
  63 #define SPINOR_OP_RDID          0x9f    /* Read JEDEC ID */
  64 #define SPINOR_OP_RDSFDP        0x5a    /* Read SFDP */
  65 #define SPINOR_OP_RDCR          0x35    /* Read configuration register */
  66 #define SPINOR_OP_RDFSR         0x70    /* Read flag status register */
  67 #define SPINOR_OP_CLFSR         0x50    /* Clear flag status register */
  68 #define SPINOR_OP_RDEAR         0xc8    /* Read Extended Address Register */
  69 #define SPINOR_OP_WREAR         0xc5    /* Write Extended Address Register */
  70
  71 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
  72 #define SPINOR_OP_READ_4B       0x13    /* Read data bytes (low frequency) */
  73 #define SPINOR_OP_READ_FAST_4B  0x0c    /* Read data bytes (high frequency) */
  74 #define SPINOR_OP_READ_1_1_2_4B 0x3c    /* Read data bytes (Dual Output SPI) */
  75 #define SPINOR_OP_READ_1_2_2_4B 0xbc    /* Read data bytes (Dual I/O SPI) */
  76 #define SPINOR_OP_READ_1_1_4_4B 0x6c    /* Read data bytes (Quad Output SPI) */
  77 #define SPINOR_OP_READ_1_4_4_4B 0xec    /* Read data bytes (Quad I/O SPI) */
  78 #define SPINOR_OP_READ_1_1_8_4B 0x7c    /* Read data bytes (Octal Output SPI) */
  79 #define SPINOR_OP_READ_1_8_8_4B 0xcc    /* Read data bytes (Octal I/O SPI) */
  80 #define SPINOR_OP_PP_4B         0x12    /* Page program (up to 256 bytes) */
  81 #define SPINOR_OP_PP_1_1_4_4B   0x34    /* Quad page program */
  82 #define SPINOR_OP_PP_1_4_4_4B   0x3e    /* Quad page program */
  83 #define SPINOR_OP_PP_1_1_8_4B   0x84    /* Octal page program */
  84 #define SPINOR_OP_PP_1_8_8_4B   0x8e    /* Octal page program */
  85 #define SPINOR_OP_BE_4K_4B      0x21    /* Erase 4KiB block */
  86 #define SPINOR_OP_BE_32K_4B     0x5c    /* Erase 32KiB block */
  87 #define SPINOR_OP_SE_4B         0xdc    /* Sector erase (usually 64KiB) */
  88
  89 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
  90 #define SPINOR_OP_READ_1_1_1_DTR        0x0d
  91 #define SPINOR_OP_READ_1_2_2_DTR        0xbd
  92 #define SPINOR_OP_READ_1_4_4_DTR        0xed
  93
  94 #define SPINOR_OP_READ_1_1_1_DTR_4B     0x0e
  95 #define SPINOR_OP_READ_1_2_2_DTR_4B     0xbe
  96 #define SPINOR_OP_READ_1_4_4_DTR_4B     0xee
  97
  98 /* Used for SST flashes only. */
  99 #define SPINOR_OP_BP            0x02    /* Byte program */
 100 #define SPINOR_OP_WRDI          0x04    /* Write disable */
 101 #define SPINOR_OP_AAI_WP        0xad    /* Auto address increment word program */
 102
 103 /* Used for S3AN flashes only */
 104 #define SPINOR_OP_XSE           0x50    /* Sector erase */
 105 #define SPINOR_OP_XPP           0x82    /* Page program */
 106 #define SPINOR_OP_XRDSR         0xd7    /* Read status register */
 107
 108 #define XSR_PAGESIZE            BIT(0)  /* Page size in Po2 or Linear */
 109 #define XSR_RDY                 BIT(7)  /* Ready */
 110
 111
 112 /* Used for Macronix and Winbond flashes. */
 113 #define SPINOR_OP_EN4B          0xb7    /* Enter 4-byte mode */
 114 #define SPINOR_OP_EX4B          0xe9    /* Exit 4-byte mode */
 115
 116 /* Used for Spansion flashes only. */
 117 #define SPINOR_OP_BRWR          0x17    /* Bank register write */
 118 #define SPINOR_OP_CLSR          0x30    /* Clear status register 1 */
 119
 120 /* Used for Micron flashes only. */
 121 #define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
 122 #define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */
 123
 124 /* Status Register bits. */
 125 #define SR_WIP                  BIT(0)  /* Write in progress */
 126 #define SR_WEL                  BIT(1)  /* Write enable latch */
 127 /* meaning of other SR_* bits may differ between vendors */
 128 #define SR_BP0                  BIT(2)  /* Block protect 0 */
 129 #define SR_BP1                  BIT(3)  /* Block protect 1 */
 130 #define SR_BP2                  BIT(4)  /* Block protect 2 */
 131 #define SR_TB_BIT5              BIT(5)  /* Top/Bottom protect */
 132 #define SR_TB_BIT6              BIT(6)  /* Top/Bottom protect */
 133 #define SR_SRWD                 BIT(7)  /* SR write protect */
 134 /* Spansion/Cypress specific status bits */
 135 #define SR_E_ERR                BIT(5)
 136 #define SR_P_ERR                BIT(6)
 137
 138 #define SR1_QUAD_EN_BIT6        BIT(6)
 139
 140 /* Enhanced Volatile Configuration Register bits */
 141 #define EVCR_QUAD_EN_MICRON     BIT(7)  /* Micron Quad I/O */
 142
 143 /* Flag Status Register bits */
 144 #define FSR_READY               BIT(7)  /* Device status, 0 = Busy, 1 = Ready */
 145 #define FSR_E_ERR               BIT(5)  /* Erase operation status */
 146 #define FSR_P_ERR               BIT(4)  /* Program operation status */
 147 #define FSR_PT_ERR              BIT(1)  /* Protection error bit */
 148
 149 /* Status Register 2 bits. */
 150 #define SR2_QUAD_EN_BIT1        BIT(1)
 151 #define SR2_QUAD_EN_BIT7        BIT(7)
 152
 153 /* Supported SPI protocols */
 154 #define SNOR_PROTO_INST_MASK    GENMASK(23, 16)
 155 #define SNOR_PROTO_INST_SHIFT   16
 156 #define SNOR_PROTO_INST(_nbits) \
 157         ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
 158          SNOR_PROTO_INST_MASK)
 159
 160 #define SNOR_PROTO_ADDR_MASK    GENMASK(15, 8)
 161 #define SNOR_PROTO_ADDR_SHIFT   8
 162 #define SNOR_PROTO_ADDR(_nbits) \
 163         ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
 164          SNOR_PROTO_ADDR_MASK)
 165
 166 #define SNOR_PROTO_DATA_MASK    GENMASK(7, 0)
 167 #define SNOR_PROTO_DATA_SHIFT   0
 168 #define SNOR_PROTO_DATA(_nbits) \
 169         ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
 170          SNOR_PROTO_DATA_MASK)
 171
 172 #define SNOR_PROTO_IS_DTR       BIT(24) /* Double Transfer Rate */
 173
 174 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)   \
 175         (SNOR_PROTO_INST(_inst_nbits) |                         \
 176          SNOR_PROTO_ADDR(_addr_nbits) |                         \
 177          SNOR_PROTO_DATA(_data_nbits))
 178 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits)   \
 179         (SNOR_PROTO_IS_DTR |                                    \
 180          SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
 181
 182 enum spi_nor_protocol {
 183         SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
 184         SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
 185         SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
 186         SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
 187         SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
 188         SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
 189         SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
 190         SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
 191         SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
 192         SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
 193
 194         SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
 195         SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
 196         SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
 197         SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
 198 };
 199
 200 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
 201 {
 202         return !!(proto & SNOR_PROTO_IS_DTR);
 203 }
 204
 205 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
 206 {
 207         return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
 208                 SNOR_PROTO_INST_SHIFT;
 209 }
 210
 211 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
 212 {
 213         return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
 214                 SNOR_PROTO_ADDR_SHIFT;
 215 }
 216
 217 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
 218 {
 219         return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
 220                 SNOR_PROTO_DATA_SHIFT;
 221 }
 222
 223 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
 224 {
 225         return spi_nor_get_protocol_data_nbits(proto);
 226 }
 227
 228 enum spi_nor_option_flags {
 229         SNOR_F_USE_FSR          = BIT(0),
 230         SNOR_F_HAS_SR_TB        = BIT(1),
 231         SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
 232         SNOR_F_READY_XSR_RDY    = BIT(3),
 233         SNOR_F_USE_CLSR         = BIT(4),
 234         SNOR_F_BROKEN_RESET     = BIT(5),
 235         SNOR_F_4B_OPCODES       = BIT(6),
 236         SNOR_F_HAS_4BAIT        = BIT(7),
 237         SNOR_F_HAS_LOCK         = BIT(8),
 238         SNOR_F_HAS_16BIT_SR     = BIT(9),
 239         SNOR_F_NO_READ_CR       = BIT(10),
 240         SNOR_F_HAS_SR_TB_BIT6   = BIT(11),
 241
 242 };
 243
 244 /**
 245  * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
 246  * @size:               the size of the sector/block erased by the erase type.
 247  *                      JEDEC JESD216B imposes erase sizes to be a power of 2.
 248  * @size_shift:         @size is a power of 2, the shift is stored in
 249  *                      @size_shift.
 250  * @size_mask:          the size mask based on @size_shift.
 251  * @opcode:             the SPI command op code to erase the sector/block.
 252  * @idx:                Erase Type index as sorted in the Basic Flash Parameter
 253  *                      Table. It will be used to synchronize the supported
 254  *                      Erase Types with the ones identified in the SFDP
 255  *                      optional tables.
 256  */
 257 struct spi_nor_erase_type {
 258         u32     size;
 259         u32     size_shift;
 260         u32     size_mask;
 261         u8      opcode;
 262         u8      idx;
 263 };
 264
 265 /**
 266  * struct spi_nor_erase_command - Used for non-uniform erases
 267  * The structure is used to describe a list of erase commands to be executed
 268  * once we validate that the erase can be performed. The elements in the list
 269  * are run-length encoded.
 270  * @list:               for inclusion into the list of erase commands.
 271  * @count:              how many times the same erase command should be
 272  *                      consecutively used.
 273  * @size:               the size of the sector/block erased by the command.
 274  * @opcode:             the SPI command op code to erase the sector/block.
 275  */
 276 struct spi_nor_erase_command {
 277         struct list_head        list;
 278         u32                     count;
 279         u32                     size;
 280         u8                      opcode;
 281 };
 282
 283 /**
 284  * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region
 285  * @offset:             the offset in the data array of erase region start.
 286  *                      LSB bits are used as a bitmask encoding flags to
 287  *                      determine if this region is overlaid, if this region is
 288  *                      the last in the SPI NOR flash memory and to indicate
 289  *                      all the supported erase commands inside this region.
 290  *                      The erase types are sorted in ascending order with the
 291  *                      smallest Erase Type size being at BIT(0).
 292  * @size:               the size of the region in bytes.
 293  */
 294 struct spi_nor_erase_region {
 295         u64             offset;
 296         u64             size;
 297 };
 298
 299 #define SNOR_ERASE_TYPE_MAX     4
 300 #define SNOR_ERASE_TYPE_MASK    GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0)
 301
 302 #define SNOR_LAST_REGION        BIT(4)
 303 #define SNOR_OVERLAID_REGION    BIT(5)
 304
 305 #define SNOR_ERASE_FLAGS_MAX    6
 306 #define SNOR_ERASE_FLAGS_MASK   GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0)
 307
 308 /**
 309  * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map
 310  * @regions:            array of erase regions. The regions are consecutive in
 311  *                      address space. Walking through the regions is done
 312  *                      incrementally.
 313  * @uniform_region:     a pre-allocated erase region for SPI NOR with a uniform
 314  *                      sector size (legacy implementation).
 315  * @erase_type:         an array of erase types shared by all the regions.
 316  *                      The erase types are sorted in ascending order, with the
 317  *                      smallest Erase Type size being the first member in the
 318  *                      erase_type array.
 319  * @uniform_erase_type: bitmask encoding erase types that can erase the
 320  *                      entire memory. This member is completed at init by
 321  *                      uniform and non-uniform SPI NOR flash memories if they
 322  *                      support at least one erase type that can erase the
 323  *                      entire memory.
 324  */
 325 struct spi_nor_erase_map {
 326         struct spi_nor_erase_region     *regions;
 327         struct spi_nor_erase_region     uniform_region;
 328         struct spi_nor_erase_type       erase_type[SNOR_ERASE_TYPE_MAX];
 329         u8                              uniform_erase_type;
 330 };
 331
 332 /**
 333  * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
 334  * supported by the SPI controller (bus master).
 335  * @mask:               the bitmask listing all the supported hw capabilies
 336  */
 337 struct spi_nor_hwcaps {
 338         u32     mask;
 339 };
 340
 341 /*
 342  *(Fast) Read capabilities.
 343  * MUST be ordered by priority: the higher bit position, the higher priority.
 344  * As a matter of performances, it is relevant to use Octal SPI protocols first,
 345  * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
 346  * (Slow) Read.
 347  */
 348 #define SNOR_HWCAPS_READ_MASK           GENMASK(14, 0)
 349 #define SNOR_HWCAPS_READ                BIT(0)
 350 #define SNOR_HWCAPS_READ_FAST           BIT(1)
 351 #define SNOR_HWCAPS_READ_1_1_1_DTR      BIT(2)
 352
 353 #define SNOR_HWCAPS_READ_DUAL           GENMASK(6, 3)
 354 #define SNOR_HWCAPS_READ_1_1_2          BIT(3)
 355 #define SNOR_HWCAPS_READ_1_2_2          BIT(4)
 356 #define SNOR_HWCAPS_READ_2_2_2          BIT(5)
 357 #define SNOR_HWCAPS_READ_1_2_2_DTR      BIT(6)
 358
 359 #define SNOR_HWCAPS_READ_QUAD           GENMASK(10, 7)
 360 #define SNOR_HWCAPS_READ_1_1_4          BIT(7)
 361 #define SNOR_HWCAPS_READ_1_4_4          BIT(8)
 362 #define SNOR_HWCAPS_READ_4_4_4          BIT(9)
 363 #define SNOR_HWCAPS_READ_1_4_4_DTR      BIT(10)
 364
 365 #define SNOR_HWCAPS_READ_OCTAL          GENMASK(14, 11)
 366 #define SNOR_HWCAPS_READ_1_1_8          BIT(11)
 367 #define SNOR_HWCAPS_READ_1_8_8          BIT(12)
 368 #define SNOR_HWCAPS_READ_8_8_8          BIT(13)
 369 #define SNOR_HWCAPS_READ_1_8_8_DTR      BIT(14)
 370
 371 /*
 372  * Page Program capabilities.
 373  * MUST be ordered by priority: the higher bit position, the higher priority.
 374  * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the
 375  * legacy SPI 1-1-1 protocol.
 376  * Note that Dual Page Programs are not supported because there is no existing
 377  * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
 378  * implements such commands.
 379  */
 380 #define SNOR_HWCAPS_PP_MASK     GENMASK(22, 16)
 381 #define SNOR_HWCAPS_PP          BIT(16)
 382
 383 #define SNOR_HWCAPS_PP_QUAD     GENMASK(19, 17)
 384 #define SNOR_HWCAPS_PP_1_1_4    BIT(17)
 385 #define SNOR_HWCAPS_PP_1_4_4    BIT(18)
 386 #define SNOR_HWCAPS_PP_4_4_4    BIT(19)
 387
 388 #define SNOR_HWCAPS_PP_OCTAL    GENMASK(22, 20)
 389 #define SNOR_HWCAPS_PP_1_1_8    BIT(20)
 390 #define SNOR_HWCAPS_PP_1_8_8    BIT(21)
 391 #define SNOR_HWCAPS_PP_8_8_8    BIT(22)
 392
 393 #define SNOR_HWCAPS_X_X_X       (SNOR_HWCAPS_READ_2_2_2 |       \
 394                                  SNOR_HWCAPS_READ_4_4_4 |       \
 395                                  SNOR_HWCAPS_READ_8_8_8 |       \
 396                                  SNOR_HWCAPS_PP_4_4_4 |         \
 397                                  SNOR_HWCAPS_PP_8_8_8)
 398
 399 #define SNOR_HWCAPS_DTR         (SNOR_HWCAPS_READ_1_1_1_DTR |   \
 400                                  SNOR_HWCAPS_READ_1_2_2_DTR |   \
 401                                  SNOR_HWCAPS_READ_1_4_4_DTR |   \
 402                                  SNOR_HWCAPS_READ_1_8_8_DTR)
 403
 404 #define SNOR_HWCAPS_ALL         (SNOR_HWCAPS_READ_MASK |        \
 405                                  SNOR_HWCAPS_PP_MASK)
 406
 407 struct spi_nor_read_command {
 408         u8                      num_mode_clocks;
 409         u8                      num_wait_states;
 410         u8                      opcode;
 411         enum spi_nor_protocol   proto;
 412 };
 413
 414 struct spi_nor_pp_command {
 415         u8                      opcode;
 416         enum spi_nor_protocol   proto;
 417 };
 418
 419 enum spi_nor_read_command_index {
 420         SNOR_CMD_READ,
 421         SNOR_CMD_READ_FAST,
 422         SNOR_CMD_READ_1_1_1_DTR,
 423
 424         /* Dual SPI */
 425         SNOR_CMD_READ_1_1_2,
 426         SNOR_CMD_READ_1_2_2,
 427         SNOR_CMD_READ_2_2_2,
 428         SNOR_CMD_READ_1_2_2_DTR,
 429
 430         /* Quad SPI */
 431         SNOR_CMD_READ_1_1_4,
 432         SNOR_CMD_READ_1_4_4,
 433         SNOR_CMD_READ_4_4_4,
 434         SNOR_CMD_READ_1_4_4_DTR,
 435
 436         /* Octal SPI */
 437         SNOR_CMD_READ_1_1_8,
 438         SNOR_CMD_READ_1_8_8,
 439         SNOR_CMD_READ_8_8_8,
 440         SNOR_CMD_READ_1_8_8_DTR,
 441
 442         SNOR_CMD_READ_MAX
 443 };
 444
 445 enum spi_nor_pp_command_index {
 446         SNOR_CMD_PP,
 447
 448         /* Quad SPI */
 449         SNOR_CMD_PP_1_1_4,
 450         SNOR_CMD_PP_1_4_4,
 451         SNOR_CMD_PP_4_4_4,
 452
 453         /* Octal SPI */
 454         SNOR_CMD_PP_1_1_8,
 455         SNOR_CMD_PP_1_8_8,
 456         SNOR_CMD_PP_8_8_8,
 457
 458         SNOR_CMD_PP_MAX
 459 };
 460
 461 /* Forward declaration that will be used in 'struct spi_nor_flash_parameter' */
 462 struct spi_nor;
 463
 464 /**
 465  * struct spi_nor_controller_ops - SPI NOR controller driver specific
 466  *                                 operations.
 467  * @prepare:            [OPTIONAL] do some preparations for the
 468  *                      read/write/erase/lock/unlock operations.
 469  * @unprepare:          [OPTIONAL] do some post work after the
 470  *                      read/write/erase/lock/unlock operations.
 471  * @read_reg:           read out the register.
 472  * @write_reg:          write data to the register.
 473  * @read:               read data from the SPI NOR.
 474  * @write:              write data to the SPI NOR.
 475  * @erase:              erase a sector of the SPI NOR at the offset @offs; if
 476  *                      not provided by the driver, spi-nor will send the erase
 477  *                      opcode via write_reg().
 478  */
 479 struct spi_nor_controller_ops {
 480         int (*prepare)(struct spi_nor *nor);
 481         void (*unprepare)(struct spi_nor *nor);
 482         int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len);
 483         int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf,
 484                          size_t len);
 485
 486         ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf);
 487         ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len,
 488                          const u8 *buf);
 489         int (*erase)(struct spi_nor *nor, loff_t offs);
 490 };
 491
 492 /**
 493  * struct spi_nor_locking_ops - SPI NOR locking methods
 494  * @lock:       lock a region of the SPI NOR.
 495  * @unlock:     unlock a region of the SPI NOR.
 496  * @is_locked:  check if a region of the SPI NOR is completely locked
 497  */
 498 struct spi_nor_locking_ops {
 499         int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 500         int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 501         int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 502 };
 503
 504 /**
 505  * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings.
 506  * Includes legacy flash parameters and settings that can be overwritten
 507  * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216
 508  * Serial Flash Discoverable Parameters (SFDP) tables.
 509  *
 510  * @size:               the flash memory density in bytes.
 511  * @page_size:          the page size of the SPI NOR flash memory.
 512  * @hwcaps:             describes the read and page program hardware
 513  *                      capabilities.
 514  * @reads:              read capabilities ordered by priority: the higher index
 515  *                      in the array, the higher priority.
 516  * @page_programs:      page program capabilities ordered by priority: the
 517  *                      higher index in the array, the higher priority.
 518  * @erase_map:          the erase map parsed from the SFDP Sector Map Parameter
 519  *                      Table.
 520  * @quad_enable:        enables SPI NOR quad mode.
 521  * @set_4byte:          puts the SPI NOR in 4 byte addressing mode.
 522  * @convert_addr:       converts an absolute address into something the flash
 523  *                      will understand. Particularly useful when pagesize is
 524  *                      not a power-of-2.
 525  * @setup:              configures the SPI NOR memory. Useful for SPI NOR
 526  *                      flashes that have peculiarities to the SPI NOR standard
 527  *                      e.g. different opcodes, specific address calculation,
 528  *                      page size, etc.
 529  * @locking_ops:        SPI NOR locking methods.
 530  */
 531 struct spi_nor_flash_parameter {
 532         u64                             size;
 533         u32                             page_size;
 534
 535         struct spi_nor_hwcaps           hwcaps;
 536         struct spi_nor_read_command     reads[SNOR_CMD_READ_MAX];
 537         struct spi_nor_pp_command       page_programs[SNOR_CMD_PP_MAX];
 538
 539         struct spi_nor_erase_map        erase_map;
 540
 541         int (*quad_enable)(struct spi_nor *nor);
 542         int (*set_4byte)(struct spi_nor *nor, bool enable);
 543         u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
 544         int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
 545
 546         const struct spi_nor_locking_ops *locking_ops;
 547 };
 548
 549 /**
 550  * struct flash_info - Forward declaration of a structure used internally by
 551  *                     spi_nor_scan()
 552  */
 553 struct flash_info;
 554
 555 /**
 556  * struct spi_nor - Structure for defining a the SPI NOR layer
 557  * @mtd:                point to a mtd_info structure
 558  * @lock:               the lock for the read/write/erase/lock/unlock operations
 559  * @dev:                point to a spi device, or a spi nor controller device.
 560  * @spimem:             point to the spi mem device
 561  * @bouncebuf:          bounce buffer used when the buffer passed by the MTD
 562  *                      layer is not DMA-able
 563  * @bouncebuf_size:     size of the bounce buffer
 564  * @info:               spi-nor part JDEC MFR id and other info
 565  * @page_size:          the page size of the SPI NOR
 566  * @addr_width:         number of address bytes
 567  * @erase_opcode:       the opcode for erasing a sector
 568  * @read_opcode:        the read opcode
 569  * @read_dummy:         the dummy needed by the read operation
 570  * @program_opcode:     the program opcode
 571  * @sst_write_second:   used by the SST write operation
 572  * @flags:              flag options for the current SPI-NOR (SNOR_F_*)
 573  * @read_proto:         the SPI protocol for read operations
 574  * @write_proto:        the SPI protocol for write operations
 575  * @reg_proto           the SPI protocol for read_reg/write_reg/erase operations
 576  * @controller_ops:     SPI NOR controller driver specific operations.
 577  * @params:             [FLASH-SPECIFIC] SPI-NOR flash parameters and settings.
 578  *                      The structure includes legacy flash parameters and
 579  *                      settings that can be overwritten by the spi_nor_fixups
 580  *                      hooks, or dynamically when parsing the SFDP tables.
 581  * @priv:               the private data
 582  */
 583 struct spi_nor {
 584         struct mtd_info         mtd;
 585         struct mutex            lock;
 586         struct device           *dev;
 587         struct spi_mem          *spimem;
 588         u8                      *bouncebuf;
 589         size_t                  bouncebuf_size;
 590         const struct flash_info *info;
 591         u32                     page_size;
 592         u8                      addr_width;
 593         u8                      erase_opcode;
 594         u8                      read_opcode;
 595         u8                      read_dummy;
 596         u8                      program_opcode;
 597         enum spi_nor_protocol   read_proto;
 598         enum spi_nor_protocol   write_proto;
 599         enum spi_nor_protocol   reg_proto;
 600         bool                    sst_write_second;
 601         u32                     flags;
 602
 603         const struct spi_nor_controller_ops *controller_ops;
 604
 605         struct spi_nor_flash_parameter params;
 606
 607         void *priv;
 608 };
 609
 610 static u64 __maybe_unused
 611 spi_nor_region_is_last(const struct spi_nor_erase_region *region)
 612 {
 613         return region->offset & SNOR_LAST_REGION;
 614 }
 615
 616 static u64 __maybe_unused
 617 spi_nor_region_end(const struct spi_nor_erase_region *region)
 618 {
 619         return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size;
 620 }
 621
 622 static void __maybe_unused
 623 spi_nor_region_mark_end(struct spi_nor_erase_region *region)
 624 {
 625         region->offset |= SNOR_LAST_REGION;
 626 }
 627
 628 static void __maybe_unused
 629 spi_nor_region_mark_overlay(struct spi_nor_erase_region *region)
 630 {
 631         region->offset |= SNOR_OVERLAID_REGION;
 632 }
 633
 634 static bool __maybe_unused spi_nor_has_uniform_erase(const struct spi_nor *nor)
 635 {
 636         return !!nor->params.erase_map.uniform_erase_type;
 637 }
 638
 639 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
 640                                           struct device_node *np)
 641 {
 642         mtd_set_of_node(&nor->mtd, np);
 643 }
 644
 645 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
 646 {
 647         return mtd_get_of_node(&nor->mtd);
 648 }
 649
 650 /**
 651  * spi_nor_scan() - scan the SPI NOR
 652  * @nor:        the spi_nor structure
 653  * @name:       the chip type name
 654  * @hwcaps:     the hardware capabilities supported by the controller driver
 655  *
 656  * The drivers can use this fuction to scan the SPI NOR.
 657  * In the scanning, it will try to get all the necessary information to
 658  * fill the mtd_info{} and the spi_nor{}.
 659  *
 660  * The chip type name can be provided through the @name parameter.
 661  *
 662  * Return: 0 for success, others for failure.
 663  */
 664 int spi_nor_scan(struct spi_nor *nor, const char *name,
 665                  const struct spi_nor_hwcaps *hwcaps);
 666
 667 /**
 668  * spi_nor_restore_addr_mode() - restore the status of SPI NOR
 669  * @nor:        the spi_nor structure
 670  */
 671 void spi_nor_restore(struct spi_nor *nor);
 672
 673 #endif