include/soc/fsl/qe/immap_qe.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * QUICC Engine (QE) Internal Memory Map.
   4  * The Internal Memory Map for devices with QE on them. This
   5  * is the superset of all QE devices (8360, etc.).
   6
   7  * Copyright (C) 2006. Freescale Semiconductor, Inc. All rights reserved.
   8  *
   9  * Authors:     Shlomi Gridish <gridish@freescale.com>
  10  *              Li Yang <leoli@freescale.com>
  11  */
  12 #ifndef _ASM_POWERPC_IMMAP_QE_H
  13 #define _ASM_POWERPC_IMMAP_QE_H
  14 #ifdef __KERNEL__
  15
  16 #include <linux/kernel.h>
  17 #include <asm/io.h>
  18
  19 #define QE_IMMAP_SIZE   (1024 * 1024)   /* 1MB from 1MB+IMMR */
  20
  21 /* QE I-RAM */
  22 struct qe_iram {
  23         __be32  iadd;           /* I-RAM Address Register */
  24         __be32  idata;          /* I-RAM Data Register */
  25         u8      res0[0x04];
  26         __be32  iready;         /* I-RAM Ready Register */
  27         u8      res1[0x70];
  28 } __attribute__ ((packed));
  29
  30 /* QE Interrupt Controller */
  31 struct qe_ic_regs {
  32         __be32  qicr;
  33         __be32  qivec;
  34         __be32  qripnr;
  35         __be32  qipnr;
  36         __be32  qipxcc;
  37         __be32  qipycc;
  38         __be32  qipwcc;
  39         __be32  qipzcc;
  40         __be32  qimr;
  41         __be32  qrimr;
  42         __be32  qicnr;
  43         u8      res0[0x4];
  44         __be32  qiprta;
  45         __be32  qiprtb;
  46         u8      res1[0x4];
  47         __be32  qricr;
  48         u8      res2[0x20];
  49         __be32  qhivec;
  50         u8      res3[0x1C];
  51 } __attribute__ ((packed));
  52
  53 /* Communications Processor */
  54 struct cp_qe {
  55         __be32  cecr;           /* QE command register */
  56         __be32  ceccr;          /* QE controller configuration register */
  57         __be32  cecdr;          /* QE command data register */
  58         u8      res0[0xA];
  59         __be16  ceter;          /* QE timer event register */
  60         u8      res1[0x2];
  61         __be16  cetmr;          /* QE timers mask register */
  62         __be32  cetscr;         /* QE time-stamp timer control register */
  63         __be32  cetsr1;         /* QE time-stamp register 1 */
  64         __be32  cetsr2;         /* QE time-stamp register 2 */
  65         u8      res2[0x8];
  66         __be32  cevter;         /* QE virtual tasks event register */
  67         __be32  cevtmr;         /* QE virtual tasks mask register */
  68         __be16  cercr;          /* QE RAM control register */
  69         u8      res3[0x2];
  70         u8      res4[0x24];
  71         __be16  ceexe1;         /* QE external request 1 event register */
  72         u8      res5[0x2];
  73         __be16  ceexm1;         /* QE external request 1 mask register */
  74         u8      res6[0x2];
  75         __be16  ceexe2;         /* QE external request 2 event register */
  76         u8      res7[0x2];
  77         __be16  ceexm2;         /* QE external request 2 mask register */
  78         u8      res8[0x2];
  79         __be16  ceexe3;         /* QE external request 3 event register */
  80         u8      res9[0x2];
  81         __be16  ceexm3;         /* QE external request 3 mask register */
  82         u8      res10[0x2];
  83         __be16  ceexe4;         /* QE external request 4 event register */
  84         u8      res11[0x2];
  85         __be16  ceexm4;         /* QE external request 4 mask register */
  86         u8      res12[0x3A];
  87         __be32  ceurnr;         /* QE microcode revision number register */
  88         u8      res13[0x244];
  89 } __attribute__ ((packed));
  90
  91 /* QE Multiplexer */
  92 struct qe_mux {
  93         __be32  cmxgcr;         /* CMX general clock route register */
  94         __be32  cmxsi1cr_l;     /* CMX SI1 clock route low register */
  95         __be32  cmxsi1cr_h;     /* CMX SI1 clock route high register */
  96         __be32  cmxsi1syr;      /* CMX SI1 SYNC route register */
  97         __be32  cmxucr[4];      /* CMX UCCx clock route registers */
  98         __be32  cmxupcr;        /* CMX UPC clock route register */
  99         u8      res0[0x1C];
 100 } __attribute__ ((packed));
 101
 102 /* QE Timers */
 103 struct qe_timers {
 104         u8      gtcfr1;         /* Timer 1 and Timer 2 global config register*/
 105         u8      res0[0x3];
 106         u8      gtcfr2;         /* Timer 3 and timer 4 global config register*/
 107         u8      res1[0xB];
 108         __be16  gtmdr1;         /* Timer 1 mode register */
 109         __be16  gtmdr2;         /* Timer 2 mode register */
 110         __be16  gtrfr1;         /* Timer 1 reference register */
 111         __be16  gtrfr2;         /* Timer 2 reference register */
 112         __be16  gtcpr1;         /* Timer 1 capture register */
 113         __be16  gtcpr2;         /* Timer 2 capture register */
 114         __be16  gtcnr1;         /* Timer 1 counter */
 115         __be16  gtcnr2;         /* Timer 2 counter */
 116         __be16  gtmdr3;         /* Timer 3 mode register */
 117         __be16  gtmdr4;         /* Timer 4 mode register */
 118         __be16  gtrfr3;         /* Timer 3 reference register */
 119         __be16  gtrfr4;         /* Timer 4 reference register */
 120         __be16  gtcpr3;         /* Timer 3 capture register */
 121         __be16  gtcpr4;         /* Timer 4 capture register */
 122         __be16  gtcnr3;         /* Timer 3 counter */
 123         __be16  gtcnr4;         /* Timer 4 counter */
 124         __be16  gtevr1;         /* Timer 1 event register */
 125         __be16  gtevr2;         /* Timer 2 event register */
 126         __be16  gtevr3;         /* Timer 3 event register */
 127         __be16  gtevr4;         /* Timer 4 event register */
 128         __be16  gtps;           /* Timer 1 prescale register */
 129         u8 res2[0x46];
 130 } __attribute__ ((packed));
 131
 132 /* BRG */
 133 struct qe_brg {
 134         __be32  brgc[16];       /* BRG configuration registers */
 135         u8      res0[0x40];
 136 } __attribute__ ((packed));
 137
 138 /* SPI */
 139 struct spi {
 140         u8      res0[0x20];
 141         __be32  spmode;         /* SPI mode register */
 142         u8      res1[0x2];
 143         u8      spie;           /* SPI event register */
 144         u8      res2[0x1];
 145         u8      res3[0x2];
 146         u8      spim;           /* SPI mask register */
 147         u8      res4[0x1];
 148         u8      res5[0x1];
 149         u8      spcom;          /* SPI command register */
 150         u8      res6[0x2];
 151         __be32  spitd;          /* SPI transmit data register (cpu mode) */
 152         __be32  spird;          /* SPI receive data register (cpu mode) */
 153         u8      res7[0x8];
 154 } __attribute__ ((packed));
 155
 156 /* SI */
 157 struct si1 {
 158         __be16  sixmr1[4];      /* SI1 TDMx (x = A B C D) mode register */
 159         u8      siglmr1_h;      /* SI1 global mode register high */
 160         u8      res0[0x1];
 161         u8      sicmdr1_h;      /* SI1 command register high */
 162         u8      res2[0x1];
 163         u8      sistr1_h;       /* SI1 status register high */
 164         u8      res3[0x1];
 165         __be16  sirsr1_h;       /* SI1 RAM shadow address register high */
 166         u8      sitarc1;        /* SI1 RAM counter Tx TDMA */
 167         u8      sitbrc1;        /* SI1 RAM counter Tx TDMB */
 168         u8      sitcrc1;        /* SI1 RAM counter Tx TDMC */
 169         u8      sitdrc1;        /* SI1 RAM counter Tx TDMD */
 170         u8      sirarc1;        /* SI1 RAM counter Rx TDMA */
 171         u8      sirbrc1;        /* SI1 RAM counter Rx TDMB */
 172         u8      sircrc1;        /* SI1 RAM counter Rx TDMC */
 173         u8      sirdrc1;        /* SI1 RAM counter Rx TDMD */
 174         u8      res4[0x8];
 175         __be16  siemr1;         /* SI1 TDME mode register 16 bits */
 176         __be16  sifmr1;         /* SI1 TDMF mode register 16 bits */
 177         __be16  sigmr1;         /* SI1 TDMG mode register 16 bits */
 178         __be16  sihmr1;         /* SI1 TDMH mode register 16 bits */
 179         u8      siglmg1_l;      /* SI1 global mode register low 8 bits */
 180         u8      res5[0x1];
 181         u8      sicmdr1_l;      /* SI1 command register low 8 bits */
 182         u8      res6[0x1];
 183         u8      sistr1_l;       /* SI1 status register low 8 bits */
 184         u8      res7[0x1];
 185         __be16  sirsr1_l;       /* SI1 RAM shadow address register low 16 bits*/
 186         u8      siterc1;        /* SI1 RAM counter Tx TDME 8 bits */
 187         u8      sitfrc1;        /* SI1 RAM counter Tx TDMF 8 bits */
 188         u8      sitgrc1;        /* SI1 RAM counter Tx TDMG 8 bits */
 189         u8      sithrc1;        /* SI1 RAM counter Tx TDMH 8 bits */
 190         u8      sirerc1;        /* SI1 RAM counter Rx TDME 8 bits */
 191         u8      sirfrc1;        /* SI1 RAM counter Rx TDMF 8 bits */
 192         u8      sirgrc1;        /* SI1 RAM counter Rx TDMG 8 bits */
 193         u8      sirhrc1;        /* SI1 RAM counter Rx TDMH 8 bits */
 194         u8      res8[0x8];
 195         __be32  siml1;          /* SI1 multiframe limit register */
 196         u8      siedm1;         /* SI1 extended diagnostic mode register */
 197         u8      res9[0xBB];
 198 } __attribute__ ((packed));
 199
 200 /* SI Routing Tables */
 201 struct sir {
 202         u8      tx[0x400];
 203         u8      rx[0x400];
 204         u8      res0[0x800];
 205 } __attribute__ ((packed));
 206
 207 /* USB Controller */
 208 struct qe_usb_ctlr {
 209         u8      usb_usmod;
 210         u8      usb_usadr;
 211         u8      usb_uscom;
 212         u8      res1[1];
 213         __be16  usb_usep[4];
 214         u8      res2[4];
 215         __be16  usb_usber;
 216         u8      res3[2];
 217         __be16  usb_usbmr;
 218         u8      res4[1];
 219         u8      usb_usbs;
 220         __be16  usb_ussft;
 221         u8      res5[2];
 222         __be16  usb_usfrn;
 223         u8      res6[0x22];
 224 } __attribute__ ((packed));
 225
 226 /* MCC */
 227 struct qe_mcc {
 228         __be32  mcce;           /* MCC event register */
 229         __be32  mccm;           /* MCC mask register */
 230         __be32  mccf;           /* MCC configuration register */
 231         __be32  merl;           /* MCC emergency request level register */
 232         u8      res0[0xF0];
 233 } __attribute__ ((packed));
 234
 235 /* QE UCC Slow */
 236 struct ucc_slow {
 237         __be32  gumr_l;         /* UCCx general mode register (low) */
 238         __be32  gumr_h;         /* UCCx general mode register (high) */
 239         __be16  upsmr;          /* UCCx protocol-specific mode register */
 240         u8      res0[0x2];
 241         __be16  utodr;          /* UCCx transmit on demand register */
 242         __be16  udsr;           /* UCCx data synchronization register */
 243         __be16  ucce;           /* UCCx event register */
 244         u8      res1[0x2];
 245         __be16  uccm;           /* UCCx mask register */
 246         u8      res2[0x1];
 247         u8      uccs;           /* UCCx status register */
 248         u8      res3[0x24];
 249         __be16  utpt;
 250         u8      res4[0x52];
 251         u8      guemr;          /* UCC general extended mode register */
 252 } __attribute__ ((packed));
 253
 254 /* QE UCC Fast */
 255 struct ucc_fast {
 256         __be32  gumr;           /* UCCx general mode register */
 257         __be32  upsmr;          /* UCCx protocol-specific mode register */
 258         __be16  utodr;          /* UCCx transmit on demand register */
 259         u8      res0[0x2];
 260         __be16  udsr;           /* UCCx data synchronization register */
 261         u8      res1[0x2];
 262         __be32  ucce;           /* UCCx event register */
 263         __be32  uccm;           /* UCCx mask register */
 264         u8      uccs;           /* UCCx status register */
 265         u8      res2[0x7];
 266         __be32  urfb;           /* UCC receive FIFO base */
 267         __be16  urfs;           /* UCC receive FIFO size */
 268         u8      res3[0x2];
 269         __be16  urfet;          /* UCC receive FIFO emergency threshold */
 270         __be16  urfset;         /* UCC receive FIFO special emergency
 271                                    threshold */
 272         __be32  utfb;           /* UCC transmit FIFO base */
 273         __be16  utfs;           /* UCC transmit FIFO size */
 274         u8      res4[0x2];
 275         __be16  utfet;          /* UCC transmit FIFO emergency threshold */
 276         u8      res5[0x2];
 277         __be16  utftt;          /* UCC transmit FIFO transmit threshold */
 278         u8      res6[0x2];
 279         __be16  utpt;           /* UCC transmit polling timer */
 280         u8      res7[0x2];
 281         __be32  urtry;          /* UCC retry counter register */
 282         u8      res8[0x4C];
 283         u8      guemr;          /* UCC general extended mode register */
 284 } __attribute__ ((packed));
 285
 286 struct ucc {
 287         union {
 288                 struct  ucc_slow slow;
 289                 struct  ucc_fast fast;
 290                 u8      res[0x200];     /* UCC blocks are 512 bytes each */
 291         };
 292 } __attribute__ ((packed));
 293
 294 /* MultiPHY UTOPIA POS Controllers (UPC) */
 295 struct upc {
 296         __be32  upgcr;          /* UTOPIA/POS general configuration register */
 297         __be32  uplpa;          /* UTOPIA/POS last PHY address */
 298         __be32  uphec;          /* ATM HEC register */
 299         __be32  upuc;           /* UTOPIA/POS UCC configuration */
 300         __be32  updc1;          /* UTOPIA/POS device 1 configuration */
 301         __be32  updc2;          /* UTOPIA/POS device 2 configuration */
 302         __be32  updc3;          /* UTOPIA/POS device 3 configuration */
 303         __be32  updc4;          /* UTOPIA/POS device 4 configuration */
 304         __be32  upstpa;         /* UTOPIA/POS STPA threshold */
 305         u8      res0[0xC];
 306         __be32  updrs1_h;       /* UTOPIA/POS device 1 rate select */
 307         __be32  updrs1_l;       /* UTOPIA/POS device 1 rate select */
 308         __be32  updrs2_h;       /* UTOPIA/POS device 2 rate select */
 309         __be32  updrs2_l;       /* UTOPIA/POS device 2 rate select */
 310         __be32  updrs3_h;       /* UTOPIA/POS device 3 rate select */
 311         __be32  updrs3_l;       /* UTOPIA/POS device 3 rate select */
 312         __be32  updrs4_h;       /* UTOPIA/POS device 4 rate select */
 313         __be32  updrs4_l;       /* UTOPIA/POS device 4 rate select */
 314         __be32  updrp1;         /* UTOPIA/POS device 1 receive priority low */
 315         __be32  updrp2;         /* UTOPIA/POS device 2 receive priority low */
 316         __be32  updrp3;         /* UTOPIA/POS device 3 receive priority low */
 317         __be32  updrp4;         /* UTOPIA/POS device 4 receive priority low */
 318         __be32  upde1;          /* UTOPIA/POS device 1 event */
 319         __be32  upde2;          /* UTOPIA/POS device 2 event */
 320         __be32  upde3;          /* UTOPIA/POS device 3 event */
 321         __be32  upde4;          /* UTOPIA/POS device 4 event */
 322         __be16  uprp1;
 323         __be16  uprp2;
 324         __be16  uprp3;
 325         __be16  uprp4;
 326         u8      res1[0x8];
 327         __be16  uptirr1_0;      /* Device 1 transmit internal rate 0 */
 328         __be16  uptirr1_1;      /* Device 1 transmit internal rate 1 */
 329         __be16  uptirr1_2;      /* Device 1 transmit internal rate 2 */
 330         __be16  uptirr1_3;      /* Device 1 transmit internal rate 3 */
 331         __be16  uptirr2_0;      /* Device 2 transmit internal rate 0 */
 332         __be16  uptirr2_1;      /* Device 2 transmit internal rate 1 */
 333         __be16  uptirr2_2;      /* Device 2 transmit internal rate 2 */
 334         __be16  uptirr2_3;      /* Device 2 transmit internal rate 3 */
 335         __be16  uptirr3_0;      /* Device 3 transmit internal rate 0 */
 336         __be16  uptirr3_1;      /* Device 3 transmit internal rate 1 */
 337         __be16  uptirr3_2;      /* Device 3 transmit internal rate 2 */
 338         __be16  uptirr3_3;      /* Device 3 transmit internal rate 3 */
 339         __be16  uptirr4_0;      /* Device 4 transmit internal rate 0 */
 340         __be16  uptirr4_1;      /* Device 4 transmit internal rate 1 */
 341         __be16  uptirr4_2;      /* Device 4 transmit internal rate 2 */
 342         __be16  uptirr4_3;      /* Device 4 transmit internal rate 3 */
 343         __be32  uper1;          /* Device 1 port enable register */
 344         __be32  uper2;          /* Device 2 port enable register */
 345         __be32  uper3;          /* Device 3 port enable register */
 346         __be32  uper4;          /* Device 4 port enable register */
 347         u8      res2[0x150];
 348 } __attribute__ ((packed));
 349
 350 /* SDMA */
 351 struct sdma {
 352         __be32  sdsr;           /* Serial DMA status register */
 353         __be32  sdmr;           /* Serial DMA mode register */
 354         __be32  sdtr1;          /* SDMA system bus threshold register */
 355         __be32  sdtr2;          /* SDMA secondary bus threshold register */
 356         __be32  sdhy1;          /* SDMA system bus hysteresis register */
 357         __be32  sdhy2;          /* SDMA secondary bus hysteresis register */
 358         __be32  sdta1;          /* SDMA system bus address register */
 359         __be32  sdta2;          /* SDMA secondary bus address register */
 360         __be32  sdtm1;          /* SDMA system bus MSNUM register */
 361         __be32  sdtm2;          /* SDMA secondary bus MSNUM register */
 362         u8      res0[0x10];
 363         __be32  sdaqr;          /* SDMA address bus qualify register */
 364         __be32  sdaqmr;         /* SDMA address bus qualify mask register */
 365         u8      res1[0x4];
 366         __be32  sdebcr;         /* SDMA CAM entries base register */
 367         u8      res2[0x38];
 368 } __attribute__ ((packed));
 369
 370 /* Debug Space */
 371 struct dbg {
 372         __be32  bpdcr;          /* Breakpoint debug command register */
 373         __be32  bpdsr;          /* Breakpoint debug status register */
 374         __be32  bpdmr;          /* Breakpoint debug mask register */
 375         __be32  bprmrr0;        /* Breakpoint request mode risc register 0 */
 376         __be32  bprmrr1;        /* Breakpoint request mode risc register 1 */
 377         u8      res0[0x8];
 378         __be32  bprmtr0;        /* Breakpoint request mode trb register 0 */
 379         __be32  bprmtr1;        /* Breakpoint request mode trb register 1 */
 380         u8      res1[0x8];
 381         __be32  bprmir;         /* Breakpoint request mode immediate register */
 382         __be32  bprmsr;         /* Breakpoint request mode serial register */
 383         __be32  bpemr;          /* Breakpoint exit mode register */
 384         u8      res2[0x48];
 385 } __attribute__ ((packed));
 386
 387 /*
 388  * RISC Special Registers (Trap and Breakpoint).  These are described in
 389  * the QE Developer's Handbook.
 390  */
 391 struct rsp {
 392         __be32 tibcr[16];       /* Trap/instruction breakpoint control regs */
 393         u8 res0[64];
 394         __be32 ibcr0;
 395         __be32 ibs0;
 396         __be32 ibcnr0;
 397         u8 res1[4];
 398         __be32 ibcr1;
 399         __be32 ibs1;
 400         __be32 ibcnr1;
 401         __be32 npcr;
 402         __be32 dbcr;
 403         __be32 dbar;
 404         __be32 dbamr;
 405         __be32 dbsr;
 406         __be32 dbcnr;
 407         u8 res2[12];
 408         __be32 dbdr_h;
 409         __be32 dbdr_l;
 410         __be32 dbdmr_h;
 411         __be32 dbdmr_l;
 412         __be32 bsr;
 413         __be32 bor;
 414         __be32 bior;
 415         u8 res3[4];
 416         __be32 iatr[4];
 417         __be32 eccr;            /* Exception control configuration register */
 418         __be32 eicr;
 419         u8 res4[0x100-0xf8];
 420 } __attribute__ ((packed));
 421
 422 struct qe_immap {
 423         struct qe_iram          iram;           /* I-RAM */
 424         struct qe_ic_regs       ic;             /* Interrupt Controller */
 425         struct cp_qe            cp;             /* Communications Processor */
 426         struct qe_mux           qmx;            /* QE Multiplexer */
 427         struct qe_timers        qet;            /* QE Timers */
 428         struct spi              spi[0x2];       /* spi */
 429         struct qe_mcc           mcc;            /* mcc */
 430         struct qe_brg           brg;            /* brg */
 431         struct qe_usb_ctlr      usb;            /* USB */
 432         struct si1              si1;            /* SI */
 433         u8                      res11[0x800];
 434         struct sir              sir;            /* SI Routing Tables */
 435         struct ucc              ucc1;           /* ucc1 */
 436         struct ucc              ucc3;           /* ucc3 */
 437         struct ucc              ucc5;           /* ucc5 */
 438         struct ucc              ucc7;           /* ucc7 */
 439         u8                      res12[0x600];
 440         struct upc              upc1;           /* MultiPHY UTOPIA POS Ctrlr 1*/
 441         struct ucc              ucc2;           /* ucc2 */
 442         struct ucc              ucc4;           /* ucc4 */
 443         struct ucc              ucc6;           /* ucc6 */
 444         struct ucc              ucc8;           /* ucc8 */
 445         u8                      res13[0x600];
 446         struct upc              upc2;           /* MultiPHY UTOPIA POS Ctrlr 2*/
 447         struct sdma             sdma;           /* SDMA */
 448         struct dbg              dbg;            /* 0x104080 - 0x1040FF
 449                                                    Debug Space */
 450         struct rsp              rsp[0x2];       /* 0x104100 - 0x1042FF
 451                                                    RISC Special Registers
 452                                                    (Trap and Breakpoint) */
 453         u8                      res14[0x300];   /* 0x104300 - 0x1045FF */
 454         u8                      res15[0x3A00];  /* 0x104600 - 0x107FFF */
 455         u8                      res16[0x8000];  /* 0x108000 - 0x110000 */
 456         u8                      muram[0xC000];  /* 0x110000 - 0x11C000
 457                                                    Multi-user RAM */
 458         u8                      res17[0x24000]; /* 0x11C000 - 0x140000 */
 459         u8                      res18[0xC0000]; /* 0x140000 - 0x200000 */
 460 } __attribute__ ((packed));
 461
 462 extern struct qe_immap __iomem *qe_immr;
 463
 464 #endif /* __KERNEL__ */
 465 #endif /* _ASM_POWERPC_IMMAP_QE_H */