include/soc/nps/common.h

   1 /*
   2  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef SOC_NPS_COMMON_H
  34 #define SOC_NPS_COMMON_H
  35
  36 #ifdef CONFIG_SMP
  37 #define NPS_IPI_IRQ                                     5
  38 #endif
  39
  40 #define NPS_HOST_REG_BASE                       0xF6000000
  41
  42 #define NPS_MSU_BLKID                           0x018
  43
  44 #define CTOP_INST_RSPI_GIC_0_R12                0x3C56117E
  45 #define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST      0x5B60
  46 #define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM      0x00010422
  47
  48 #ifndef __ASSEMBLY__
  49
  50 /* In order to increase compilation test coverage */
  51 #ifdef CONFIG_ARC
  52 static inline void nps_ack_gic(void)
  53 {
  54         __asm__ __volatile__ (
  55         "       .word %0\n"
  56         :
  57         : "i"(CTOP_INST_RSPI_GIC_0_R12)
  58         : "memory");
  59 }
  60 #else
  61 static inline void nps_ack_gic(void) { }
  62 #define write_aux_reg(r, v)
  63 #define read_aux_reg(r) 0
  64 #endif
  65
  66 /* CPU global ID */
  67 struct global_id {
  68         union {
  69                 struct {
  70 #ifdef CONFIG_EZNPS_MTM_EXT
  71                         u32 __reserved:20, cluster:4, core:4, thread:4;
  72 #else
  73                         u32 __reserved:24, cluster:4, core:4;
  74 #endif
  75                 };
  76                 u32 value;
  77         };
  78 };
  79
  80 /*
  81  * Convert logical to physical CPU IDs
  82  *
  83  * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
  84  * Now quad of logical clusters id's are adjacent physically,
  85  * and not like the id's physically came with each cluster.
  86  * Below table is 4x4 mesh of core clusters as it layout on chip.
  87  * Cluster ids are in format: logical (physical)
  88  *
  89  *    -----------------   ------------------
  90  * 3 |  5 (3)   7 (7)  | | 13 (11)   15 (15)|
  91  *
  92  * 2 |  4 (2)   6 (6)  | | 12 (10)   14 (14)|
  93  *    -----------------   ------------------
  94  * 1 |  1 (1)   3 (5)  | |  9  (9)   11 (13)|
  95  *
  96  * 0 |  0 (0)   2 (4)  | |  8  (8)   10 (12)|
  97  *    -----------------   ------------------
  98  *       0       1            2        3
  99  */
 100 static inline int nps_cluster_logic_to_phys(int cluster)
 101 {
 102 #ifdef __arc__
 103          __asm__ __volatile__(
 104         "       mov r3,%0\n"
 105         "       .short %1\n"
 106         "       .word %2\n"
 107         "       mov %0,r3\n"
 108         : "+r"(cluster)
 109         : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
 110           "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
 111         : "r3");
 112 #endif
 113
 114         return cluster;
 115 }
 116
 117 #define NPS_CPU_TO_CLUSTER_NUM(cpu) \
 118         ({ struct global_id gid; gid.value = cpu; \
 119                 nps_cluster_logic_to_phys(gid.cluster); })
 120
 121 struct nps_host_reg_address {
 122         union {
 123                 struct {
 124                         u32 base:8, cl_x:4, cl_y:4,
 125                         blkid:6, reg:8, __reserved:2;
 126                 };
 127                 u32 value;
 128         };
 129 };
 130
 131 struct nps_host_reg_address_non_cl {
 132         union {
 133                 struct {
 134                         u32 base:7, blkid:11, reg:12, __reserved:2;
 135                 };
 136                 u32 value;
 137         };
 138 };
 139
 140 static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
 141 {
 142         struct nps_host_reg_address_non_cl reg_address;
 143
 144         reg_address.value = NPS_HOST_REG_BASE;
 145         reg_address.blkid = blkid;
 146         reg_address.reg = reg;
 147
 148         return (void *)reg_address.value;
 149 }
 150
 151 static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
 152 {
 153         struct nps_host_reg_address reg_address;
 154         u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
 155
 156         reg_address.value = NPS_HOST_REG_BASE;
 157         reg_address.cl_x  = (cl >> 2) & 0x3;
 158         reg_address.cl_y  = cl & 0x3;
 159         reg_address.blkid = blkid;
 160         reg_address.reg   = reg;
 161
 162         return (void *)reg_address.value;
 163 }
 164 #endif /* __ASSEMBLY__ */
 165
 166 #endif /* SOC_NPS_COMMON_H */