arch/microblaze/include/asm/mmu.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
   4  * Copyright (C) 2008-2009 PetaLogix
   5  * Copyright (C) 2006 Atmark Techno, Inc.
   6  */
   7
   8 #ifndef _ASM_MICROBLAZE_MMU_H
   9 #define _ASM_MICROBLAZE_MMU_H
  10
  11 # ifndef CONFIG_MMU
  12 #  include <asm-generic/mmu.h>
  13 # else /* CONFIG_MMU */
  14 #  ifdef __KERNEL__
  15 #   ifndef __ASSEMBLY__
  16
  17 /* Default "unsigned long" context */
  18 typedef unsigned long mm_context_t;
  19
  20 /* Hardware Page Table Entry */
  21 typedef struct _PTE {
  22         unsigned long    v:1;   /* Entry is valid */
  23         unsigned long vsid:24;  /* Virtual segment identifier */
  24         unsigned long    h:1;   /* Hash algorithm indicator */
  25         unsigned long  api:6;   /* Abbreviated page index */
  26         unsigned long  rpn:20;  /* Real (physical) page number */
  27         unsigned long     :3;   /* Unused */
  28         unsigned long    r:1;   /* Referenced */
  29         unsigned long    c:1;   /* Changed */
  30         unsigned long    w:1;   /* Write-thru cache mode */
  31         unsigned long    i:1;   /* Cache inhibited */
  32         unsigned long    m:1;   /* Memory coherence */
  33         unsigned long    g:1;   /* Guarded */
  34         unsigned long     :1;   /* Unused */
  35         unsigned long   pp:2;   /* Page protection */
  36 } PTE;
  37
  38 /* Values for PP (assumes Ks=0, Kp=1) */
  39 #  define PP_RWXX       0 /* Supervisor read/write, User none */
  40 #  define PP_RWRX       1 /* Supervisor read/write, User read */
  41 #  define PP_RWRW       2 /* Supervisor read/write, User read/write */
  42 #  define PP_RXRX       3 /* Supervisor read,       User read */
  43
  44 /* Segment Register */
  45 typedef struct _SEGREG {
  46         unsigned long    t:1;   /* Normal or I/O  type */
  47         unsigned long   ks:1;   /* Supervisor 'key' (normally 0) */
  48         unsigned long   kp:1;   /* User 'key' (normally 1) */
  49         unsigned long    n:1;   /* No-execute */
  50         unsigned long     :4;   /* Unused */
  51         unsigned long vsid:24;  /* Virtual Segment Identifier */
  52 } SEGREG;
  53
  54 extern void _tlbie(unsigned long va);   /* invalidate a TLB entry */
  55 extern void _tlbia(void);               /* invalidate all TLB entries */
  56
  57 /*
  58  * tlb_skip size stores actual number skipped TLBs from TLB0 - every directy TLB
  59  * mapping has to increase tlb_skip size.
  60  */
  61 extern u32 tlb_skip;
  62 #   endif /* __ASSEMBLY__ */
  63
  64 /*
  65  * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
  66  * instruction and data sides share a unified, 64-entry, semi-associative
  67  * TLB which is maintained totally under software control. In addition, the
  68  * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative
  69  * TLB which serves as a first level to the shared TLB. These two TLBs are
  70  * known as the UTLB and ITLB, respectively.
  71  */
  72
  73 #  define MICROBLAZE_TLB_SIZE 64
  74
  75 /* For cases when you want to skip some TLB entries */
  76 #  define MICROBLAZE_TLB_SKIP 0
  77
  78 /* Use the last TLB for temporary access to LMB */
  79 #  define MICROBLAZE_LMB_TLB_ID 63
  80
  81 /*
  82  * TLB entries are defined by a "high" tag portion and a "low" data
  83  * portion. The data portion is 32-bits.
  84  *
  85  * TLB entries are managed entirely under software control by reading,
  86  * writing, and searching using the MTS and MFS instructions.
  87  */
  88
  89 #  define TLB_LO                1
  90 #  define TLB_HI                0
  91 #  define TLB_DATA              TLB_LO
  92 #  define TLB_TAG               TLB_HI
  93
  94 /* Tag portion */
  95 #  define TLB_EPN_MASK          0xFFFFFC00 /* Effective Page Number */
  96 #  define TLB_PAGESZ_MASK       0x00000380
  97 #  define TLB_PAGESZ(x)         (((x) & 0x7) << 7)
  98 #  define PAGESZ_1K             0
  99 #  define PAGESZ_4K             1
 100 #  define PAGESZ_16K            2
 101 #  define PAGESZ_64K            3
 102 #  define PAGESZ_256K           4
 103 #  define PAGESZ_1M             5
 104 #  define PAGESZ_4M             6
 105 #  define PAGESZ_16M            7
 106 #  define TLB_VALID             0x00000040 /* Entry is valid */
 107
 108 /* Data portion */
 109 #  define TLB_RPN_MASK          0xFFFFFC00 /* Real Page Number */
 110 #  define TLB_PERM_MASK         0x00000300
 111 #  define TLB_EX                0x00000200 /* Instruction execution allowed */
 112 #  define TLB_WR                0x00000100 /* Writes permitted */
 113 #  define TLB_ZSEL_MASK         0x000000F0
 114 #  define TLB_ZSEL(x)           (((x) & 0xF) << 4)
 115 #  define TLB_ATTR_MASK         0x0000000F
 116 #  define TLB_W                 0x00000008 /* Caching is write-through */
 117 #  define TLB_I                 0x00000004 /* Caching is inhibited */
 118 #  define TLB_M                 0x00000002 /* Memory is coherent */
 119 #  define TLB_G                 0x00000001 /* Memory is guarded from prefetch */
 120
 121 #  endif /* __KERNEL__ */
 122 # endif /* CONFIG_MMU */
 123 #endif /* _ASM_MICROBLAZE_MMU_H */