arch/microblaze/pci/pci-common.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Contains common pci routines for ALL ppc platform
   4  * (based on pci_32.c and pci_64.c)
   5  *
   6  * Port for PPC64 David Engebretsen, IBM Corp.
   7  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
   8  *
   9  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
  10  *   Rework, based on alpha PCI code.
  11  *
  12  * Common pmac/prep/chrp pci routines. -- Cort
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/pci.h>
  17 #include <linux/string.h>
  18 #include <linux/init.h>
  19 #include <linux/memblock.h>
  20 #include <linux/mm.h>
  21 #include <linux/shmem_fs.h>
  22 #include <linux/list.h>
  23 #include <linux/syscalls.h>
  24 #include <linux/irq.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/slab.h>
  27 #include <linux/of.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_irq.h>
  30 #include <linux/of_pci.h>
  31 #include <linux/export.h>
  32
  33 #include <asm/processor.h>
  34 #include <linux/io.h>
  35 #include <asm/pci-bridge.h>
  36 #include <asm/byteorder.h>
  37
  38 static DEFINE_SPINLOCK(hose_spinlock);
  39 LIST_HEAD(hose_list);
  40
  41 /* XXX kill that some day ... */
  42 static int global_phb_number;           /* Global phb counter */
  43
  44 /* ISA Memory physical address */
  45 resource_size_t isa_mem_base;
  46
  47 unsigned long isa_io_base;
  48 EXPORT_SYMBOL(isa_io_base);
  49
  50 static int pci_bus_count;
  51
  52 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
  53 {
  54         struct pci_controller *phb;
  55
  56         phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
  57         if (!phb)
  58                 return NULL;
  59         spin_lock(&hose_spinlock);
  60         phb->global_number = global_phb_number++;
  61         list_add_tail(&phb->list_node, &hose_list);
  62         spin_unlock(&hose_spinlock);
  63         phb->dn = dev;
  64         phb->is_dynamic = mem_init_done;
  65         return phb;
  66 }
  67
  68 void pcibios_free_controller(struct pci_controller *phb)
  69 {
  70         spin_lock(&hose_spinlock);
  71         list_del(&phb->list_node);
  72         spin_unlock(&hose_spinlock);
  73
  74         if (phb->is_dynamic)
  75                 kfree(phb);
  76 }
  77
  78 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
  79 {
  80         return resource_size(&hose->io_resource);
  81 }
  82
  83 int pcibios_vaddr_is_ioport(void __iomem *address)
  84 {
  85         int ret = 0;
  86         struct pci_controller *hose;
  87         resource_size_t size;
  88
  89         spin_lock(&hose_spinlock);
  90         list_for_each_entry(hose, &hose_list, list_node) {
  91                 size = pcibios_io_size(hose);
  92                 if (address >= hose->io_base_virt &&
  93                     address < (hose->io_base_virt + size)) {
  94                         ret = 1;
  95                         break;
  96                 }
  97         }
  98         spin_unlock(&hose_spinlock);
  99         return ret;
 100 }
 101
 102 unsigned long pci_address_to_pio(phys_addr_t address)
 103 {
 104         struct pci_controller *hose;
 105         resource_size_t size;
 106         unsigned long ret = ~0;
 107
 108         spin_lock(&hose_spinlock);
 109         list_for_each_entry(hose, &hose_list, list_node) {
 110                 size = pcibios_io_size(hose);
 111                 if (address >= hose->io_base_phys &&
 112                     address < (hose->io_base_phys + size)) {
 113                         unsigned long base =
 114                                 (unsigned long)hose->io_base_virt - _IO_BASE;
 115                         ret = base + (address - hose->io_base_phys);
 116                         break;
 117                 }
 118         }
 119         spin_unlock(&hose_spinlock);
 120
 121         return ret;
 122 }
 123 EXPORT_SYMBOL_GPL(pci_address_to_pio);
 124
 125 /* This routine is meant to be used early during boot, when the
 126  * PCI bus numbers have not yet been assigned, and you need to
 127  * issue PCI config cycles to an OF device.
 128  * It could also be used to "fix" RTAS config cycles if you want
 129  * to set pci_assign_all_buses to 1 and still use RTAS for PCI
 130  * config cycles.
 131  */
 132 struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
 133 {
 134         while (node) {
 135                 struct pci_controller *hose, *tmp;
 136                 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
 137                         if (hose->dn == node)
 138                                 return hose;
 139                 node = node->parent;
 140         }
 141         return NULL;
 142 }
 143
 144 void pcibios_set_master(struct pci_dev *dev)
 145 {
 146         /* No special bus mastering setup handling */
 147 }
 148
 149 /*
 150  * Platform support for /proc/bus/pci/X/Y mmap()s.
 151  */
 152
 153 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
 154 {
 155         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 156         resource_size_t ioaddr = pci_resource_start(pdev, bar);
 157
 158         if (!hose)
 159                 return -EINVAL;         /* should never happen */
 160
 161         /* Convert to an offset within this PCI controller */
 162         ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
 163
 164         vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
 165         return 0;
 166 }
 167
 168 /*
 169  * This one is used by /dev/mem and fbdev who have no clue about the
 170  * PCI device, it tries to find the PCI device first and calls the
 171  * above routine
 172  */
 173 pgprot_t pci_phys_mem_access_prot(struct file *file,
 174                                   unsigned long pfn,
 175                                   unsigned long size,
 176                                   pgprot_t prot)
 177 {
 178         struct pci_dev *pdev = NULL;
 179         struct resource *found = NULL;
 180         resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
 181         int i;
 182
 183         if (page_is_ram(pfn))
 184                 return prot;
 185
 186         prot = pgprot_noncached(prot);
 187         for_each_pci_dev(pdev) {
 188                 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 189                         struct resource *rp = &pdev->resource[i];
 190                         int flags = rp->flags;
 191
 192                         /* Active and same type? */
 193                         if ((flags & IORESOURCE_MEM) == 0)
 194                                 continue;
 195                         /* In the range of this resource? */
 196                         if (offset < (rp->start & PAGE_MASK) ||
 197                             offset > rp->end)
 198                                 continue;
 199                         found = rp;
 200                         break;
 201                 }
 202                 if (found)
 203                         break;
 204         }
 205         if (found) {
 206                 if (found->flags & IORESOURCE_PREFETCH)
 207                         prot = pgprot_noncached_wc(prot);
 208                 pci_dev_put(pdev);
 209         }
 210
 211         pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
 212                  (unsigned long long)offset, pgprot_val(prot));
 213
 214         return prot;
 215 }
 216
 217 /* This provides legacy IO read access on a bus */
 218 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
 219 {
 220         unsigned long offset;
 221         struct pci_controller *hose = pci_bus_to_host(bus);
 222         struct resource *rp = &hose->io_resource;
 223         void __iomem *addr;
 224
 225         /* Check if port can be supported by that bus. We only check
 226          * the ranges of the PHB though, not the bus itself as the rules
 227          * for forwarding legacy cycles down bridges are not our problem
 228          * here. So if the host bridge supports it, we do it.
 229          */
 230         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 231         offset += port;
 232
 233         if (!(rp->flags & IORESOURCE_IO))
 234                 return -ENXIO;
 235         if (offset < rp->start || (offset + size) > rp->end)
 236                 return -ENXIO;
 237         addr = hose->io_base_virt + port;
 238
 239         switch (size) {
 240         case 1:
 241                 *((u8 *)val) = in_8(addr);
 242                 return 1;
 243         case 2:
 244                 if (port & 1)
 245                         return -EINVAL;
 246                 *((u16 *)val) = in_le16(addr);
 247                 return 2;
 248         case 4:
 249                 if (port & 3)
 250                         return -EINVAL;
 251                 *((u32 *)val) = in_le32(addr);
 252                 return 4;
 253         }
 254         return -EINVAL;
 255 }
 256
 257 /* This provides legacy IO write access on a bus */
 258 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
 259 {
 260         unsigned long offset;
 261         struct pci_controller *hose = pci_bus_to_host(bus);
 262         struct resource *rp = &hose->io_resource;
 263         void __iomem *addr;
 264
 265         /* Check if port can be supported by that bus. We only check
 266          * the ranges of the PHB though, not the bus itself as the rules
 267          * for forwarding legacy cycles down bridges are not our problem
 268          * here. So if the host bridge supports it, we do it.
 269          */
 270         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 271         offset += port;
 272
 273         if (!(rp->flags & IORESOURCE_IO))
 274                 return -ENXIO;
 275         if (offset < rp->start || (offset + size) > rp->end)
 276                 return -ENXIO;
 277         addr = hose->io_base_virt + port;
 278
 279         /* WARNING: The generic code is idiotic. It gets passed a pointer
 280          * to what can be a 1, 2 or 4 byte quantity and always reads that
 281          * as a u32, which means that we have to correct the location of
 282          * the data read within those 32 bits for size 1 and 2
 283          */
 284         switch (size) {
 285         case 1:
 286                 out_8(addr, val >> 24);
 287                 return 1;
 288         case 2:
 289                 if (port & 1)
 290                         return -EINVAL;
 291                 out_le16(addr, val >> 16);
 292                 return 2;
 293         case 4:
 294                 if (port & 3)
 295                         return -EINVAL;
 296                 out_le32(addr, val);
 297                 return 4;
 298         }
 299         return -EINVAL;
 300 }
 301
 302 /* This provides legacy IO or memory mmap access on a bus */
 303 int pci_mmap_legacy_page_range(struct pci_bus *bus,
 304                                struct vm_area_struct *vma,
 305                                enum pci_mmap_state mmap_state)
 306 {
 307         struct pci_controller *hose = pci_bus_to_host(bus);
 308         resource_size_t offset =
 309                 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
 310         resource_size_t size = vma->vm_end - vma->vm_start;
 311         struct resource *rp;
 312
 313         pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
 314                  pci_domain_nr(bus), bus->number,
 315                  mmap_state == pci_mmap_mem ? "MEM" : "IO",
 316                  (unsigned long long)offset,
 317                  (unsigned long long)(offset + size - 1));
 318
 319         if (mmap_state == pci_mmap_mem) {
 320                 /* Hack alert !
 321                  *
 322                  * Because X is lame and can fail starting if it gets an error
 323                  * trying to mmap legacy_mem (instead of just moving on without
 324                  * legacy memory access) we fake it here by giving it anonymous
 325                  * memory, effectively behaving just like /dev/zero
 326                  */
 327                 if ((offset + size) > hose->isa_mem_size) {
 328 #ifdef CONFIG_MMU
 329                         pr_debug("Process %s (pid:%d) mapped non-existing PCI",
 330                                 current->comm, current->pid);
 331                         pr_debug("legacy memory for 0%04x:%02x\n",
 332                                 pci_domain_nr(bus), bus->number);
 333 #endif
 334                         if (vma->vm_flags & VM_SHARED)
 335                                 return shmem_zero_setup(vma);
 336                         return 0;
 337                 }
 338                 offset += hose->isa_mem_phys;
 339         } else {
 340                 unsigned long io_offset = (unsigned long)hose->io_base_virt -
 341                                                                 _IO_BASE;
 342                 unsigned long roffset = offset + io_offset;
 343                 rp = &hose->io_resource;
 344                 if (!(rp->flags & IORESOURCE_IO))
 345                         return -ENXIO;
 346                 if (roffset < rp->start || (roffset + size) > rp->end)
 347                         return -ENXIO;
 348                 offset += hose->io_base_phys;
 349         }
 350         pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
 351
 352         vma->vm_pgoff = offset >> PAGE_SHIFT;
 353         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 354         return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 355                                vma->vm_end - vma->vm_start,
 356                                vma->vm_page_prot);
 357 }
 358
 359 void pci_resource_to_user(const struct pci_dev *dev, int bar,
 360                           const struct resource *rsrc,
 361                           resource_size_t *start, resource_size_t *end)
 362 {
 363         struct pci_bus_region region;
 364
 365         if (rsrc->flags & IORESOURCE_IO) {
 366                 pcibios_resource_to_bus(dev->bus, &region,
 367                                         (struct resource *) rsrc);
 368                 *start = region.start;
 369                 *end = region.end;
 370                 return;
 371         }
 372
 373         /* We pass a CPU physical address to userland for MMIO instead of a
 374          * BAR value because X is lame and expects to be able to use that
 375          * to pass to /dev/mem!
 376          *
 377          * That means we may have 64-bit values where some apps only expect
 378          * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
 379          */
 380         *start = rsrc->start;
 381         *end = rsrc->end;
 382 }
 383
 384 /**
 385  * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
 386  * @hose: newly allocated pci_controller to be setup
 387  * @dev: device node of the host bridge
 388  * @primary: set if primary bus (32 bits only, soon to be deprecated)
 389  *
 390  * This function will parse the "ranges" property of a PCI host bridge device
 391  * node and setup the resource mapping of a pci controller based on its
 392  * content.
 393  *
 394  * Life would be boring if it wasn't for a few issues that we have to deal
 395  * with here:
 396  *
 397  *   - We can only cope with one IO space range and up to 3 Memory space
 398  *     ranges. However, some machines (thanks Apple !) tend to split their
 399  *     space into lots of small contiguous ranges. So we have to coalesce.
 400  *
 401  *   - We can only cope with all memory ranges having the same offset
 402  *     between CPU addresses and PCI addresses. Unfortunately, some bridges
 403  *     are setup for a large 1:1 mapping along with a small "window" which
 404  *     maps PCI address 0 to some arbitrary high address of the CPU space in
 405  *     order to give access to the ISA memory hole.
 406  *     The way out of here that I've chosen for now is to always set the
 407  *     offset based on the first resource found, then override it if we
 408  *     have a different offset and the previous was set by an ISA hole.
 409  *
 410  *   - Some busses have IO space not starting at 0, which causes trouble with
 411  *     the way we do our IO resource renumbering. The code somewhat deals with
 412  *     it for 64 bits but I would expect problems on 32 bits.
 413  *
 414  *   - Some 32 bits platforms such as 4xx can have physical space larger than
 415  *     32 bits so we need to use 64 bits values for the parsing
 416  */
 417 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 418                                   struct device_node *dev, int primary)
 419 {
 420         int memno = 0, isa_hole = -1;
 421         unsigned long long isa_mb = 0;
 422         struct resource *res;
 423         struct of_pci_range range;
 424         struct of_pci_range_parser parser;
 425
 426         pr_info("PCI host bridge %pOF %s ranges:\n",
 427                dev, primary ? "(primary)" : "");
 428
 429         /* Check for ranges property */
 430         if (of_pci_range_parser_init(&parser, dev))
 431                 return;
 432
 433         pr_debug("Parsing ranges property...\n");
 434         for_each_of_pci_range(&parser, &range) {
 435                 /* Read next ranges element */
 436
 437                 /* If we failed translation or got a zero-sized region
 438                  * (some FW try to feed us with non sensical zero sized regions
 439                  * such as power3 which look like some kind of attempt
 440                  * at exposing the VGA memory hole)
 441                  */
 442                 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
 443                         continue;
 444
 445                 /* Act based on address space type */
 446                 res = NULL;
 447                 switch (range.flags & IORESOURCE_TYPE_BITS) {
 448                 case IORESOURCE_IO:
 449                         pr_info("  IO 0x%016llx..0x%016llx -> 0x%016llx\n",
 450                                 range.cpu_addr, range.cpu_addr + range.size - 1,
 451                                 range.pci_addr);
 452
 453                         /* We support only one IO range */
 454                         if (hose->pci_io_size) {
 455                                 pr_info(" \\--> Skipped (too many) !\n");
 456                                 continue;
 457                         }
 458                         /* On 32 bits, limit I/O space to 16MB */
 459                         if (range.size > 0x01000000)
 460                                 range.size = 0x01000000;
 461
 462                         /* 32 bits needs to map IOs here */
 463                         hose->io_base_virt = ioremap(range.cpu_addr,
 464                                                 range.size);
 465
 466                         /* Expect trouble if pci_addr is not 0 */
 467                         if (primary)
 468                                 isa_io_base =
 469                                         (unsigned long)hose->io_base_virt;
 470                         /* pci_io_size and io_base_phys always represent IO
 471                          * space starting at 0 so we factor in pci_addr
 472                          */
 473                         hose->pci_io_size = range.pci_addr + range.size;
 474                         hose->io_base_phys = range.cpu_addr - range.pci_addr;
 475
 476                         /* Build resource */
 477                         res = &hose->io_resource;
 478                         range.cpu_addr = range.pci_addr;
 479
 480                         break;
 481                 case IORESOURCE_MEM:
 482                         pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
 483                                 range.cpu_addr, range.cpu_addr + range.size - 1,
 484                                 range.pci_addr,
 485                                 (range.flags & IORESOURCE_PREFETCH) ?
 486                                 "Prefetch" : "");
 487
 488                         /* We support only 3 memory ranges */
 489                         if (memno >= 3) {
 490                                 pr_info(" \\--> Skipped (too many) !\n");
 491                                 continue;
 492                         }
 493                         /* Handles ISA memory hole space here */
 494                         if (range.pci_addr == 0) {
 495                                 isa_mb = range.cpu_addr;
 496                                 isa_hole = memno;
 497                                 if (primary || isa_mem_base == 0)
 498                                         isa_mem_base = range.cpu_addr;
 499                                 hose->isa_mem_phys = range.cpu_addr;
 500                                 hose->isa_mem_size = range.size;
 501                         }
 502
 503                         /* We get the PCI/Mem offset from the first range or
 504                          * the, current one if the offset came from an ISA
 505                          * hole. If they don't match, bugger.
 506                          */
 507                         if (memno == 0 ||
 508                             (isa_hole >= 0 && range.pci_addr != 0 &&
 509                              hose->pci_mem_offset == isa_mb))
 510                                 hose->pci_mem_offset = range.cpu_addr -
 511                                                         range.pci_addr;
 512                         else if (range.pci_addr != 0 &&
 513                                  hose->pci_mem_offset != range.cpu_addr -
 514                                                         range.pci_addr) {
 515                                 pr_info(" \\--> Skipped (offset mismatch) !\n");
 516                                 continue;
 517                         }
 518
 519                         /* Build resource */
 520                         res = &hose->mem_resources[memno++];
 521                         break;
 522                 }
 523                 if (res != NULL) {
 524                         res->name = dev->full_name;
 525                         res->flags = range.flags;
 526                         res->start = range.cpu_addr;
 527                         res->end = range.cpu_addr + range.size - 1;
 528                         res->parent = res->child = res->sibling = NULL;
 529                 }
 530         }
 531
 532         /* If there's an ISA hole and the pci_mem_offset is -not- matching
 533          * the ISA hole offset, then we need to remove the ISA hole from
 534          * the resource list for that brige
 535          */
 536         if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
 537                 unsigned int next = isa_hole + 1;
 538                 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
 539                 if (next < memno)
 540                         memmove(&hose->mem_resources[isa_hole],
 541                                 &hose->mem_resources[next],
 542                                 sizeof(struct resource) * (memno - next));
 543                 hose->mem_resources[--memno].flags = 0;
 544         }
 545 }
 546
 547 /* Display the domain number in /proc */
 548 int pci_proc_domain(struct pci_bus *bus)
 549 {
 550         return pci_domain_nr(bus);
 551 }
 552
 553 /* This header fixup will do the resource fixup for all devices as they are
 554  * probed, but not for bridge ranges
 555  */
 556 static void pcibios_fixup_resources(struct pci_dev *dev)
 557 {
 558         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 559         int i;
 560
 561         if (!hose) {
 562                 pr_err("No host bridge for PCI dev %s !\n",
 563                        pci_name(dev));
 564                 return;
 565         }
 566         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 567                 struct resource *res = dev->resource + i;
 568                 if (!res->flags)
 569                         continue;
 570                 if (res->start == 0) {
 571                         pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
 572                                  pci_name(dev), i,
 573                                  (unsigned long long)res->start,
 574                                  (unsigned long long)res->end,
 575                                  (unsigned int)res->flags);
 576                         pr_debug("is unassigned\n");
 577                         res->end -= res->start;
 578                         res->start = 0;
 579                         res->flags |= IORESOURCE_UNSET;
 580                         continue;
 581                 }
 582
 583                 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
 584                          pci_name(dev), i,
 585                          (unsigned long long)res->start,
 586                          (unsigned long long)res->end,
 587                          (unsigned int)res->flags);
 588         }
 589 }
 590 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
 591
 592 int pcibios_add_device(struct pci_dev *dev)
 593 {
 594         dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
 595
 596         return 0;
 597 }
 598 EXPORT_SYMBOL(pcibios_add_device);
 599
 600 /*
 601  * Reparent resource children of pr that conflict with res
 602  * under res, and make res replace those children.
 603  */
 604 static int __init reparent_resources(struct resource *parent,
 605                                      struct resource *res)
 606 {
 607         struct resource *p, **pp;
 608         struct resource **firstpp = NULL;
 609
 610         for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
 611                 if (p->end < res->start)
 612                         continue;
 613                 if (res->end < p->start)
 614                         break;
 615                 if (p->start < res->start || p->end > res->end)
 616                         return -1;      /* not completely contained */
 617                 if (firstpp == NULL)
 618                         firstpp = pp;
 619         }
 620         if (firstpp == NULL)
 621                 return -1;      /* didn't find any conflicting entries? */
 622         res->parent = parent;
 623         res->child = *firstpp;
 624         res->sibling = *pp;
 625         *firstpp = res;
 626         *pp = NULL;
 627         for (p = res->child; p != NULL; p = p->sibling) {
 628                 p->parent = res;
 629                 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
 630                          p->name,
 631                          (unsigned long long)p->start,
 632                          (unsigned long long)p->end, res->name);
 633         }
 634         return 0;
 635 }
 636
 637 /*
 638  *  Handle resources of PCI devices.  If the world were perfect, we could
 639  *  just allocate all the resource regions and do nothing more.  It isn't.
 640  *  On the other hand, we cannot just re-allocate all devices, as it would
 641  *  require us to know lots of host bridge internals.  So we attempt to
 642  *  keep as much of the original configuration as possible, but tweak it
 643  *  when it's found to be wrong.
 644  *
 645  *  Known BIOS problems we have to work around:
 646  *      - I/O or memory regions not configured
 647  *      - regions configured, but not enabled in the command register
 648  *      - bogus I/O addresses above 64K used
 649  *      - expansion ROMs left enabled (this may sound harmless, but given
 650  *        the fact the PCI specs explicitly allow address decoders to be
 651  *        shared between expansion ROMs and other resource regions, it's
 652  *        at least dangerous)
 653  *
 654  *  Our solution:
 655  *      (1) Allocate resources for all buses behind PCI-to-PCI bridges.
 656  *          This gives us fixed barriers on where we can allocate.
 657  *      (2) Allocate resources for all enabled devices.  If there is
 658  *          a collision, just mark the resource as unallocated. Also
 659  *          disable expansion ROMs during this step.
 660  *      (3) Try to allocate resources for disabled devices.  If the
 661  *          resources were assigned correctly, everything goes well,
 662  *          if they weren't, they won't disturb allocation of other
 663  *          resources.
 664  *      (4) Assign new addresses to resources which were either
 665  *          not configured at all or misconfigured.  If explicitly
 666  *          requested by the user, configure expansion ROM address
 667  *          as well.
 668  */
 669
 670 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
 671 {
 672         struct pci_bus *b;
 673         int i;
 674         struct resource *res, *pr;
 675
 676         pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
 677                  pci_domain_nr(bus), bus->number);
 678
 679         pci_bus_for_each_resource(bus, res, i) {
 680                 if (!res || !res->flags
 681                     || res->start > res->end || res->parent)
 682                         continue;
 683                 if (bus->parent == NULL)
 684                         pr = (res->flags & IORESOURCE_IO) ?
 685                                 &ioport_resource : &iomem_resource;
 686                 else {
 687                         /* Don't bother with non-root busses when
 688                          * re-assigning all resources. We clear the
 689                          * resource flags as if they were colliding
 690                          * and as such ensure proper re-allocation
 691                          * later.
 692                          */
 693                         pr = pci_find_parent_resource(bus->self, res);
 694                         if (pr == res) {
 695                                 /* this happens when the generic PCI
 696                                  * code (wrongly) decides that this
 697                                  * bridge is transparent  -- paulus
 698                                  */
 699                                 continue;
 700                         }
 701                 }
 702
 703                 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
 704                          bus->self ? pci_name(bus->self) : "PHB",
 705                          bus->number, i,
 706                          (unsigned long long)res->start,
 707                          (unsigned long long)res->end);
 708                 pr_debug("[0x%x], parent %p (%s)\n",
 709                          (unsigned int)res->flags,
 710                          pr, (pr && pr->name) ? pr->name : "nil");
 711
 712                 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
 713                         struct pci_dev *dev = bus->self;
 714
 715                         if (request_resource(pr, res) == 0)
 716                                 continue;
 717                         /*
 718                          * Must be a conflict with an existing entry.
 719                          * Move that entry (or entries) under the
 720                          * bridge resource and try again.
 721                          */
 722                         if (reparent_resources(pr, res) == 0)
 723                                 continue;
 724
 725                         if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
 726                             pci_claim_bridge_resource(dev,
 727                                                  i + PCI_BRIDGE_RESOURCES) == 0)
 728                                 continue;
 729
 730                 }
 731                 pr_warn("PCI: Cannot allocate resource region ");
 732                 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
 733                 res->start = res->end = 0;
 734                 res->flags = 0;
 735         }
 736
 737         list_for_each_entry(b, &bus->children, node)
 738                 pcibios_allocate_bus_resources(b);
 739 }
 740
 741 static inline void alloc_resource(struct pci_dev *dev, int idx)
 742 {
 743         struct resource *pr, *r = &dev->resource[idx];
 744
 745         pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
 746                  pci_name(dev), idx,
 747                  (unsigned long long)r->start,
 748                  (unsigned long long)r->end,
 749                  (unsigned int)r->flags);
 750
 751         pr = pci_find_parent_resource(dev, r);
 752         if (!pr || (pr->flags & IORESOURCE_UNSET) ||
 753             request_resource(pr, r) < 0) {
 754                 pr_warn("PCI: Cannot allocate resource region %d ", idx);
 755                 pr_cont("of device %s, will remap\n", pci_name(dev));
 756                 if (pr)
 757                         pr_debug("PCI:  parent is %p: %016llx-%016llx [%x]\n",
 758                                  pr,
 759                                  (unsigned long long)pr->start,
 760                                  (unsigned long long)pr->end,
 761                                  (unsigned int)pr->flags);
 762                 /* We'll assign a new address later */
 763                 r->flags |= IORESOURCE_UNSET;
 764                 r->end -= r->start;
 765                 r->start = 0;
 766         }
 767 }
 768
 769 static void __init pcibios_allocate_resources(int pass)
 770 {
 771         struct pci_dev *dev = NULL;
 772         int idx, disabled;
 773         u16 command;
 774         struct resource *r;
 775
 776         for_each_pci_dev(dev) {
 777                 pci_read_config_word(dev, PCI_COMMAND, &command);
 778                 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
 779                         r = &dev->resource[idx];
 780                         if (r->parent)          /* Already allocated */
 781                                 continue;
 782                         if (!r->flags || (r->flags & IORESOURCE_UNSET))
 783                                 continue;       /* Not assigned at all */
 784                         /* We only allocate ROMs on pass 1 just in case they
 785                          * have been screwed up by firmware
 786                          */
 787                         if (idx == PCI_ROM_RESOURCE)
 788                                 disabled = 1;
 789                         if (r->flags & IORESOURCE_IO)
 790                                 disabled = !(command & PCI_COMMAND_IO);
 791                         else
 792                                 disabled = !(command & PCI_COMMAND_MEMORY);
 793                         if (pass == disabled)
 794                                 alloc_resource(dev, idx);
 795                 }
 796                 if (pass)
 797                         continue;
 798                 r = &dev->resource[PCI_ROM_RESOURCE];
 799                 if (r->flags) {
 800                         /* Turn the ROM off, leave the resource region,
 801                          * but keep it unregistered.
 802                          */
 803                         u32 reg;
 804                         pci_read_config_dword(dev, dev->rom_base_reg, &reg);
 805                         if (reg & PCI_ROM_ADDRESS_ENABLE) {
 806                                 pr_debug("PCI: Switching off ROM of %s\n",
 807                                          pci_name(dev));
 808                                 r->flags &= ~IORESOURCE_ROM_ENABLE;
 809                                 pci_write_config_dword(dev, dev->rom_base_reg,
 810                                                 reg & ~PCI_ROM_ADDRESS_ENABLE);
 811                         }
 812                 }
 813         }
 814 }
 815
 816 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
 817 {
 818         struct pci_controller *hose = pci_bus_to_host(bus);
 819         resource_size_t offset;
 820         struct resource *res, *pres;
 821         int i;
 822
 823         pr_debug("Reserving legacy ranges for domain %04x\n",
 824                                                         pci_domain_nr(bus));
 825
 826         /* Check for IO */
 827         if (!(hose->io_resource.flags & IORESOURCE_IO))
 828                 goto no_io;
 829         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 830         res = kzalloc(sizeof(struct resource), GFP_KERNEL);
 831         BUG_ON(res == NULL);
 832         res->name = "Legacy IO";
 833         res->flags = IORESOURCE_IO;
 834         res->start = offset;
 835         res->end = (offset + 0xfff) & 0xfffffffful;
 836         pr_debug("Candidate legacy IO: %pR\n", res);
 837         if (request_resource(&hose->io_resource, res)) {
 838                 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
 839                        pci_domain_nr(bus), bus->number, res);
 840                 kfree(res);
 841         }
 842
 843  no_io:
 844         /* Check for memory */
 845         offset = hose->pci_mem_offset;
 846         pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
 847         for (i = 0; i < 3; i++) {
 848                 pres = &hose->mem_resources[i];
 849                 if (!(pres->flags & IORESOURCE_MEM))
 850                         continue;
 851                 pr_debug("hose mem res: %pR\n", pres);
 852                 if ((pres->start - offset) <= 0xa0000 &&
 853                     (pres->end - offset) >= 0xbffff)
 854                         break;
 855         }
 856         if (i >= 3)
 857                 return;
 858         res = kzalloc(sizeof(struct resource), GFP_KERNEL);
 859         BUG_ON(res == NULL);
 860         res->name = "Legacy VGA memory";
 861         res->flags = IORESOURCE_MEM;
 862         res->start = 0xa0000 + offset;
 863         res->end = 0xbffff + offset;
 864         pr_debug("Candidate VGA memory: %pR\n", res);
 865         if (request_resource(pres, res)) {
 866                 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
 867                        pci_domain_nr(bus), bus->number, res);
 868                 kfree(res);
 869         }
 870 }
 871
 872 void __init pcibios_resource_survey(void)
 873 {
 874         struct pci_bus *b;
 875
 876         /* Allocate and assign resources. If we re-assign everything, then
 877          * we skip the allocate phase
 878          */
 879         list_for_each_entry(b, &pci_root_buses, node)
 880                 pcibios_allocate_bus_resources(b);
 881
 882         pcibios_allocate_resources(0);
 883         pcibios_allocate_resources(1);
 884
 885         /* Before we start assigning unassigned resource, we try to reserve
 886          * the low IO area and the VGA memory area if they intersect the
 887          * bus available resources to avoid allocating things on top of them
 888          */
 889         list_for_each_entry(b, &pci_root_buses, node)
 890                 pcibios_reserve_legacy_regions(b);
 891
 892         /* Now proceed to assigning things that were left unassigned */
 893         pr_debug("PCI: Assigning unassigned resources...\n");
 894         pci_assign_unassigned_resources();
 895 }
 896
 897 static void pcibios_setup_phb_resources(struct pci_controller *hose,
 898                                         struct list_head *resources)
 899 {
 900         unsigned long io_offset;
 901         struct resource *res;
 902         int i;
 903
 904         /* Hookup PHB IO resource */
 905         res = &hose->io_resource;
 906
 907         /* Fixup IO space offset */
 908         io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
 909         res->start = (res->start + io_offset) & 0xffffffffu;
 910         res->end = (res->end + io_offset) & 0xffffffffu;
 911
 912         if (!res->flags) {
 913                 pr_warn("PCI: I/O resource not set for host ");
 914                 pr_cont("bridge %pOF (domain %d)\n",
 915                         hose->dn, hose->global_number);
 916                 /* Workaround for lack of IO resource only on 32-bit */
 917                 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
 918                 res->end = res->start + IO_SPACE_LIMIT;
 919                 res->flags = IORESOURCE_IO;
 920         }
 921         pci_add_resource_offset(resources, res,
 922                 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
 923
 924         pr_debug("PCI: PHB IO resource    = %016llx-%016llx [%lx]\n",
 925                  (unsigned long long)res->start,
 926                  (unsigned long long)res->end,
 927                  (unsigned long)res->flags);
 928
 929         /* Hookup PHB Memory resources */
 930         for (i = 0; i < 3; ++i) {
 931                 res = &hose->mem_resources[i];
 932                 if (!res->flags) {
 933                         if (i > 0)
 934                                 continue;
 935                         pr_err("PCI: Memory resource 0 not set for ");
 936                         pr_cont("host bridge %pOF (domain %d)\n",
 937                                 hose->dn, hose->global_number);
 938
 939                         /* Workaround for lack of MEM resource only on 32-bit */
 940                         res->start = hose->pci_mem_offset;
 941                         res->end = (resource_size_t)-1LL;
 942                         res->flags = IORESOURCE_MEM;
 943
 944                 }
 945                 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
 946
 947                 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
 948                         i, (unsigned long long)res->start,
 949                         (unsigned long long)res->end,
 950                         (unsigned long)res->flags);
 951         }
 952
 953         pr_debug("PCI: PHB MEM offset     = %016llx\n",
 954                  (unsigned long long)hose->pci_mem_offset);
 955         pr_debug("PCI: PHB IO  offset     = %08lx\n",
 956                  (unsigned long)hose->io_base_virt - _IO_BASE);
 957 }
 958
 959 static void pcibios_scan_phb(struct pci_controller *hose)
 960 {
 961         LIST_HEAD(resources);
 962         struct pci_bus *bus;
 963         struct device_node *node = hose->dn;
 964
 965         pr_debug("PCI: Scanning PHB %pOF\n", node);
 966
 967         pcibios_setup_phb_resources(hose, &resources);
 968
 969         bus = pci_scan_root_bus(hose->parent, hose->first_busno,
 970                                 hose->ops, hose, &resources);
 971         if (bus == NULL) {
 972                 pr_err("Failed to create bus for PCI domain %04x\n",
 973                        hose->global_number);
 974                 pci_free_resource_list(&resources);
 975                 return;
 976         }
 977         bus->busn_res.start = hose->first_busno;
 978         hose->bus = bus;
 979
 980         hose->last_busno = bus->busn_res.end;
 981 }
 982
 983 static int __init pcibios_init(void)
 984 {
 985         struct pci_controller *hose, *tmp;
 986         int next_busno = 0;
 987
 988         pr_info("PCI: Probing PCI hardware\n");
 989
 990         /* Scan all of the recorded PCI controllers.  */
 991         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 992                 hose->last_busno = 0xff;
 993                 pcibios_scan_phb(hose);
 994                 if (next_busno <= hose->last_busno)
 995                         next_busno = hose->last_busno + 1;
 996         }
 997         pci_bus_count = next_busno;
 998
 999         /* Call common code to handle resource allocation */
1000         pcibios_resource_survey();
1001         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1002                 if (hose->bus)
1003                         pci_bus_add_devices(hose->bus);
1004         }
1005
1006         return 0;
1007 }
1008
1009 subsys_initcall(pcibios_init);
1010
1011 static struct pci_controller *pci_bus_to_hose(int bus)
1012 {
1013         struct pci_controller *hose, *tmp;
1014
1015         list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1016                 if (bus >= hose->first_busno && bus <= hose->last_busno)
1017                         return hose;
1018         return NULL;
1019 }
1020
1021 /* Provide information on locations of various I/O regions in physical
1022  * memory.  Do this on a per-card basis so that we choose the right
1023  * root bridge.
1024  * Note that the returned IO or memory base is a physical address
1025  */
1026
1027 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1028 {
1029         struct pci_controller *hose;
1030         long result = -EOPNOTSUPP;
1031
1032         hose = pci_bus_to_hose(bus);
1033         if (!hose)
1034                 return -ENODEV;
1035
1036         switch (which) {
1037         case IOBASE_BRIDGE_NUMBER:
1038                 return (long)hose->first_busno;
1039         case IOBASE_MEMORY:
1040                 return (long)hose->pci_mem_offset;
1041         case IOBASE_IO:
1042                 return (long)hose->io_base_phys;
1043         case IOBASE_ISA_IO:
1044                 return (long)isa_io_base;
1045         case IOBASE_ISA_MEM:
1046                 return (long)isa_mem_base;
1047         }
1048
1049         return result;
1050 }
1051
1052 /*
1053  * Null PCI config access functions, for the case when we can't
1054  * find a hose.
1055  */
1056 #define NULL_PCI_OP(rw, size, type)                                     \
1057 static int                                                              \
1058 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val)    \
1059 {                                                                       \
1060         return PCIBIOS_DEVICE_NOT_FOUND;                                \
1061 }
1062
1063 static int
1064 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1065                  int len, u32 *val)
1066 {
1067         return PCIBIOS_DEVICE_NOT_FOUND;
1068 }
1069
1070 static int
1071 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1072                   int len, u32 val)
1073 {
1074         return PCIBIOS_DEVICE_NOT_FOUND;
1075 }
1076
1077 static struct pci_ops null_pci_ops = {
1078         .read = null_read_config,
1079         .write = null_write_config,
1080 };
1081
1082 /*
1083  * These functions are used early on before PCI scanning is done
1084  * and all of the pci_dev and pci_bus structures have been created.
1085  */
1086 static struct pci_bus *
1087 fake_pci_bus(struct pci_controller *hose, int busnr)
1088 {
1089         static struct pci_bus bus;
1090
1091         if (!hose)
1092                 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1093
1094         bus.number = busnr;
1095         bus.sysdata = hose;
1096         bus.ops = hose ? hose->ops : &null_pci_ops;
1097         return &bus;
1098 }
1099
1100 #define EARLY_PCI_OP(rw, size, type)                                    \
1101 int early_##rw##_config_##size(struct pci_controller *hose, int bus,    \
1102                                int devfn, int offset, type value)       \
1103 {                                                                       \
1104         return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus),    \
1105                                             devfn, offset, value);      \
1106 }
1107
1108 EARLY_PCI_OP(read, byte, u8 *)
1109 EARLY_PCI_OP(read, word, u16 *)
1110 EARLY_PCI_OP(read, dword, u32 *)
1111 EARLY_PCI_OP(write, byte, u8)
1112 EARLY_PCI_OP(write, word, u16)
1113 EARLY_PCI_OP(write, dword, u32)
1114
1115 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1116                           int cap)
1117 {
1118         return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1119 }