arch/x86/include/asm/processor.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_X86_PROCESSOR_H
   3 #define _ASM_X86_PROCESSOR_H
   4
   5 #include <asm/processor-flags.h>
   6
   7 /* Forward declaration, a strange C thing */
   8 struct task_struct;
   9 struct mm_struct;
  10 struct io_bitmap;
  11 struct vm86;
  12
  13 #include <asm/math_emu.h>
  14 #include <asm/segment.h>
  15 #include <asm/types.h>
  16 #include <uapi/asm/sigcontext.h>
  17 #include <asm/current.h>
  18 #include <asm/cpufeatures.h>
  19 #include <asm/page.h>
  20 #include <asm/pgtable_types.h>
  21 #include <asm/percpu.h>
  22 #include <asm/msr.h>
  23 #include <asm/desc_defs.h>
  24 #include <asm/nops.h>
  25 #include <asm/special_insns.h>
  26 #include <asm/fpu/types.h>
  27 #include <asm/unwind_hints.h>
  28 #include <asm/vmxfeatures.h>
  29 #include <asm/vdso/processor.h>
  30
  31 #include <linux/personality.h>
  32 #include <linux/cache.h>
  33 #include <linux/threads.h>
  34 #include <linux/math64.h>
  35 #include <linux/err.h>
  36 #include <linux/irqflags.h>
  37 #include <linux/mem_encrypt.h>
  38
  39 /*
  40  * We handle most unaligned accesses in hardware.  On the other hand
  41  * unaligned DMA can be quite expensive on some Nehalem processors.
  42  *
  43  * Based on this we disable the IP header alignment in network drivers.
  44  */
  45 #define NET_IP_ALIGN    0
  46
  47 #define HBP_NUM 4
  48
  49 /*
  50  * These alignment constraints are for performance in the vSMP case,
  51  * but in the task_struct case we must also meet hardware imposed
  52  * alignment requirements of the FPU state:
  53  */
  54 #ifdef CONFIG_X86_VSMP
  55 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  56 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  57 #else
  58 # define ARCH_MIN_TASKALIGN             __alignof__(union fpregs_state)
  59 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  60 #endif
  61
  62 enum tlb_infos {
  63         ENTRIES,
  64         NR_INFO
  65 };
  66
  67 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
  68 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
  69 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
  70 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
  71 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
  72 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
  73 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
  74
  75 /*
  76  *  CPU type and hardware bug flags. Kept separately for each CPU.
  77  *  Members of this structure are referenced in head_32.S, so think twice
  78  *  before touching them. [mj]
  79  */
  80
  81 struct cpuinfo_x86 {
  82         __u8                    x86;            /* CPU family */
  83         __u8                    x86_vendor;     /* CPU vendor */
  84         __u8                    x86_model;
  85         __u8                    x86_stepping;
  86 #ifdef CONFIG_X86_64
  87         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  88         int                     x86_tlbsize;
  89 #endif
  90 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
  91         __u32                   vmx_capability[NVMXINTS];
  92 #endif
  93         __u8                    x86_virt_bits;
  94         __u8                    x86_phys_bits;
  95         /* CPUID returned core id bits: */
  96         __u8                    x86_coreid_bits;
  97         __u8                    cu_id;
  98         /* Max extended CPUID function supported: */
  99         __u32                   extended_cpuid_level;
 100         /* Maximum supported CPUID level, -1=no CPUID: */
 101         int                     cpuid_level;
 102         /*
 103          * Align to size of unsigned long because the x86_capability array
 104          * is passed to bitops which require the alignment. Use unnamed
 105          * union to enforce the array is aligned to size of unsigned long.
 106          */
 107         union {
 108                 __u32           x86_capability[NCAPINTS + NBUGINTS];
 109                 unsigned long   x86_capability_alignment;
 110         };
 111         char                    x86_vendor_id[16];
 112         char                    x86_model_id[64];
 113         /* in KB - valid for CPUS which support this call: */
 114         unsigned int            x86_cache_size;
 115         int                     x86_cache_alignment;    /* In bytes */
 116         /* Cache QoS architectural values, valid only on the BSP: */
 117         int                     x86_cache_max_rmid;     /* max index */
 118         int                     x86_cache_occ_scale;    /* scale to bytes */
 119         int                     x86_cache_mbm_width_offset;
 120         int                     x86_power;
 121         unsigned long           loops_per_jiffy;
 122         /* cpuid returned max cores value: */
 123         u16                     x86_max_cores;
 124         u16                     apicid;
 125         u16                     initial_apicid;
 126         u16                     x86_clflush_size;
 127         /* number of cores as seen by the OS: */
 128         u16                     booted_cores;
 129         /* Physical processor id: */
 130         u16                     phys_proc_id;
 131         /* Logical processor id: */
 132         u16                     logical_proc_id;
 133         /* Core id: */
 134         u16                     cpu_core_id;
 135         u16                     cpu_die_id;
 136         u16                     logical_die_id;
 137         /* Index into per_cpu list: */
 138         u16                     cpu_index;
 139         u32                     microcode;
 140         /* Address space bits used by the cache internally */
 141         u8                      x86_cache_bits;
 142         unsigned                initialized : 1;
 143 } __randomize_layout;
 144
 145 struct cpuid_regs {
 146         u32 eax, ebx, ecx, edx;
 147 };
 148
 149 enum cpuid_regs_idx {
 150         CPUID_EAX = 0,
 151         CPUID_EBX,
 152         CPUID_ECX,
 153         CPUID_EDX,
 154 };
 155
 156 #define X86_VENDOR_INTEL        0
 157 #define X86_VENDOR_CYRIX        1
 158 #define X86_VENDOR_AMD          2
 159 #define X86_VENDOR_UMC          3
 160 #define X86_VENDOR_CENTAUR      5
 161 #define X86_VENDOR_TRANSMETA    7
 162 #define X86_VENDOR_NSC          8
 163 #define X86_VENDOR_HYGON        9
 164 #define X86_VENDOR_ZHAOXIN      10
 165 #define X86_VENDOR_NUM          11
 166
 167 #define X86_VENDOR_UNKNOWN      0xff
 168
 169 /*
 170  * capabilities of CPUs
 171  */
 172 extern struct cpuinfo_x86       boot_cpu_data;
 173 extern struct cpuinfo_x86       new_cpu_data;
 174
 175 extern __u32                    cpu_caps_cleared[NCAPINTS + NBUGINTS];
 176 extern __u32                    cpu_caps_set[NCAPINTS + NBUGINTS];
 177
 178 #ifdef CONFIG_SMP
 179 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
 180 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 181 #else
 182 #define cpu_info                boot_cpu_data
 183 #define cpu_data(cpu)           boot_cpu_data
 184 #endif
 185
 186 extern const struct seq_operations cpuinfo_op;
 187
 188 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 189
 190 extern void cpu_detect(struct cpuinfo_x86 *c);
 191
 192 static inline unsigned long long l1tf_pfn_limit(void)
 193 {
 194         return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
 195 }
 196
 197 extern void early_cpu_init(void);
 198 extern void identify_boot_cpu(void);
 199 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 200 extern void print_cpu_info(struct cpuinfo_x86 *);
 201 void print_cpu_msr(struct cpuinfo_x86 *);
 202
 203 #ifdef CONFIG_X86_32
 204 extern int have_cpuid_p(void);
 205 #else
 206 static inline int have_cpuid_p(void)
 207 {
 208         return 1;
 209 }
 210 #endif
 211 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 212                                 unsigned int *ecx, unsigned int *edx)
 213 {
 214         /* ecx is often an input as well as an output. */
 215         asm volatile("cpuid"
 216             : "=a" (*eax),
 217               "=b" (*ebx),
 218               "=c" (*ecx),
 219               "=d" (*edx)
 220             : "0" (*eax), "2" (*ecx)
 221             : "memory");
 222 }
 223
 224 #define native_cpuid_reg(reg)                                   \
 225 static inline unsigned int native_cpuid_##reg(unsigned int op)  \
 226 {                                                               \
 227         unsigned int eax = op, ebx, ecx = 0, edx;               \
 228                                                                 \
 229         native_cpuid(&eax, &ebx, &ecx, &edx);                   \
 230                                                                 \
 231         return reg;                                             \
 232 }
 233
 234 /*
 235  * Native CPUID functions returning a single datum.
 236  */
 237 native_cpuid_reg(eax)
 238 native_cpuid_reg(ebx)
 239 native_cpuid_reg(ecx)
 240 native_cpuid_reg(edx)
 241
 242 /*
 243  * Friendlier CR3 helpers.
 244  */
 245 static inline unsigned long read_cr3_pa(void)
 246 {
 247         return __read_cr3() & CR3_ADDR_MASK;
 248 }
 249
 250 static inline unsigned long native_read_cr3_pa(void)
 251 {
 252         return __native_read_cr3() & CR3_ADDR_MASK;
 253 }
 254
 255 static inline void load_cr3(pgd_t *pgdir)
 256 {
 257         write_cr3(__sme_pa(pgdir));
 258 }
 259
 260 /*
 261  * Note that while the legacy 'TSS' name comes from 'Task State Segment',
 262  * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
 263  * unrelated to the task-switch mechanism:
 264  */
 265 #ifdef CONFIG_X86_32
 266 /* This is the TSS defined by the hardware. */
 267 struct x86_hw_tss {
 268         unsigned short          back_link, __blh;
 269         unsigned long           sp0;
 270         unsigned short          ss0, __ss0h;
 271         unsigned long           sp1;
 272
 273         /*
 274          * We don't use ring 1, so ss1 is a convenient scratch space in
 275          * the same cacheline as sp0.  We use ss1 to cache the value in
 276          * MSR_IA32_SYSENTER_CS.  When we context switch
 277          * MSR_IA32_SYSENTER_CS, we first check if the new value being
 278          * written matches ss1, and, if it's not, then we wrmsr the new
 279          * value and update ss1.
 280          *
 281          * The only reason we context switch MSR_IA32_SYSENTER_CS is
 282          * that we set it to zero in vm86 tasks to avoid corrupting the
 283          * stack if we were to go through the sysenter path from vm86
 284          * mode.
 285          */
 286         unsigned short          ss1;    /* MSR_IA32_SYSENTER_CS */
 287
 288         unsigned short          __ss1h;
 289         unsigned long           sp2;
 290         unsigned short          ss2, __ss2h;
 291         unsigned long           __cr3;
 292         unsigned long           ip;
 293         unsigned long           flags;
 294         unsigned long           ax;
 295         unsigned long           cx;
 296         unsigned long           dx;
 297         unsigned long           bx;
 298         unsigned long           sp;
 299         unsigned long           bp;
 300         unsigned long           si;
 301         unsigned long           di;
 302         unsigned short          es, __esh;
 303         unsigned short          cs, __csh;
 304         unsigned short          ss, __ssh;
 305         unsigned short          ds, __dsh;
 306         unsigned short          fs, __fsh;
 307         unsigned short          gs, __gsh;
 308         unsigned short          ldt, __ldth;
 309         unsigned short          trace;
 310         unsigned short          io_bitmap_base;
 311
 312 } __attribute__((packed));
 313 #else
 314 struct x86_hw_tss {
 315         u32                     reserved1;
 316         u64                     sp0;
 317
 318         /*
 319          * We store cpu_current_top_of_stack in sp1 so it's always accessible.
 320          * Linux does not use ring 1, so sp1 is not otherwise needed.
 321          */
 322         u64                     sp1;
 323
 324         /*
 325          * Since Linux does not use ring 2, the 'sp2' slot is unused by
 326          * hardware.  entry_SYSCALL_64 uses it as scratch space to stash
 327          * the user RSP value.
 328          */
 329         u64                     sp2;
 330
 331         u64                     reserved2;
 332         u64                     ist[7];
 333         u32                     reserved3;
 334         u32                     reserved4;
 335         u16                     reserved5;
 336         u16                     io_bitmap_base;
 337
 338 } __attribute__((packed));
 339 #endif
 340
 341 /*
 342  * IO-bitmap sizes:
 343  */
 344 #define IO_BITMAP_BITS                  65536
 345 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS / BITS_PER_BYTE)
 346 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES / sizeof(long))
 347
 348 #define IO_BITMAP_OFFSET_VALID_MAP                              \
 349         (offsetof(struct tss_struct, io_bitmap.bitmap) -        \
 350          offsetof(struct tss_struct, x86_tss))
 351
 352 #define IO_BITMAP_OFFSET_VALID_ALL                              \
 353         (offsetof(struct tss_struct, io_bitmap.mapall) -        \
 354          offsetof(struct tss_struct, x86_tss))
 355
 356 #ifdef CONFIG_X86_IOPL_IOPERM
 357 /*
 358  * sizeof(unsigned long) coming from an extra "long" at the end of the
 359  * iobitmap. The limit is inclusive, i.e. the last valid byte.
 360  */
 361 # define __KERNEL_TSS_LIMIT     \
 362         (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \
 363          sizeof(unsigned long) - 1)
 364 #else
 365 # define __KERNEL_TSS_LIMIT     \
 366         (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1)
 367 #endif
 368
 369 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */
 370 #define IO_BITMAP_OFFSET_INVALID        (__KERNEL_TSS_LIMIT + 1)
 371
 372 struct entry_stack {
 373         unsigned long           words[64];
 374 };
 375
 376 struct entry_stack_page {
 377         struct entry_stack stack;
 378 } __aligned(PAGE_SIZE);
 379
 380 /*
 381  * All IO bitmap related data stored in the TSS:
 382  */
 383 struct x86_io_bitmap {
 384         /* The sequence number of the last active bitmap. */
 385         u64                     prev_sequence;
 386
 387         /*
 388          * Store the dirty size of the last io bitmap offender. The next
 389          * one will have to do the cleanup as the switch out to a non io
 390          * bitmap user will just set x86_tss.io_bitmap_base to a value
 391          * outside of the TSS limit. So for sane tasks there is no need to
 392          * actually touch the io_bitmap at all.
 393          */
 394         unsigned int            prev_max;
 395
 396         /*
 397          * The extra 1 is there because the CPU will access an
 398          * additional byte beyond the end of the IO permission
 399          * bitmap. The extra byte must be all 1 bits, and must
 400          * be within the limit.
 401          */
 402         unsigned long           bitmap[IO_BITMAP_LONGS + 1];
 403
 404         /*
 405          * Special I/O bitmap to emulate IOPL(3). All bytes zero,
 406          * except the additional byte at the end.
 407          */
 408         unsigned long           mapall[IO_BITMAP_LONGS + 1];
 409 };
 410
 411 struct tss_struct {
 412         /*
 413          * The fixed hardware portion.  This must not cross a page boundary
 414          * at risk of violating the SDM's advice and potentially triggering
 415          * errata.
 416          */
 417         struct x86_hw_tss       x86_tss;
 418
 419         struct x86_io_bitmap    io_bitmap;
 420 } __aligned(PAGE_SIZE);
 421
 422 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
 423
 424 /* Per CPU interrupt stacks */
 425 struct irq_stack {
 426         char            stack[IRQ_STACK_SIZE];
 427 } __aligned(IRQ_STACK_SIZE);
 428
 429 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
 430
 431 #ifdef CONFIG_X86_32
 432 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
 433 #else
 434 /* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */
 435 #define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1
 436 #endif
 437
 438 #ifdef CONFIG_X86_64
 439 struct fixed_percpu_data {
 440         /*
 441          * GCC hardcodes the stack canary as %gs:40.  Since the
 442          * irq_stack is the object at %gs:0, we reserve the bottom
 443          * 48 bytes of the irq stack for the canary.
 444          */
 445         char            gs_base[40];
 446         unsigned long   stack_canary;
 447 };
 448
 449 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible;
 450 DECLARE_INIT_PER_CPU(fixed_percpu_data);
 451
 452 static inline unsigned long cpu_kernelmode_gs_base(int cpu)
 453 {
 454         return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu);
 455 }
 456
 457 DECLARE_PER_CPU(unsigned int, irq_count);
 458 extern asmlinkage void ignore_sysret(void);
 459
 460 #if IS_ENABLED(CONFIG_KVM)
 461 /* Save actual FS/GS selectors and bases to current->thread */
 462 void save_fsgs_for_kvm(void);
 463 #endif
 464 #else   /* X86_64 */
 465 #ifdef CONFIG_STACKPROTECTOR
 466 /*
 467  * Make sure stack canary segment base is cached-aligned:
 468  *   "For Intel Atom processors, avoid non zero segment base address
 469  *    that is not aligned to cache line boundary at all cost."
 470  * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
 471  */
 472 struct stack_canary {
 473         char __pad[20];         /* canary at %gs:20 */
 474         unsigned long canary;
 475 };
 476 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
 477 #endif
 478 /* Per CPU softirq stack pointer */
 479 DECLARE_PER_CPU(struct irq_stack *, softirq_stack_ptr);
 480 #endif  /* X86_64 */
 481
 482 extern unsigned int fpu_kernel_xstate_size;
 483 extern unsigned int fpu_user_xstate_size;
 484
 485 struct perf_event;
 486
 487 typedef struct {
 488         unsigned long           seg;
 489 } mm_segment_t;
 490
 491 struct thread_struct {
 492         /* Cached TLS descriptors: */
 493         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 494 #ifdef CONFIG_X86_32
 495         unsigned long           sp0;
 496 #endif
 497         unsigned long           sp;
 498 #ifdef CONFIG_X86_32
 499         unsigned long           sysenter_cs;
 500 #else
 501         unsigned short          es;
 502         unsigned short          ds;
 503         unsigned short          fsindex;
 504         unsigned short          gsindex;
 505 #endif
 506
 507 #ifdef CONFIG_X86_64
 508         unsigned long           fsbase;
 509         unsigned long           gsbase;
 510 #else
 511         /*
 512          * XXX: this could presumably be unsigned short.  Alternatively,
 513          * 32-bit kernels could be taught to use fsindex instead.
 514          */
 515         unsigned long fs;
 516         unsigned long gs;
 517 #endif
 518
 519         /* Save middle states of ptrace breakpoints */
 520         struct perf_event       *ptrace_bps[HBP_NUM];
 521         /* Debug status used for traps, single steps, etc... */
 522         unsigned long           debugreg6;
 523         /* Keep track of the exact dr7 value set by the user */
 524         unsigned long           ptrace_dr7;
 525         /* Fault info: */
 526         unsigned long           cr2;
 527         unsigned long           trap_nr;
 528         unsigned long           error_code;
 529 #ifdef CONFIG_VM86
 530         /* Virtual 86 mode info */
 531         struct vm86             *vm86;
 532 #endif
 533         /* IO permissions: */
 534         struct io_bitmap        *io_bitmap;
 535
 536         /*
 537          * IOPL. Priviledge level dependent I/O permission which is
 538          * emulated via the I/O bitmap to prevent user space from disabling
 539          * interrupts.
 540          */
 541         unsigned long           iopl_emul;
 542
 543         mm_segment_t            addr_limit;
 544
 545         unsigned int            sig_on_uaccess_err:1;
 546
 547         /* Floating point and extended processor state */
 548         struct fpu              fpu;
 549         /*
 550          * WARNING: 'fpu' is dynamically-sized.  It *MUST* be at
 551          * the end.
 552          */
 553 };
 554
 555 /* Whitelist the FPU state from the task_struct for hardened usercopy. */
 556 static inline void arch_thread_struct_whitelist(unsigned long *offset,
 557                                                 unsigned long *size)
 558 {
 559         *offset = offsetof(struct thread_struct, fpu.state);
 560         *size = fpu_kernel_xstate_size;
 561 }
 562
 563 /*
 564  * Thread-synchronous status.
 565  *
 566  * This is different from the flags in that nobody else
 567  * ever touches our thread-synchronous status, so we don't
 568  * have to worry about atomic accesses.
 569  */
 570 #define TS_COMPAT               0x0002  /* 32bit syscall active (64BIT)*/
 571
 572 static inline void
 573 native_load_sp0(unsigned long sp0)
 574 {
 575         this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
 576 }
 577
 578 static inline void native_swapgs(void)
 579 {
 580 #ifdef CONFIG_X86_64
 581         asm volatile("swapgs" ::: "memory");
 582 #endif
 583 }
 584
 585 static inline unsigned long current_top_of_stack(void)
 586 {
 587         /*
 588          *  We can't read directly from tss.sp0: sp0 on x86_32 is special in
 589          *  and around vm86 mode and sp0 on x86_64 is special because of the
 590          *  entry trampoline.
 591          */
 592         return this_cpu_read_stable(cpu_current_top_of_stack);
 593 }
 594
 595 static inline bool on_thread_stack(void)
 596 {
 597         return (unsigned long)(current_top_of_stack() -
 598                                current_stack_pointer) < THREAD_SIZE;
 599 }
 600
 601 #ifdef CONFIG_PARAVIRT_XXL
 602 #include <asm/paravirt.h>
 603 #else
 604 #define __cpuid                 native_cpuid
 605
 606 static inline void load_sp0(unsigned long sp0)
 607 {
 608         native_load_sp0(sp0);
 609 }
 610
 611 #endif /* CONFIG_PARAVIRT_XXL */
 612
 613 /* Free all resources held by a thread. */
 614 extern void release_thread(struct task_struct *);
 615
 616 unsigned long get_wchan(struct task_struct *p);
 617
 618 /*
 619  * Generic CPUID function
 620  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 621  * resulting in stale register contents being returned.
 622  */
 623 static inline void cpuid(unsigned int op,
 624                          unsigned int *eax, unsigned int *ebx,
 625                          unsigned int *ecx, unsigned int *edx)
 626 {
 627         *eax = op;
 628         *ecx = 0;
 629         __cpuid(eax, ebx, ecx, edx);
 630 }
 631
 632 /* Some CPUID calls want 'count' to be placed in ecx */
 633 static inline void cpuid_count(unsigned int op, int count,
 634                                unsigned int *eax, unsigned int *ebx,
 635                                unsigned int *ecx, unsigned int *edx)
 636 {
 637         *eax = op;
 638         *ecx = count;
 639         __cpuid(eax, ebx, ecx, edx);
 640 }
 641
 642 /*
 643  * CPUID functions returning a single datum
 644  */
 645 static inline unsigned int cpuid_eax(unsigned int op)
 646 {
 647         unsigned int eax, ebx, ecx, edx;
 648
 649         cpuid(op, &eax, &ebx, &ecx, &edx);
 650
 651         return eax;
 652 }
 653
 654 static inline unsigned int cpuid_ebx(unsigned int op)
 655 {
 656         unsigned int eax, ebx, ecx, edx;
 657
 658         cpuid(op, &eax, &ebx, &ecx, &edx);
 659
 660         return ebx;
 661 }
 662
 663 static inline unsigned int cpuid_ecx(unsigned int op)
 664 {
 665         unsigned int eax, ebx, ecx, edx;
 666
 667         cpuid(op, &eax, &ebx, &ecx, &edx);
 668
 669         return ecx;
 670 }
 671
 672 static inline unsigned int cpuid_edx(unsigned int op)
 673 {
 674         unsigned int eax, ebx, ecx, edx;
 675
 676         cpuid(op, &eax, &ebx, &ecx, &edx);
 677
 678         return edx;
 679 }
 680
 681 /*
 682  * This function forces the icache and prefetched instruction stream to
 683  * catch up with reality in two very specific cases:
 684  *
 685  *  a) Text was modified using one virtual address and is about to be executed
 686  *     from the same physical page at a different virtual address.
 687  *
 688  *  b) Text was modified on a different CPU, may subsequently be
 689  *     executed on this CPU, and you want to make sure the new version
 690  *     gets executed.  This generally means you're calling this in a IPI.
 691  *
 692  * If you're calling this for a different reason, you're probably doing
 693  * it wrong.
 694  */
 695 static inline void sync_core(void)
 696 {
 697         /*
 698          * There are quite a few ways to do this.  IRET-to-self is nice
 699          * because it works on every CPU, at any CPL (so it's compatible
 700          * with paravirtualization), and it never exits to a hypervisor.
 701          * The only down sides are that it's a bit slow (it seems to be
 702          * a bit more than 2x slower than the fastest options) and that
 703          * it unmasks NMIs.  The "push %cs" is needed because, in
 704          * paravirtual environments, __KERNEL_CS may not be a valid CS
 705          * value when we do IRET directly.
 706          *
 707          * In case NMI unmasking or performance ever becomes a problem,
 708          * the next best option appears to be MOV-to-CR2 and an
 709          * unconditional jump.  That sequence also works on all CPUs,
 710          * but it will fault at CPL3 (i.e. Xen PV).
 711          *
 712          * CPUID is the conventional way, but it's nasty: it doesn't
 713          * exist on some 486-like CPUs, and it usually exits to a
 714          * hypervisor.
 715          *
 716          * Like all of Linux's memory ordering operations, this is a
 717          * compiler barrier as well.
 718          */
 719 #ifdef CONFIG_X86_32
 720         asm volatile (
 721                 "pushfl\n\t"
 722                 "pushl %%cs\n\t"
 723                 "pushl $1f\n\t"
 724                 "iret\n\t"
 725                 "1:"
 726                 : ASM_CALL_CONSTRAINT : : "memory");
 727 #else
 728         unsigned int tmp;
 729
 730         asm volatile (
 731                 UNWIND_HINT_SAVE
 732                 "mov %%ss, %0\n\t"
 733                 "pushq %q0\n\t"
 734                 "pushq %%rsp\n\t"
 735                 "addq $8, (%%rsp)\n\t"
 736                 "pushfq\n\t"
 737                 "mov %%cs, %0\n\t"
 738                 "pushq %q0\n\t"
 739                 "pushq $1f\n\t"
 740                 "iretq\n\t"
 741                 UNWIND_HINT_RESTORE
 742                 "1:"
 743                 : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");
 744 #endif
 745 }
 746
 747 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 748 extern void amd_e400_c1e_apic_setup(void);
 749
 750 extern unsigned long            boot_option_idle_override;
 751
 752 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
 753                          IDLE_POLL};
 754
 755 extern void enable_sep_cpu(void);
 756 extern int sysenter_setup(void);
 757
 758
 759 /* Defined in head.S */
 760 extern struct desc_ptr          early_gdt_descr;
 761
 762 extern void switch_to_new_gdt(int);
 763 extern void load_direct_gdt(int);
 764 extern void load_fixmap_gdt(int);
 765 extern void load_percpu_segment(int);
 766 extern void cpu_init(void);
 767 extern void cr4_init(void);
 768
 769 static inline unsigned long get_debugctlmsr(void)
 770 {
 771         unsigned long debugctlmsr = 0;
 772
 773 #ifndef CONFIG_X86_DEBUGCTLMSR
 774         if (boot_cpu_data.x86 < 6)
 775                 return 0;
 776 #endif
 777         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 778
 779         return debugctlmsr;
 780 }
 781
 782 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 783 {
 784 #ifndef CONFIG_X86_DEBUGCTLMSR
 785         if (boot_cpu_data.x86 < 6)
 786                 return;
 787 #endif
 788         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 789 }
 790
 791 extern void set_task_blockstep(struct task_struct *task, bool on);
 792
 793 /* Boot loader type from the setup header: */
 794 extern int                      bootloader_type;
 795 extern int                      bootloader_version;
 796
 797 extern char                     ignore_fpu_irq;
 798
 799 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 800 #define ARCH_HAS_PREFETCHW
 801 #define ARCH_HAS_SPINLOCK_PREFETCH
 802
 803 #ifdef CONFIG_X86_32
 804 # define BASE_PREFETCH          ""
 805 # define ARCH_HAS_PREFETCH
 806 #else
 807 # define BASE_PREFETCH          "prefetcht0 %P1"
 808 #endif
 809
 810 /*
 811  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 812  *
 813  * It's not worth to care about 3dnow prefetches for the K6
 814  * because they are microcoded there and very slow.
 815  */
 816 static inline void prefetch(const void *x)
 817 {
 818         alternative_input(BASE_PREFETCH, "prefetchnta %P1",
 819                           X86_FEATURE_XMM,
 820                           "m" (*(const char *)x));
 821 }
 822
 823 /*
 824  * 3dnow prefetch to get an exclusive cache line.
 825  * Useful for spinlocks to avoid one state transition in the
 826  * cache coherency protocol:
 827  */
 828 static inline void prefetchw(const void *x)
 829 {
 830         alternative_input(BASE_PREFETCH, "prefetchw %P1",
 831                           X86_FEATURE_3DNOWPREFETCH,
 832                           "m" (*(const char *)x));
 833 }
 834
 835 static inline void spin_lock_prefetch(const void *x)
 836 {
 837         prefetchw(x);
 838 }
 839
 840 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
 841                            TOP_OF_KERNEL_STACK_PADDING)
 842
 843 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
 844
 845 #define task_pt_regs(task) \
 846 ({                                                                      \
 847         unsigned long __ptr = (unsigned long)task_stack_page(task);     \
 848         __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;             \
 849         ((struct pt_regs *)__ptr) - 1;                                  \
 850 })
 851
 852 #ifdef CONFIG_X86_32
 853 /*
 854  * User space process size: 3GB (default).
 855  */
 856 #define IA32_PAGE_OFFSET        PAGE_OFFSET
 857 #define TASK_SIZE               PAGE_OFFSET
 858 #define TASK_SIZE_LOW           TASK_SIZE
 859 #define TASK_SIZE_MAX           TASK_SIZE
 860 #define DEFAULT_MAP_WINDOW      TASK_SIZE
 861 #define STACK_TOP               TASK_SIZE
 862 #define STACK_TOP_MAX           STACK_TOP
 863
 864 #define INIT_THREAD  {                                                    \
 865         .sp0                    = TOP_OF_INIT_STACK,                      \
 866         .sysenter_cs            = __KERNEL_CS,                            \
 867         .addr_limit             = KERNEL_DS,                              \
 868 }
 869
 870 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 871
 872 #else
 873 /*
 874  * User space process size.  This is the first address outside the user range.
 875  * There are a few constraints that determine this:
 876  *
 877  * On Intel CPUs, if a SYSCALL instruction is at the highest canonical
 878  * address, then that syscall will enter the kernel with a
 879  * non-canonical return address, and SYSRET will explode dangerously.
 880  * We avoid this particular problem by preventing anything executable
 881  * from being mapped at the maximum canonical address.
 882  *
 883  * On AMD CPUs in the Ryzen family, there's a nasty bug in which the
 884  * CPUs malfunction if they execute code from the highest canonical page.
 885  * They'll speculate right off the end of the canonical space, and
 886  * bad things happen.  This is worked around in the same way as the
 887  * Intel problem.
 888  *
 889  * With page table isolation enabled, we map the LDT in ... [stay tuned]
 890  */
 891 #define TASK_SIZE_MAX   ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)
 892
 893 #define DEFAULT_MAP_WINDOW      ((1UL << 47) - PAGE_SIZE)
 894
 895 /* This decides where the kernel will search for a free chunk of vm
 896  * space during mmap's.
 897  */
 898 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 899                                         0xc0000000 : 0xFFFFe000)
 900
 901 #define TASK_SIZE_LOW           (test_thread_flag(TIF_ADDR32) ? \
 902                                         IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW)
 903 #define TASK_SIZE               (test_thread_flag(TIF_ADDR32) ? \
 904                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 905 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
 906                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 907
 908 #define STACK_TOP               TASK_SIZE_LOW
 909 #define STACK_TOP_MAX           TASK_SIZE_MAX
 910
 911 #define INIT_THREAD  {                                          \
 912         .addr_limit             = KERNEL_DS,                    \
 913 }
 914
 915 extern unsigned long KSTK_ESP(struct task_struct *task);
 916
 917 #endif /* CONFIG_X86_64 */
 918
 919 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 920                                                unsigned long new_sp);
 921
 922 /*
 923  * This decides where the kernel will search for a free chunk of vm
 924  * space during mmap's.
 925  */
 926 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
 927 #define TASK_UNMAPPED_BASE              __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
 928
 929 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 930
 931 /* Get/set a process' ability to use the timestamp counter instruction */
 932 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 933 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 934
 935 extern int get_tsc_mode(unsigned long adr);
 936 extern int set_tsc_mode(unsigned int val);
 937
 938 DECLARE_PER_CPU(u64, msr_misc_features_shadow);
 939
 940 #ifdef CONFIG_CPU_SUP_AMD
 941 extern u16 amd_get_nb_id(int cpu);
 942 extern u32 amd_get_nodes_per_socket(void);
 943 #else
 944 static inline u16 amd_get_nb_id(int cpu)                { return 0; }
 945 static inline u32 amd_get_nodes_per_socket(void)        { return 0; }
 946 #endif
 947
 948 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
 949 {
 950         uint32_t base, eax, signature[3];
 951
 952         for (base = 0x40000000; base < 0x40010000; base += 0x100) {
 953                 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
 954
 955                 if (!memcmp(sig, signature, 12) &&
 956                     (leaves == 0 || ((eax - base) >= leaves)))
 957                         return base;
 958         }
 959
 960         return 0;
 961 }
 962
 963 extern unsigned long arch_align_stack(unsigned long sp);
 964 void free_init_pages(const char *what, unsigned long begin, unsigned long end);
 965 extern void free_kernel_image_pages(const char *what, void *begin, void *end);
 966
 967 void default_idle(void);
 968 #ifdef  CONFIG_XEN
 969 bool xen_set_default_idle(void);
 970 #else
 971 #define xen_set_default_idle 0
 972 #endif
 973
 974 void stop_this_cpu(void *dummy);
 975 void microcode_check(void);
 976
 977 enum l1tf_mitigations {
 978         L1TF_MITIGATION_OFF,
 979         L1TF_MITIGATION_FLUSH_NOWARN,
 980         L1TF_MITIGATION_FLUSH,
 981         L1TF_MITIGATION_FLUSH_NOSMT,
 982         L1TF_MITIGATION_FULL,
 983         L1TF_MITIGATION_FULL_FORCE
 984 };
 985
 986 extern enum l1tf_mitigations l1tf_mitigation;
 987
 988 enum mds_mitigations {
 989         MDS_MITIGATION_OFF,
 990         MDS_MITIGATION_FULL,
 991         MDS_MITIGATION_VMWERV,
 992 };
 993
 994 #endif /* _ASM_X86_PROCESSOR_H */