2 * Copyright (C) 1995 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
9 * This file handles the architecture-dependent parts of process handling..
12 #include <linux/cpu.h>
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/sched/task.h>
16 #include <linux/sched/task_stack.h>
18 #include <linux/kernel.h>
20 #include <linux/elfcore.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/slab.h>
24 #include <linux/vmalloc.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/reboot.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/export.h>
31 #include <linux/kallsyms.h>
32 #include <linux/ptrace.h>
33 #include <linux/personality.h>
34 #include <linux/percpu.h>
35 #include <linux/prctl.h>
36 #include <linux/ftrace.h>
37 #include <linux/uaccess.h>
39 #include <linux/kdebug.h>
40 #include <linux/syscalls.h>
42 #include <asm/pgtable.h>
44 #include <asm/processor.h>
45 #include <asm/fpu/internal.h>
48 #include <linux/err.h>
50 #include <asm/tlbflush.h>
52 #include <asm/debugreg.h>
53 #include <asm/switch_to.h>
55 #include <asm/resctrl_sched.h>
56 #include <asm/proto.h>
60 void __show_regs(struct pt_regs
*regs
, enum show_regs_mode mode
)
62 unsigned long cr0
= 0L, cr2
= 0L, cr3
= 0L, cr4
= 0L;
63 unsigned long d0
, d1
, d2
, d3
, d6
, d7
;
67 gs
= get_user_gs(regs
);
71 show_ip(regs
, KERN_DEFAULT
);
73 printk(KERN_DEFAULT
"EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
74 regs
->ax
, regs
->bx
, regs
->cx
, regs
->dx
);
75 printk(KERN_DEFAULT
"ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
76 regs
->si
, regs
->di
, regs
->bp
, regs
->sp
);
77 printk(KERN_DEFAULT
"DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x EFLAGS: %08lx\n",
78 (u16
)regs
->ds
, (u16
)regs
->es
, (u16
)regs
->fs
, gs
, regs
->ss
, regs
->flags
);
80 if (mode
!= SHOW_REGS_ALL
)
87 printk(KERN_DEFAULT
"CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
97 /* Only print out debug registers if they are in their non-default state. */
98 if ((d0
== 0) && (d1
== 0) && (d2
== 0) && (d3
== 0) &&
99 (d6
== DR6_RESERVED
) && (d7
== 0x400))
102 printk(KERN_DEFAULT
"DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
104 printk(KERN_DEFAULT
"DR6: %08lx DR7: %08lx\n",
108 void release_thread(struct task_struct
*dead_task
)
110 BUG_ON(dead_task
->mm
);
111 release_vm86_irqs(dead_task
);
115 start_thread(struct pt_regs
*regs
, unsigned long new_ip
, unsigned long new_sp
)
117 set_user_gs(regs
, 0);
119 regs
->ds
= __USER_DS
;
120 regs
->es
= __USER_DS
;
121 regs
->ss
= __USER_DS
;
122 regs
->cs
= __USER_CS
;
125 regs
->flags
= X86_EFLAGS_IF
;
127 EXPORT_SYMBOL_GPL(start_thread
);
131 * switch_to(x,y) should switch tasks from x to y.
133 * We fsave/fwait so that an exception goes off at the right time
134 * (as a call from the fsave or fwait in effect) rather than to
135 * the wrong process. Lazy FP saving no longer makes any sense
136 * with modern CPU's, and this simplifies a lot of things (SMP
137 * and UP become the same).
139 * NOTE! We used to use the x86 hardware context switching. The
140 * reason for not using it any more becomes apparent when you
141 * try to recover gracefully from saved state that is no longer
142 * valid (stale segment register values in particular). With the
143 * hardware task-switch, there is no way to fix up bad state in
144 * a reasonable manner.
146 * The fact that Intel documents the hardware task-switching to
147 * be slow is a fairly red herring - this code is not noticeably
148 * faster. However, there _is_ some room for improvement here,
149 * so the performance issues may eventually be a valid point.
150 * More important, however, is the fact that this allows us much
153 * The return value (in %ax) will be the "prev" task after
154 * the task-switch, and shows up in ret_from_fork in entry.S,
157 __visible __notrace_funcgraph
struct task_struct
*
158 __switch_to(struct task_struct
*prev_p
, struct task_struct
*next_p
)
160 struct thread_struct
*prev
= &prev_p
->thread
,
161 *next
= &next_p
->thread
;
162 struct fpu
*prev_fpu
= &prev
->fpu
;
163 struct fpu
*next_fpu
= &next
->fpu
;
164 int cpu
= smp_processor_id();
166 /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
168 if (!test_thread_flag(TIF_NEED_FPU_LOAD
))
169 switch_fpu_prepare(prev_fpu
, cpu
);
172 * Save away %gs. No need to save %fs, as it was saved on the
173 * stack on entry. No need to save %es and %ds, as those are
174 * always kernel segments while inside the kernel. Doing this
175 * before setting the new TLS descriptors avoids the situation
176 * where we temporarily have non-reloadable segments in %fs
177 * and %gs. This could be an issue if the NMI handler ever
178 * used %fs or %gs (it does not today), or if the kernel is
179 * running inside of a hypervisor layer.
181 lazy_save_gs(prev
->gs
);
184 * Load the per-thread Thread-Local Storage descriptor.
188 switch_to_extra(prev_p
, next_p
);
191 * Leave lazy mode, flushing any hypercalls made here.
192 * This must be done before restoring TLS segments so
193 * the GDT and LDT are properly updated.
195 arch_end_context_switch(next_p
);
198 * Reload esp0 and cpu_current_top_of_stack. This changes
199 * current_thread_info(). Refresh the SYSENTER configuration in
200 * case prev or next is vm86.
202 update_task_stack(next_p
);
203 refresh_sysenter_cs(next
);
204 this_cpu_write(cpu_current_top_of_stack
,
205 (unsigned long)task_stack_page(next_p
) +
209 * Restore %gs if needed (which is common)
211 if (prev
->gs
| next
->gs
)
212 lazy_load_gs(next
->gs
);
214 this_cpu_write(current_task
, next_p
);
216 switch_fpu_finish(next_fpu
);
218 /* Load the Intel cache allocation PQR MSR. */
224 SYSCALL_DEFINE2(arch_prctl
, int, option
, unsigned long, arg2
)
226 return do_arch_prctl_common(current
, option
, arg2
);