arch/x86/kvm/vmx/vmx.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __KVM_X86_VMX_H
   3 #define __KVM_X86_VMX_H
   4
   5 #include <linux/kvm_host.h>
   6
   7 #include <asm/kvm.h>
   8 #include <asm/intel_pt.h>
   9
  10 #include "capabilities.h"
  11 #include "ops.h"
  12 #include "vmcs.h"
  13
  14 extern const u32 vmx_msr_index[];
  15
  16 #define MSR_TYPE_R      1
  17 #define MSR_TYPE_W      2
  18 #define MSR_TYPE_RW     3
  19
  20 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
  21
  22 #ifdef CONFIG_X86_64
  23 #define NR_SHARED_MSRS  7
  24 #else
  25 #define NR_SHARED_MSRS  4
  26 #endif
  27
  28 #define NR_LOADSTORE_MSRS 8
  29
  30 struct vmx_msrs {
  31         unsigned int            nr;
  32         struct vmx_msr_entry    val[NR_LOADSTORE_MSRS];
  33 };
  34
  35 struct shared_msr_entry {
  36         unsigned index;
  37         u64 data;
  38         u64 mask;
  39 };
  40
  41 enum segment_cache_field {
  42         SEG_FIELD_SEL = 0,
  43         SEG_FIELD_BASE = 1,
  44         SEG_FIELD_LIMIT = 2,
  45         SEG_FIELD_AR = 3,
  46
  47         SEG_FIELD_NR = 4
  48 };
  49
  50 /* Posted-Interrupt Descriptor */
  51 struct pi_desc {
  52         u32 pir[8];     /* Posted interrupt requested */
  53         union {
  54                 struct {
  55                                 /* bit 256 - Outstanding Notification */
  56                         u16     on      : 1,
  57                                 /* bit 257 - Suppress Notification */
  58                                 sn      : 1,
  59                                 /* bit 271:258 - Reserved */
  60                                 rsvd_1  : 14;
  61                                 /* bit 279:272 - Notification Vector */
  62                         u8      nv;
  63                                 /* bit 287:280 - Reserved */
  64                         u8      rsvd_2;
  65                                 /* bit 319:288 - Notification Destination */
  66                         u32     ndst;
  67                 };
  68                 u64 control;
  69         };
  70         u32 rsvd[6];
  71 } __aligned(64);
  72
  73 #define RTIT_ADDR_RANGE         4
  74
  75 struct pt_ctx {
  76         u64 ctl;
  77         u64 status;
  78         u64 output_base;
  79         u64 output_mask;
  80         u64 cr3_match;
  81         u64 addr_a[RTIT_ADDR_RANGE];
  82         u64 addr_b[RTIT_ADDR_RANGE];
  83 };
  84
  85 struct pt_desc {
  86         u64 ctl_bitmask;
  87         u32 addr_range;
  88         u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
  89         struct pt_ctx host;
  90         struct pt_ctx guest;
  91 };
  92
  93 /*
  94  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
  95  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
  96  */
  97 struct nested_vmx {
  98         /* Has the level1 guest done vmxon? */
  99         bool vmxon;
 100         gpa_t vmxon_ptr;
 101         bool pml_full;
 102
 103         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 104         gpa_t current_vmptr;
 105         /*
 106          * Cache of the guest's VMCS, existing outside of guest memory.
 107          * Loaded from guest memory during VMPTRLD. Flushed to guest
 108          * memory during VMCLEAR and VMPTRLD.
 109          */
 110         struct vmcs12 *cached_vmcs12;
 111         /*
 112          * Cache of the guest's shadow VMCS, existing outside of guest
 113          * memory. Loaded from guest memory during VM entry. Flushed
 114          * to guest memory during VM exit.
 115          */
 116         struct vmcs12 *cached_shadow_vmcs12;
 117
 118         /*
 119          * Indicates if the shadow vmcs or enlightened vmcs must be updated
 120          * with the data held by struct vmcs12.
 121          */
 122         bool need_vmcs12_to_shadow_sync;
 123         bool dirty_vmcs12;
 124
 125         /*
 126          * Indicates lazily loaded guest state has not yet been decached from
 127          * vmcs02.
 128          */
 129         bool need_sync_vmcs02_to_vmcs12_rare;
 130
 131         /*
 132          * vmcs02 has been initialized, i.e. state that is constant for
 133          * vmcs02 has been written to the backing VMCS.  Initialization
 134          * is delayed until L1 actually attempts to run a nested VM.
 135          */
 136         bool vmcs02_initialized;
 137
 138         bool change_vmcs01_virtual_apic_mode;
 139
 140         /*
 141          * Enlightened VMCS has been enabled. It does not mean that L1 has to
 142          * use it. However, VMX features available to L1 will be limited based
 143          * on what the enlightened VMCS supports.
 144          */
 145         bool enlightened_vmcs_enabled;
 146
 147         /* L2 must run next, and mustn't decide to exit to L1. */
 148         bool nested_run_pending;
 149
 150         /* Pending MTF VM-exit into L1.  */
 151         bool mtf_pending;
 152
 153         struct loaded_vmcs vmcs02;
 154
 155         /*
 156          * Guest pages referred to in the vmcs02 with host-physical
 157          * pointers, so we must keep them pinned while L2 runs.
 158          */
 159         struct page *apic_access_page;
 160         struct kvm_host_map virtual_apic_map;
 161         struct kvm_host_map pi_desc_map;
 162
 163         struct kvm_host_map msr_bitmap_map;
 164
 165         struct pi_desc *pi_desc;
 166         bool pi_pending;
 167         u16 posted_intr_nv;
 168
 169         struct hrtimer preemption_timer;
 170         bool preemption_timer_expired;
 171
 172         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 173         u64 vmcs01_debugctl;
 174         u64 vmcs01_guest_bndcfgs;
 175
 176         /* to migrate it to L1 if L2 writes to L1's CR8 directly */
 177         int l1_tpr_threshold;
 178
 179         u16 vpid02;
 180         u16 last_vpid;
 181
 182         struct nested_vmx_msrs msrs;
 183
 184         /* SMM related state */
 185         struct {
 186                 /* in VMX operation on SMM entry? */
 187                 bool vmxon;
 188                 /* in guest mode on SMM entry? */
 189                 bool guest_mode;
 190         } smm;
 191
 192         gpa_t hv_evmcs_vmptr;
 193         struct kvm_host_map hv_evmcs_map;
 194         struct hv_enlightened_vmcs *hv_evmcs;
 195 };
 196
 197 struct vcpu_vmx {
 198         struct kvm_vcpu       vcpu;
 199         u8                    fail;
 200         u8                    msr_bitmap_mode;
 201
 202         /*
 203          * If true, host state has been stored in vmx->loaded_vmcs for
 204          * the CPU registers that only need to be switched when transitioning
 205          * to/from the kernel, and the registers have been loaded with guest
 206          * values.  If false, host state is loaded in the CPU registers
 207          * and vmx->loaded_vmcs->host_state is invalid.
 208          */
 209         bool                  guest_state_loaded;
 210
 211         u32                   exit_intr_info;
 212         u32                   idt_vectoring_info;
 213         ulong                 rflags;
 214
 215         struct shared_msr_entry guest_msrs[NR_SHARED_MSRS];
 216         int                   nmsrs;
 217         int                   save_nmsrs;
 218         bool                  guest_msrs_ready;
 219 #ifdef CONFIG_X86_64
 220         u64                   msr_host_kernel_gs_base;
 221         u64                   msr_guest_kernel_gs_base;
 222 #endif
 223
 224         u64                   spec_ctrl;
 225         u32                   msr_ia32_umwait_control;
 226
 227         u32 secondary_exec_control;
 228
 229         /*
 230          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 231          * non-nested (L1) guest, it always points to vmcs01. For a nested
 232          * guest (L2), it points to a different VMCS.
 233          */
 234         struct loaded_vmcs    vmcs01;
 235         struct loaded_vmcs   *loaded_vmcs;
 236
 237         struct msr_autoload {
 238                 struct vmx_msrs guest;
 239                 struct vmx_msrs host;
 240         } msr_autoload;
 241
 242         struct msr_autostore {
 243                 struct vmx_msrs guest;
 244         } msr_autostore;
 245
 246         struct {
 247                 int vm86_active;
 248                 ulong save_rflags;
 249                 struct kvm_segment segs[8];
 250         } rmode;
 251         struct {
 252                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 253                 struct kvm_save_segment {
 254                         u16 selector;
 255                         unsigned long base;
 256                         u32 limit;
 257                         u32 ar;
 258                 } seg[8];
 259         } segment_cache;
 260         int vpid;
 261         bool emulation_required;
 262
 263         u32 exit_reason;
 264
 265         /* Posted interrupt descriptor */
 266         struct pi_desc pi_desc;
 267
 268         /* Support for a guest hypervisor (nested VMX) */
 269         struct nested_vmx nested;
 270
 271         /* Dynamic PLE window. */
 272         unsigned int ple_window;
 273         bool ple_window_dirty;
 274
 275         bool req_immediate_exit;
 276
 277         /* Support for PML */
 278 #define PML_ENTITY_NUM          512
 279         struct page *pml_pg;
 280
 281         /* apic deadline value in host tsc */
 282         u64 hv_deadline_tsc;
 283
 284         u64 current_tsc_ratio;
 285
 286         u32 host_pkru;
 287
 288         unsigned long host_debugctlmsr;
 289
 290         /*
 291          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 292          * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
 293          * in msr_ia32_feature_control_valid_bits.
 294          */
 295         u64 msr_ia32_feature_control;
 296         u64 msr_ia32_feature_control_valid_bits;
 297         u64 ept_pointer;
 298
 299         struct pt_desc pt_desc;
 300 };
 301
 302 enum ept_pointers_status {
 303         EPT_POINTERS_CHECK = 0,
 304         EPT_POINTERS_MATCH = 1,
 305         EPT_POINTERS_MISMATCH = 2
 306 };
 307
 308 struct kvm_vmx {
 309         struct kvm kvm;
 310
 311         unsigned int tss_addr;
 312         bool ept_identity_pagetable_done;
 313         gpa_t ept_identity_map_addr;
 314
 315         enum ept_pointers_status ept_pointers_match;
 316         spinlock_t ept_pointer_lock;
 317 };
 318
 319 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
 320 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
 321                         struct loaded_vmcs *buddy);
 322 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 323 int allocate_vpid(void);
 324 void free_vpid(int vpid);
 325 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
 326 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
 327 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
 328                         unsigned long fs_base, unsigned long gs_base);
 329 int vmx_get_cpl(struct kvm_vcpu *vcpu);
 330 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
 331 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 332 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
 333 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
 334 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
 335 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 336 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
 337 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
 338 void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long cr3);
 339 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 340 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
 341 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
 342 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 343 void update_exception_bitmap(struct kvm_vcpu *vcpu);
 344 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
 345 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
 346 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 347 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
 348 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr);
 349 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx);
 350 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
 351 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr);
 352
 353 #define POSTED_INTR_ON  0
 354 #define POSTED_INTR_SN  1
 355
 356 static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
 357 {
 358         return test_and_set_bit(POSTED_INTR_ON,
 359                         (unsigned long *)&pi_desc->control);
 360 }
 361
 362 static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 363 {
 364         return test_and_clear_bit(POSTED_INTR_ON,
 365                         (unsigned long *)&pi_desc->control);
 366 }
 367
 368 static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 369 {
 370         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 371 }
 372
 373 static inline bool pi_is_pir_empty(struct pi_desc *pi_desc)
 374 {
 375         return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS);
 376 }
 377
 378 static inline void pi_set_sn(struct pi_desc *pi_desc)
 379 {
 380         set_bit(POSTED_INTR_SN,
 381                 (unsigned long *)&pi_desc->control);
 382 }
 383
 384 static inline void pi_set_on(struct pi_desc *pi_desc)
 385 {
 386         set_bit(POSTED_INTR_ON,
 387                 (unsigned long *)&pi_desc->control);
 388 }
 389
 390 static inline void pi_clear_on(struct pi_desc *pi_desc)
 391 {
 392         clear_bit(POSTED_INTR_ON,
 393                 (unsigned long *)&pi_desc->control);
 394 }
 395
 396 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 397 {
 398         clear_bit(POSTED_INTR_SN,
 399                 (unsigned long *)&pi_desc->control);
 400 }
 401
 402 static inline int pi_test_on(struct pi_desc *pi_desc)
 403 {
 404         return test_bit(POSTED_INTR_ON,
 405                         (unsigned long *)&pi_desc->control);
 406 }
 407
 408 static inline int pi_test_sn(struct pi_desc *pi_desc)
 409 {
 410         return test_bit(POSTED_INTR_SN,
 411                         (unsigned long *)&pi_desc->control);
 412 }
 413
 414 static inline u8 vmx_get_rvi(void)
 415 {
 416         return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
 417 }
 418
 419 #define BUILD_CONTROLS_SHADOW(lname, uname)                                 \
 420 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val)      \
 421 {                                                                           \
 422         if (vmx->loaded_vmcs->controls_shadow.lname != val) {               \
 423                 vmcs_write32(uname, val);                                   \
 424                 vmx->loaded_vmcs->controls_shadow.lname = val;              \
 425         }                                                                   \
 426 }                                                                           \
 427 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx)                \
 428 {                                                                           \
 429         return vmx->loaded_vmcs->controls_shadow.lname;                     \
 430 }                                                                           \
 431 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val)   \
 432 {                                                                           \
 433         lname##_controls_set(vmx, lname##_controls_get(vmx) | val);         \
 434 }                                                                           \
 435 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
 436 {                                                                           \
 437         lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val);        \
 438 }
 439 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
 440 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
 441 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
 442 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
 443 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
 444
 445 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
 446 {
 447         vmx->segment_cache.bitmask = 0;
 448 }
 449
 450 static inline u32 vmx_vmentry_ctrl(void)
 451 {
 452         u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
 453         if (vmx_pt_mode_is_system())
 454                 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
 455                                   VM_ENTRY_LOAD_IA32_RTIT_CTL);
 456         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
 457         return vmentry_ctrl &
 458                 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
 459 }
 460
 461 static inline u32 vmx_vmexit_ctrl(void)
 462 {
 463         u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
 464         if (vmx_pt_mode_is_system())
 465                 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
 466                                  VM_EXIT_CLEAR_IA32_RTIT_CTL);
 467         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
 468         return vmexit_ctrl &
 469                 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
 470 }
 471
 472 u32 vmx_exec_control(struct vcpu_vmx *vmx);
 473 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx);
 474
 475 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
 476 {
 477         return container_of(kvm, struct kvm_vmx, kvm);
 478 }
 479
 480 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 481 {
 482         return container_of(vcpu, struct vcpu_vmx, vcpu);
 483 }
 484
 485 static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 486 {
 487         return &(to_vmx(vcpu)->pi_desc);
 488 }
 489
 490 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
 491 void free_vmcs(struct vmcs *vmcs);
 492 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
 493 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
 494 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
 495
 496 static inline struct vmcs *alloc_vmcs(bool shadow)
 497 {
 498         return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
 499                               GFP_KERNEL_ACCOUNT);
 500 }
 501
 502 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 503
 504 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
 505                                 bool invalidate_gpa)
 506 {
 507         if (enable_ept && (invalidate_gpa || !enable_vpid)) {
 508                 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
 509                         return;
 510                 ept_sync_context(construct_eptp(vcpu,
 511                                                 vcpu->arch.mmu->root_hpa));
 512         } else {
 513                 vpid_sync_context(vpid);
 514         }
 515 }
 516
 517 static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
 518 {
 519         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
 520 }
 521
 522 static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
 523 {
 524         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
 525         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
 526 }
 527
 528 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
 529 {
 530         return vmx->secondary_exec_control &
 531                 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
 532 }
 533
 534 void dump_vmcs(void);
 535
 536 #endif /* __KVM_X86_VMX_H */