arch/x86/kvm/x86.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef ARCH_X86_KVM_X86_H
   3 #define ARCH_X86_KVM_X86_H
   4
   5 #include <linux/kvm_host.h>
   6 #include <asm/pvclock.h>
   7 #include "kvm_cache_regs.h"
   8 #include "kvm_emulate.h"
   9
  10 #define KVM_DEFAULT_PLE_GAP             128
  11 #define KVM_VMX_DEFAULT_PLE_WINDOW      4096
  12 #define KVM_DEFAULT_PLE_WINDOW_GROW     2
  13 #define KVM_DEFAULT_PLE_WINDOW_SHRINK   0
  14 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX  UINT_MAX
  15 #define KVM_SVM_DEFAULT_PLE_WINDOW_MAX  USHRT_MAX
  16 #define KVM_SVM_DEFAULT_PLE_WINDOW      3000
  17
  18 static inline unsigned int __grow_ple_window(unsigned int val,
  19                 unsigned int base, unsigned int modifier, unsigned int max)
  20 {
  21         u64 ret = val;
  22
  23         if (modifier < 1)
  24                 return base;
  25
  26         if (modifier < base)
  27                 ret *= modifier;
  28         else
  29                 ret += modifier;
  30
  31         return min(ret, (u64)max);
  32 }
  33
  34 static inline unsigned int __shrink_ple_window(unsigned int val,
  35                 unsigned int base, unsigned int modifier, unsigned int min)
  36 {
  37         if (modifier < 1)
  38                 return base;
  39
  40         if (modifier < base)
  41                 val /= modifier;
  42         else
  43                 val -= modifier;
  44
  45         return max(val, min);
  46 }
  47
  48 #define MSR_IA32_CR_PAT_DEFAULT  0x0007040600070406ULL
  49
  50 static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
  51 {
  52         vcpu->arch.exception.pending = false;
  53         vcpu->arch.exception.injected = false;
  54 }
  55
  56 static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
  57         bool soft)
  58 {
  59         vcpu->arch.interrupt.injected = true;
  60         vcpu->arch.interrupt.soft = soft;
  61         vcpu->arch.interrupt.nr = vector;
  62 }
  63
  64 static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
  65 {
  66         vcpu->arch.interrupt.injected = false;
  67 }
  68
  69 static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
  70 {
  71         return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
  72                 vcpu->arch.nmi_injected;
  73 }
  74
  75 static inline bool kvm_exception_is_soft(unsigned int nr)
  76 {
  77         return (nr == BP_VECTOR) || (nr == OF_VECTOR);
  78 }
  79
  80 static inline bool is_protmode(struct kvm_vcpu *vcpu)
  81 {
  82         return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
  83 }
  84
  85 static inline int is_long_mode(struct kvm_vcpu *vcpu)
  86 {
  87 #ifdef CONFIG_X86_64
  88         return vcpu->arch.efer & EFER_LMA;
  89 #else
  90         return 0;
  91 #endif
  92 }
  93
  94 static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
  95 {
  96         int cs_db, cs_l;
  97
  98         if (!is_long_mode(vcpu))
  99                 return false;
 100         kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 101         return cs_l;
 102 }
 103
 104 static inline bool is_la57_mode(struct kvm_vcpu *vcpu)
 105 {
 106 #ifdef CONFIG_X86_64
 107         return (vcpu->arch.efer & EFER_LMA) &&
 108                  kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
 109 #else
 110         return 0;
 111 #endif
 112 }
 113
 114 static inline bool x86_exception_has_error_code(unsigned int vector)
 115 {
 116         static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
 117                         BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
 118                         BIT(PF_VECTOR) | BIT(AC_VECTOR);
 119
 120         return (1U << vector) & exception_has_error_code;
 121 }
 122
 123 static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
 124 {
 125         return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
 126 }
 127
 128 static inline int is_pae(struct kvm_vcpu *vcpu)
 129 {
 130         return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
 131 }
 132
 133 static inline int is_pse(struct kvm_vcpu *vcpu)
 134 {
 135         return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
 136 }
 137
 138 static inline int is_paging(struct kvm_vcpu *vcpu)
 139 {
 140         return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG));
 141 }
 142
 143 static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
 144 {
 145         return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
 146 }
 147
 148 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
 149 {
 150         return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
 151 }
 152
 153 static inline u64 get_canonical(u64 la, u8 vaddr_bits)
 154 {
 155         return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
 156 }
 157
 158 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
 159 {
 160         return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
 161 }
 162
 163 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
 164                                         gva_t gva, gfn_t gfn, unsigned access)
 165 {
 166         u64 gen = kvm_memslots(vcpu->kvm)->generation;
 167
 168         if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
 169                 return;
 170
 171         /*
 172          * If this is a shadow nested page table, the "GVA" is
 173          * actually a nGPA.
 174          */
 175         vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
 176         vcpu->arch.mmio_access = access;
 177         vcpu->arch.mmio_gfn = gfn;
 178         vcpu->arch.mmio_gen = gen;
 179 }
 180
 181 static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
 182 {
 183         return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
 184 }
 185
 186 /*
 187  * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
 188  * clear all mmio cache info.
 189  */
 190 #define MMIO_GVA_ANY (~(gva_t)0)
 191
 192 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
 193 {
 194         if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
 195                 return;
 196
 197         vcpu->arch.mmio_gva = 0;
 198 }
 199
 200 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
 201 {
 202         if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
 203               vcpu->arch.mmio_gva == (gva & PAGE_MASK))
 204                 return true;
 205
 206         return false;
 207 }
 208
 209 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
 210 {
 211         if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
 212               vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
 213                 return true;
 214
 215         return false;
 216 }
 217
 218 static inline unsigned long kvm_register_readl(struct kvm_vcpu *vcpu, int reg)
 219 {
 220         unsigned long val = kvm_register_read(vcpu, reg);
 221
 222         return is_64_bit_mode(vcpu) ? val : (u32)val;
 223 }
 224
 225 static inline void kvm_register_writel(struct kvm_vcpu *vcpu,
 226                                        int reg, unsigned long val)
 227 {
 228         if (!is_64_bit_mode(vcpu))
 229                 val = (u32)val;
 230         return kvm_register_write(vcpu, reg, val);
 231 }
 232
 233 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
 234 {
 235         return !(kvm->arch.disabled_quirks & quirk);
 236 }
 237
 238 static inline bool kvm_vcpu_latch_init(struct kvm_vcpu *vcpu)
 239 {
 240         return is_smm(vcpu) || kvm_x86_ops.apic_init_signal_blocked(vcpu);
 241 }
 242
 243 void kvm_set_pending_timer(struct kvm_vcpu *vcpu);
 244 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
 245
 246 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr);
 247 u64 get_kvmclock_ns(struct kvm *kvm);
 248
 249 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
 250         gva_t addr, void *val, unsigned int bytes,
 251         struct x86_exception *exception);
 252
 253 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
 254         gva_t addr, void *val, unsigned int bytes,
 255         struct x86_exception *exception);
 256
 257 int handle_ud(struct kvm_vcpu *vcpu);
 258
 259 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu);
 260
 261 void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu);
 262 u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
 263 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
 264 int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
 265 int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
 266 bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
 267                                           int page_num);
 268 bool kvm_vector_hashing_enabled(void);
 269 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
 270                             int emulation_type, void *insn, int insn_len);
 271 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu);
 272
 273 extern u64 host_xcr0;
 274 extern u64 supported_xcr0;
 275 extern u64 supported_xss;
 276
 277 static inline bool kvm_mpx_supported(void)
 278 {
 279         return (supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
 280                 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 281 }
 282
 283 extern unsigned int min_timer_period_us;
 284
 285 extern bool enable_vmware_backdoor;
 286
 287 extern int pi_inject_timer;
 288
 289 extern struct static_key kvm_no_apic_vcpu;
 290
 291 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
 292 {
 293         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
 294                                    vcpu->arch.virtual_tsc_shift);
 295 }
 296
 297 /* Same "calling convention" as do_div:
 298  * - divide (n << 32) by base
 299  * - put result in n
 300  * - return remainder
 301  */
 302 #define do_shl32_div32(n, base)                                 \
 303         ({                                                      \
 304             u32 __quot, __rem;                                  \
 305             asm("divl %2" : "=a" (__quot), "=d" (__rem)         \
 306                         : "rm" (base), "0" (0), "1" ((u32) n)); \
 307             n = __quot;                                         \
 308             __rem;                                              \
 309          })
 310
 311 static inline bool kvm_mwait_in_guest(struct kvm *kvm)
 312 {
 313         return kvm->arch.mwait_in_guest;
 314 }
 315
 316 static inline bool kvm_hlt_in_guest(struct kvm *kvm)
 317 {
 318         return kvm->arch.hlt_in_guest;
 319 }
 320
 321 static inline bool kvm_pause_in_guest(struct kvm *kvm)
 322 {
 323         return kvm->arch.pause_in_guest;
 324 }
 325
 326 static inline bool kvm_cstate_in_guest(struct kvm *kvm)
 327 {
 328         return kvm->arch.cstate_in_guest;
 329 }
 330
 331 DECLARE_PER_CPU(struct kvm_vcpu *, current_vcpu);
 332
 333 static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu)
 334 {
 335         __this_cpu_write(current_vcpu, vcpu);
 336 }
 337
 338 static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
 339 {
 340         __this_cpu_write(current_vcpu, NULL);
 341 }
 342
 343
 344 static inline bool kvm_pat_valid(u64 data)
 345 {
 346         if (data & 0xF8F8F8F8F8F8F8F8ull)
 347                 return false;
 348         /* 0, 1, 4, 5, 6, 7 are valid values.  */
 349         return (data | ((data & 0x0202020202020202ull) << 1)) == data;
 350 }
 351
 352 static inline bool kvm_dr7_valid(u64 data)
 353 {
 354         /* Bits [63:32] are reserved */
 355         return !(data >> 32);
 356 }
 357
 358 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu);
 359 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu);
 360 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu);
 361
 362 #endif