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Revert "tty: hvc: Fix data abort due to race in hvc_open"
[linux/fpc-iii.git] / drivers / iommu / amd_iommu.c
blob2883ac389abbede137326ae61d887c818104fecb
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
10
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-direct.h>
23 #include <linux/dma-iommu.h>
24 #include <linux/iommu-helper.h>
25 #include <linux/iommu.h>
26 #include <linux/delay.h>
27 #include <linux/amd-iommu.h>
28 #include <linux/notifier.h>
29 #include <linux/export.h>
30 #include <linux/irq.h>
31 #include <linux/msi.h>
32 #include <linux/dma-contiguous.h>
33 #include <linux/irqdomain.h>
34 #include <linux/percpu.h>
35 #include <linux/iova.h>
36 #include <asm/irq_remapping.h>
37 #include <asm/io_apic.h>
38 #include <asm/apic.h>
39 #include <asm/hw_irq.h>
40 #include <asm/msidef.h>
41 #include <asm/proto.h>
42 #include <asm/iommu.h>
43 #include <asm/gart.h>
44 #include <asm/dma.h>
45
46 #include "amd_iommu_proto.h"
47 #include "amd_iommu_types.h"
48 #include "irq_remapping.h"
49
50 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
51
52 #define LOOP_TIMEOUT 100000
53
54 /* IO virtual address start page frame number */
55 #define IOVA_START_PFN (1)
56 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
57
58 /* Reserved IOVA ranges */
59 #define MSI_RANGE_START (0xfee00000)
60 #define MSI_RANGE_END (0xfeefffff)
61 #define HT_RANGE_START (0xfd00000000ULL)
62 #define HT_RANGE_END (0xffffffffffULL)
63
64 /*
65 * This bitmap is used to advertise the page sizes our hardware support
66 * to the IOMMU core, which will then use this information to split
67 * physically contiguous memory regions it is mapping into page sizes
68 * that we support.
69 *
70 * 512GB Pages are not supported due to a hardware bug
71 */
72 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
73
74 static DEFINE_SPINLOCK(pd_bitmap_lock);
75
76 /* List of all available dev_data structures */
77 static LLIST_HEAD(dev_data_list);
78
79 LIST_HEAD(ioapic_map);
80 LIST_HEAD(hpet_map);
81 LIST_HEAD(acpihid_map);
82
83 /*
84 * Domain for untranslated devices - only allocated
85 * if iommu=pt passed on kernel cmd line.
86 */
87 const struct iommu_ops amd_iommu_ops;
88
89 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
90 int amd_iommu_max_glx_val = -1;
91
92 /*
93 * general struct to manage commands send to an IOMMU
94 */
95 struct iommu_cmd {
96 u32 data[4];
97 };
98
99 struct kmem_cache *amd_iommu_irq_cache;
100
101 static void update_domain(struct protection_domain *domain);
102 static int protection_domain_init(struct protection_domain *domain);
103 static void detach_device(struct device *dev);
104 static void update_and_flush_device_table(struct protection_domain *domain,
105 struct domain_pgtable *pgtable);
106
107 /****************************************************************************
108 *
109 * Helper functions
110 *
111 ****************************************************************************/
112
113 static inline u16 get_pci_device_id(struct device *dev)
114 {
115 struct pci_dev *pdev = to_pci_dev(dev);
116
117 return pci_dev_id(pdev);
118 }
119
120 static inline int get_acpihid_device_id(struct device *dev,
121 struct acpihid_map_entry **entry)
122 {
123 struct acpi_device *adev = ACPI_COMPANION(dev);
124 struct acpihid_map_entry *p;
125
126 if (!adev)
127 return -ENODEV;
128
129 list_for_each_entry(p, &acpihid_map, list) {
130 if (acpi_dev_hid_uid_match(adev, p->hid,
131 p->uid[0] ? p->uid : NULL)) {
132 if (entry)
133 *entry = p;
134 return p->devid;
135 }
136 }
137 return -EINVAL;
138 }
139
140 static inline int get_device_id(struct device *dev)
141 {
142 int devid;
143
144 if (dev_is_pci(dev))
145 devid = get_pci_device_id(dev);
146 else
147 devid = get_acpihid_device_id(dev, NULL);
148
149 return devid;
150 }
151
152 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
153 {
154 return container_of(dom, struct protection_domain, domain);
155 }
156
157 static void amd_iommu_domain_get_pgtable(struct protection_domain *domain,
158 struct domain_pgtable *pgtable)
159 {
160 u64 pt_root = atomic64_read(&domain->pt_root);
161
162 pgtable->root = (u64 *)(pt_root & PAGE_MASK);
163 pgtable->mode = pt_root & 7; /* lowest 3 bits encode pgtable mode */
164 }
165
166 static u64 amd_iommu_domain_encode_pgtable(u64 *root, int mode)
167 {
168 u64 pt_root;
169
170 /* lowest 3 bits encode pgtable mode */
171 pt_root = mode & 7;
172 pt_root |= (u64)root;
173
174 return pt_root;
175 }
176
177 static struct iommu_dev_data *alloc_dev_data(u16 devid)
178 {
179 struct iommu_dev_data *dev_data;
180
181 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
182 if (!dev_data)
183 return NULL;
184
185 spin_lock_init(&dev_data->lock);
186 dev_data->devid = devid;
187 ratelimit_default_init(&dev_data->rs);
188
189 llist_add(&dev_data->dev_data_list, &dev_data_list);
190 return dev_data;
191 }
192
193 static struct iommu_dev_data *search_dev_data(u16 devid)
194 {
195 struct iommu_dev_data *dev_data;
196 struct llist_node *node;
197
198 if (llist_empty(&dev_data_list))
199 return NULL;
200
201 node = dev_data_list.first;
202 llist_for_each_entry(dev_data, node, dev_data_list) {
203 if (dev_data->devid == devid)
204 return dev_data;
205 }
206
207 return NULL;
208 }
209
210 static int clone_alias(struct pci_dev *pdev, u16 alias, void *data)
211 {
212 u16 devid = pci_dev_id(pdev);
213
214 if (devid == alias)
215 return 0;
216
217 amd_iommu_rlookup_table[alias] =
218 amd_iommu_rlookup_table[devid];
219 memcpy(amd_iommu_dev_table[alias].data,
220 amd_iommu_dev_table[devid].data,
221 sizeof(amd_iommu_dev_table[alias].data));
222
223 return 0;
224 }
225
226 static void clone_aliases(struct pci_dev *pdev)
227 {
228 if (!pdev)
229 return;
230
231 /*
232 * The IVRS alias stored in the alias table may not be
233 * part of the PCI DMA aliases if it's bus differs
234 * from the original device.
235 */
236 clone_alias(pdev, amd_iommu_alias_table[pci_dev_id(pdev)], NULL);
237
238 pci_for_each_dma_alias(pdev, clone_alias, NULL);
239 }
240
241 static struct pci_dev *setup_aliases(struct device *dev)
242 {
243 struct pci_dev *pdev = to_pci_dev(dev);
244 u16 ivrs_alias;
245
246 /* For ACPI HID devices, there are no aliases */
247 if (!dev_is_pci(dev))
248 return NULL;
249
250 /*
251 * Add the IVRS alias to the pci aliases if it is on the same
252 * bus. The IVRS table may know about a quirk that we don't.
253 */
254 ivrs_alias = amd_iommu_alias_table[pci_dev_id(pdev)];
255 if (ivrs_alias != pci_dev_id(pdev) &&
256 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number)
257 pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1);
258
259 clone_aliases(pdev);
260
261 return pdev;
262 }
263
264 static struct iommu_dev_data *find_dev_data(u16 devid)
265 {
266 struct iommu_dev_data *dev_data;
267 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
268
269 dev_data = search_dev_data(devid);
270
271 if (dev_data == NULL) {
272 dev_data = alloc_dev_data(devid);
273 if (!dev_data)
274 return NULL;
275
276 if (translation_pre_enabled(iommu))
277 dev_data->defer_attach = true;
278 }
279
280 return dev_data;
281 }
282
283 struct iommu_dev_data *get_dev_data(struct device *dev)
284 {
285 return dev->archdata.iommu;
286 }
287 EXPORT_SYMBOL(get_dev_data);
288
289 /*
290 * Find or create an IOMMU group for a acpihid device.
291 */
292 static struct iommu_group *acpihid_device_group(struct device *dev)
293 {
294 struct acpihid_map_entry *p, *entry = NULL;
295 int devid;
296
297 devid = get_acpihid_device_id(dev, &entry);
298 if (devid < 0)
299 return ERR_PTR(devid);
300
301 list_for_each_entry(p, &acpihid_map, list) {
302 if ((devid == p->devid) && p->group)
303 entry->group = p->group;
304 }
305
306 if (!entry->group)
307 entry->group = generic_device_group(dev);
308 else
309 iommu_group_ref_get(entry->group);
310
311 return entry->group;
312 }
313
314 static bool pci_iommuv2_capable(struct pci_dev *pdev)
315 {
316 static const int caps[] = {
317 PCI_EXT_CAP_ID_ATS,
318 PCI_EXT_CAP_ID_PRI,
319 PCI_EXT_CAP_ID_PASID,
320 };
321 int i, pos;
322
323 if (pci_ats_disabled())
324 return false;
325
326 for (i = 0; i < 3; ++i) {
327 pos = pci_find_ext_capability(pdev, caps[i]);
328 if (pos == 0)
329 return false;
330 }
331
332 return true;
333 }
334
335 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
336 {
337 struct iommu_dev_data *dev_data;
338
339 dev_data = get_dev_data(&pdev->dev);
340
341 return dev_data->errata & (1 << erratum) ? true : false;
342 }
343
344 /*
345 * This function checks if the driver got a valid device from the caller to
346 * avoid dereferencing invalid pointers.
347 */
348 static bool check_device(struct device *dev)
349 {
350 int devid;
351
352 if (!dev || !dev->dma_mask)
353 return false;
354
355 devid = get_device_id(dev);
356 if (devid < 0)
357 return false;
358
359 /* Out of our scope? */
360 if (devid > amd_iommu_last_bdf)
361 return false;
362
363 if (amd_iommu_rlookup_table[devid] == NULL)
364 return false;
365
366 return true;
367 }
368
369 static void init_iommu_group(struct device *dev)
370 {
371 struct iommu_group *group;
372
373 group = iommu_group_get_for_dev(dev);
374 if (IS_ERR(group))
375 return;
376
377 iommu_group_put(group);
378 }
379
380 static int iommu_init_device(struct device *dev)
381 {
382 struct iommu_dev_data *dev_data;
383 struct amd_iommu *iommu;
384 int devid;
385
386 if (dev->archdata.iommu)
387 return 0;
388
389 devid = get_device_id(dev);
390 if (devid < 0)
391 return devid;
392
393 iommu = amd_iommu_rlookup_table[devid];
394
395 dev_data = find_dev_data(devid);
396 if (!dev_data)
397 return -ENOMEM;
398
399 dev_data->pdev = setup_aliases(dev);
400
401 /*
402 * By default we use passthrough mode for IOMMUv2 capable device.
403 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
404 * invalid address), we ignore the capability for the device so
405 * it'll be forced to go into translation mode.
406 */
407 if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
408 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
409 struct amd_iommu *iommu;
410
411 iommu = amd_iommu_rlookup_table[dev_data->devid];
412 dev_data->iommu_v2 = iommu->is_iommu_v2;
413 }
414
415 dev->archdata.iommu = dev_data;
416
417 iommu_device_link(&iommu->iommu, dev);
418
419 return 0;
420 }
421
422 static void iommu_ignore_device(struct device *dev)
423 {
424 int devid;
425
426 devid = get_device_id(dev);
427 if (devid < 0)
428 return;
429
430 amd_iommu_rlookup_table[devid] = NULL;
431 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
432
433 setup_aliases(dev);
434 }
435
436 static void iommu_uninit_device(struct device *dev)
437 {
438 struct iommu_dev_data *dev_data;
439 struct amd_iommu *iommu;
440 int devid;
441
442 devid = get_device_id(dev);
443 if (devid < 0)
444 return;
445
446 iommu = amd_iommu_rlookup_table[devid];
447
448 dev_data = search_dev_data(devid);
449 if (!dev_data)
450 return;
451
452 if (dev_data->domain)
453 detach_device(dev);
454
455 iommu_device_unlink(&iommu->iommu, dev);
456
457 iommu_group_remove_device(dev);
458
459 /* Remove dma-ops */
460 dev->dma_ops = NULL;
461
462 /*
463 * We keep dev_data around for unplugged devices and reuse it when the
464 * device is re-plugged - not doing so would introduce a ton of races.
465 */
466 }
467
468 /*
469 * Helper function to get the first pte of a large mapping
470 */
471 static u64 *first_pte_l7(u64 *pte, unsigned long *page_size,
472 unsigned long *count)
473 {
474 unsigned long pte_mask, pg_size, cnt;
475 u64 *fpte;
476
477 pg_size = PTE_PAGE_SIZE(*pte);
478 cnt = PAGE_SIZE_PTE_COUNT(pg_size);
479 pte_mask = ~((cnt << 3) - 1);
480 fpte = (u64 *)(((unsigned long)pte) & pte_mask);
481
482 if (page_size)
483 *page_size = pg_size;
484
485 if (count)
486 *count = cnt;
487
488 return fpte;
489 }
490
491 /****************************************************************************
492 *
493 * Interrupt handling functions
494 *
495 ****************************************************************************/
496
497 static void dump_dte_entry(u16 devid)
498 {
499 int i;
500
501 for (i = 0; i < 4; ++i)
502 pr_err("DTE[%d]: %016llx\n", i,
503 amd_iommu_dev_table[devid].data[i]);
504 }
505
506 static void dump_command(unsigned long phys_addr)
507 {
508 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
509 int i;
510
511 for (i = 0; i < 4; ++i)
512 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
513 }
514
515 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
516 u64 address, int flags)
517 {
518 struct iommu_dev_data *dev_data = NULL;
519 struct pci_dev *pdev;
520
521 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
522 devid & 0xff);
523 if (pdev)
524 dev_data = get_dev_data(&pdev->dev);
525
526 if (dev_data && __ratelimit(&dev_data->rs)) {
527 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
528 domain_id, address, flags);
529 } else if (printk_ratelimit()) {
530 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
531 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
532 domain_id, address, flags);
533 }
534
535 if (pdev)
536 pci_dev_put(pdev);
537 }
538
539 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
540 {
541 struct device *dev = iommu->iommu.dev;
542 int type, devid, pasid, flags, tag;
543 volatile u32 *event = __evt;
544 int count = 0;
545 u64 address;
546
547 retry:
548 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
549 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
550 pasid = (event[0] & EVENT_DOMID_MASK_HI) |
551 (event[1] & EVENT_DOMID_MASK_LO);
552 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
553 address = (u64)(((u64)event[3]) << 32) | event[2];
554
555 if (type == 0) {
556 /* Did we hit the erratum? */
557 if (++count == LOOP_TIMEOUT) {
558 pr_err("No event written to event log\n");
559 return;
560 }
561 udelay(1);
562 goto retry;
563 }
564
565 if (type == EVENT_TYPE_IO_FAULT) {
566 amd_iommu_report_page_fault(devid, pasid, address, flags);
567 return;
568 }
569
570 switch (type) {
571 case EVENT_TYPE_ILL_DEV:
572 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
573 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
574 pasid, address, flags);
575 dump_dte_entry(devid);
576 break;
577 case EVENT_TYPE_DEV_TAB_ERR:
578 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
579 "address=0x%llx flags=0x%04x]\n",
580 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
581 address, flags);
582 break;
583 case EVENT_TYPE_PAGE_TAB_ERR:
584 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
585 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
586 pasid, address, flags);
587 break;
588 case EVENT_TYPE_ILL_CMD:
589 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
590 dump_command(address);
591 break;
592 case EVENT_TYPE_CMD_HARD_ERR:
593 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
594 address, flags);
595 break;
596 case EVENT_TYPE_IOTLB_INV_TO:
597 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
598 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
599 address);
600 break;
601 case EVENT_TYPE_INV_DEV_REQ:
602 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
603 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
604 pasid, address, flags);
605 break;
606 case EVENT_TYPE_INV_PPR_REQ:
607 pasid = PPR_PASID(*((u64 *)__evt));
608 tag = event[1] & 0x03FF;
609 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
610 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
611 pasid, address, flags, tag);
612 break;
613 default:
614 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
615 event[0], event[1], event[2], event[3]);
616 }
617
618 memset(__evt, 0, 4 * sizeof(u32));
619 }
620
621 static void iommu_poll_events(struct amd_iommu *iommu)
622 {
623 u32 head, tail;
624
625 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
626 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
627
628 while (head != tail) {
629 iommu_print_event(iommu, iommu->evt_buf + head);
630 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
631 }
632
633 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
634 }
635
636 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
637 {
638 struct amd_iommu_fault fault;
639
640 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
641 pr_err_ratelimited("Unknown PPR request received\n");
642 return;
643 }
644
645 fault.address = raw[1];
646 fault.pasid = PPR_PASID(raw[0]);
647 fault.device_id = PPR_DEVID(raw[0]);
648 fault.tag = PPR_TAG(raw[0]);
649 fault.flags = PPR_FLAGS(raw[0]);
650
651 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
652 }
653
654 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
655 {
656 u32 head, tail;
657
658 if (iommu->ppr_log == NULL)
659 return;
660
661 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
662 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
663
664 while (head != tail) {
665 volatile u64 *raw;
666 u64 entry[2];
667 int i;
668
669 raw = (u64 *)(iommu->ppr_log + head);
670
671 /*
672 * Hardware bug: Interrupt may arrive before the entry is
673 * written to memory. If this happens we need to wait for the
674 * entry to arrive.
675 */
676 for (i = 0; i < LOOP_TIMEOUT; ++i) {
677 if (PPR_REQ_TYPE(raw[0]) != 0)
678 break;
679 udelay(1);
680 }
681
682 /* Avoid memcpy function-call overhead */
683 entry[0] = raw[0];
684 entry[1] = raw[1];
685
686 /*
687 * To detect the hardware bug we need to clear the entry
688 * back to zero.
689 */
690 raw[0] = raw[1] = 0UL;
691
692 /* Update head pointer of hardware ring-buffer */
693 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
694 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
695
696 /* Handle PPR entry */
697 iommu_handle_ppr_entry(iommu, entry);
698
699 /* Refresh ring-buffer information */
700 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
701 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
702 }
703 }
704
705 #ifdef CONFIG_IRQ_REMAP
706 static int (*iommu_ga_log_notifier)(u32);
707
708 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
709 {
710 iommu_ga_log_notifier = notifier;
711
712 return 0;
713 }
714 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
715
716 static void iommu_poll_ga_log(struct amd_iommu *iommu)
717 {
718 u32 head, tail, cnt = 0;
719
720 if (iommu->ga_log == NULL)
721 return;
722
723 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
724 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
725
726 while (head != tail) {
727 volatile u64 *raw;
728 u64 log_entry;
729
730 raw = (u64 *)(iommu->ga_log + head);
731 cnt++;
732
733 /* Avoid memcpy function-call overhead */
734 log_entry = *raw;
735
736 /* Update head pointer of hardware ring-buffer */
737 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
738 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
739
740 /* Handle GA entry */
741 switch (GA_REQ_TYPE(log_entry)) {
742 case GA_GUEST_NR:
743 if (!iommu_ga_log_notifier)
744 break;
745
746 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
747 __func__, GA_DEVID(log_entry),
748 GA_TAG(log_entry));
749
750 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
751 pr_err("GA log notifier failed.\n");
752 break;
753 default:
754 break;
755 }
756 }
757 }
758 #endif /* CONFIG_IRQ_REMAP */
759
760 #define AMD_IOMMU_INT_MASK \
761 (MMIO_STATUS_EVT_INT_MASK | \
762 MMIO_STATUS_PPR_INT_MASK | \
763 MMIO_STATUS_GALOG_INT_MASK)
764
765 irqreturn_t amd_iommu_int_thread(int irq, void *data)
766 {
767 struct amd_iommu *iommu = (struct amd_iommu *) data;
768 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
769
770 while (status & AMD_IOMMU_INT_MASK) {
771 /* Enable EVT and PPR and GA interrupts again */
772 writel(AMD_IOMMU_INT_MASK,
773 iommu->mmio_base + MMIO_STATUS_OFFSET);
774
775 if (status & MMIO_STATUS_EVT_INT_MASK) {
776 pr_devel("Processing IOMMU Event Log\n");
777 iommu_poll_events(iommu);
778 }
779
780 if (status & MMIO_STATUS_PPR_INT_MASK) {
781 pr_devel("Processing IOMMU PPR Log\n");
782 iommu_poll_ppr_log(iommu);
783 }
784
785 #ifdef CONFIG_IRQ_REMAP
786 if (status & MMIO_STATUS_GALOG_INT_MASK) {
787 pr_devel("Processing IOMMU GA Log\n");
788 iommu_poll_ga_log(iommu);
789 }
790 #endif
791
792 /*
793 * Hardware bug: ERBT1312
794 * When re-enabling interrupt (by writing 1
795 * to clear the bit), the hardware might also try to set
796 * the interrupt bit in the event status register.
797 * In this scenario, the bit will be set, and disable
798 * subsequent interrupts.
799 *
800 * Workaround: The IOMMU driver should read back the
801 * status register and check if the interrupt bits are cleared.
802 * If not, driver will need to go through the interrupt handler
803 * again and re-clear the bits
804 */
805 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
806 }
807 return IRQ_HANDLED;
808 }
809
810 irqreturn_t amd_iommu_int_handler(int irq, void *data)
811 {
812 return IRQ_WAKE_THREAD;
813 }
814
815 /****************************************************************************
816 *
817 * IOMMU command queuing functions
818 *
819 ****************************************************************************/
820
821 static int wait_on_sem(volatile u64 *sem)
822 {
823 int i = 0;
824
825 while (*sem == 0 && i < LOOP_TIMEOUT) {
826 udelay(1);
827 i += 1;
828 }
829
830 if (i == LOOP_TIMEOUT) {
831 pr_alert("Completion-Wait loop timed out\n");
832 return -EIO;
833 }
834
835 return 0;
836 }
837
838 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
839 struct iommu_cmd *cmd)
840 {
841 u8 *target;
842 u32 tail;
843
844 /* Copy command to buffer */
845 tail = iommu->cmd_buf_tail;
846 target = iommu->cmd_buf + tail;
847 memcpy(target, cmd, sizeof(*cmd));
848
849 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
850 iommu->cmd_buf_tail = tail;
851
852 /* Tell the IOMMU about it */
853 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
854 }
855
856 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
857 {
858 u64 paddr = iommu_virt_to_phys((void *)address);
859
860 WARN_ON(address & 0x7ULL);
861
862 memset(cmd, 0, sizeof(*cmd));
863 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
864 cmd->data[1] = upper_32_bits(paddr);
865 cmd->data[2] = 1;
866 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
867 }
868
869 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
870 {
871 memset(cmd, 0, sizeof(*cmd));
872 cmd->data[0] = devid;
873 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
874 }
875
876 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
877 size_t size, u16 domid, int pde)
878 {
879 u64 pages;
880 bool s;
881
882 pages = iommu_num_pages(address, size, PAGE_SIZE);
883 s = false;
884
885 if (pages > 1) {
886 /*
887 * If we have to flush more than one page, flush all
888 * TLB entries for this domain
889 */
890 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
891 s = true;
892 }
893
894 address &= PAGE_MASK;
895
896 memset(cmd, 0, sizeof(*cmd));
897 cmd->data[1] |= domid;
898 cmd->data[2] = lower_32_bits(address);
899 cmd->data[3] = upper_32_bits(address);
900 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
901 if (s) /* size bit - we flush more than one 4kb page */
902 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
903 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
904 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
905 }
906
907 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
908 u64 address, size_t size)
909 {
910 u64 pages;
911 bool s;
912
913 pages = iommu_num_pages(address, size, PAGE_SIZE);
914 s = false;
915
916 if (pages > 1) {
917 /*
918 * If we have to flush more than one page, flush all
919 * TLB entries for this domain
920 */
921 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
922 s = true;
923 }
924
925 address &= PAGE_MASK;
926
927 memset(cmd, 0, sizeof(*cmd));
928 cmd->data[0] = devid;
929 cmd->data[0] |= (qdep & 0xff) << 24;
930 cmd->data[1] = devid;
931 cmd->data[2] = lower_32_bits(address);
932 cmd->data[3] = upper_32_bits(address);
933 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
934 if (s)
935 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
936 }
937
938 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
939 u64 address, bool size)
940 {
941 memset(cmd, 0, sizeof(*cmd));
942
943 address &= ~(0xfffULL);
944
945 cmd->data[0] = pasid;
946 cmd->data[1] = domid;
947 cmd->data[2] = lower_32_bits(address);
948 cmd->data[3] = upper_32_bits(address);
949 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
950 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
951 if (size)
952 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
953 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
954 }
955
956 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
957 int qdep, u64 address, bool size)
958 {
959 memset(cmd, 0, sizeof(*cmd));
960
961 address &= ~(0xfffULL);
962
963 cmd->data[0] = devid;
964 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
965 cmd->data[0] |= (qdep & 0xff) << 24;
966 cmd->data[1] = devid;
967 cmd->data[1] |= (pasid & 0xff) << 16;
968 cmd->data[2] = lower_32_bits(address);
969 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
970 cmd->data[3] = upper_32_bits(address);
971 if (size)
972 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
973 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
974 }
975
976 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
977 int status, int tag, bool gn)
978 {
979 memset(cmd, 0, sizeof(*cmd));
980
981 cmd->data[0] = devid;
982 if (gn) {
983 cmd->data[1] = pasid;
984 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
985 }
986 cmd->data[3] = tag & 0x1ff;
987 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
988
989 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
990 }
991
992 static void build_inv_all(struct iommu_cmd *cmd)
993 {
994 memset(cmd, 0, sizeof(*cmd));
995 CMD_SET_TYPE(cmd, CMD_INV_ALL);
996 }
997
998 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
999 {
1000 memset(cmd, 0, sizeof(*cmd));
1001 cmd->data[0] = devid;
1002 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1003 }
1004
1005 /*
1006 * Writes the command to the IOMMUs command buffer and informs the
1007 * hardware about the new command.
1008 */
1009 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1010 struct iommu_cmd *cmd,
1011 bool sync)
1012 {
1013 unsigned int count = 0;
1014 u32 left, next_tail;
1015
1016 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1017 again:
1018 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1019
1020 if (left <= 0x20) {
1021 /* Skip udelay() the first time around */
1022 if (count++) {
1023 if (count == LOOP_TIMEOUT) {
1024 pr_err("Command buffer timeout\n");
1025 return -EIO;
1026 }
1027
1028 udelay(1);
1029 }
1030
1031 /* Update head and recheck remaining space */
1032 iommu->cmd_buf_head = readl(iommu->mmio_base +
1033 MMIO_CMD_HEAD_OFFSET);
1034
1035 goto again;
1036 }
1037
1038 copy_cmd_to_buffer(iommu, cmd);
1039
1040 /* Do we need to make sure all commands are processed? */
1041 iommu->need_sync = sync;
1042
1043 return 0;
1044 }
1045
1046 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1047 struct iommu_cmd *cmd,
1048 bool sync)
1049 {
1050 unsigned long flags;
1051 int ret;
1052
1053 raw_spin_lock_irqsave(&iommu->lock, flags);
1054 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1055 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1056
1057 return ret;
1058 }
1059
1060 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1061 {
1062 return iommu_queue_command_sync(iommu, cmd, true);
1063 }
1064
1065 /*
1066 * This function queues a completion wait command into the command
1067 * buffer of an IOMMU
1068 */
1069 static int iommu_completion_wait(struct amd_iommu *iommu)
1070 {
1071 struct iommu_cmd cmd;
1072 unsigned long flags;
1073 int ret;
1074
1075 if (!iommu->need_sync)
1076 return 0;
1077
1078
1079 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1080
1081 raw_spin_lock_irqsave(&iommu->lock, flags);
1082
1083 iommu->cmd_sem = 0;
1084
1085 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1086 if (ret)
1087 goto out_unlock;
1088
1089 ret = wait_on_sem(&iommu->cmd_sem);
1090
1091 out_unlock:
1092 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1093
1094 return ret;
1095 }
1096
1097 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1098 {
1099 struct iommu_cmd cmd;
1100
1101 build_inv_dte(&cmd, devid);
1102
1103 return iommu_queue_command(iommu, &cmd);
1104 }
1105
1106 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1107 {
1108 u32 devid;
1109
1110 for (devid = 0; devid <= 0xffff; ++devid)
1111 iommu_flush_dte(iommu, devid);
1112
1113 iommu_completion_wait(iommu);
1114 }
1115
1116 /*
1117 * This function uses heavy locking and may disable irqs for some time. But
1118 * this is no issue because it is only called during resume.
1119 */
1120 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1121 {
1122 u32 dom_id;
1123
1124 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1125 struct iommu_cmd cmd;
1126 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1127 dom_id, 1);
1128 iommu_queue_command(iommu, &cmd);
1129 }
1130
1131 iommu_completion_wait(iommu);
1132 }
1133
1134 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1135 {
1136 struct iommu_cmd cmd;
1137
1138 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1139 dom_id, 1);
1140 iommu_queue_command(iommu, &cmd);
1141
1142 iommu_completion_wait(iommu);
1143 }
1144
1145 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1146 {
1147 struct iommu_cmd cmd;
1148
1149 build_inv_all(&cmd);
1150
1151 iommu_queue_command(iommu, &cmd);
1152 iommu_completion_wait(iommu);
1153 }
1154
1155 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1156 {
1157 struct iommu_cmd cmd;
1158
1159 build_inv_irt(&cmd, devid);
1160
1161 iommu_queue_command(iommu, &cmd);
1162 }
1163
1164 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1165 {
1166 u32 devid;
1167
1168 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1169 iommu_flush_irt(iommu, devid);
1170
1171 iommu_completion_wait(iommu);
1172 }
1173
1174 void iommu_flush_all_caches(struct amd_iommu *iommu)
1175 {
1176 if (iommu_feature(iommu, FEATURE_IA)) {
1177 amd_iommu_flush_all(iommu);
1178 } else {
1179 amd_iommu_flush_dte_all(iommu);
1180 amd_iommu_flush_irt_all(iommu);
1181 amd_iommu_flush_tlb_all(iommu);
1182 }
1183 }
1184
1185 /*
1186 * Command send function for flushing on-device TLB
1187 */
1188 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1189 u64 address, size_t size)
1190 {
1191 struct amd_iommu *iommu;
1192 struct iommu_cmd cmd;
1193 int qdep;
1194
1195 qdep = dev_data->ats.qdep;
1196 iommu = amd_iommu_rlookup_table[dev_data->devid];
1197
1198 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1199
1200 return iommu_queue_command(iommu, &cmd);
1201 }
1202
1203 static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data)
1204 {
1205 struct amd_iommu *iommu = data;
1206
1207 return iommu_flush_dte(iommu, alias);
1208 }
1209
1210 /*
1211 * Command send function for invalidating a device table entry
1212 */
1213 static int device_flush_dte(struct iommu_dev_data *dev_data)
1214 {
1215 struct amd_iommu *iommu;
1216 u16 alias;
1217 int ret;
1218
1219 iommu = amd_iommu_rlookup_table[dev_data->devid];
1220
1221 if (dev_data->pdev)
1222 ret = pci_for_each_dma_alias(dev_data->pdev,
1223 device_flush_dte_alias, iommu);
1224 else
1225 ret = iommu_flush_dte(iommu, dev_data->devid);
1226 if (ret)
1227 return ret;
1228
1229 alias = amd_iommu_alias_table[dev_data->devid];
1230 if (alias != dev_data->devid) {
1231 ret = iommu_flush_dte(iommu, alias);
1232 if (ret)
1233 return ret;
1234 }
1235
1236 if (dev_data->ats.enabled)
1237 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1238
1239 return ret;
1240 }
1241
1242 /*
1243 * TLB invalidation function which is called from the mapping functions.
1244 * It invalidates a single PTE if the range to flush is within a single
1245 * page. Otherwise it flushes the whole TLB of the IOMMU.
1246 */
1247 static void __domain_flush_pages(struct protection_domain *domain,
1248 u64 address, size_t size, int pde)
1249 {
1250 struct iommu_dev_data *dev_data;
1251 struct iommu_cmd cmd;
1252 int ret = 0, i;
1253
1254 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1255
1256 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1257 if (!domain->dev_iommu[i])
1258 continue;
1259
1260 /*
1261 * Devices of this domain are behind this IOMMU
1262 * We need a TLB flush
1263 */
1264 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1265 }
1266
1267 list_for_each_entry(dev_data, &domain->dev_list, list) {
1268
1269 if (!dev_data->ats.enabled)
1270 continue;
1271
1272 ret |= device_flush_iotlb(dev_data, address, size);
1273 }
1274
1275 WARN_ON(ret);
1276 }
1277
1278 static void domain_flush_pages(struct protection_domain *domain,
1279 u64 address, size_t size)
1280 {
1281 __domain_flush_pages(domain, address, size, 0);
1282 }
1283
1284 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1285 static void domain_flush_tlb_pde(struct protection_domain *domain)
1286 {
1287 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1288 }
1289
1290 static void domain_flush_complete(struct protection_domain *domain)
1291 {
1292 int i;
1293
1294 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1295 if (domain && !domain->dev_iommu[i])
1296 continue;
1297
1298 /*
1299 * Devices of this domain are behind this IOMMU
1300 * We need to wait for completion of all commands.
1301 */
1302 iommu_completion_wait(amd_iommus[i]);
1303 }
1304 }
1305
1306 /* Flush the not present cache if it exists */
1307 static void domain_flush_np_cache(struct protection_domain *domain,
1308 dma_addr_t iova, size_t size)
1309 {
1310 if (unlikely(amd_iommu_np_cache)) {
1311 unsigned long flags;
1312
1313 spin_lock_irqsave(&domain->lock, flags);
1314 domain_flush_pages(domain, iova, size);
1315 domain_flush_complete(domain);
1316 spin_unlock_irqrestore(&domain->lock, flags);
1317 }
1318 }
1319
1320
1321 /*
1322 * This function flushes the DTEs for all devices in domain
1323 */
1324 static void domain_flush_devices(struct protection_domain *domain)
1325 {
1326 struct iommu_dev_data *dev_data;
1327
1328 list_for_each_entry(dev_data, &domain->dev_list, list)
1329 device_flush_dte(dev_data);
1330 }
1331
1332 /****************************************************************************
1333 *
1334 * The functions below are used the create the page table mappings for
1335 * unity mapped regions.
1336 *
1337 ****************************************************************************/
1338
1339 static void free_page_list(struct page *freelist)
1340 {
1341 while (freelist != NULL) {
1342 unsigned long p = (unsigned long)page_address(freelist);
1343 freelist = freelist->freelist;
1344 free_page(p);
1345 }
1346 }
1347
1348 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1349 {
1350 struct page *p = virt_to_page((void *)pt);
1351
1352 p->freelist = freelist;
1353
1354 return p;
1355 }
1356
1357 #define DEFINE_FREE_PT_FN(LVL, FN) \
1358 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1359 { \
1360 unsigned long p; \
1361 u64 *pt; \
1362 int i; \
1363 \
1364 pt = (u64 *)__pt; \
1365 \
1366 for (i = 0; i < 512; ++i) { \
1367 /* PTE present? */ \
1368 if (!IOMMU_PTE_PRESENT(pt[i])) \
1369 continue; \
1370 \
1371 /* Large PTE? */ \
1372 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1373 PM_PTE_LEVEL(pt[i]) == 7) \
1374 continue; \
1375 \
1376 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1377 freelist = FN(p, freelist); \
1378 } \
1379 \
1380 return free_pt_page((unsigned long)pt, freelist); \
1381 }
1382
1383 DEFINE_FREE_PT_FN(l2, free_pt_page)
1384 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1385 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1386 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1387 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1388
1389 static struct page *free_sub_pt(unsigned long root, int mode,
1390 struct page *freelist)
1391 {
1392 switch (mode) {
1393 case PAGE_MODE_NONE:
1394 case PAGE_MODE_7_LEVEL:
1395 break;
1396 case PAGE_MODE_1_LEVEL:
1397 freelist = free_pt_page(root, freelist);
1398 break;
1399 case PAGE_MODE_2_LEVEL:
1400 freelist = free_pt_l2(root, freelist);
1401 break;
1402 case PAGE_MODE_3_LEVEL:
1403 freelist = free_pt_l3(root, freelist);
1404 break;
1405 case PAGE_MODE_4_LEVEL:
1406 freelist = free_pt_l4(root, freelist);
1407 break;
1408 case PAGE_MODE_5_LEVEL:
1409 freelist = free_pt_l5(root, freelist);
1410 break;
1411 case PAGE_MODE_6_LEVEL:
1412 freelist = free_pt_l6(root, freelist);
1413 break;
1414 default:
1415 BUG();
1416 }
1417
1418 return freelist;
1419 }
1420
1421 static void free_pagetable(struct protection_domain *domain)
1422 {
1423 struct domain_pgtable pgtable;
1424 struct page *freelist = NULL;
1425 unsigned long root;
1426
1427 amd_iommu_domain_get_pgtable(domain, &pgtable);
1428 atomic64_set(&domain->pt_root, 0);
1429
1430 BUG_ON(pgtable.mode < PAGE_MODE_NONE ||
1431 pgtable.mode > PAGE_MODE_6_LEVEL);
1432
1433 root = (unsigned long)pgtable.root;
1434 freelist = free_sub_pt(root, pgtable.mode, freelist);
1435
1436 free_page_list(freelist);
1437 }
1438
1439 /*
1440 * This function is used to add another level to an IO page table. Adding
1441 * another level increases the size of the address space by 9 bits to a size up
1442 * to 64 bits.
1443 */
1444 static bool increase_address_space(struct protection_domain *domain,
1445 unsigned long address,
1446 gfp_t gfp)
1447 {
1448 struct domain_pgtable pgtable;
1449 unsigned long flags;
1450 bool ret = true;
1451 u64 *pte, root;
1452
1453 spin_lock_irqsave(&domain->lock, flags);
1454
1455 amd_iommu_domain_get_pgtable(domain, &pgtable);
1456
1457 if (address <= PM_LEVEL_SIZE(pgtable.mode))
1458 goto out;
1459
1460 ret = false;
1461 if (WARN_ON_ONCE(pgtable.mode == PAGE_MODE_6_LEVEL))
1462 goto out;
1463
1464 pte = (void *)get_zeroed_page(gfp);
1465 if (!pte)
1466 goto out;
1467
1468 *pte = PM_LEVEL_PDE(pgtable.mode, iommu_virt_to_phys(pgtable.root));
1469
1470 pgtable.root = pte;
1471 pgtable.mode += 1;
1472 update_and_flush_device_table(domain, &pgtable);
1473 domain_flush_complete(domain);
1474
1475 /*
1476 * Device Table needs to be updated and flushed before the new root can
1477 * be published.
1478 */
1479 root = amd_iommu_domain_encode_pgtable(pte, pgtable.mode);
1480 atomic64_set(&domain->pt_root, root);
1481
1482 ret = true;
1483
1484 out:
1485 spin_unlock_irqrestore(&domain->lock, flags);
1486
1487 return ret;
1488 }
1489
1490 static u64 *alloc_pte(struct protection_domain *domain,
1491 unsigned long address,
1492 unsigned long page_size,
1493 u64 **pte_page,
1494 gfp_t gfp,
1495 bool *updated)
1496 {
1497 struct domain_pgtable pgtable;
1498 int level, end_lvl;
1499 u64 *pte, *page;
1500
1501 BUG_ON(!is_power_of_2(page_size));
1502
1503 amd_iommu_domain_get_pgtable(domain, &pgtable);
1504
1505 while (address > PM_LEVEL_SIZE(pgtable.mode)) {
1506 /*
1507 * Return an error if there is no memory to update the
1508 * page-table.
1509 */
1510 if (!increase_address_space(domain, address, gfp))
1511 return NULL;
1512
1513 /* Read new values to check if update was successful */
1514 amd_iommu_domain_get_pgtable(domain, &pgtable);
1515 }
1516
1517
1518 level = pgtable.mode - 1;
1519 pte = &pgtable.root[PM_LEVEL_INDEX(level, address)];
1520 address = PAGE_SIZE_ALIGN(address, page_size);
1521 end_lvl = PAGE_SIZE_LEVEL(page_size);
1522
1523 while (level > end_lvl) {
1524 u64 __pte, __npte;
1525 int pte_level;
1526
1527 __pte = *pte;
1528 pte_level = PM_PTE_LEVEL(__pte);
1529
1530 /*
1531 * If we replace a series of large PTEs, we need
1532 * to tear down all of them.
1533 */
1534 if (IOMMU_PTE_PRESENT(__pte) &&
1535 pte_level == PAGE_MODE_7_LEVEL) {
1536 unsigned long count, i;
1537 u64 *lpte;
1538
1539 lpte = first_pte_l7(pte, NULL, &count);
1540
1541 /*
1542 * Unmap the replicated PTEs that still match the
1543 * original large mapping
1544 */
1545 for (i = 0; i < count; ++i)
1546 cmpxchg64(&lpte[i], __pte, 0ULL);
1547
1548 *updated = true;
1549 continue;
1550 }
1551
1552 if (!IOMMU_PTE_PRESENT(__pte) ||
1553 pte_level == PAGE_MODE_NONE) {
1554 page = (u64 *)get_zeroed_page(gfp);
1555
1556 if (!page)
1557 return NULL;
1558
1559 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1560
1561 /* pte could have been changed somewhere. */
1562 if (cmpxchg64(pte, __pte, __npte) != __pte)
1563 free_page((unsigned long)page);
1564 else if (IOMMU_PTE_PRESENT(__pte))
1565 *updated = true;
1566
1567 continue;
1568 }
1569
1570 /* No level skipping support yet */
1571 if (pte_level != level)
1572 return NULL;
1573
1574 level -= 1;
1575
1576 pte = IOMMU_PTE_PAGE(__pte);
1577
1578 if (pte_page && level == end_lvl)
1579 *pte_page = pte;
1580
1581 pte = &pte[PM_LEVEL_INDEX(level, address)];
1582 }
1583
1584 return pte;
1585 }
1586
1587 /*
1588 * This function checks if there is a PTE for a given dma address. If
1589 * there is one, it returns the pointer to it.
1590 */
1591 static u64 *fetch_pte(struct protection_domain *domain,
1592 unsigned long address,
1593 unsigned long *page_size)
1594 {
1595 struct domain_pgtable pgtable;
1596 int level;
1597 u64 *pte;
1598
1599 *page_size = 0;
1600
1601 amd_iommu_domain_get_pgtable(domain, &pgtable);
1602
1603 if (address > PM_LEVEL_SIZE(pgtable.mode))
1604 return NULL;
1605
1606 level = pgtable.mode - 1;
1607 pte = &pgtable.root[PM_LEVEL_INDEX(level, address)];
1608 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1609
1610 while (level > 0) {
1611
1612 /* Not Present */
1613 if (!IOMMU_PTE_PRESENT(*pte))
1614 return NULL;
1615
1616 /* Large PTE */
1617 if (PM_PTE_LEVEL(*pte) == 7 ||
1618 PM_PTE_LEVEL(*pte) == 0)
1619 break;
1620
1621 /* No level skipping support yet */
1622 if (PM_PTE_LEVEL(*pte) != level)
1623 return NULL;
1624
1625 level -= 1;
1626
1627 /* Walk to the next level */
1628 pte = IOMMU_PTE_PAGE(*pte);
1629 pte = &pte[PM_LEVEL_INDEX(level, address)];
1630 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1631 }
1632
1633 /*
1634 * If we have a series of large PTEs, make
1635 * sure to return a pointer to the first one.
1636 */
1637 if (PM_PTE_LEVEL(*pte) == PAGE_MODE_7_LEVEL)
1638 pte = first_pte_l7(pte, page_size, NULL);
1639
1640 return pte;
1641 }
1642
1643 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1644 {
1645 unsigned long pt;
1646 int mode;
1647
1648 while (cmpxchg64(pte, pteval, 0) != pteval) {
1649 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1650 pteval = *pte;
1651 }
1652
1653 if (!IOMMU_PTE_PRESENT(pteval))
1654 return freelist;
1655
1656 pt = (unsigned long)IOMMU_PTE_PAGE(pteval);
1657 mode = IOMMU_PTE_MODE(pteval);
1658
1659 return free_sub_pt(pt, mode, freelist);
1660 }
1661
1662 /*
1663 * Generic mapping functions. It maps a physical address into a DMA
1664 * address space. It allocates the page table pages if necessary.
1665 * In the future it can be extended to a generic mapping function
1666 * supporting all features of AMD IOMMU page tables like level skipping
1667 * and full 64 bit address spaces.
1668 */
1669 static int iommu_map_page(struct protection_domain *dom,
1670 unsigned long bus_addr,
1671 unsigned long phys_addr,
1672 unsigned long page_size,
1673 int prot,
1674 gfp_t gfp)
1675 {
1676 struct page *freelist = NULL;
1677 bool updated = false;
1678 u64 __pte, *pte;
1679 int ret, i, count;
1680
1681 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1682 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1683
1684 ret = -EINVAL;
1685 if (!(prot & IOMMU_PROT_MASK))
1686 goto out;
1687
1688 count = PAGE_SIZE_PTE_COUNT(page_size);
1689 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp, &updated);
1690
1691 ret = -ENOMEM;
1692 if (!pte)
1693 goto out;
1694
1695 for (i = 0; i < count; ++i)
1696 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1697
1698 if (freelist != NULL)
1699 updated = true;
1700
1701 if (count > 1) {
1702 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1703 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1704 } else
1705 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1706
1707 if (prot & IOMMU_PROT_IR)
1708 __pte |= IOMMU_PTE_IR;
1709 if (prot & IOMMU_PROT_IW)
1710 __pte |= IOMMU_PTE_IW;
1711
1712 for (i = 0; i < count; ++i)
1713 pte[i] = __pte;
1714
1715 ret = 0;
1716
1717 out:
1718 if (updated) {
1719 unsigned long flags;
1720
1721 spin_lock_irqsave(&dom->lock, flags);
1722 /*
1723 * Flush domain TLB(s) and wait for completion. Any Device-Table
1724 * Updates and flushing already happened in
1725 * increase_address_space().
1726 */
1727 domain_flush_tlb_pde(dom);
1728 domain_flush_complete(dom);
1729 spin_unlock_irqrestore(&dom->lock, flags);
1730 }
1731
1732 /* Everything flushed out, free pages now */
1733 free_page_list(freelist);
1734
1735 return ret;
1736 }
1737
1738 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1739 unsigned long bus_addr,
1740 unsigned long page_size)
1741 {
1742 unsigned long long unmapped;
1743 unsigned long unmap_size;
1744 u64 *pte;
1745
1746 BUG_ON(!is_power_of_2(page_size));
1747
1748 unmapped = 0;
1749
1750 while (unmapped < page_size) {
1751
1752 pte = fetch_pte(dom, bus_addr, &unmap_size);
1753
1754 if (pte) {
1755 int i, count;
1756
1757 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1758 for (i = 0; i < count; i++)
1759 pte[i] = 0ULL;
1760 }
1761
1762 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1763 unmapped += unmap_size;
1764 }
1765
1766 BUG_ON(unmapped && !is_power_of_2(unmapped));
1767
1768 return unmapped;
1769 }
1770
1771 /****************************************************************************
1772 *
1773 * The next functions belong to the domain allocation. A domain is
1774 * allocated for every IOMMU as the default domain. If device isolation
1775 * is enabled, every device get its own domain. The most important thing
1776 * about domains is the page table mapping the DMA address space they
1777 * contain.
1778 *
1779 ****************************************************************************/
1780
1781 static u16 domain_id_alloc(void)
1782 {
1783 int id;
1784
1785 spin_lock(&pd_bitmap_lock);
1786 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1787 BUG_ON(id == 0);
1788 if (id > 0 && id < MAX_DOMAIN_ID)
1789 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1790 else
1791 id = 0;
1792 spin_unlock(&pd_bitmap_lock);
1793
1794 return id;
1795 }
1796
1797 static void domain_id_free(int id)
1798 {
1799 spin_lock(&pd_bitmap_lock);
1800 if (id > 0 && id < MAX_DOMAIN_ID)
1801 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1802 spin_unlock(&pd_bitmap_lock);
1803 }
1804
1805 static void free_gcr3_tbl_level1(u64 *tbl)
1806 {
1807 u64 *ptr;
1808 int i;
1809
1810 for (i = 0; i < 512; ++i) {
1811 if (!(tbl[i] & GCR3_VALID))
1812 continue;
1813
1814 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1815
1816 free_page((unsigned long)ptr);
1817 }
1818 }
1819
1820 static void free_gcr3_tbl_level2(u64 *tbl)
1821 {
1822 u64 *ptr;
1823 int i;
1824
1825 for (i = 0; i < 512; ++i) {
1826 if (!(tbl[i] & GCR3_VALID))
1827 continue;
1828
1829 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1830
1831 free_gcr3_tbl_level1(ptr);
1832 }
1833 }
1834
1835 static void free_gcr3_table(struct protection_domain *domain)
1836 {
1837 if (domain->glx == 2)
1838 free_gcr3_tbl_level2(domain->gcr3_tbl);
1839 else if (domain->glx == 1)
1840 free_gcr3_tbl_level1(domain->gcr3_tbl);
1841 else
1842 BUG_ON(domain->glx != 0);
1843
1844 free_page((unsigned long)domain->gcr3_tbl);
1845 }
1846
1847 /*
1848 * Free a domain, only used if something went wrong in the
1849 * allocation path and we need to free an already allocated page table
1850 */
1851 static void dma_ops_domain_free(struct protection_domain *domain)
1852 {
1853 if (!domain)
1854 return;
1855
1856 iommu_put_dma_cookie(&domain->domain);
1857
1858 free_pagetable(domain);
1859
1860 if (domain->id)
1861 domain_id_free(domain->id);
1862
1863 kfree(domain);
1864 }
1865
1866 /*
1867 * Allocates a new protection domain usable for the dma_ops functions.
1868 * It also initializes the page table and the address allocator data
1869 * structures required for the dma_ops interface
1870 */
1871 static struct protection_domain *dma_ops_domain_alloc(void)
1872 {
1873 struct protection_domain *domain;
1874 u64 *pt_root, root;
1875
1876 domain = kzalloc(sizeof(struct protection_domain), GFP_KERNEL);
1877 if (!domain)
1878 return NULL;
1879
1880 if (protection_domain_init(domain))
1881 goto free_domain;
1882
1883 pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1884 if (!pt_root)
1885 goto free_domain;
1886
1887 root = amd_iommu_domain_encode_pgtable(pt_root, PAGE_MODE_3_LEVEL);
1888 atomic64_set(&domain->pt_root, root);
1889 domain->flags = PD_DMA_OPS_MASK;
1890
1891 if (iommu_get_dma_cookie(&domain->domain) == -ENOMEM)
1892 goto free_domain;
1893
1894 return domain;
1895
1896 free_domain:
1897 dma_ops_domain_free(domain);
1898
1899 return NULL;
1900 }
1901
1902 /*
1903 * little helper function to check whether a given protection domain is a
1904 * dma_ops domain
1905 */
1906 static bool dma_ops_domain(struct protection_domain *domain)
1907 {
1908 return domain->flags & PD_DMA_OPS_MASK;
1909 }
1910
1911 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1912 struct domain_pgtable *pgtable,
1913 bool ats, bool ppr)
1914 {
1915 u64 pte_root = 0;
1916 u64 flags = 0;
1917 u32 old_domid;
1918
1919 if (pgtable->mode != PAGE_MODE_NONE)
1920 pte_root = iommu_virt_to_phys(pgtable->root);
1921
1922 pte_root |= (pgtable->mode & DEV_ENTRY_MODE_MASK)
1923 << DEV_ENTRY_MODE_SHIFT;
1924 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1925
1926 flags = amd_iommu_dev_table[devid].data[1];
1927
1928 if (ats)
1929 flags |= DTE_FLAG_IOTLB;
1930
1931 if (ppr) {
1932 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1933
1934 if (iommu_feature(iommu, FEATURE_EPHSUP))
1935 pte_root |= 1ULL << DEV_ENTRY_PPR;
1936 }
1937
1938 if (domain->flags & PD_IOMMUV2_MASK) {
1939 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1940 u64 glx = domain->glx;
1941 u64 tmp;
1942
1943 pte_root |= DTE_FLAG_GV;
1944 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1945
1946 /* First mask out possible old values for GCR3 table */
1947 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1948 flags &= ~tmp;
1949
1950 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1951 flags &= ~tmp;
1952
1953 /* Encode GCR3 table into DTE */
1954 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1955 pte_root |= tmp;
1956
1957 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1958 flags |= tmp;
1959
1960 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1961 flags |= tmp;
1962 }
1963
1964 flags &= ~DEV_DOMID_MASK;
1965 flags |= domain->id;
1966
1967 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
1968 amd_iommu_dev_table[devid].data[1] = flags;
1969 amd_iommu_dev_table[devid].data[0] = pte_root;
1970
1971 /*
1972 * A kdump kernel might be replacing a domain ID that was copied from
1973 * the previous kernel--if so, it needs to flush the translation cache
1974 * entries for the old domain ID that is being overwritten
1975 */
1976 if (old_domid) {
1977 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1978
1979 amd_iommu_flush_tlb_domid(iommu, old_domid);
1980 }
1981 }
1982
1983 static void clear_dte_entry(u16 devid)
1984 {
1985 /* remove entry from the device table seen by the hardware */
1986 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1987 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1988
1989 amd_iommu_apply_erratum_63(devid);
1990 }
1991
1992 static void do_attach(struct iommu_dev_data *dev_data,
1993 struct protection_domain *domain)
1994 {
1995 struct domain_pgtable pgtable;
1996 struct amd_iommu *iommu;
1997 bool ats;
1998
1999 iommu = amd_iommu_rlookup_table[dev_data->devid];
2000 ats = dev_data->ats.enabled;
2001
2002 /* Update data structures */
2003 dev_data->domain = domain;
2004 list_add(&dev_data->list, &domain->dev_list);
2005
2006 /* Do reference counting */
2007 domain->dev_iommu[iommu->index] += 1;
2008 domain->dev_cnt += 1;
2009
2010 /* Update device table */
2011 amd_iommu_domain_get_pgtable(domain, &pgtable);
2012 set_dte_entry(dev_data->devid, domain, &pgtable,
2013 ats, dev_data->iommu_v2);
2014 clone_aliases(dev_data->pdev);
2015
2016 device_flush_dte(dev_data);
2017 }
2018
2019 static void do_detach(struct iommu_dev_data *dev_data)
2020 {
2021 struct protection_domain *domain = dev_data->domain;
2022 struct amd_iommu *iommu;
2023
2024 iommu = amd_iommu_rlookup_table[dev_data->devid];
2025
2026 /* Update data structures */
2027 dev_data->domain = NULL;
2028 list_del(&dev_data->list);
2029 clear_dte_entry(dev_data->devid);
2030 clone_aliases(dev_data->pdev);
2031
2032 /* Flush the DTE entry */
2033 device_flush_dte(dev_data);
2034
2035 /* Flush IOTLB */
2036 domain_flush_tlb_pde(domain);
2037
2038 /* Wait for the flushes to finish */
2039 domain_flush_complete(domain);
2040
2041 /* decrease reference counters - needs to happen after the flushes */
2042 domain->dev_iommu[iommu->index] -= 1;
2043 domain->dev_cnt -= 1;
2044 }
2045
2046 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2047 {
2048 pci_disable_ats(pdev);
2049 pci_disable_pri(pdev);
2050 pci_disable_pasid(pdev);
2051 }
2052
2053 /* FIXME: Change generic reset-function to do the same */
2054 static int pri_reset_while_enabled(struct pci_dev *pdev)
2055 {
2056 u16 control;
2057 int pos;
2058
2059 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2060 if (!pos)
2061 return -EINVAL;
2062
2063 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2064 control |= PCI_PRI_CTRL_RESET;
2065 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2066
2067 return 0;
2068 }
2069
2070 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2071 {
2072 bool reset_enable;
2073 int reqs, ret;
2074
2075 /* FIXME: Hardcode number of outstanding requests for now */
2076 reqs = 32;
2077 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2078 reqs = 1;
2079 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2080
2081 /* Only allow access to user-accessible pages */
2082 ret = pci_enable_pasid(pdev, 0);
2083 if (ret)
2084 goto out_err;
2085
2086 /* First reset the PRI state of the device */
2087 ret = pci_reset_pri(pdev);
2088 if (ret)
2089 goto out_err;
2090
2091 /* Enable PRI */
2092 ret = pci_enable_pri(pdev, reqs);
2093 if (ret)
2094 goto out_err;
2095
2096 if (reset_enable) {
2097 ret = pri_reset_while_enabled(pdev);
2098 if (ret)
2099 goto out_err;
2100 }
2101
2102 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2103 if (ret)
2104 goto out_err;
2105
2106 return 0;
2107
2108 out_err:
2109 pci_disable_pri(pdev);
2110 pci_disable_pasid(pdev);
2111
2112 return ret;
2113 }
2114
2115 /*
2116 * If a device is not yet associated with a domain, this function makes the
2117 * device visible in the domain
2118 */
2119 static int attach_device(struct device *dev,
2120 struct protection_domain *domain)
2121 {
2122 struct pci_dev *pdev;
2123 struct iommu_dev_data *dev_data;
2124 unsigned long flags;
2125 int ret;
2126
2127 spin_lock_irqsave(&domain->lock, flags);
2128
2129 dev_data = get_dev_data(dev);
2130
2131 spin_lock(&dev_data->lock);
2132
2133 ret = -EBUSY;
2134 if (dev_data->domain != NULL)
2135 goto out;
2136
2137 if (!dev_is_pci(dev))
2138 goto skip_ats_check;
2139
2140 pdev = to_pci_dev(dev);
2141 if (domain->flags & PD_IOMMUV2_MASK) {
2142 ret = -EINVAL;
2143 if (!dev_data->passthrough)
2144 goto out;
2145
2146 if (dev_data->iommu_v2) {
2147 if (pdev_iommuv2_enable(pdev) != 0)
2148 goto out;
2149
2150 dev_data->ats.enabled = true;
2151 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2152 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
2153 }
2154 } else if (amd_iommu_iotlb_sup &&
2155 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2156 dev_data->ats.enabled = true;
2157 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2158 }
2159
2160 skip_ats_check:
2161 ret = 0;
2162
2163 do_attach(dev_data, domain);
2164
2165 /*
2166 * We might boot into a crash-kernel here. The crashed kernel
2167 * left the caches in the IOMMU dirty. So we have to flush
2168 * here to evict all dirty stuff.
2169 */
2170 domain_flush_tlb_pde(domain);
2171
2172 domain_flush_complete(domain);
2173
2174 out:
2175 spin_unlock(&dev_data->lock);
2176
2177 spin_unlock_irqrestore(&domain->lock, flags);
2178
2179 return ret;
2180 }
2181
2182 /*
2183 * Removes a device from a protection domain (with devtable_lock held)
2184 */
2185 static void detach_device(struct device *dev)
2186 {
2187 struct protection_domain *domain;
2188 struct iommu_dev_data *dev_data;
2189 unsigned long flags;
2190
2191 dev_data = get_dev_data(dev);
2192 domain = dev_data->domain;
2193
2194 spin_lock_irqsave(&domain->lock, flags);
2195
2196 spin_lock(&dev_data->lock);
2197
2198 /*
2199 * First check if the device is still attached. It might already
2200 * be detached from its domain because the generic
2201 * iommu_detach_group code detached it and we try again here in
2202 * our alias handling.
2203 */
2204 if (WARN_ON(!dev_data->domain))
2205 goto out;
2206
2207 do_detach(dev_data);
2208
2209 if (!dev_is_pci(dev))
2210 goto out;
2211
2212 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2213 pdev_iommuv2_disable(to_pci_dev(dev));
2214 else if (dev_data->ats.enabled)
2215 pci_disable_ats(to_pci_dev(dev));
2216
2217 dev_data->ats.enabled = false;
2218
2219 out:
2220 spin_unlock(&dev_data->lock);
2221
2222 spin_unlock_irqrestore(&domain->lock, flags);
2223 }
2224
2225 static int amd_iommu_add_device(struct device *dev)
2226 {
2227 struct iommu_dev_data *dev_data;
2228 struct iommu_domain *domain;
2229 struct amd_iommu *iommu;
2230 int ret, devid;
2231
2232 if (!check_device(dev) || get_dev_data(dev))
2233 return 0;
2234
2235 devid = get_device_id(dev);
2236 if (devid < 0)
2237 return devid;
2238
2239 iommu = amd_iommu_rlookup_table[devid];
2240
2241 ret = iommu_init_device(dev);
2242 if (ret) {
2243 if (ret != -ENOTSUPP)
2244 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
2245
2246 iommu_ignore_device(dev);
2247 dev->dma_ops = NULL;
2248 goto out;
2249 }
2250 init_iommu_group(dev);
2251
2252 dev_data = get_dev_data(dev);
2253
2254 BUG_ON(!dev_data);
2255
2256 if (dev_data->iommu_v2)
2257 iommu_request_dm_for_dev(dev);
2258
2259 /* Domains are initialized for this device - have a look what we ended up with */
2260 domain = iommu_get_domain_for_dev(dev);
2261 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2262 dev_data->passthrough = true;
2263 else if (domain->type == IOMMU_DOMAIN_DMA)
2264 iommu_setup_dma_ops(dev, IOVA_START_PFN << PAGE_SHIFT, 0);
2265
2266 out:
2267 iommu_completion_wait(iommu);
2268
2269 return 0;
2270 }
2271
2272 static void amd_iommu_remove_device(struct device *dev)
2273 {
2274 struct amd_iommu *iommu;
2275 int devid;
2276
2277 if (!check_device(dev))
2278 return;
2279
2280 devid = get_device_id(dev);
2281 if (devid < 0)
2282 return;
2283
2284 iommu = amd_iommu_rlookup_table[devid];
2285
2286 iommu_uninit_device(dev);
2287 iommu_completion_wait(iommu);
2288 }
2289
2290 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2291 {
2292 if (dev_is_pci(dev))
2293 return pci_device_group(dev);
2294
2295 return acpihid_device_group(dev);
2296 }
2297
2298 static int amd_iommu_domain_get_attr(struct iommu_domain *domain,
2299 enum iommu_attr attr, void *data)
2300 {
2301 switch (domain->type) {
2302 case IOMMU_DOMAIN_UNMANAGED:
2303 return -ENODEV;
2304 case IOMMU_DOMAIN_DMA:
2305 switch (attr) {
2306 case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE:
2307 *(int *)data = !amd_iommu_unmap_flush;
2308 return 0;
2309 default:
2310 return -ENODEV;
2311 }
2312 break;
2313 default:
2314 return -EINVAL;
2315 }
2316 }
2317
2318 /*****************************************************************************
2319 *
2320 * The next functions belong to the dma_ops mapping/unmapping code.
2321 *
2322 *****************************************************************************/
2323
2324 static void update_device_table(struct protection_domain *domain,
2325 struct domain_pgtable *pgtable)
2326 {
2327 struct iommu_dev_data *dev_data;
2328
2329 list_for_each_entry(dev_data, &domain->dev_list, list) {
2330 set_dte_entry(dev_data->devid, domain, pgtable,
2331 dev_data->ats.enabled, dev_data->iommu_v2);
2332 clone_aliases(dev_data->pdev);
2333 }
2334 }
2335
2336 static void update_and_flush_device_table(struct protection_domain *domain,
2337 struct domain_pgtable *pgtable)
2338 {
2339 update_device_table(domain, pgtable);
2340 domain_flush_devices(domain);
2341 }
2342
2343 static void update_domain(struct protection_domain *domain)
2344 {
2345 struct domain_pgtable pgtable;
2346
2347 /* Update device table */
2348 amd_iommu_domain_get_pgtable(domain, &pgtable);
2349 update_and_flush_device_table(domain, &pgtable);
2350
2351 /* Flush domain TLB(s) and wait for completion */
2352 domain_flush_tlb_pde(domain);
2353 domain_flush_complete(domain);
2354 }
2355
2356 int __init amd_iommu_init_api(void)
2357 {
2358 int ret, err = 0;
2359
2360 ret = iova_cache_get();
2361 if (ret)
2362 return ret;
2363
2364 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2365 if (err)
2366 return err;
2367 #ifdef CONFIG_ARM_AMBA
2368 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2369 if (err)
2370 return err;
2371 #endif
2372 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2373 if (err)
2374 return err;
2375
2376 return 0;
2377 }
2378
2379 int __init amd_iommu_init_dma_ops(void)
2380 {
2381 swiotlb = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
2382
2383 if (amd_iommu_unmap_flush)
2384 pr_info("IO/TLB flush on unmap enabled\n");
2385 else
2386 pr_info("Lazy IO/TLB flushing enabled\n");
2387
2388 return 0;
2389
2390 }
2391
2392 /*****************************************************************************
2393 *
2394 * The following functions belong to the exported interface of AMD IOMMU
2395 *
2396 * This interface allows access to lower level functions of the IOMMU
2397 * like protection domain handling and assignement of devices to domains
2398 * which is not possible with the dma_ops interface.
2399 *
2400 *****************************************************************************/
2401
2402 static void cleanup_domain(struct protection_domain *domain)
2403 {
2404 struct iommu_dev_data *entry;
2405 unsigned long flags;
2406
2407 spin_lock_irqsave(&domain->lock, flags);
2408
2409 while (!list_empty(&domain->dev_list)) {
2410 entry = list_first_entry(&domain->dev_list,
2411 struct iommu_dev_data, list);
2412 BUG_ON(!entry->domain);
2413 do_detach(entry);
2414 }
2415
2416 spin_unlock_irqrestore(&domain->lock, flags);
2417 }
2418
2419 static void protection_domain_free(struct protection_domain *domain)
2420 {
2421 if (!domain)
2422 return;
2423
2424 if (domain->id)
2425 domain_id_free(domain->id);
2426
2427 kfree(domain);
2428 }
2429
2430 static int protection_domain_init(struct protection_domain *domain)
2431 {
2432 spin_lock_init(&domain->lock);
2433 domain->id = domain_id_alloc();
2434 if (!domain->id)
2435 return -ENOMEM;
2436 INIT_LIST_HEAD(&domain->dev_list);
2437
2438 return 0;
2439 }
2440
2441 static struct protection_domain *protection_domain_alloc(void)
2442 {
2443 struct protection_domain *domain;
2444
2445 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2446 if (!domain)
2447 return NULL;
2448
2449 if (protection_domain_init(domain))
2450 goto out_err;
2451
2452 return domain;
2453
2454 out_err:
2455 kfree(domain);
2456
2457 return NULL;
2458 }
2459
2460 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2461 {
2462 struct protection_domain *pdomain;
2463 u64 *pt_root, root;
2464
2465 switch (type) {
2466 case IOMMU_DOMAIN_UNMANAGED:
2467 pdomain = protection_domain_alloc();
2468 if (!pdomain)
2469 return NULL;
2470
2471 pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2472 if (!pt_root) {
2473 protection_domain_free(pdomain);
2474 return NULL;
2475 }
2476
2477 root = amd_iommu_domain_encode_pgtable(pt_root, PAGE_MODE_3_LEVEL);
2478 atomic64_set(&pdomain->pt_root, root);
2479
2480 pdomain->domain.geometry.aperture_start = 0;
2481 pdomain->domain.geometry.aperture_end = ~0ULL;
2482 pdomain->domain.geometry.force_aperture = true;
2483
2484 break;
2485 case IOMMU_DOMAIN_DMA:
2486 pdomain = dma_ops_domain_alloc();
2487 if (!pdomain) {
2488 pr_err("Failed to allocate\n");
2489 return NULL;
2490 }
2491 break;
2492 case IOMMU_DOMAIN_IDENTITY:
2493 pdomain = protection_domain_alloc();
2494 if (!pdomain)
2495 return NULL;
2496
2497 atomic64_set(&pdomain->pt_root, PAGE_MODE_NONE);
2498 break;
2499 default:
2500 return NULL;
2501 }
2502
2503 return &pdomain->domain;
2504 }
2505
2506 static void amd_iommu_domain_free(struct iommu_domain *dom)
2507 {
2508 struct protection_domain *domain;
2509 struct domain_pgtable pgtable;
2510
2511 domain = to_pdomain(dom);
2512
2513 if (domain->dev_cnt > 0)
2514 cleanup_domain(domain);
2515
2516 BUG_ON(domain->dev_cnt != 0);
2517
2518 if (!dom)
2519 return;
2520
2521 switch (dom->type) {
2522 case IOMMU_DOMAIN_DMA:
2523 /* Now release the domain */
2524 dma_ops_domain_free(domain);
2525 break;
2526 default:
2527 amd_iommu_domain_get_pgtable(domain, &pgtable);
2528
2529 if (pgtable.mode != PAGE_MODE_NONE)
2530 free_pagetable(domain);
2531
2532 if (domain->flags & PD_IOMMUV2_MASK)
2533 free_gcr3_table(domain);
2534
2535 protection_domain_free(domain);
2536 break;
2537 }
2538 }
2539
2540 static void amd_iommu_detach_device(struct iommu_domain *dom,
2541 struct device *dev)
2542 {
2543 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2544 struct amd_iommu *iommu;
2545 int devid;
2546
2547 if (!check_device(dev))
2548 return;
2549
2550 devid = get_device_id(dev);
2551 if (devid < 0)
2552 return;
2553
2554 if (dev_data->domain != NULL)
2555 detach_device(dev);
2556
2557 iommu = amd_iommu_rlookup_table[devid];
2558 if (!iommu)
2559 return;
2560
2561 #ifdef CONFIG_IRQ_REMAP
2562 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2563 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2564 dev_data->use_vapic = 0;
2565 #endif
2566
2567 iommu_completion_wait(iommu);
2568 }
2569
2570 static int amd_iommu_attach_device(struct iommu_domain *dom,
2571 struct device *dev)
2572 {
2573 struct protection_domain *domain = to_pdomain(dom);
2574 struct iommu_dev_data *dev_data;
2575 struct amd_iommu *iommu;
2576 int ret;
2577
2578 if (!check_device(dev))
2579 return -EINVAL;
2580
2581 dev_data = dev->archdata.iommu;
2582 dev_data->defer_attach = false;
2583
2584 iommu = amd_iommu_rlookup_table[dev_data->devid];
2585 if (!iommu)
2586 return -EINVAL;
2587
2588 if (dev_data->domain)
2589 detach_device(dev);
2590
2591 ret = attach_device(dev, domain);
2592
2593 #ifdef CONFIG_IRQ_REMAP
2594 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2595 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
2596 dev_data->use_vapic = 1;
2597 else
2598 dev_data->use_vapic = 0;
2599 }
2600 #endif
2601
2602 iommu_completion_wait(iommu);
2603
2604 return ret;
2605 }
2606
2607 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2608 phys_addr_t paddr, size_t page_size, int iommu_prot,
2609 gfp_t gfp)
2610 {
2611 struct protection_domain *domain = to_pdomain(dom);
2612 struct domain_pgtable pgtable;
2613 int prot = 0;
2614 int ret;
2615
2616 amd_iommu_domain_get_pgtable(domain, &pgtable);
2617 if (pgtable.mode == PAGE_MODE_NONE)
2618 return -EINVAL;
2619
2620 if (iommu_prot & IOMMU_READ)
2621 prot |= IOMMU_PROT_IR;
2622 if (iommu_prot & IOMMU_WRITE)
2623 prot |= IOMMU_PROT_IW;
2624
2625 ret = iommu_map_page(domain, iova, paddr, page_size, prot, gfp);
2626
2627 domain_flush_np_cache(domain, iova, page_size);
2628
2629 return ret;
2630 }
2631
2632 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2633 size_t page_size,
2634 struct iommu_iotlb_gather *gather)
2635 {
2636 struct protection_domain *domain = to_pdomain(dom);
2637 struct domain_pgtable pgtable;
2638
2639 amd_iommu_domain_get_pgtable(domain, &pgtable);
2640 if (pgtable.mode == PAGE_MODE_NONE)
2641 return 0;
2642
2643 return iommu_unmap_page(domain, iova, page_size);
2644 }
2645
2646 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2647 dma_addr_t iova)
2648 {
2649 struct protection_domain *domain = to_pdomain(dom);
2650 unsigned long offset_mask, pte_pgsize;
2651 struct domain_pgtable pgtable;
2652 u64 *pte, __pte;
2653
2654 amd_iommu_domain_get_pgtable(domain, &pgtable);
2655 if (pgtable.mode == PAGE_MODE_NONE)
2656 return iova;
2657
2658 pte = fetch_pte(domain, iova, &pte_pgsize);
2659
2660 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2661 return 0;
2662
2663 offset_mask = pte_pgsize - 1;
2664 __pte = __sme_clr(*pte & PM_ADDR_MASK);
2665
2666 return (__pte & ~offset_mask) | (iova & offset_mask);
2667 }
2668
2669 static bool amd_iommu_capable(enum iommu_cap cap)
2670 {
2671 switch (cap) {
2672 case IOMMU_CAP_CACHE_COHERENCY:
2673 return true;
2674 case IOMMU_CAP_INTR_REMAP:
2675 return (irq_remapping_enabled == 1);
2676 case IOMMU_CAP_NOEXEC:
2677 return false;
2678 default:
2679 break;
2680 }
2681
2682 return false;
2683 }
2684
2685 static void amd_iommu_get_resv_regions(struct device *dev,
2686 struct list_head *head)
2687 {
2688 struct iommu_resv_region *region;
2689 struct unity_map_entry *entry;
2690 int devid;
2691
2692 devid = get_device_id(dev);
2693 if (devid < 0)
2694 return;
2695
2696 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
2697 int type, prot = 0;
2698 size_t length;
2699
2700 if (devid < entry->devid_start || devid > entry->devid_end)
2701 continue;
2702
2703 type = IOMMU_RESV_DIRECT;
2704 length = entry->address_end - entry->address_start;
2705 if (entry->prot & IOMMU_PROT_IR)
2706 prot |= IOMMU_READ;
2707 if (entry->prot & IOMMU_PROT_IW)
2708 prot |= IOMMU_WRITE;
2709 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
2710 /* Exclusion range */
2711 type = IOMMU_RESV_RESERVED;
2712
2713 region = iommu_alloc_resv_region(entry->address_start,
2714 length, prot, type);
2715 if (!region) {
2716 dev_err(dev, "Out of memory allocating dm-regions\n");
2717 return;
2718 }
2719 list_add_tail(&region->list, head);
2720 }
2721
2722 region = iommu_alloc_resv_region(MSI_RANGE_START,
2723 MSI_RANGE_END - MSI_RANGE_START + 1,
2724 0, IOMMU_RESV_MSI);
2725 if (!region)
2726 return;
2727 list_add_tail(&region->list, head);
2728
2729 region = iommu_alloc_resv_region(HT_RANGE_START,
2730 HT_RANGE_END - HT_RANGE_START + 1,
2731 0, IOMMU_RESV_RESERVED);
2732 if (!region)
2733 return;
2734 list_add_tail(&region->list, head);
2735 }
2736
2737 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
2738 struct device *dev)
2739 {
2740 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2741 return dev_data->defer_attach;
2742 }
2743
2744 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
2745 {
2746 struct protection_domain *dom = to_pdomain(domain);
2747 unsigned long flags;
2748
2749 spin_lock_irqsave(&dom->lock, flags);
2750 domain_flush_tlb_pde(dom);
2751 domain_flush_complete(dom);
2752 spin_unlock_irqrestore(&dom->lock, flags);
2753 }
2754
2755 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
2756 struct iommu_iotlb_gather *gather)
2757 {
2758 amd_iommu_flush_iotlb_all(domain);
2759 }
2760
2761 const struct iommu_ops amd_iommu_ops = {
2762 .capable = amd_iommu_capable,
2763 .domain_alloc = amd_iommu_domain_alloc,
2764 .domain_free = amd_iommu_domain_free,
2765 .attach_dev = amd_iommu_attach_device,
2766 .detach_dev = amd_iommu_detach_device,
2767 .map = amd_iommu_map,
2768 .unmap = amd_iommu_unmap,
2769 .iova_to_phys = amd_iommu_iova_to_phys,
2770 .add_device = amd_iommu_add_device,
2771 .remove_device = amd_iommu_remove_device,
2772 .device_group = amd_iommu_device_group,
2773 .domain_get_attr = amd_iommu_domain_get_attr,
2774 .get_resv_regions = amd_iommu_get_resv_regions,
2775 .put_resv_regions = generic_iommu_put_resv_regions,
2776 .is_attach_deferred = amd_iommu_is_attach_deferred,
2777 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
2778 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
2779 .iotlb_sync = amd_iommu_iotlb_sync,
2780 };
2781
2782 /*****************************************************************************
2783 *
2784 * The next functions do a basic initialization of IOMMU for pass through
2785 * mode
2786 *
2787 * In passthrough mode the IOMMU is initialized and enabled but not used for
2788 * DMA-API translation.
2789 *
2790 *****************************************************************************/
2791
2792 /* IOMMUv2 specific functions */
2793 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
2794 {
2795 return atomic_notifier_chain_register(&ppr_notifier, nb);
2796 }
2797 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
2798
2799 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
2800 {
2801 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
2802 }
2803 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
2804
2805 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
2806 {
2807 struct protection_domain *domain = to_pdomain(dom);
2808 struct domain_pgtable pgtable;
2809 unsigned long flags;
2810 u64 pt_root;
2811
2812 spin_lock_irqsave(&domain->lock, flags);
2813
2814 /* First save pgtable configuration*/
2815 amd_iommu_domain_get_pgtable(domain, &pgtable);
2816
2817 /* Update data structure */
2818 pt_root = amd_iommu_domain_encode_pgtable(NULL, PAGE_MODE_NONE);
2819 atomic64_set(&domain->pt_root, pt_root);
2820
2821 /* Make changes visible to IOMMUs */
2822 update_domain(domain);
2823
2824 /* Restore old pgtable in domain->ptroot to free page-table */
2825 pt_root = amd_iommu_domain_encode_pgtable(pgtable.root, pgtable.mode);
2826 atomic64_set(&domain->pt_root, pt_root);
2827
2828 /* Page-table is not visible to IOMMU anymore, so free it */
2829 free_pagetable(domain);
2830
2831 spin_unlock_irqrestore(&domain->lock, flags);
2832 }
2833 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
2834
2835 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
2836 {
2837 struct protection_domain *domain = to_pdomain(dom);
2838 unsigned long flags;
2839 int levels, ret;
2840
2841 if (pasids <= 0 || pasids > (PASID_MASK + 1))
2842 return -EINVAL;
2843
2844 /* Number of GCR3 table levels required */
2845 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
2846 levels += 1;
2847
2848 if (levels > amd_iommu_max_glx_val)
2849 return -EINVAL;
2850
2851 spin_lock_irqsave(&domain->lock, flags);
2852
2853 /*
2854 * Save us all sanity checks whether devices already in the
2855 * domain support IOMMUv2. Just force that the domain has no
2856 * devices attached when it is switched into IOMMUv2 mode.
2857 */
2858 ret = -EBUSY;
2859 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
2860 goto out;
2861
2862 ret = -ENOMEM;
2863 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
2864 if (domain->gcr3_tbl == NULL)
2865 goto out;
2866
2867 domain->glx = levels;
2868 domain->flags |= PD_IOMMUV2_MASK;
2869
2870 update_domain(domain);
2871
2872 ret = 0;
2873
2874 out:
2875 spin_unlock_irqrestore(&domain->lock, flags);
2876
2877 return ret;
2878 }
2879 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
2880
2881 static int __flush_pasid(struct protection_domain *domain, int pasid,
2882 u64 address, bool size)
2883 {
2884 struct iommu_dev_data *dev_data;
2885 struct iommu_cmd cmd;
2886 int i, ret;
2887
2888 if (!(domain->flags & PD_IOMMUV2_MASK))
2889 return -EINVAL;
2890
2891 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
2892
2893 /*
2894 * IOMMU TLB needs to be flushed before Device TLB to
2895 * prevent device TLB refill from IOMMU TLB
2896 */
2897 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
2898 if (domain->dev_iommu[i] == 0)
2899 continue;
2900
2901 ret = iommu_queue_command(amd_iommus[i], &cmd);
2902 if (ret != 0)
2903 goto out;
2904 }
2905
2906 /* Wait until IOMMU TLB flushes are complete */
2907 domain_flush_complete(domain);
2908
2909 /* Now flush device TLBs */
2910 list_for_each_entry(dev_data, &domain->dev_list, list) {
2911 struct amd_iommu *iommu;
2912 int qdep;
2913
2914 /*
2915 There might be non-IOMMUv2 capable devices in an IOMMUv2
2916 * domain.
2917 */
2918 if (!dev_data->ats.enabled)
2919 continue;
2920
2921 qdep = dev_data->ats.qdep;
2922 iommu = amd_iommu_rlookup_table[dev_data->devid];
2923
2924 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
2925 qdep, address, size);
2926
2927 ret = iommu_queue_command(iommu, &cmd);
2928 if (ret != 0)
2929 goto out;
2930 }
2931
2932 /* Wait until all device TLBs are flushed */
2933 domain_flush_complete(domain);
2934
2935 ret = 0;
2936
2937 out:
2938
2939 return ret;
2940 }
2941
2942 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
2943 u64 address)
2944 {
2945 return __flush_pasid(domain, pasid, address, false);
2946 }
2947
2948 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
2949 u64 address)
2950 {
2951 struct protection_domain *domain = to_pdomain(dom);
2952 unsigned long flags;
2953 int ret;
2954
2955 spin_lock_irqsave(&domain->lock, flags);
2956 ret = __amd_iommu_flush_page(domain, pasid, address);
2957 spin_unlock_irqrestore(&domain->lock, flags);
2958
2959 return ret;
2960 }
2961 EXPORT_SYMBOL(amd_iommu_flush_page);
2962
2963 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
2964 {
2965 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
2966 true);
2967 }
2968
2969 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
2970 {
2971 struct protection_domain *domain = to_pdomain(dom);
2972 unsigned long flags;
2973 int ret;
2974
2975 spin_lock_irqsave(&domain->lock, flags);
2976 ret = __amd_iommu_flush_tlb(domain, pasid);
2977 spin_unlock_irqrestore(&domain->lock, flags);
2978
2979 return ret;
2980 }
2981 EXPORT_SYMBOL(amd_iommu_flush_tlb);
2982
2983 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
2984 {
2985 int index;
2986 u64 *pte;
2987
2988 while (true) {
2989
2990 index = (pasid >> (9 * level)) & 0x1ff;
2991 pte = &root[index];
2992
2993 if (level == 0)
2994 break;
2995
2996 if (!(*pte & GCR3_VALID)) {
2997 if (!alloc)
2998 return NULL;
2999
3000 root = (void *)get_zeroed_page(GFP_ATOMIC);
3001 if (root == NULL)
3002 return NULL;
3003
3004 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3005 }
3006
3007 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3008
3009 level -= 1;
3010 }
3011
3012 return pte;
3013 }
3014
3015 static int __set_gcr3(struct protection_domain *domain, int pasid,
3016 unsigned long cr3)
3017 {
3018 struct domain_pgtable pgtable;
3019 u64 *pte;
3020
3021 amd_iommu_domain_get_pgtable(domain, &pgtable);
3022 if (pgtable.mode != PAGE_MODE_NONE)
3023 return -EINVAL;
3024
3025 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3026 if (pte == NULL)
3027 return -ENOMEM;
3028
3029 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3030
3031 return __amd_iommu_flush_tlb(domain, pasid);
3032 }
3033
3034 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3035 {
3036 struct domain_pgtable pgtable;
3037 u64 *pte;
3038
3039 amd_iommu_domain_get_pgtable(domain, &pgtable);
3040 if (pgtable.mode != PAGE_MODE_NONE)
3041 return -EINVAL;
3042
3043 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3044 if (pte == NULL)
3045 return 0;
3046
3047 *pte = 0;
3048
3049 return __amd_iommu_flush_tlb(domain, pasid);
3050 }
3051
3052 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3053 unsigned long cr3)
3054 {
3055 struct protection_domain *domain = to_pdomain(dom);
3056 unsigned long flags;
3057 int ret;
3058
3059 spin_lock_irqsave(&domain->lock, flags);
3060 ret = __set_gcr3(domain, pasid, cr3);
3061 spin_unlock_irqrestore(&domain->lock, flags);
3062
3063 return ret;
3064 }
3065 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3066
3067 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3068 {
3069 struct protection_domain *domain = to_pdomain(dom);
3070 unsigned long flags;
3071 int ret;
3072
3073 spin_lock_irqsave(&domain->lock, flags);
3074 ret = __clear_gcr3(domain, pasid);
3075 spin_unlock_irqrestore(&domain->lock, flags);
3076
3077 return ret;
3078 }
3079 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3080
3081 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3082 int status, int tag)
3083 {
3084 struct iommu_dev_data *dev_data;
3085 struct amd_iommu *iommu;
3086 struct iommu_cmd cmd;
3087
3088 dev_data = get_dev_data(&pdev->dev);
3089 iommu = amd_iommu_rlookup_table[dev_data->devid];
3090
3091 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3092 tag, dev_data->pri_tlp);
3093
3094 return iommu_queue_command(iommu, &cmd);
3095 }
3096 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3097
3098 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3099 {
3100 struct protection_domain *pdomain;
3101 struct iommu_domain *io_domain;
3102 struct device *dev = &pdev->dev;
3103
3104 if (!check_device(dev))
3105 return NULL;
3106
3107 pdomain = get_dev_data(dev)->domain;
3108 if (pdomain == NULL && get_dev_data(dev)->defer_attach) {
3109 get_dev_data(dev)->defer_attach = false;
3110 io_domain = iommu_get_domain_for_dev(dev);
3111 pdomain = to_pdomain(io_domain);
3112 attach_device(dev, pdomain);
3113 }
3114 if (pdomain == NULL)
3115 return NULL;
3116
3117 if (!dma_ops_domain(pdomain))
3118 return NULL;
3119
3120 /* Only return IOMMUv2 domains */
3121 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3122 return NULL;
3123
3124 return &pdomain->domain;
3125 }
3126 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3127
3128 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3129 {
3130 struct iommu_dev_data *dev_data;
3131
3132 if (!amd_iommu_v2_supported())
3133 return;
3134
3135 dev_data = get_dev_data(&pdev->dev);
3136 dev_data->errata |= (1 << erratum);
3137 }
3138 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3139
3140 int amd_iommu_device_info(struct pci_dev *pdev,
3141 struct amd_iommu_device_info *info)
3142 {
3143 int max_pasids;
3144 int pos;
3145
3146 if (pdev == NULL || info == NULL)
3147 return -EINVAL;
3148
3149 if (!amd_iommu_v2_supported())
3150 return -EINVAL;
3151
3152 memset(info, 0, sizeof(*info));
3153
3154 if (!pci_ats_disabled()) {
3155 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3156 if (pos)
3157 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3158 }
3159
3160 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3161 if (pos)
3162 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3163
3164 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3165 if (pos) {
3166 int features;
3167
3168 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3169 max_pasids = min(max_pasids, (1 << 20));
3170
3171 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3172 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3173
3174 features = pci_pasid_features(pdev);
3175 if (features & PCI_PASID_CAP_EXEC)
3176 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3177 if (features & PCI_PASID_CAP_PRIV)
3178 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3179 }
3180
3181 return 0;
3182 }
3183 EXPORT_SYMBOL(amd_iommu_device_info);
3184
3185 #ifdef CONFIG_IRQ_REMAP
3186
3187 /*****************************************************************************
3188 *
3189 * Interrupt Remapping Implementation
3190 *
3191 *****************************************************************************/
3192
3193 static struct irq_chip amd_ir_chip;
3194 static DEFINE_SPINLOCK(iommu_table_lock);
3195
3196 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3197 {
3198 u64 dte;
3199
3200 dte = amd_iommu_dev_table[devid].data[2];
3201 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3202 dte |= iommu_virt_to_phys(table->table);
3203 dte |= DTE_IRQ_REMAP_INTCTL;
3204 dte |= DTE_IRQ_TABLE_LEN;
3205 dte |= DTE_IRQ_REMAP_ENABLE;
3206
3207 amd_iommu_dev_table[devid].data[2] = dte;
3208 }
3209
3210 static struct irq_remap_table *get_irq_table(u16 devid)
3211 {
3212 struct irq_remap_table *table;
3213
3214 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3215 "%s: no iommu for devid %x\n", __func__, devid))
3216 return NULL;
3217
3218 table = irq_lookup_table[devid];
3219 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3220 return NULL;
3221
3222 return table;
3223 }
3224
3225 static struct irq_remap_table *__alloc_irq_table(void)
3226 {
3227 struct irq_remap_table *table;
3228
3229 table = kzalloc(sizeof(*table), GFP_KERNEL);
3230 if (!table)
3231 return NULL;
3232
3233 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3234 if (!table->table) {
3235 kfree(table);
3236 return NULL;
3237 }
3238 raw_spin_lock_init(&table->lock);
3239
3240 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3241 memset(table->table, 0,
3242 MAX_IRQS_PER_TABLE * sizeof(u32));
3243 else
3244 memset(table->table, 0,
3245 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3246 return table;
3247 }
3248
3249 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3250 struct irq_remap_table *table)
3251 {
3252 irq_lookup_table[devid] = table;
3253 set_dte_irq_entry(devid, table);
3254 iommu_flush_dte(iommu, devid);
3255 }
3256
3257 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias,
3258 void *data)
3259 {
3260 struct irq_remap_table *table = data;
3261
3262 irq_lookup_table[alias] = table;
3263 set_dte_irq_entry(alias, table);
3264
3265 iommu_flush_dte(amd_iommu_rlookup_table[alias], alias);
3266
3267 return 0;
3268 }
3269
3270 static struct irq_remap_table *alloc_irq_table(u16 devid, struct pci_dev *pdev)
3271 {
3272 struct irq_remap_table *table = NULL;
3273 struct irq_remap_table *new_table = NULL;
3274 struct amd_iommu *iommu;
3275 unsigned long flags;
3276 u16 alias;
3277
3278 spin_lock_irqsave(&iommu_table_lock, flags);
3279
3280 iommu = amd_iommu_rlookup_table[devid];
3281 if (!iommu)
3282 goto out_unlock;
3283
3284 table = irq_lookup_table[devid];
3285 if (table)
3286 goto out_unlock;
3287
3288 alias = amd_iommu_alias_table[devid];
3289 table = irq_lookup_table[alias];
3290 if (table) {
3291 set_remap_table_entry(iommu, devid, table);
3292 goto out_wait;
3293 }
3294 spin_unlock_irqrestore(&iommu_table_lock, flags);
3295
3296 /* Nothing there yet, allocate new irq remapping table */
3297 new_table = __alloc_irq_table();
3298 if (!new_table)
3299 return NULL;
3300
3301 spin_lock_irqsave(&iommu_table_lock, flags);
3302
3303 table = irq_lookup_table[devid];
3304 if (table)
3305 goto out_unlock;
3306
3307 table = irq_lookup_table[alias];
3308 if (table) {
3309 set_remap_table_entry(iommu, devid, table);
3310 goto out_wait;
3311 }
3312
3313 table = new_table;
3314 new_table = NULL;
3315
3316 if (pdev)
3317 pci_for_each_dma_alias(pdev, set_remap_table_entry_alias,
3318 table);
3319 else
3320 set_remap_table_entry(iommu, devid, table);
3321
3322 if (devid != alias)
3323 set_remap_table_entry(iommu, alias, table);
3324
3325 out_wait:
3326 iommu_completion_wait(iommu);
3327
3328 out_unlock:
3329 spin_unlock_irqrestore(&iommu_table_lock, flags);
3330
3331 if (new_table) {
3332 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3333 kfree(new_table);
3334 }
3335 return table;
3336 }
3337
3338 static int alloc_irq_index(u16 devid, int count, bool align,
3339 struct pci_dev *pdev)
3340 {
3341 struct irq_remap_table *table;
3342 int index, c, alignment = 1;
3343 unsigned long flags;
3344 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3345
3346 if (!iommu)
3347 return -ENODEV;
3348
3349 table = alloc_irq_table(devid, pdev);
3350 if (!table)
3351 return -ENODEV;
3352
3353 if (align)
3354 alignment = roundup_pow_of_two(count);
3355
3356 raw_spin_lock_irqsave(&table->lock, flags);
3357
3358 /* Scan table for free entries */
3359 for (index = ALIGN(table->min_index, alignment), c = 0;
3360 index < MAX_IRQS_PER_TABLE;) {
3361 if (!iommu->irte_ops->is_allocated(table, index)) {
3362 c += 1;
3363 } else {
3364 c = 0;
3365 index = ALIGN(index + 1, alignment);
3366 continue;
3367 }
3368
3369 if (c == count) {
3370 for (; c != 0; --c)
3371 iommu->irte_ops->set_allocated(table, index - c + 1);
3372
3373 index -= count - 1;
3374 goto out;
3375 }
3376
3377 index++;
3378 }
3379
3380 index = -ENOSPC;
3381
3382 out:
3383 raw_spin_unlock_irqrestore(&table->lock, flags);
3384
3385 return index;
3386 }
3387
3388 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3389 struct amd_ir_data *data)
3390 {
3391 struct irq_remap_table *table;
3392 struct amd_iommu *iommu;
3393 unsigned long flags;
3394 struct irte_ga *entry;
3395
3396 iommu = amd_iommu_rlookup_table[devid];
3397 if (iommu == NULL)
3398 return -EINVAL;
3399
3400 table = get_irq_table(devid);
3401 if (!table)
3402 return -ENOMEM;
3403
3404 raw_spin_lock_irqsave(&table->lock, flags);
3405
3406 entry = (struct irte_ga *)table->table;
3407 entry = &entry[index];
3408 entry->lo.fields_remap.valid = 0;
3409 entry->hi.val = irte->hi.val;
3410 entry->lo.val = irte->lo.val;
3411 entry->lo.fields_remap.valid = 1;
3412 if (data)
3413 data->ref = entry;
3414
3415 raw_spin_unlock_irqrestore(&table->lock, flags);
3416
3417 iommu_flush_irt(iommu, devid);
3418 iommu_completion_wait(iommu);
3419
3420 return 0;
3421 }
3422
3423 static int modify_irte(u16 devid, int index, union irte *irte)
3424 {
3425 struct irq_remap_table *table;
3426 struct amd_iommu *iommu;
3427 unsigned long flags;
3428
3429 iommu = amd_iommu_rlookup_table[devid];
3430 if (iommu == NULL)
3431 return -EINVAL;
3432
3433 table = get_irq_table(devid);
3434 if (!table)
3435 return -ENOMEM;
3436
3437 raw_spin_lock_irqsave(&table->lock, flags);
3438 table->table[index] = irte->val;
3439 raw_spin_unlock_irqrestore(&table->lock, flags);
3440
3441 iommu_flush_irt(iommu, devid);
3442 iommu_completion_wait(iommu);
3443
3444 return 0;
3445 }
3446
3447 static void free_irte(u16 devid, int index)
3448 {
3449 struct irq_remap_table *table;
3450 struct amd_iommu *iommu;
3451 unsigned long flags;
3452
3453 iommu = amd_iommu_rlookup_table[devid];
3454 if (iommu == NULL)
3455 return;
3456
3457 table = get_irq_table(devid);
3458 if (!table)
3459 return;
3460
3461 raw_spin_lock_irqsave(&table->lock, flags);
3462 iommu->irte_ops->clear_allocated(table, index);
3463 raw_spin_unlock_irqrestore(&table->lock, flags);
3464
3465 iommu_flush_irt(iommu, devid);
3466 iommu_completion_wait(iommu);
3467 }
3468
3469 static void irte_prepare(void *entry,
3470 u32 delivery_mode, u32 dest_mode,
3471 u8 vector, u32 dest_apicid, int devid)
3472 {
3473 union irte *irte = (union irte *) entry;
3474
3475 irte->val = 0;
3476 irte->fields.vector = vector;
3477 irte->fields.int_type = delivery_mode;
3478 irte->fields.destination = dest_apicid;
3479 irte->fields.dm = dest_mode;
3480 irte->fields.valid = 1;
3481 }
3482
3483 static void irte_ga_prepare(void *entry,
3484 u32 delivery_mode, u32 dest_mode,
3485 u8 vector, u32 dest_apicid, int devid)
3486 {
3487 struct irte_ga *irte = (struct irte_ga *) entry;
3488
3489 irte->lo.val = 0;
3490 irte->hi.val = 0;
3491 irte->lo.fields_remap.int_type = delivery_mode;
3492 irte->lo.fields_remap.dm = dest_mode;
3493 irte->hi.fields.vector = vector;
3494 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3495 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3496 irte->lo.fields_remap.valid = 1;
3497 }
3498
3499 static void irte_activate(void *entry, u16 devid, u16 index)
3500 {
3501 union irte *irte = (union irte *) entry;
3502
3503 irte->fields.valid = 1;
3504 modify_irte(devid, index, irte);
3505 }
3506
3507 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3508 {
3509 struct irte_ga *irte = (struct irte_ga *) entry;
3510
3511 irte->lo.fields_remap.valid = 1;
3512 modify_irte_ga(devid, index, irte, NULL);
3513 }
3514
3515 static void irte_deactivate(void *entry, u16 devid, u16 index)
3516 {
3517 union irte *irte = (union irte *) entry;
3518
3519 irte->fields.valid = 0;
3520 modify_irte(devid, index, irte);
3521 }
3522
3523 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3524 {
3525 struct irte_ga *irte = (struct irte_ga *) entry;
3526
3527 irte->lo.fields_remap.valid = 0;
3528 modify_irte_ga(devid, index, irte, NULL);
3529 }
3530
3531 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3532 u8 vector, u32 dest_apicid)
3533 {
3534 union irte *irte = (union irte *) entry;
3535
3536 irte->fields.vector = vector;
3537 irte->fields.destination = dest_apicid;
3538 modify_irte(devid, index, irte);
3539 }
3540
3541 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3542 u8 vector, u32 dest_apicid)
3543 {
3544 struct irte_ga *irte = (struct irte_ga *) entry;
3545
3546 if (!irte->lo.fields_remap.guest_mode) {
3547 irte->hi.fields.vector = vector;
3548 irte->lo.fields_remap.destination =
3549 APICID_TO_IRTE_DEST_LO(dest_apicid);
3550 irte->hi.fields.destination =
3551 APICID_TO_IRTE_DEST_HI(dest_apicid);
3552 modify_irte_ga(devid, index, irte, NULL);
3553 }
3554 }
3555
3556 #define IRTE_ALLOCATED (~1U)
3557 static void irte_set_allocated(struct irq_remap_table *table, int index)
3558 {
3559 table->table[index] = IRTE_ALLOCATED;
3560 }
3561
3562 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3563 {
3564 struct irte_ga *ptr = (struct irte_ga *)table->table;
3565 struct irte_ga *irte = &ptr[index];
3566
3567 memset(&irte->lo.val, 0, sizeof(u64));
3568 memset(&irte->hi.val, 0, sizeof(u64));
3569 irte->hi.fields.vector = 0xff;
3570 }
3571
3572 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3573 {
3574 union irte *ptr = (union irte *)table->table;
3575 union irte *irte = &ptr[index];
3576
3577 return irte->val != 0;
3578 }
3579
3580 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3581 {
3582 struct irte_ga *ptr = (struct irte_ga *)table->table;
3583 struct irte_ga *irte = &ptr[index];
3584
3585 return irte->hi.fields.vector != 0;
3586 }
3587
3588 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3589 {
3590 table->table[index] = 0;
3591 }
3592
3593 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3594 {
3595 struct irte_ga *ptr = (struct irte_ga *)table->table;
3596 struct irte_ga *irte = &ptr[index];
3597
3598 memset(&irte->lo.val, 0, sizeof(u64));
3599 memset(&irte->hi.val, 0, sizeof(u64));
3600 }
3601
3602 static int get_devid(struct irq_alloc_info *info)
3603 {
3604 int devid = -1;
3605
3606 switch (info->type) {
3607 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3608 devid = get_ioapic_devid(info->ioapic_id);
3609 break;
3610 case X86_IRQ_ALLOC_TYPE_HPET:
3611 devid = get_hpet_devid(info->hpet_id);
3612 break;
3613 case X86_IRQ_ALLOC_TYPE_MSI:
3614 case X86_IRQ_ALLOC_TYPE_MSIX:
3615 devid = get_device_id(&info->msi_dev->dev);
3616 break;
3617 default:
3618 BUG_ON(1);
3619 break;
3620 }
3621
3622 return devid;
3623 }
3624
3625 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3626 {
3627 struct amd_iommu *iommu;
3628 int devid;
3629
3630 if (!info)
3631 return NULL;
3632
3633 devid = get_devid(info);
3634 if (devid >= 0) {
3635 iommu = amd_iommu_rlookup_table[devid];
3636 if (iommu)
3637 return iommu->ir_domain;
3638 }
3639
3640 return NULL;
3641 }
3642
3643 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3644 {
3645 struct amd_iommu *iommu;
3646 int devid;
3647
3648 if (!info)
3649 return NULL;
3650
3651 switch (info->type) {
3652 case X86_IRQ_ALLOC_TYPE_MSI:
3653 case X86_IRQ_ALLOC_TYPE_MSIX:
3654 devid = get_device_id(&info->msi_dev->dev);
3655 if (devid < 0)
3656 return NULL;
3657
3658 iommu = amd_iommu_rlookup_table[devid];
3659 if (iommu)
3660 return iommu->msi_domain;
3661 break;
3662 default:
3663 break;
3664 }
3665
3666 return NULL;
3667 }
3668
3669 struct irq_remap_ops amd_iommu_irq_ops = {
3670 .prepare = amd_iommu_prepare,
3671 .enable = amd_iommu_enable,
3672 .disable = amd_iommu_disable,
3673 .reenable = amd_iommu_reenable,
3674 .enable_faulting = amd_iommu_enable_faulting,
3675 .get_ir_irq_domain = get_ir_irq_domain,
3676 .get_irq_domain = get_irq_domain,
3677 };
3678
3679 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3680 struct irq_cfg *irq_cfg,
3681 struct irq_alloc_info *info,
3682 int devid, int index, int sub_handle)
3683 {
3684 struct irq_2_irte *irte_info = &data->irq_2_irte;
3685 struct msi_msg *msg = &data->msi_entry;
3686 struct IO_APIC_route_entry *entry;
3687 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3688
3689 if (!iommu)
3690 return;
3691
3692 data->irq_2_irte.devid = devid;
3693 data->irq_2_irte.index = index + sub_handle;
3694 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
3695 apic->irq_dest_mode, irq_cfg->vector,
3696 irq_cfg->dest_apicid, devid);
3697
3698 switch (info->type) {
3699 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3700 /* Setup IOAPIC entry */
3701 entry = info->ioapic_entry;
3702 info->ioapic_entry = NULL;
3703 memset(entry, 0, sizeof(*entry));
3704 entry->vector = index;
3705 entry->mask = 0;
3706 entry->trigger = info->ioapic_trigger;
3707 entry->polarity = info->ioapic_polarity;
3708 /* Mask level triggered irqs. */
3709 if (info->ioapic_trigger)
3710 entry->mask = 1;
3711 break;
3712
3713 case X86_IRQ_ALLOC_TYPE_HPET:
3714 case X86_IRQ_ALLOC_TYPE_MSI:
3715 case X86_IRQ_ALLOC_TYPE_MSIX:
3716 msg->address_hi = MSI_ADDR_BASE_HI;
3717 msg->address_lo = MSI_ADDR_BASE_LO;
3718 msg->data = irte_info->index;
3719 break;
3720
3721 default:
3722 BUG_ON(1);
3723 break;
3724 }
3725 }
3726
3727 struct amd_irte_ops irte_32_ops = {
3728 .prepare = irte_prepare,
3729 .activate = irte_activate,
3730 .deactivate = irte_deactivate,
3731 .set_affinity = irte_set_affinity,
3732 .set_allocated = irte_set_allocated,
3733 .is_allocated = irte_is_allocated,
3734 .clear_allocated = irte_clear_allocated,
3735 };
3736
3737 struct amd_irte_ops irte_128_ops = {
3738 .prepare = irte_ga_prepare,
3739 .activate = irte_ga_activate,
3740 .deactivate = irte_ga_deactivate,
3741 .set_affinity = irte_ga_set_affinity,
3742 .set_allocated = irte_ga_set_allocated,
3743 .is_allocated = irte_ga_is_allocated,
3744 .clear_allocated = irte_ga_clear_allocated,
3745 };
3746
3747 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3748 unsigned int nr_irqs, void *arg)
3749 {
3750 struct irq_alloc_info *info = arg;
3751 struct irq_data *irq_data;
3752 struct amd_ir_data *data = NULL;
3753 struct irq_cfg *cfg;
3754 int i, ret, devid;
3755 int index;
3756
3757 if (!info)
3758 return -EINVAL;
3759 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
3760 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
3761 return -EINVAL;
3762
3763 /*
3764 * With IRQ remapping enabled, don't need contiguous CPU vectors
3765 * to support multiple MSI interrupts.
3766 */
3767 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
3768 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3769
3770 devid = get_devid(info);
3771 if (devid < 0)
3772 return -EINVAL;
3773
3774 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3775 if (ret < 0)
3776 return ret;
3777
3778 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3779 struct irq_remap_table *table;
3780 struct amd_iommu *iommu;
3781
3782 table = alloc_irq_table(devid, NULL);
3783 if (table) {
3784 if (!table->min_index) {
3785 /*
3786 * Keep the first 32 indexes free for IOAPIC
3787 * interrupts.
3788 */
3789 table->min_index = 32;
3790 iommu = amd_iommu_rlookup_table[devid];
3791 for (i = 0; i < 32; ++i)
3792 iommu->irte_ops->set_allocated(table, i);
3793 }
3794 WARN_ON(table->min_index != 32);
3795 index = info->ioapic_pin;
3796 } else {
3797 index = -ENOMEM;
3798 }
3799 } else if (info->type == X86_IRQ_ALLOC_TYPE_MSI ||
3800 info->type == X86_IRQ_ALLOC_TYPE_MSIX) {
3801 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
3802
3803 index = alloc_irq_index(devid, nr_irqs, align, info->msi_dev);
3804 } else {
3805 index = alloc_irq_index(devid, nr_irqs, false, NULL);
3806 }
3807
3808 if (index < 0) {
3809 pr_warn("Failed to allocate IRTE\n");
3810 ret = index;
3811 goto out_free_parent;
3812 }
3813
3814 for (i = 0; i < nr_irqs; i++) {
3815 irq_data = irq_domain_get_irq_data(domain, virq + i);
3816 cfg = irqd_cfg(irq_data);
3817 if (!irq_data || !cfg) {
3818 ret = -EINVAL;
3819 goto out_free_data;
3820 }
3821
3822 ret = -ENOMEM;
3823 data = kzalloc(sizeof(*data), GFP_KERNEL);
3824 if (!data)
3825 goto out_free_data;
3826
3827 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3828 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
3829 else
3830 data->entry = kzalloc(sizeof(struct irte_ga),
3831 GFP_KERNEL);
3832 if (!data->entry) {
3833 kfree(data);
3834 goto out_free_data;
3835 }
3836
3837 irq_data->hwirq = (devid << 16) + i;
3838 irq_data->chip_data = data;
3839 irq_data->chip = &amd_ir_chip;
3840 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3841 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3842 }
3843
3844 return 0;
3845
3846 out_free_data:
3847 for (i--; i >= 0; i--) {
3848 irq_data = irq_domain_get_irq_data(domain, virq + i);
3849 if (irq_data)
3850 kfree(irq_data->chip_data);
3851 }
3852 for (i = 0; i < nr_irqs; i++)
3853 free_irte(devid, index + i);
3854 out_free_parent:
3855 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3856 return ret;
3857 }
3858
3859 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3860 unsigned int nr_irqs)
3861 {
3862 struct irq_2_irte *irte_info;
3863 struct irq_data *irq_data;
3864 struct amd_ir_data *data;
3865 int i;
3866
3867 for (i = 0; i < nr_irqs; i++) {
3868 irq_data = irq_domain_get_irq_data(domain, virq + i);
3869 if (irq_data && irq_data->chip_data) {
3870 data = irq_data->chip_data;
3871 irte_info = &data->irq_2_irte;
3872 free_irte(irte_info->devid, irte_info->index);
3873 kfree(data->entry);
3874 kfree(data);
3875 }
3876 }
3877 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3878 }
3879
3880 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3881 struct amd_ir_data *ir_data,
3882 struct irq_2_irte *irte_info,
3883 struct irq_cfg *cfg);
3884
3885 static int irq_remapping_activate(struct irq_domain *domain,
3886 struct irq_data *irq_data, bool reserve)
3887 {
3888 struct amd_ir_data *data = irq_data->chip_data;
3889 struct irq_2_irte *irte_info = &data->irq_2_irte;
3890 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3891 struct irq_cfg *cfg = irqd_cfg(irq_data);
3892
3893 if (!iommu)
3894 return 0;
3895
3896 iommu->irte_ops->activate(data->entry, irte_info->devid,
3897 irte_info->index);
3898 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
3899 return 0;
3900 }
3901
3902 static void irq_remapping_deactivate(struct irq_domain *domain,
3903 struct irq_data *irq_data)
3904 {
3905 struct amd_ir_data *data = irq_data->chip_data;
3906 struct irq_2_irte *irte_info = &data->irq_2_irte;
3907 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3908
3909 if (iommu)
3910 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
3911 irte_info->index);
3912 }
3913
3914 static const struct irq_domain_ops amd_ir_domain_ops = {
3915 .alloc = irq_remapping_alloc,
3916 .free = irq_remapping_free,
3917 .activate = irq_remapping_activate,
3918 .deactivate = irq_remapping_deactivate,
3919 };
3920
3921 int amd_iommu_activate_guest_mode(void *data)
3922 {
3923 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3924 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3925
3926 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3927 !entry || entry->lo.fields_vapic.guest_mode)
3928 return 0;
3929
3930 entry->lo.val = 0;
3931 entry->hi.val = 0;
3932
3933 entry->lo.fields_vapic.guest_mode = 1;
3934 entry->lo.fields_vapic.ga_log_intr = 1;
3935 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr;
3936 entry->hi.fields.vector = ir_data->ga_vector;
3937 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;
3938
3939 return modify_irte_ga(ir_data->irq_2_irte.devid,
3940 ir_data->irq_2_irte.index, entry, ir_data);
3941 }
3942 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
3943
3944 int amd_iommu_deactivate_guest_mode(void *data)
3945 {
3946 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3947 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3948 struct irq_cfg *cfg = ir_data->cfg;
3949
3950 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3951 !entry || !entry->lo.fields_vapic.guest_mode)
3952 return 0;
3953
3954 entry->lo.val = 0;
3955 entry->hi.val = 0;
3956
3957 entry->lo.fields_remap.dm = apic->irq_dest_mode;
3958 entry->lo.fields_remap.int_type = apic->irq_delivery_mode;
3959 entry->hi.fields.vector = cfg->vector;
3960 entry->lo.fields_remap.destination =
3961 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
3962 entry->hi.fields.destination =
3963 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
3964
3965 return modify_irte_ga(ir_data->irq_2_irte.devid,
3966 ir_data->irq_2_irte.index, entry, ir_data);
3967 }
3968 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
3969
3970 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
3971 {
3972 int ret;
3973 struct amd_iommu *iommu;
3974 struct amd_iommu_pi_data *pi_data = vcpu_info;
3975 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
3976 struct amd_ir_data *ir_data = data->chip_data;
3977 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3978 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
3979
3980 /* Note:
3981 * This device has never been set up for guest mode.
3982 * we should not modify the IRTE
3983 */
3984 if (!dev_data || !dev_data->use_vapic)
3985 return 0;
3986
3987 ir_data->cfg = irqd_cfg(data);
3988 pi_data->ir_data = ir_data;
3989
3990 /* Note:
3991 * SVM tries to set up for VAPIC mode, but we are in
3992 * legacy mode. So, we force legacy mode instead.
3993 */
3994 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3995 pr_debug("%s: Fall back to using intr legacy remap\n",
3996 __func__);
3997 pi_data->is_guest_mode = false;
3998 }
3999
4000 iommu = amd_iommu_rlookup_table[irte_info->devid];
4001 if (iommu == NULL)
4002 return -EINVAL;
4003
4004 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4005 if (pi_data->is_guest_mode) {
4006 ir_data->ga_root_ptr = (pi_data->base >> 12);
4007 ir_data->ga_vector = vcpu_pi_info->vector;
4008 ir_data->ga_tag = pi_data->ga_tag;
4009 ret = amd_iommu_activate_guest_mode(ir_data);
4010 if (!ret)
4011 ir_data->cached_ga_tag = pi_data->ga_tag;
4012 } else {
4013 ret = amd_iommu_deactivate_guest_mode(ir_data);
4014
4015 /*
4016 * This communicates the ga_tag back to the caller
4017 * so that it can do all the necessary clean up.
4018 */
4019 if (!ret)
4020 ir_data->cached_ga_tag = 0;
4021 }
4022
4023 return ret;
4024 }
4025
4026
4027 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4028 struct amd_ir_data *ir_data,
4029 struct irq_2_irte *irte_info,
4030 struct irq_cfg *cfg)
4031 {
4032
4033 /*
4034 * Atomically updates the IRTE with the new destination, vector
4035 * and flushes the interrupt entry cache.
4036 */
4037 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4038 irte_info->index, cfg->vector,
4039 cfg->dest_apicid);
4040 }
4041
4042 static int amd_ir_set_affinity(struct irq_data *data,
4043 const struct cpumask *mask, bool force)
4044 {
4045 struct amd_ir_data *ir_data = data->chip_data;
4046 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4047 struct irq_cfg *cfg = irqd_cfg(data);
4048 struct irq_data *parent = data->parent_data;
4049 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4050 int ret;
4051
4052 if (!iommu)
4053 return -ENODEV;
4054
4055 ret = parent->chip->irq_set_affinity(parent, mask, force);
4056 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4057 return ret;
4058
4059 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4060 /*
4061 * After this point, all the interrupts will start arriving
4062 * at the new destination. So, time to cleanup the previous
4063 * vector allocation.
4064 */
4065 send_cleanup_vector(cfg);
4066
4067 return IRQ_SET_MASK_OK_DONE;
4068 }
4069
4070 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4071 {
4072 struct amd_ir_data *ir_data = irq_data->chip_data;
4073
4074 *msg = ir_data->msi_entry;
4075 }
4076
4077 static struct irq_chip amd_ir_chip = {
4078 .name = "AMD-IR",
4079 .irq_ack = apic_ack_irq,
4080 .irq_set_affinity = amd_ir_set_affinity,
4081 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4082 .irq_compose_msi_msg = ir_compose_msi_msg,
4083 };
4084
4085 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4086 {
4087 struct fwnode_handle *fn;
4088
4089 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4090 if (!fn)
4091 return -ENOMEM;
4092 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4093 irq_domain_free_fwnode(fn);
4094 if (!iommu->ir_domain)
4095 return -ENOMEM;
4096
4097 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4098 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4099 "AMD-IR-MSI",
4100 iommu->index);
4101 return 0;
4102 }
4103
4104 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4105 {
4106 unsigned long flags;
4107 struct amd_iommu *iommu;
4108 struct irq_remap_table *table;
4109 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4110 int devid = ir_data->irq_2_irte.devid;
4111 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4112 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4113
4114 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4115 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4116 return 0;
4117
4118 iommu = amd_iommu_rlookup_table[devid];
4119 if (!iommu)
4120 return -ENODEV;
4121
4122 table = get_irq_table(devid);
4123 if (!table)
4124 return -ENODEV;
4125
4126 raw_spin_lock_irqsave(&table->lock, flags);
4127
4128 if (ref->lo.fields_vapic.guest_mode) {
4129 if (cpu >= 0) {
4130 ref->lo.fields_vapic.destination =
4131 APICID_TO_IRTE_DEST_LO(cpu);
4132 ref->hi.fields.destination =
4133 APICID_TO_IRTE_DEST_HI(cpu);
4134 }
4135 ref->lo.fields_vapic.is_run = is_run;
4136 barrier();
4137 }
4138
4139 raw_spin_unlock_irqrestore(&table->lock, flags);
4140
4141 iommu_flush_irt(iommu, devid);
4142 iommu_completion_wait(iommu);
4143 return 0;
4144 }
4145 EXPORT_SYMBOL(amd_iommu_update_ga);
4146 #endif
Linux with added FPC-III support