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Revert "tty: hvc: Fix data abort due to race in hvc_open"
[linux/fpc-iii.git] / drivers / iommu / dmar.c
blob7df5621bba8de1e188b7215308077f6c3cbd59f7
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2006, Intel Corporation.
4 *
5 * Copyright (C) 2006-2008 Intel Corporation
6 * Author: Ashok Raj <ashok.raj@intel.com>
7 * Author: Shaohua Li <shaohua.li@intel.com>
8 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
9 *
10 * This file implements early detection/parsing of Remapping Devices
11 * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
12 * tables.
13 *
14 * These routines are used by both DMA-remapping and Interrupt-remapping
15 */
16
17 #define pr_fmt(fmt) "DMAR: " fmt
18
19 #include <linux/pci.h>
20 #include <linux/dmar.h>
21 #include <linux/iova.h>
22 #include <linux/intel-iommu.h>
23 #include <linux/timer.h>
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/tboot.h>
27 #include <linux/dmi.h>
28 #include <linux/slab.h>
29 #include <linux/iommu.h>
30 #include <linux/numa.h>
31 #include <linux/limits.h>
32 #include <asm/irq_remapping.h>
33 #include <asm/iommu_table.h>
34
35 #include "irq_remapping.h"
36
37 typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *);
38 struct dmar_res_callback {
39 dmar_res_handler_t cb[ACPI_DMAR_TYPE_RESERVED];
40 void *arg[ACPI_DMAR_TYPE_RESERVED];
41 bool ignore_unhandled;
42 bool print_entry;
43 };
44
45 /*
46 * Assumptions:
47 * 1) The hotplug framework guarentees that DMAR unit will be hot-added
48 * before IO devices managed by that unit.
49 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
50 * after IO devices managed by that unit.
51 * 3) Hotplug events are rare.
52 *
53 * Locking rules for DMA and interrupt remapping related global data structures:
54 * 1) Use dmar_global_lock in process context
55 * 2) Use RCU in interrupt context
56 */
57 DECLARE_RWSEM(dmar_global_lock);
58 LIST_HEAD(dmar_drhd_units);
59
60 struct acpi_table_header * __initdata dmar_tbl;
61 static int dmar_dev_scope_status = 1;
62 static unsigned long dmar_seq_ids[BITS_TO_LONGS(DMAR_UNITS_SUPPORTED)];
63
64 static int alloc_iommu(struct dmar_drhd_unit *drhd);
65 static void free_iommu(struct intel_iommu *iommu);
66
67 extern const struct iommu_ops intel_iommu_ops;
68
69 static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
70 {
71 /*
72 * add INCLUDE_ALL at the tail, so scan the list will find it at
73 * the very end.
74 */
75 if (drhd->include_all)
76 list_add_tail_rcu(&drhd->list, &dmar_drhd_units);
77 else
78 list_add_rcu(&drhd->list, &dmar_drhd_units);
79 }
80
81 void *dmar_alloc_dev_scope(void *start, void *end, int *cnt)
82 {
83 struct acpi_dmar_device_scope *scope;
84
85 *cnt = 0;
86 while (start < end) {
87 scope = start;
88 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE ||
89 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
90 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE)
91 (*cnt)++;
92 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC &&
93 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) {
94 pr_warn("Unsupported device scope\n");
95 }
96 start += scope->length;
97 }
98 if (*cnt == 0)
99 return NULL;
100
101 return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL);
102 }
103
104 void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt)
105 {
106 int i;
107 struct device *tmp_dev;
108
109 if (*devices && *cnt) {
110 for_each_active_dev_scope(*devices, *cnt, i, tmp_dev)
111 put_device(tmp_dev);
112 kfree(*devices);
113 }
114
115 *devices = NULL;
116 *cnt = 0;
117 }
118
119 /* Optimize out kzalloc()/kfree() for normal cases */
120 static char dmar_pci_notify_info_buf[64];
121
122 static struct dmar_pci_notify_info *
123 dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event)
124 {
125 int level = 0;
126 size_t size;
127 struct pci_dev *tmp;
128 struct dmar_pci_notify_info *info;
129
130 BUG_ON(dev->is_virtfn);
131
132 /*
133 * Ignore devices that have a domain number higher than what can
134 * be looked up in DMAR, e.g. VMD subdevices with domain 0x10000
135 */
136 if (pci_domain_nr(dev->bus) > U16_MAX)
137 return NULL;
138
139 /* Only generate path[] for device addition event */
140 if (event == BUS_NOTIFY_ADD_DEVICE)
141 for (tmp = dev; tmp; tmp = tmp->bus->self)
142 level++;
143
144 size = struct_size(info, path, level);
145 if (size <= sizeof(dmar_pci_notify_info_buf)) {
146 info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf;
147 } else {
148 info = kzalloc(size, GFP_KERNEL);
149 if (!info) {
150 pr_warn("Out of memory when allocating notify_info "
151 "for %s.\n", pci_name(dev));
152 if (dmar_dev_scope_status == 0)
153 dmar_dev_scope_status = -ENOMEM;
154 return NULL;
155 }
156 }
157
158 info->event = event;
159 info->dev = dev;
160 info->seg = pci_domain_nr(dev->bus);
161 info->level = level;
162 if (event == BUS_NOTIFY_ADD_DEVICE) {
163 for (tmp = dev; tmp; tmp = tmp->bus->self) {
164 level--;
165 info->path[level].bus = tmp->bus->number;
166 info->path[level].device = PCI_SLOT(tmp->devfn);
167 info->path[level].function = PCI_FUNC(tmp->devfn);
168 if (pci_is_root_bus(tmp->bus))
169 info->bus = tmp->bus->number;
170 }
171 }
172
173 return info;
174 }
175
176 static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info)
177 {
178 if ((void *)info != dmar_pci_notify_info_buf)
179 kfree(info);
180 }
181
182 static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus,
183 struct acpi_dmar_pci_path *path, int count)
184 {
185 int i;
186
187 if (info->bus != bus)
188 goto fallback;
189 if (info->level != count)
190 goto fallback;
191
192 for (i = 0; i < count; i++) {
193 if (path[i].device != info->path[i].device ||
194 path[i].function != info->path[i].function)
195 goto fallback;
196 }
197
198 return true;
199
200 fallback:
201
202 if (count != 1)
203 return false;
204
205 i = info->level - 1;
206 if (bus == info->path[i].bus &&
207 path[0].device == info->path[i].device &&
208 path[0].function == info->path[i].function) {
209 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n",
210 bus, path[0].device, path[0].function);
211 return true;
212 }
213
214 return false;
215 }
216
217 /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */
218 int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
219 void *start, void*end, u16 segment,
220 struct dmar_dev_scope *devices,
221 int devices_cnt)
222 {
223 int i, level;
224 struct device *tmp, *dev = &info->dev->dev;
225 struct acpi_dmar_device_scope *scope;
226 struct acpi_dmar_pci_path *path;
227
228 if (segment != info->seg)
229 return 0;
230
231 for (; start < end; start += scope->length) {
232 scope = start;
233 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
234 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
235 continue;
236
237 path = (struct acpi_dmar_pci_path *)(scope + 1);
238 level = (scope->length - sizeof(*scope)) / sizeof(*path);
239 if (!dmar_match_pci_path(info, scope->bus, path, level))
240 continue;
241
242 /*
243 * We expect devices with endpoint scope to have normal PCI
244 * headers, and devices with bridge scope to have bridge PCI
245 * headers. However PCI NTB devices may be listed in the
246 * DMAR table with bridge scope, even though they have a
247 * normal PCI header. NTB devices are identified by class
248 * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch
249 * for this special case.
250 */
251 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
252 info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) ||
253 (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE &&
254 (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
255 info->dev->class >> 16 != PCI_BASE_CLASS_BRIDGE))) {
256 pr_warn("Device scope type does not match for %s\n",
257 pci_name(info->dev));
258 return -EINVAL;
259 }
260
261 for_each_dev_scope(devices, devices_cnt, i, tmp)
262 if (tmp == NULL) {
263 devices[i].bus = info->dev->bus->number;
264 devices[i].devfn = info->dev->devfn;
265 rcu_assign_pointer(devices[i].dev,
266 get_device(dev));
267 return 1;
268 }
269 BUG_ON(i >= devices_cnt);
270 }
271
272 return 0;
273 }
274
275 int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment,
276 struct dmar_dev_scope *devices, int count)
277 {
278 int index;
279 struct device *tmp;
280
281 if (info->seg != segment)
282 return 0;
283
284 for_each_active_dev_scope(devices, count, index, tmp)
285 if (tmp == &info->dev->dev) {
286 RCU_INIT_POINTER(devices[index].dev, NULL);
287 synchronize_rcu();
288 put_device(tmp);
289 return 1;
290 }
291
292 return 0;
293 }
294
295 static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info)
296 {
297 int ret = 0;
298 struct dmar_drhd_unit *dmaru;
299 struct acpi_dmar_hardware_unit *drhd;
300
301 for_each_drhd_unit(dmaru) {
302 if (dmaru->include_all)
303 continue;
304
305 drhd = container_of(dmaru->hdr,
306 struct acpi_dmar_hardware_unit, header);
307 ret = dmar_insert_dev_scope(info, (void *)(drhd + 1),
308 ((void *)drhd) + drhd->header.length,
309 dmaru->segment,
310 dmaru->devices, dmaru->devices_cnt);
311 if (ret)
312 break;
313 }
314 if (ret >= 0)
315 ret = dmar_iommu_notify_scope_dev(info);
316 if (ret < 0 && dmar_dev_scope_status == 0)
317 dmar_dev_scope_status = ret;
318
319 return ret;
320 }
321
322 static void dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info)
323 {
324 struct dmar_drhd_unit *dmaru;
325
326 for_each_drhd_unit(dmaru)
327 if (dmar_remove_dev_scope(info, dmaru->segment,
328 dmaru->devices, dmaru->devices_cnt))
329 break;
330 dmar_iommu_notify_scope_dev(info);
331 }
332
333 static int dmar_pci_bus_notifier(struct notifier_block *nb,
334 unsigned long action, void *data)
335 {
336 struct pci_dev *pdev = to_pci_dev(data);
337 struct dmar_pci_notify_info *info;
338
339 /* Only care about add/remove events for physical functions.
340 * For VFs we actually do the lookup based on the corresponding
341 * PF in device_to_iommu() anyway. */
342 if (pdev->is_virtfn)
343 return NOTIFY_DONE;
344 if (action != BUS_NOTIFY_ADD_DEVICE &&
345 action != BUS_NOTIFY_REMOVED_DEVICE)
346 return NOTIFY_DONE;
347
348 info = dmar_alloc_pci_notify_info(pdev, action);
349 if (!info)
350 return NOTIFY_DONE;
351
352 down_write(&dmar_global_lock);
353 if (action == BUS_NOTIFY_ADD_DEVICE)
354 dmar_pci_bus_add_dev(info);
355 else if (action == BUS_NOTIFY_REMOVED_DEVICE)
356 dmar_pci_bus_del_dev(info);
357 up_write(&dmar_global_lock);
358
359 dmar_free_pci_notify_info(info);
360
361 return NOTIFY_OK;
362 }
363
364 static struct notifier_block dmar_pci_bus_nb = {
365 .notifier_call = dmar_pci_bus_notifier,
366 .priority = INT_MIN,
367 };
368
369 static struct dmar_drhd_unit *
370 dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd)
371 {
372 struct dmar_drhd_unit *dmaru;
373
374 list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list,
375 dmar_rcu_check())
376 if (dmaru->segment == drhd->segment &&
377 dmaru->reg_base_addr == drhd->address)
378 return dmaru;
379
380 return NULL;
381 }
382
383 /**
384 * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
385 * structure which uniquely represent one DMA remapping hardware unit
386 * present in the platform
387 */
388 static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg)
389 {
390 struct acpi_dmar_hardware_unit *drhd;
391 struct dmar_drhd_unit *dmaru;
392 int ret;
393
394 drhd = (struct acpi_dmar_hardware_unit *)header;
395 dmaru = dmar_find_dmaru(drhd);
396 if (dmaru)
397 goto out;
398
399 dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL);
400 if (!dmaru)
401 return -ENOMEM;
402
403 /*
404 * If header is allocated from slab by ACPI _DSM method, we need to
405 * copy the content because the memory buffer will be freed on return.
406 */
407 dmaru->hdr = (void *)(dmaru + 1);
408 memcpy(dmaru->hdr, header, header->length);
409 dmaru->reg_base_addr = drhd->address;
410 dmaru->segment = drhd->segment;
411 dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */
412 dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1),
413 ((void *)drhd) + drhd->header.length,
414 &dmaru->devices_cnt);
415 if (dmaru->devices_cnt && dmaru->devices == NULL) {
416 kfree(dmaru);
417 return -ENOMEM;
418 }
419
420 ret = alloc_iommu(dmaru);
421 if (ret) {
422 dmar_free_dev_scope(&dmaru->devices,
423 &dmaru->devices_cnt);
424 kfree(dmaru);
425 return ret;
426 }
427 dmar_register_drhd_unit(dmaru);
428
429 out:
430 if (arg)
431 (*(int *)arg)++;
432
433 return 0;
434 }
435
436 static void dmar_free_drhd(struct dmar_drhd_unit *dmaru)
437 {
438 if (dmaru->devices && dmaru->devices_cnt)
439 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt);
440 if (dmaru->iommu)
441 free_iommu(dmaru->iommu);
442 kfree(dmaru);
443 }
444
445 static int __init dmar_parse_one_andd(struct acpi_dmar_header *header,
446 void *arg)
447 {
448 struct acpi_dmar_andd *andd = (void *)header;
449
450 /* Check for NUL termination within the designated length */
451 if (strnlen(andd->device_name, header->length - 8) == header->length - 8) {
452 pr_warn(FW_BUG
453 "Your BIOS is broken; ANDD object name is not NUL-terminated\n"
454 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
455 dmi_get_system_info(DMI_BIOS_VENDOR),
456 dmi_get_system_info(DMI_BIOS_VERSION),
457 dmi_get_system_info(DMI_PRODUCT_VERSION));
458 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
459 return -EINVAL;
460 }
461 pr_info("ANDD device: %x name: %s\n", andd->device_number,
462 andd->device_name);
463
464 return 0;
465 }
466
467 #ifdef CONFIG_ACPI_NUMA
468 static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg)
469 {
470 struct acpi_dmar_rhsa *rhsa;
471 struct dmar_drhd_unit *drhd;
472
473 rhsa = (struct acpi_dmar_rhsa *)header;
474 for_each_drhd_unit(drhd) {
475 if (drhd->reg_base_addr == rhsa->base_address) {
476 int node = acpi_map_pxm_to_node(rhsa->proximity_domain);
477
478 if (!node_online(node))
479 node = NUMA_NO_NODE;
480 drhd->iommu->node = node;
481 return 0;
482 }
483 }
484 pr_warn(FW_BUG
485 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n"
486 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
487 rhsa->base_address,
488 dmi_get_system_info(DMI_BIOS_VENDOR),
489 dmi_get_system_info(DMI_BIOS_VERSION),
490 dmi_get_system_info(DMI_PRODUCT_VERSION));
491 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
492
493 return 0;
494 }
495 #else
496 #define dmar_parse_one_rhsa dmar_res_noop
497 #endif
498
499 static void
500 dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
501 {
502 struct acpi_dmar_hardware_unit *drhd;
503 struct acpi_dmar_reserved_memory *rmrr;
504 struct acpi_dmar_atsr *atsr;
505 struct acpi_dmar_rhsa *rhsa;
506
507 switch (header->type) {
508 case ACPI_DMAR_TYPE_HARDWARE_UNIT:
509 drhd = container_of(header, struct acpi_dmar_hardware_unit,
510 header);
511 pr_info("DRHD base: %#016Lx flags: %#x\n",
512 (unsigned long long)drhd->address, drhd->flags);
513 break;
514 case ACPI_DMAR_TYPE_RESERVED_MEMORY:
515 rmrr = container_of(header, struct acpi_dmar_reserved_memory,
516 header);
517 pr_info("RMRR base: %#016Lx end: %#016Lx\n",
518 (unsigned long long)rmrr->base_address,
519 (unsigned long long)rmrr->end_address);
520 break;
521 case ACPI_DMAR_TYPE_ROOT_ATS:
522 atsr = container_of(header, struct acpi_dmar_atsr, header);
523 pr_info("ATSR flags: %#x\n", atsr->flags);
524 break;
525 case ACPI_DMAR_TYPE_HARDWARE_AFFINITY:
526 rhsa = container_of(header, struct acpi_dmar_rhsa, header);
527 pr_info("RHSA base: %#016Lx proximity domain: %#x\n",
528 (unsigned long long)rhsa->base_address,
529 rhsa->proximity_domain);
530 break;
531 case ACPI_DMAR_TYPE_NAMESPACE:
532 /* We don't print this here because we need to sanity-check
533 it first. So print it in dmar_parse_one_andd() instead. */
534 break;
535 }
536 }
537
538 /**
539 * dmar_table_detect - checks to see if the platform supports DMAR devices
540 */
541 static int __init dmar_table_detect(void)
542 {
543 acpi_status status = AE_OK;
544
545 /* if we could find DMAR table, then there are DMAR devices */
546 status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
547
548 if (ACPI_SUCCESS(status) && !dmar_tbl) {
549 pr_warn("Unable to map DMAR\n");
550 status = AE_NOT_FOUND;
551 }
552
553 return ACPI_SUCCESS(status) ? 0 : -ENOENT;
554 }
555
556 static int dmar_walk_remapping_entries(struct acpi_dmar_header *start,
557 size_t len, struct dmar_res_callback *cb)
558 {
559 struct acpi_dmar_header *iter, *next;
560 struct acpi_dmar_header *end = ((void *)start) + len;
561
562 for (iter = start; iter < end; iter = next) {
563 next = (void *)iter + iter->length;
564 if (iter->length == 0) {
565 /* Avoid looping forever on bad ACPI tables */
566 pr_debug(FW_BUG "Invalid 0-length structure\n");
567 break;
568 } else if (next > end) {
569 /* Avoid passing table end */
570 pr_warn(FW_BUG "Record passes table end\n");
571 return -EINVAL;
572 }
573
574 if (cb->print_entry)
575 dmar_table_print_dmar_entry(iter);
576
577 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) {
578 /* continue for forward compatibility */
579 pr_debug("Unknown DMAR structure type %d\n",
580 iter->type);
581 } else if (cb->cb[iter->type]) {
582 int ret;
583
584 ret = cb->cb[iter->type](iter, cb->arg[iter->type]);
585 if (ret)
586 return ret;
587 } else if (!cb->ignore_unhandled) {
588 pr_warn("No handler for DMAR structure type %d\n",
589 iter->type);
590 return -EINVAL;
591 }
592 }
593
594 return 0;
595 }
596
597 static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar,
598 struct dmar_res_callback *cb)
599 {
600 return dmar_walk_remapping_entries((void *)(dmar + 1),
601 dmar->header.length - sizeof(*dmar), cb);
602 }
603
604 /**
605 * parse_dmar_table - parses the DMA reporting table
606 */
607 static int __init
608 parse_dmar_table(void)
609 {
610 struct acpi_table_dmar *dmar;
611 int drhd_count = 0;
612 int ret;
613 struct dmar_res_callback cb = {
614 .print_entry = true,
615 .ignore_unhandled = true,
616 .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count,
617 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd,
618 .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr,
619 .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr,
620 .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa,
621 .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd,
622 };
623
624 /*
625 * Do it again, earlier dmar_tbl mapping could be mapped with
626 * fixed map.
627 */
628 dmar_table_detect();
629
630 /*
631 * ACPI tables may not be DMA protected by tboot, so use DMAR copy
632 * SINIT saved in SinitMleData in TXT heap (which is DMA protected)
633 */
634 dmar_tbl = tboot_get_dmar_table(dmar_tbl);
635
636 dmar = (struct acpi_table_dmar *)dmar_tbl;
637 if (!dmar)
638 return -ENODEV;
639
640 if (dmar->width < PAGE_SHIFT - 1) {
641 pr_warn("Invalid DMAR haw\n");
642 return -EINVAL;
643 }
644
645 pr_info("Host address width %d\n", dmar->width + 1);
646 ret = dmar_walk_dmar_table(dmar, &cb);
647 if (ret == 0 && drhd_count == 0)
648 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n");
649
650 return ret;
651 }
652
653 static int dmar_pci_device_match(struct dmar_dev_scope devices[],
654 int cnt, struct pci_dev *dev)
655 {
656 int index;
657 struct device *tmp;
658
659 while (dev) {
660 for_each_active_dev_scope(devices, cnt, index, tmp)
661 if (dev_is_pci(tmp) && dev == to_pci_dev(tmp))
662 return 1;
663
664 /* Check our parent */
665 dev = dev->bus->self;
666 }
667
668 return 0;
669 }
670
671 struct dmar_drhd_unit *
672 dmar_find_matched_drhd_unit(struct pci_dev *dev)
673 {
674 struct dmar_drhd_unit *dmaru;
675 struct acpi_dmar_hardware_unit *drhd;
676
677 dev = pci_physfn(dev);
678
679 rcu_read_lock();
680 for_each_drhd_unit(dmaru) {
681 drhd = container_of(dmaru->hdr,
682 struct acpi_dmar_hardware_unit,
683 header);
684
685 if (dmaru->include_all &&
686 drhd->segment == pci_domain_nr(dev->bus))
687 goto out;
688
689 if (dmar_pci_device_match(dmaru->devices,
690 dmaru->devices_cnt, dev))
691 goto out;
692 }
693 dmaru = NULL;
694 out:
695 rcu_read_unlock();
696
697 return dmaru;
698 }
699
700 static void __init dmar_acpi_insert_dev_scope(u8 device_number,
701 struct acpi_device *adev)
702 {
703 struct dmar_drhd_unit *dmaru;
704 struct acpi_dmar_hardware_unit *drhd;
705 struct acpi_dmar_device_scope *scope;
706 struct device *tmp;
707 int i;
708 struct acpi_dmar_pci_path *path;
709
710 for_each_drhd_unit(dmaru) {
711 drhd = container_of(dmaru->hdr,
712 struct acpi_dmar_hardware_unit,
713 header);
714
715 for (scope = (void *)(drhd + 1);
716 (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length;
717 scope = ((void *)scope) + scope->length) {
718 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE)
719 continue;
720 if (scope->enumeration_id != device_number)
721 continue;
722
723 path = (void *)(scope + 1);
724 pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n",
725 dev_name(&adev->dev), dmaru->reg_base_addr,
726 scope->bus, path->device, path->function);
727 for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp)
728 if (tmp == NULL) {
729 dmaru->devices[i].bus = scope->bus;
730 dmaru->devices[i].devfn = PCI_DEVFN(path->device,
731 path->function);
732 rcu_assign_pointer(dmaru->devices[i].dev,
733 get_device(&adev->dev));
734 return;
735 }
736 BUG_ON(i >= dmaru->devices_cnt);
737 }
738 }
739 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n",
740 device_number, dev_name(&adev->dev));
741 }
742
743 static int __init dmar_acpi_dev_scope_init(void)
744 {
745 struct acpi_dmar_andd *andd;
746
747 if (dmar_tbl == NULL)
748 return -ENODEV;
749
750 for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar);
751 ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length;
752 andd = ((void *)andd) + andd->header.length) {
753 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) {
754 acpi_handle h;
755 struct acpi_device *adev;
756
757 if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT,
758 andd->device_name,
759 &h))) {
760 pr_err("Failed to find handle for ACPI object %s\n",
761 andd->device_name);
762 continue;
763 }
764 if (acpi_bus_get_device(h, &adev)) {
765 pr_err("Failed to get device for ACPI object %s\n",
766 andd->device_name);
767 continue;
768 }
769 dmar_acpi_insert_dev_scope(andd->device_number, adev);
770 }
771 }
772 return 0;
773 }
774
775 int __init dmar_dev_scope_init(void)
776 {
777 struct pci_dev *dev = NULL;
778 struct dmar_pci_notify_info *info;
779
780 if (dmar_dev_scope_status != 1)
781 return dmar_dev_scope_status;
782
783 if (list_empty(&dmar_drhd_units)) {
784 dmar_dev_scope_status = -ENODEV;
785 } else {
786 dmar_dev_scope_status = 0;
787
788 dmar_acpi_dev_scope_init();
789
790 for_each_pci_dev(dev) {
791 if (dev->is_virtfn)
792 continue;
793
794 info = dmar_alloc_pci_notify_info(dev,
795 BUS_NOTIFY_ADD_DEVICE);
796 if (!info) {
797 return dmar_dev_scope_status;
798 } else {
799 dmar_pci_bus_add_dev(info);
800 dmar_free_pci_notify_info(info);
801 }
802 }
803 }
804
805 return dmar_dev_scope_status;
806 }
807
808 void __init dmar_register_bus_notifier(void)
809 {
810 bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb);
811 }
812
813
814 int __init dmar_table_init(void)
815 {
816 static int dmar_table_initialized;
817 int ret;
818
819 if (dmar_table_initialized == 0) {
820 ret = parse_dmar_table();
821 if (ret < 0) {
822 if (ret != -ENODEV)
823 pr_info("Parse DMAR table failure.\n");
824 } else if (list_empty(&dmar_drhd_units)) {
825 pr_info("No DMAR devices found\n");
826 ret = -ENODEV;
827 }
828
829 if (ret < 0)
830 dmar_table_initialized = ret;
831 else
832 dmar_table_initialized = 1;
833 }
834
835 return dmar_table_initialized < 0 ? dmar_table_initialized : 0;
836 }
837
838 static void warn_invalid_dmar(u64 addr, const char *message)
839 {
840 pr_warn_once(FW_BUG
841 "Your BIOS is broken; DMAR reported at address %llx%s!\n"
842 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
843 addr, message,
844 dmi_get_system_info(DMI_BIOS_VENDOR),
845 dmi_get_system_info(DMI_BIOS_VERSION),
846 dmi_get_system_info(DMI_PRODUCT_VERSION));
847 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
848 }
849
850 static int __ref
851 dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg)
852 {
853 struct acpi_dmar_hardware_unit *drhd;
854 void __iomem *addr;
855 u64 cap, ecap;
856
857 drhd = (void *)entry;
858 if (!drhd->address) {
859 warn_invalid_dmar(0, "");
860 return -EINVAL;
861 }
862
863 if (arg)
864 addr = ioremap(drhd->address, VTD_PAGE_SIZE);
865 else
866 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE);
867 if (!addr) {
868 pr_warn("Can't validate DRHD address: %llx\n", drhd->address);
869 return -EINVAL;
870 }
871
872 cap = dmar_readq(addr + DMAR_CAP_REG);
873 ecap = dmar_readq(addr + DMAR_ECAP_REG);
874
875 if (arg)
876 iounmap(addr);
877 else
878 early_iounmap(addr, VTD_PAGE_SIZE);
879
880 if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) {
881 warn_invalid_dmar(drhd->address, " returns all ones");
882 return -EINVAL;
883 }
884
885 return 0;
886 }
887
888 int __init detect_intel_iommu(void)
889 {
890 int ret;
891 struct dmar_res_callback validate_drhd_cb = {
892 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd,
893 .ignore_unhandled = true,
894 };
895
896 down_write(&dmar_global_lock);
897 ret = dmar_table_detect();
898 if (!ret)
899 ret = dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl,
900 &validate_drhd_cb);
901 if (!ret && !no_iommu && !iommu_detected &&
902 (!dmar_disabled || dmar_platform_optin())) {
903 iommu_detected = 1;
904 /* Make sure ACS will be enabled */
905 pci_request_acs();
906 }
907
908 #ifdef CONFIG_X86
909 if (!ret) {
910 x86_init.iommu.iommu_init = intel_iommu_init;
911 x86_platform.iommu_shutdown = intel_iommu_shutdown;
912 }
913
914 #endif
915
916 if (dmar_tbl) {
917 acpi_put_table(dmar_tbl);
918 dmar_tbl = NULL;
919 }
920 up_write(&dmar_global_lock);
921
922 return ret ? ret : 1;
923 }
924
925 static void unmap_iommu(struct intel_iommu *iommu)
926 {
927 iounmap(iommu->reg);
928 release_mem_region(iommu->reg_phys, iommu->reg_size);
929 }
930
931 /**
932 * map_iommu: map the iommu's registers
933 * @iommu: the iommu to map
934 * @phys_addr: the physical address of the base resgister
935 *
936 * Memory map the iommu's registers. Start w/ a single page, and
937 * possibly expand if that turns out to be insufficent.
938 */
939 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
940 {
941 int map_size, err=0;
942
943 iommu->reg_phys = phys_addr;
944 iommu->reg_size = VTD_PAGE_SIZE;
945
946 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {
947 pr_err("Can't reserve memory\n");
948 err = -EBUSY;
949 goto out;
950 }
951
952 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
953 if (!iommu->reg) {
954 pr_err("Can't map the region\n");
955 err = -ENOMEM;
956 goto release;
957 }
958
959 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
960 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
961
962 if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {
963 err = -EINVAL;
964 warn_invalid_dmar(phys_addr, " returns all ones");
965 goto unmap;
966 }
967
968 /* the registers might be more than one page */
969 map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
970 cap_max_fault_reg_offset(iommu->cap));
971 map_size = VTD_PAGE_ALIGN(map_size);
972 if (map_size > iommu->reg_size) {
973 iounmap(iommu->reg);
974 release_mem_region(iommu->reg_phys, iommu->reg_size);
975 iommu->reg_size = map_size;
976 if (!request_mem_region(iommu->reg_phys, iommu->reg_size,
977 iommu->name)) {
978 pr_err("Can't reserve memory\n");
979 err = -EBUSY;
980 goto out;
981 }
982 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
983 if (!iommu->reg) {
984 pr_err("Can't map the region\n");
985 err = -ENOMEM;
986 goto release;
987 }
988 }
989 err = 0;
990 goto out;
991
992 unmap:
993 iounmap(iommu->reg);
994 release:
995 release_mem_region(iommu->reg_phys, iommu->reg_size);
996 out:
997 return err;
998 }
999
1000 static int dmar_alloc_seq_id(struct intel_iommu *iommu)
1001 {
1002 iommu->seq_id = find_first_zero_bit(dmar_seq_ids,
1003 DMAR_UNITS_SUPPORTED);
1004 if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) {
1005 iommu->seq_id = -1;
1006 } else {
1007 set_bit(iommu->seq_id, dmar_seq_ids);
1008 sprintf(iommu->name, "dmar%d", iommu->seq_id);
1009 }
1010
1011 return iommu->seq_id;
1012 }
1013
1014 static void dmar_free_seq_id(struct intel_iommu *iommu)
1015 {
1016 if (iommu->seq_id >= 0) {
1017 clear_bit(iommu->seq_id, dmar_seq_ids);
1018 iommu->seq_id = -1;
1019 }
1020 }
1021
1022 static int alloc_iommu(struct dmar_drhd_unit *drhd)
1023 {
1024 struct intel_iommu *iommu;
1025 u32 ver, sts;
1026 int agaw = 0;
1027 int msagaw = 0;
1028 int err;
1029
1030 if (!drhd->reg_base_addr) {
1031 warn_invalid_dmar(0, "");
1032 return -EINVAL;
1033 }
1034
1035 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
1036 if (!iommu)
1037 return -ENOMEM;
1038
1039 if (dmar_alloc_seq_id(iommu) < 0) {
1040 pr_err("Failed to allocate seq_id\n");
1041 err = -ENOSPC;
1042 goto error;
1043 }
1044
1045 err = map_iommu(iommu, drhd->reg_base_addr);
1046 if (err) {
1047 pr_err("Failed to map %s\n", iommu->name);
1048 goto error_free_seq_id;
1049 }
1050
1051 err = -EINVAL;
1052 agaw = iommu_calculate_agaw(iommu);
1053 if (agaw < 0) {
1054 pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n",
1055 iommu->seq_id);
1056 goto err_unmap;
1057 }
1058 msagaw = iommu_calculate_max_sagaw(iommu);
1059 if (msagaw < 0) {
1060 pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n",
1061 iommu->seq_id);
1062 goto err_unmap;
1063 }
1064 iommu->agaw = agaw;
1065 iommu->msagaw = msagaw;
1066 iommu->segment = drhd->segment;
1067
1068 iommu->node = NUMA_NO_NODE;
1069
1070 ver = readl(iommu->reg + DMAR_VER_REG);
1071 pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n",
1072 iommu->name,
1073 (unsigned long long)drhd->reg_base_addr,
1074 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
1075 (unsigned long long)iommu->cap,
1076 (unsigned long long)iommu->ecap);
1077
1078 /* Reflect status in gcmd */
1079 sts = readl(iommu->reg + DMAR_GSTS_REG);
1080 if (sts & DMA_GSTS_IRES)
1081 iommu->gcmd |= DMA_GCMD_IRE;
1082 if (sts & DMA_GSTS_TES)
1083 iommu->gcmd |= DMA_GCMD_TE;
1084 if (sts & DMA_GSTS_QIES)
1085 iommu->gcmd |= DMA_GCMD_QIE;
1086
1087 raw_spin_lock_init(&iommu->register_lock);
1088
1089 if (intel_iommu_enabled) {
1090 err = iommu_device_sysfs_add(&iommu->iommu, NULL,
1091 intel_iommu_groups,
1092 "%s", iommu->name);
1093 if (err)
1094 goto err_unmap;
1095
1096 iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops);
1097
1098 err = iommu_device_register(&iommu->iommu);
1099 if (err)
1100 goto err_unmap;
1101 }
1102
1103 drhd->iommu = iommu;
1104
1105 return 0;
1106
1107 err_unmap:
1108 unmap_iommu(iommu);
1109 error_free_seq_id:
1110 dmar_free_seq_id(iommu);
1111 error:
1112 kfree(iommu);
1113 return err;
1114 }
1115
1116 static void free_iommu(struct intel_iommu *iommu)
1117 {
1118 if (intel_iommu_enabled) {
1119 iommu_device_unregister(&iommu->iommu);
1120 iommu_device_sysfs_remove(&iommu->iommu);
1121 }
1122
1123 if (iommu->irq) {
1124 if (iommu->pr_irq) {
1125 free_irq(iommu->pr_irq, iommu);
1126 dmar_free_hwirq(iommu->pr_irq);
1127 iommu->pr_irq = 0;
1128 }
1129 free_irq(iommu->irq, iommu);
1130 dmar_free_hwirq(iommu->irq);
1131 iommu->irq = 0;
1132 }
1133
1134 if (iommu->qi) {
1135 free_page((unsigned long)iommu->qi->desc);
1136 kfree(iommu->qi->desc_status);
1137 kfree(iommu->qi);
1138 }
1139
1140 if (iommu->reg)
1141 unmap_iommu(iommu);
1142
1143 dmar_free_seq_id(iommu);
1144 kfree(iommu);
1145 }
1146
1147 /*
1148 * Reclaim all the submitted descriptors which have completed its work.
1149 */
1150 static inline void reclaim_free_desc(struct q_inval *qi)
1151 {
1152 while (qi->desc_status[qi->free_tail] == QI_DONE ||
1153 qi->desc_status[qi->free_tail] == QI_ABORT) {
1154 qi->desc_status[qi->free_tail] = QI_FREE;
1155 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH;
1156 qi->free_cnt++;
1157 }
1158 }
1159
1160 static int qi_check_fault(struct intel_iommu *iommu, int index)
1161 {
1162 u32 fault;
1163 int head, tail;
1164 struct q_inval *qi = iommu->qi;
1165 int wait_index = (index + 1) % QI_LENGTH;
1166 int shift = qi_shift(iommu);
1167
1168 if (qi->desc_status[wait_index] == QI_ABORT)
1169 return -EAGAIN;
1170
1171 fault = readl(iommu->reg + DMAR_FSTS_REG);
1172
1173 /*
1174 * If IQE happens, the head points to the descriptor associated
1175 * with the error. No new descriptors are fetched until the IQE
1176 * is cleared.
1177 */
1178 if (fault & DMA_FSTS_IQE) {
1179 head = readl(iommu->reg + DMAR_IQH_REG);
1180 if ((head >> shift) == index) {
1181 struct qi_desc *desc = qi->desc + head;
1182
1183 /*
1184 * desc->qw2 and desc->qw3 are either reserved or
1185 * used by software as private data. We won't print
1186 * out these two qw's for security consideration.
1187 */
1188 pr_err("VT-d detected invalid descriptor: qw0 = %llx, qw1 = %llx\n",
1189 (unsigned long long)desc->qw0,
1190 (unsigned long long)desc->qw1);
1191 memcpy(desc, qi->desc + (wait_index << shift),
1192 1 << shift);
1193 writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);
1194 return -EINVAL;
1195 }
1196 }
1197
1198 /*
1199 * If ITE happens, all pending wait_desc commands are aborted.
1200 * No new descriptors are fetched until the ITE is cleared.
1201 */
1202 if (fault & DMA_FSTS_ITE) {
1203 head = readl(iommu->reg + DMAR_IQH_REG);
1204 head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
1205 head |= 1;
1206 tail = readl(iommu->reg + DMAR_IQT_REG);
1207 tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
1208
1209 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
1210
1211 do {
1212 if (qi->desc_status[head] == QI_IN_USE)
1213 qi->desc_status[head] = QI_ABORT;
1214 head = (head - 2 + QI_LENGTH) % QI_LENGTH;
1215 } while (head != tail);
1216
1217 if (qi->desc_status[wait_index] == QI_ABORT)
1218 return -EAGAIN;
1219 }
1220
1221 if (fault & DMA_FSTS_ICE)
1222 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);
1223
1224 return 0;
1225 }
1226
1227 /*
1228 * Submit the queued invalidation descriptor to the remapping
1229 * hardware unit and wait for its completion.
1230 */
1231 int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu)
1232 {
1233 int rc;
1234 struct q_inval *qi = iommu->qi;
1235 int offset, shift, length;
1236 struct qi_desc wait_desc;
1237 int wait_index, index;
1238 unsigned long flags;
1239
1240 if (!qi)
1241 return 0;
1242
1243 restart:
1244 rc = 0;
1245
1246 raw_spin_lock_irqsave(&qi->q_lock, flags);
1247 while (qi->free_cnt < 3) {
1248 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1249 cpu_relax();
1250 raw_spin_lock_irqsave(&qi->q_lock, flags);
1251 }
1252
1253 index = qi->free_head;
1254 wait_index = (index + 1) % QI_LENGTH;
1255 shift = qi_shift(iommu);
1256 length = 1 << shift;
1257
1258 qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE;
1259
1260 offset = index << shift;
1261 memcpy(qi->desc + offset, desc, length);
1262 wait_desc.qw0 = QI_IWD_STATUS_DATA(QI_DONE) |
1263 QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
1264 wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]);
1265 wait_desc.qw2 = 0;
1266 wait_desc.qw3 = 0;
1267
1268 offset = wait_index << shift;
1269 memcpy(qi->desc + offset, &wait_desc, length);
1270
1271 qi->free_head = (qi->free_head + 2) % QI_LENGTH;
1272 qi->free_cnt -= 2;
1273
1274 /*
1275 * update the HW tail register indicating the presence of
1276 * new descriptors.
1277 */
1278 writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG);
1279
1280 while (qi->desc_status[wait_index] != QI_DONE) {
1281 /*
1282 * We will leave the interrupts disabled, to prevent interrupt
1283 * context to queue another cmd while a cmd is already submitted
1284 * and waiting for completion on this cpu. This is to avoid
1285 * a deadlock where the interrupt context can wait indefinitely
1286 * for free slots in the queue.
1287 */
1288 rc = qi_check_fault(iommu, index);
1289 if (rc)
1290 break;
1291
1292 raw_spin_unlock(&qi->q_lock);
1293 cpu_relax();
1294 raw_spin_lock(&qi->q_lock);
1295 }
1296
1297 qi->desc_status[index] = QI_DONE;
1298
1299 reclaim_free_desc(qi);
1300 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1301
1302 if (rc == -EAGAIN)
1303 goto restart;
1304
1305 return rc;
1306 }
1307
1308 /*
1309 * Flush the global interrupt entry cache.
1310 */
1311 void qi_global_iec(struct intel_iommu *iommu)
1312 {
1313 struct qi_desc desc;
1314
1315 desc.qw0 = QI_IEC_TYPE;
1316 desc.qw1 = 0;
1317 desc.qw2 = 0;
1318 desc.qw3 = 0;
1319
1320 /* should never fail */
1321 qi_submit_sync(&desc, iommu);
1322 }
1323
1324 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
1325 u64 type)
1326 {
1327 struct qi_desc desc;
1328
1329 desc.qw0 = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
1330 | QI_CC_GRAN(type) | QI_CC_TYPE;
1331 desc.qw1 = 0;
1332 desc.qw2 = 0;
1333 desc.qw3 = 0;
1334
1335 qi_submit_sync(&desc, iommu);
1336 }
1337
1338 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1339 unsigned int size_order, u64 type)
1340 {
1341 u8 dw = 0, dr = 0;
1342
1343 struct qi_desc desc;
1344 int ih = 0;
1345
1346 if (cap_write_drain(iommu->cap))
1347 dw = 1;
1348
1349 if (cap_read_drain(iommu->cap))
1350 dr = 1;
1351
1352 desc.qw0 = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
1353 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
1354 desc.qw1 = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
1355 | QI_IOTLB_AM(size_order);
1356 desc.qw2 = 0;
1357 desc.qw3 = 0;
1358
1359 qi_submit_sync(&desc, iommu);
1360 }
1361
1362 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
1363 u16 qdep, u64 addr, unsigned mask)
1364 {
1365 struct qi_desc desc;
1366
1367 if (mask) {
1368 addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
1369 desc.qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
1370 } else
1371 desc.qw1 = QI_DEV_IOTLB_ADDR(addr);
1372
1373 if (qdep >= QI_DEV_IOTLB_MAX_INVS)
1374 qdep = 0;
1375
1376 desc.qw0 = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
1377 QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid);
1378 desc.qw2 = 0;
1379 desc.qw3 = 0;
1380
1381 qi_submit_sync(&desc, iommu);
1382 }
1383
1384 /* PASID-based IOTLB invalidation */
1385 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
1386 unsigned long npages, bool ih)
1387 {
1388 struct qi_desc desc = {.qw2 = 0, .qw3 = 0};
1389
1390 /*
1391 * npages == -1 means a PASID-selective invalidation, otherwise,
1392 * a positive value for Page-selective-within-PASID invalidation.
1393 * 0 is not a valid input.
1394 */
1395 if (WARN_ON(!npages)) {
1396 pr_err("Invalid input npages = %ld\n", npages);
1397 return;
1398 }
1399
1400 if (npages == -1) {
1401 desc.qw0 = QI_EIOTLB_PASID(pasid) |
1402 QI_EIOTLB_DID(did) |
1403 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
1404 QI_EIOTLB_TYPE;
1405 desc.qw1 = 0;
1406 } else {
1407 int mask = ilog2(__roundup_pow_of_two(npages));
1408 unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask));
1409
1410 if (WARN_ON_ONCE(!ALIGN(addr, align)))
1411 addr &= ~(align - 1);
1412
1413 desc.qw0 = QI_EIOTLB_PASID(pasid) |
1414 QI_EIOTLB_DID(did) |
1415 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
1416 QI_EIOTLB_TYPE;
1417 desc.qw1 = QI_EIOTLB_ADDR(addr) |
1418 QI_EIOTLB_IH(ih) |
1419 QI_EIOTLB_AM(mask);
1420 }
1421
1422 qi_submit_sync(&desc, iommu);
1423 }
1424
1425 /*
1426 * Disable Queued Invalidation interface.
1427 */
1428 void dmar_disable_qi(struct intel_iommu *iommu)
1429 {
1430 unsigned long flags;
1431 u32 sts;
1432 cycles_t start_time = get_cycles();
1433
1434 if (!ecap_qis(iommu->ecap))
1435 return;
1436
1437 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1438
1439 sts = readl(iommu->reg + DMAR_GSTS_REG);
1440 if (!(sts & DMA_GSTS_QIES))
1441 goto end;
1442
1443 /*
1444 * Give a chance to HW to complete the pending invalidation requests.
1445 */
1446 while ((readl(iommu->reg + DMAR_IQT_REG) !=
1447 readl(iommu->reg + DMAR_IQH_REG)) &&
1448 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time)))
1449 cpu_relax();
1450
1451 iommu->gcmd &= ~DMA_GCMD_QIE;
1452 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1453
1454 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
1455 !(sts & DMA_GSTS_QIES), sts);
1456 end:
1457 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1458 }
1459
1460 /*
1461 * Enable queued invalidation.
1462 */
1463 static void __dmar_enable_qi(struct intel_iommu *iommu)
1464 {
1465 u32 sts;
1466 unsigned long flags;
1467 struct q_inval *qi = iommu->qi;
1468 u64 val = virt_to_phys(qi->desc);
1469
1470 qi->free_head = qi->free_tail = 0;
1471 qi->free_cnt = QI_LENGTH;
1472
1473 /*
1474 * Set DW=1 and QS=1 in IQA_REG when Scalable Mode capability
1475 * is present.
1476 */
1477 if (ecap_smts(iommu->ecap))
1478 val |= (1 << 11) | 1;
1479
1480 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1481
1482 /* write zero to the tail reg */
1483 writel(0, iommu->reg + DMAR_IQT_REG);
1484
1485 dmar_writeq(iommu->reg + DMAR_IQA_REG, val);
1486
1487 iommu->gcmd |= DMA_GCMD_QIE;
1488 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1489
1490 /* Make sure hardware complete it */
1491 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
1492
1493 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1494 }
1495
1496 /*
1497 * Enable Queued Invalidation interface. This is a must to support
1498 * interrupt-remapping. Also used by DMA-remapping, which replaces
1499 * register based IOTLB invalidation.
1500 */
1501 int dmar_enable_qi(struct intel_iommu *iommu)
1502 {
1503 struct q_inval *qi;
1504 struct page *desc_page;
1505
1506 if (!ecap_qis(iommu->ecap))
1507 return -ENOENT;
1508
1509 /*
1510 * queued invalidation is already setup and enabled.
1511 */
1512 if (iommu->qi)
1513 return 0;
1514
1515 iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);
1516 if (!iommu->qi)
1517 return -ENOMEM;
1518
1519 qi = iommu->qi;
1520
1521 /*
1522 * Need two pages to accommodate 256 descriptors of 256 bits each
1523 * if the remapping hardware supports scalable mode translation.
1524 */
1525 desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,
1526 !!ecap_smts(iommu->ecap));
1527 if (!desc_page) {
1528 kfree(qi);
1529 iommu->qi = NULL;
1530 return -ENOMEM;
1531 }
1532
1533 qi->desc = page_address(desc_page);
1534
1535 qi->desc_status = kcalloc(QI_LENGTH, sizeof(int), GFP_ATOMIC);
1536 if (!qi->desc_status) {
1537 free_page((unsigned long) qi->desc);
1538 kfree(qi);
1539 iommu->qi = NULL;
1540 return -ENOMEM;
1541 }
1542
1543 raw_spin_lock_init(&qi->q_lock);
1544
1545 __dmar_enable_qi(iommu);
1546
1547 return 0;
1548 }
1549
1550 /* iommu interrupt handling. Most stuff are MSI-like. */
1551
1552 enum faulttype {
1553 DMA_REMAP,
1554 INTR_REMAP,
1555 UNKNOWN,
1556 };
1557
1558 static const char *dma_remap_fault_reasons[] =
1559 {
1560 "Software",
1561 "Present bit in root entry is clear",
1562 "Present bit in context entry is clear",
1563 "Invalid context entry",
1564 "Access beyond MGAW",
1565 "PTE Write access is not set",
1566 "PTE Read access is not set",
1567 "Next page table ptr is invalid",
1568 "Root table address invalid",
1569 "Context table ptr is invalid",
1570 "non-zero reserved fields in RTP",
1571 "non-zero reserved fields in CTP",
1572 "non-zero reserved fields in PTE",
1573 "PCE for translation request specifies blocking",
1574 };
1575
1576 static const char * const dma_remap_sm_fault_reasons[] = {
1577 "SM: Invalid Root Table Address",
1578 "SM: TTM 0 for request with PASID",
1579 "SM: TTM 0 for page group request",
1580 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x33-0x37 */
1581 "SM: Error attempting to access Root Entry",
1582 "SM: Present bit in Root Entry is clear",
1583 "SM: Non-zero reserved field set in Root Entry",
1584 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x3B-0x3F */
1585 "SM: Error attempting to access Context Entry",
1586 "SM: Present bit in Context Entry is clear",
1587 "SM: Non-zero reserved field set in the Context Entry",
1588 "SM: Invalid Context Entry",
1589 "SM: DTE field in Context Entry is clear",
1590 "SM: PASID Enable field in Context Entry is clear",
1591 "SM: PASID is larger than the max in Context Entry",
1592 "SM: PRE field in Context-Entry is clear",
1593 "SM: RID_PASID field error in Context-Entry",
1594 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x49-0x4F */
1595 "SM: Error attempting to access the PASID Directory Entry",
1596 "SM: Present bit in Directory Entry is clear",
1597 "SM: Non-zero reserved field set in PASID Directory Entry",
1598 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x53-0x57 */
1599 "SM: Error attempting to access PASID Table Entry",
1600 "SM: Present bit in PASID Table Entry is clear",
1601 "SM: Non-zero reserved field set in PASID Table Entry",
1602 "SM: Invalid Scalable-Mode PASID Table Entry",
1603 "SM: ERE field is clear in PASID Table Entry",
1604 "SM: SRE field is clear in PASID Table Entry",
1605 "Unknown", "Unknown",/* 0x5E-0x5F */
1606 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x60-0x67 */
1607 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x68-0x6F */
1608 "SM: Error attempting to access first-level paging entry",
1609 "SM: Present bit in first-level paging entry is clear",
1610 "SM: Non-zero reserved field set in first-level paging entry",
1611 "SM: Error attempting to access FL-PML4 entry",
1612 "SM: First-level entry address beyond MGAW in Nested translation",
1613 "SM: Read permission error in FL-PML4 entry in Nested translation",
1614 "SM: Read permission error in first-level paging entry in Nested translation",
1615 "SM: Write permission error in first-level paging entry in Nested translation",
1616 "SM: Error attempting to access second-level paging entry",
1617 "SM: Read/Write permission error in second-level paging entry",
1618 "SM: Non-zero reserved field set in second-level paging entry",
1619 "SM: Invalid second-level page table pointer",
1620 "SM: A/D bit update needed in second-level entry when set up in no snoop",
1621 "Unknown", "Unknown", "Unknown", /* 0x7D-0x7F */
1622 "SM: Address in first-level translation is not canonical",
1623 "SM: U/S set 0 for first-level translation with user privilege",
1624 "SM: No execute permission for request with PASID and ER=1",
1625 "SM: Address beyond the DMA hardware max",
1626 "SM: Second-level entry address beyond the max",
1627 "SM: No write permission for Write/AtomicOp request",
1628 "SM: No read permission for Read/AtomicOp request",
1629 "SM: Invalid address-interrupt address",
1630 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x88-0x8F */
1631 "SM: A/D bit update needed in first-level entry when set up in no snoop",
1632 };
1633
1634 static const char *irq_remap_fault_reasons[] =
1635 {
1636 "Detected reserved fields in the decoded interrupt-remapped request",
1637 "Interrupt index exceeded the interrupt-remapping table size",
1638 "Present field in the IRTE entry is clear",
1639 "Error accessing interrupt-remapping table pointed by IRTA_REG",
1640 "Detected reserved fields in the IRTE entry",
1641 "Blocked a compatibility format interrupt request",
1642 "Blocked an interrupt request due to source-id verification failure",
1643 };
1644
1645 static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type)
1646 {
1647 if (fault_reason >= 0x20 && (fault_reason - 0x20 <
1648 ARRAY_SIZE(irq_remap_fault_reasons))) {
1649 *fault_type = INTR_REMAP;
1650 return irq_remap_fault_reasons[fault_reason - 0x20];
1651 } else if (fault_reason >= 0x30 && (fault_reason - 0x30 <
1652 ARRAY_SIZE(dma_remap_sm_fault_reasons))) {
1653 *fault_type = DMA_REMAP;
1654 return dma_remap_sm_fault_reasons[fault_reason - 0x30];
1655 } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) {
1656 *fault_type = DMA_REMAP;
1657 return dma_remap_fault_reasons[fault_reason];
1658 } else {
1659 *fault_type = UNKNOWN;
1660 return "Unknown";
1661 }
1662 }
1663
1664
1665 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq)
1666 {
1667 if (iommu->irq == irq)
1668 return DMAR_FECTL_REG;
1669 else if (iommu->pr_irq == irq)
1670 return DMAR_PECTL_REG;
1671 else
1672 BUG();
1673 }
1674
1675 void dmar_msi_unmask(struct irq_data *data)
1676 {
1677 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1678 int reg = dmar_msi_reg(iommu, data->irq);
1679 unsigned long flag;
1680
1681 /* unmask it */
1682 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1683 writel(0, iommu->reg + reg);
1684 /* Read a reg to force flush the post write */
1685 readl(iommu->reg + reg);
1686 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1687 }
1688
1689 void dmar_msi_mask(struct irq_data *data)
1690 {
1691 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1692 int reg = dmar_msi_reg(iommu, data->irq);
1693 unsigned long flag;
1694
1695 /* mask it */
1696 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1697 writel(DMA_FECTL_IM, iommu->reg + reg);
1698 /* Read a reg to force flush the post write */
1699 readl(iommu->reg + reg);
1700 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1701 }
1702
1703 void dmar_msi_write(int irq, struct msi_msg *msg)
1704 {
1705 struct intel_iommu *iommu = irq_get_handler_data(irq);
1706 int reg = dmar_msi_reg(iommu, irq);
1707 unsigned long flag;
1708
1709 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1710 writel(msg->data, iommu->reg + reg + 4);
1711 writel(msg->address_lo, iommu->reg + reg + 8);
1712 writel(msg->address_hi, iommu->reg + reg + 12);
1713 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1714 }
1715
1716 void dmar_msi_read(int irq, struct msi_msg *msg)
1717 {
1718 struct intel_iommu *iommu = irq_get_handler_data(irq);
1719 int reg = dmar_msi_reg(iommu, irq);
1720 unsigned long flag;
1721
1722 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1723 msg->data = readl(iommu->reg + reg + 4);
1724 msg->address_lo = readl(iommu->reg + reg + 8);
1725 msg->address_hi = readl(iommu->reg + reg + 12);
1726 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1727 }
1728
1729 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
1730 u8 fault_reason, int pasid, u16 source_id,
1731 unsigned long long addr)
1732 {
1733 const char *reason;
1734 int fault_type;
1735
1736 reason = dmar_get_fault_reason(fault_reason, &fault_type);
1737
1738 if (fault_type == INTR_REMAP)
1739 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index %llx [fault reason %02d] %s\n",
1740 source_id >> 8, PCI_SLOT(source_id & 0xFF),
1741 PCI_FUNC(source_id & 0xFF), addr >> 48,
1742 fault_reason, reason);
1743 else
1744 pr_err("[%s] Request device [%02x:%02x.%d] PASID %x fault addr %llx [fault reason %02d] %s\n",
1745 type ? "DMA Read" : "DMA Write",
1746 source_id >> 8, PCI_SLOT(source_id & 0xFF),
1747 PCI_FUNC(source_id & 0xFF), pasid, addr,
1748 fault_reason, reason);
1749 return 0;
1750 }
1751
1752 #define PRIMARY_FAULT_REG_LEN (16)
1753 irqreturn_t dmar_fault(int irq, void *dev_id)
1754 {
1755 struct intel_iommu *iommu = dev_id;
1756 int reg, fault_index;
1757 u32 fault_status;
1758 unsigned long flag;
1759 static DEFINE_RATELIMIT_STATE(rs,
1760 DEFAULT_RATELIMIT_INTERVAL,
1761 DEFAULT_RATELIMIT_BURST);
1762
1763 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1764 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1765 if (fault_status && __ratelimit(&rs))
1766 pr_err("DRHD: handling fault status reg %x\n", fault_status);
1767
1768 /* TBD: ignore advanced fault log currently */
1769 if (!(fault_status & DMA_FSTS_PPF))
1770 goto unlock_exit;
1771
1772 fault_index = dma_fsts_fault_record_index(fault_status);
1773 reg = cap_fault_reg_offset(iommu->cap);
1774 while (1) {
1775 /* Disable printing, simply clear the fault when ratelimited */
1776 bool ratelimited = !__ratelimit(&rs);
1777 u8 fault_reason;
1778 u16 source_id;
1779 u64 guest_addr;
1780 int type, pasid;
1781 u32 data;
1782 bool pasid_present;
1783
1784 /* highest 32 bits */
1785 data = readl(iommu->reg + reg +
1786 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1787 if (!(data & DMA_FRCD_F))
1788 break;
1789
1790 if (!ratelimited) {
1791 fault_reason = dma_frcd_fault_reason(data);
1792 type = dma_frcd_type(data);
1793
1794 pasid = dma_frcd_pasid_value(data);
1795 data = readl(iommu->reg + reg +
1796 fault_index * PRIMARY_FAULT_REG_LEN + 8);
1797 source_id = dma_frcd_source_id(data);
1798
1799 pasid_present = dma_frcd_pasid_present(data);
1800 guest_addr = dmar_readq(iommu->reg + reg +
1801 fault_index * PRIMARY_FAULT_REG_LEN);
1802 guest_addr = dma_frcd_page_addr(guest_addr);
1803 }
1804
1805 /* clear the fault */
1806 writel(DMA_FRCD_F, iommu->reg + reg +
1807 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1808
1809 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1810
1811 if (!ratelimited)
1812 /* Using pasid -1 if pasid is not present */
1813 dmar_fault_do_one(iommu, type, fault_reason,
1814 pasid_present ? pasid : -1,
1815 source_id, guest_addr);
1816
1817 fault_index++;
1818 if (fault_index >= cap_num_fault_regs(iommu->cap))
1819 fault_index = 0;
1820 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1821 }
1822
1823 writel(DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_PRO,
1824 iommu->reg + DMAR_FSTS_REG);
1825
1826 unlock_exit:
1827 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1828 return IRQ_HANDLED;
1829 }
1830
1831 int dmar_set_interrupt(struct intel_iommu *iommu)
1832 {
1833 int irq, ret;
1834
1835 /*
1836 * Check if the fault interrupt is already initialized.
1837 */
1838 if (iommu->irq)
1839 return 0;
1840
1841 irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu);
1842 if (irq > 0) {
1843 iommu->irq = irq;
1844 } else {
1845 pr_err("No free IRQ vectors\n");
1846 return -EINVAL;
1847 }
1848
1849 ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);
1850 if (ret)
1851 pr_err("Can't request irq\n");
1852 return ret;
1853 }
1854
1855 int __init enable_drhd_fault_handling(void)
1856 {
1857 struct dmar_drhd_unit *drhd;
1858 struct intel_iommu *iommu;
1859
1860 /*
1861 * Enable fault control interrupt.
1862 */
1863 for_each_iommu(iommu, drhd) {
1864 u32 fault_status;
1865 int ret = dmar_set_interrupt(iommu);
1866
1867 if (ret) {
1868 pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n",
1869 (unsigned long long)drhd->reg_base_addr, ret);
1870 return -1;
1871 }
1872
1873 /*
1874 * Clear any previous faults.
1875 */
1876 dmar_fault(iommu->irq, iommu);
1877 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1878 writel(fault_status, iommu->reg + DMAR_FSTS_REG);
1879 }
1880
1881 return 0;
1882 }
1883
1884 /*
1885 * Re-enable Queued Invalidation interface.
1886 */
1887 int dmar_reenable_qi(struct intel_iommu *iommu)
1888 {
1889 if (!ecap_qis(iommu->ecap))
1890 return -ENOENT;
1891
1892 if (!iommu->qi)
1893 return -ENOENT;
1894
1895 /*
1896 * First disable queued invalidation.
1897 */
1898 dmar_disable_qi(iommu);
1899 /*
1900 * Then enable queued invalidation again. Since there is no pending
1901 * invalidation requests now, it's safe to re-enable queued
1902 * invalidation.
1903 */
1904 __dmar_enable_qi(iommu);
1905
1906 return 0;
1907 }
1908
1909 /*
1910 * Check interrupt remapping support in DMAR table description.
1911 */
1912 int __init dmar_ir_support(void)
1913 {
1914 struct acpi_table_dmar *dmar;
1915 dmar = (struct acpi_table_dmar *)dmar_tbl;
1916 if (!dmar)
1917 return 0;
1918 return dmar->flags & 0x1;
1919 }
1920
1921 /* Check whether DMAR units are in use */
1922 static inline bool dmar_in_use(void)
1923 {
1924 return irq_remapping_enabled || intel_iommu_enabled;
1925 }
1926
1927 static int __init dmar_free_unused_resources(void)
1928 {
1929 struct dmar_drhd_unit *dmaru, *dmaru_n;
1930
1931 if (dmar_in_use())
1932 return 0;
1933
1934 if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units))
1935 bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb);
1936
1937 down_write(&dmar_global_lock);
1938 list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) {
1939 list_del(&dmaru->list);
1940 dmar_free_drhd(dmaru);
1941 }
1942 up_write(&dmar_global_lock);
1943
1944 return 0;
1945 }
1946
1947 late_initcall(dmar_free_unused_resources);
1948 IOMMU_INIT_POST(detect_intel_iommu);
1949
1950 /*
1951 * DMAR Hotplug Support
1952 * For more details, please refer to Intel(R) Virtualization Technology
1953 * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8
1954 * "Remapping Hardware Unit Hot Plug".
1955 */
1956 static guid_t dmar_hp_guid =
1957 GUID_INIT(0xD8C1A3A6, 0xBE9B, 0x4C9B,
1958 0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF);
1959
1960 /*
1961 * Currently there's only one revision and BIOS will not check the revision id,
1962 * so use 0 for safety.
1963 */
1964 #define DMAR_DSM_REV_ID 0
1965 #define DMAR_DSM_FUNC_DRHD 1
1966 #define DMAR_DSM_FUNC_ATSR 2
1967 #define DMAR_DSM_FUNC_RHSA 3
1968
1969 static inline bool dmar_detect_dsm(acpi_handle handle, int func)
1970 {
1971 return acpi_check_dsm(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, 1 << func);
1972 }
1973
1974 static int dmar_walk_dsm_resource(acpi_handle handle, int func,
1975 dmar_res_handler_t handler, void *arg)
1976 {
1977 int ret = -ENODEV;
1978 union acpi_object *obj;
1979 struct acpi_dmar_header *start;
1980 struct dmar_res_callback callback;
1981 static int res_type[] = {
1982 [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT,
1983 [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS,
1984 [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY,
1985 };
1986
1987 if (!dmar_detect_dsm(handle, func))
1988 return 0;
1989
1990 obj = acpi_evaluate_dsm_typed(handle, &dmar_hp_guid, DMAR_DSM_REV_ID,
1991 func, NULL, ACPI_TYPE_BUFFER);
1992 if (!obj)
1993 return -ENODEV;
1994
1995 memset(&callback, 0, sizeof(callback));
1996 callback.cb[res_type[func]] = handler;
1997 callback.arg[res_type[func]] = arg;
1998 start = (struct acpi_dmar_header *)obj->buffer.pointer;
1999 ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback);
2000
2001 ACPI_FREE(obj);
2002
2003 return ret;
2004 }
2005
2006 static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg)
2007 {
2008 int ret;
2009 struct dmar_drhd_unit *dmaru;
2010
2011 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2012 if (!dmaru)
2013 return -ENODEV;
2014
2015 ret = dmar_ir_hotplug(dmaru, true);
2016 if (ret == 0)
2017 ret = dmar_iommu_hotplug(dmaru, true);
2018
2019 return ret;
2020 }
2021
2022 static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg)
2023 {
2024 int i, ret;
2025 struct device *dev;
2026 struct dmar_drhd_unit *dmaru;
2027
2028 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2029 if (!dmaru)
2030 return 0;
2031
2032 /*
2033 * All PCI devices managed by this unit should have been destroyed.
2034 */
2035 if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) {
2036 for_each_active_dev_scope(dmaru->devices,
2037 dmaru->devices_cnt, i, dev)
2038 return -EBUSY;
2039 }
2040
2041 ret = dmar_ir_hotplug(dmaru, false);
2042 if (ret == 0)
2043 ret = dmar_iommu_hotplug(dmaru, false);
2044
2045 return ret;
2046 }
2047
2048 static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg)
2049 {
2050 struct dmar_drhd_unit *dmaru;
2051
2052 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2053 if (dmaru) {
2054 list_del_rcu(&dmaru->list);
2055 synchronize_rcu();
2056 dmar_free_drhd(dmaru);
2057 }
2058
2059 return 0;
2060 }
2061
2062 static int dmar_hotplug_insert(acpi_handle handle)
2063 {
2064 int ret;
2065 int drhd_count = 0;
2066
2067 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2068 &dmar_validate_one_drhd, (void *)1);
2069 if (ret)
2070 goto out;
2071
2072 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2073 &dmar_parse_one_drhd, (void *)&drhd_count);
2074 if (ret == 0 && drhd_count == 0) {
2075 pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n");
2076 goto out;
2077 } else if (ret) {
2078 goto release_drhd;
2079 }
2080
2081 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA,
2082 &dmar_parse_one_rhsa, NULL);
2083 if (ret)
2084 goto release_drhd;
2085
2086 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2087 &dmar_parse_one_atsr, NULL);
2088 if (ret)
2089 goto release_atsr;
2090
2091 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2092 &dmar_hp_add_drhd, NULL);
2093 if (!ret)
2094 return 0;
2095
2096 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2097 &dmar_hp_remove_drhd, NULL);
2098 release_atsr:
2099 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2100 &dmar_release_one_atsr, NULL);
2101 release_drhd:
2102 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2103 &dmar_hp_release_drhd, NULL);
2104 out:
2105 return ret;
2106 }
2107
2108 static int dmar_hotplug_remove(acpi_handle handle)
2109 {
2110 int ret;
2111
2112 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2113 &dmar_check_one_atsr, NULL);
2114 if (ret)
2115 return ret;
2116
2117 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2118 &dmar_hp_remove_drhd, NULL);
2119 if (ret == 0) {
2120 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2121 &dmar_release_one_atsr, NULL));
2122 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2123 &dmar_hp_release_drhd, NULL));
2124 } else {
2125 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2126 &dmar_hp_add_drhd, NULL);
2127 }
2128
2129 return ret;
2130 }
2131
2132 static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl,
2133 void *context, void **retval)
2134 {
2135 acpi_handle *phdl = retval;
2136
2137 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2138 *phdl = handle;
2139 return AE_CTRL_TERMINATE;
2140 }
2141
2142 return AE_OK;
2143 }
2144
2145 static int dmar_device_hotplug(acpi_handle handle, bool insert)
2146 {
2147 int ret;
2148 acpi_handle tmp = NULL;
2149 acpi_status status;
2150
2151 if (!dmar_in_use())
2152 return 0;
2153
2154 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2155 tmp = handle;
2156 } else {
2157 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle,
2158 ACPI_UINT32_MAX,
2159 dmar_get_dsm_handle,
2160 NULL, NULL, &tmp);
2161 if (ACPI_FAILURE(status)) {
2162 pr_warn("Failed to locate _DSM method.\n");
2163 return -ENXIO;
2164 }
2165 }
2166 if (tmp == NULL)
2167 return 0;
2168
2169 down_write(&dmar_global_lock);
2170 if (insert)
2171 ret = dmar_hotplug_insert(tmp);
2172 else
2173 ret = dmar_hotplug_remove(tmp);
2174 up_write(&dmar_global_lock);
2175
2176 return ret;
2177 }
2178
2179 int dmar_device_add(acpi_handle handle)
2180 {
2181 return dmar_device_hotplug(handle, true);
2182 }
2183
2184 int dmar_device_remove(acpi_handle handle)
2185 {
2186 return dmar_device_hotplug(handle, false);
2187 }
2188
2189 /*
2190 * dmar_platform_optin - Is %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in DMAR table
2191 *
2192 * Returns true if the platform has %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in
2193 * the ACPI DMAR table. This means that the platform boot firmware has made
2194 * sure no device can issue DMA outside of RMRR regions.
2195 */
2196 bool dmar_platform_optin(void)
2197 {
2198 struct acpi_table_dmar *dmar;
2199 acpi_status status;
2200 bool ret;
2201
2202 status = acpi_get_table(ACPI_SIG_DMAR, 0,
2203 (struct acpi_table_header **)&dmar);
2204 if (ACPI_FAILURE(status))
2205 return false;
2206
2207 ret = !!(dmar->flags & DMAR_PLATFORM_OPT_IN);
2208 acpi_put_table((struct acpi_table_header *)dmar);
2209
2210 return ret;
2211 }
2212 EXPORT_SYMBOL_GPL(dmar_platform_optin);
Linux with added FPC-III support