drivers/iommu/intel-pasid.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * intel-pasid.c - PASID idr, table and entry manipulation
   4  *
   5  * Copyright (C) 2018 Intel Corporation
   6  *
   7  * Author: Lu Baolu <baolu.lu@linux.intel.com>
   8  */
   9
  10 #define pr_fmt(fmt)     "DMAR: " fmt
  11
  12 #include <linux/bitops.h>
  13 #include <linux/cpufeature.h>
  14 #include <linux/dmar.h>
  15 #include <linux/intel-iommu.h>
  16 #include <linux/iommu.h>
  17 #include <linux/memory.h>
  18 #include <linux/pci.h>
  19 #include <linux/pci-ats.h>
  20 #include <linux/spinlock.h>
  21
  22 #include "intel-pasid.h"
  23
  24 /*
  25  * Intel IOMMU system wide PASID name space:
  26  */
  27 static DEFINE_SPINLOCK(pasid_lock);
  28 u32 intel_pasid_max_id = PASID_MAX;
  29
  30 /*
  31  * Per device pasid table management:
  32  */
  33 static inline void
  34 device_attach_pasid_table(struct device_domain_info *info,
  35                           struct pasid_table *pasid_table)
  36 {
  37         info->pasid_table = pasid_table;
  38         list_add(&info->table, &pasid_table->dev);
  39 }
  40
  41 static inline void
  42 device_detach_pasid_table(struct device_domain_info *info,
  43                           struct pasid_table *pasid_table)
  44 {
  45         info->pasid_table = NULL;
  46         list_del(&info->table);
  47 }
  48
  49 struct pasid_table_opaque {
  50         struct pasid_table      **pasid_table;
  51         int                     segment;
  52         int                     bus;
  53         int                     devfn;
  54 };
  55
  56 static int search_pasid_table(struct device_domain_info *info, void *opaque)
  57 {
  58         struct pasid_table_opaque *data = opaque;
  59
  60         if (info->iommu->segment == data->segment &&
  61             info->bus == data->bus &&
  62             info->devfn == data->devfn &&
  63             info->pasid_table) {
  64                 *data->pasid_table = info->pasid_table;
  65                 return 1;
  66         }
  67
  68         return 0;
  69 }
  70
  71 static int get_alias_pasid_table(struct pci_dev *pdev, u16 alias, void *opaque)
  72 {
  73         struct pasid_table_opaque *data = opaque;
  74
  75         data->segment = pci_domain_nr(pdev->bus);
  76         data->bus = PCI_BUS_NUM(alias);
  77         data->devfn = alias & 0xff;
  78
  79         return for_each_device_domain(&search_pasid_table, data);
  80 }
  81
  82 /*
  83  * Allocate a pasid table for @dev. It should be called in a
  84  * single-thread context.
  85  */
  86 int intel_pasid_alloc_table(struct device *dev)
  87 {
  88         struct device_domain_info *info;
  89         struct pasid_table *pasid_table;
  90         struct pasid_table_opaque data;
  91         struct page *pages;
  92         int max_pasid = 0;
  93         int ret, order;
  94         int size;
  95
  96         might_sleep();
  97         info = dev->archdata.iommu;
  98         if (WARN_ON(!info || !dev_is_pci(dev) || info->pasid_table))
  99                 return -EINVAL;
 100
 101         /* DMA alias device already has a pasid table, use it: */
 102         data.pasid_table = &pasid_table;
 103         ret = pci_for_each_dma_alias(to_pci_dev(dev),
 104                                      &get_alias_pasid_table, &data);
 105         if (ret)
 106                 goto attach_out;
 107
 108         pasid_table = kzalloc(sizeof(*pasid_table), GFP_KERNEL);
 109         if (!pasid_table)
 110                 return -ENOMEM;
 111         INIT_LIST_HEAD(&pasid_table->dev);
 112
 113         if (info->pasid_supported)
 114                 max_pasid = min_t(int, pci_max_pasids(to_pci_dev(dev)),
 115                                   intel_pasid_max_id);
 116
 117         size = max_pasid >> (PASID_PDE_SHIFT - 3);
 118         order = size ? get_order(size) : 0;
 119         pages = alloc_pages_node(info->iommu->node,
 120                                  GFP_KERNEL | __GFP_ZERO, order);
 121         if (!pages) {
 122                 kfree(pasid_table);
 123                 return -ENOMEM;
 124         }
 125
 126         pasid_table->table = page_address(pages);
 127         pasid_table->order = order;
 128         pasid_table->max_pasid = 1 << (order + PAGE_SHIFT + 3);
 129
 130 attach_out:
 131         device_attach_pasid_table(info, pasid_table);
 132
 133         return 0;
 134 }
 135
 136 void intel_pasid_free_table(struct device *dev)
 137 {
 138         struct device_domain_info *info;
 139         struct pasid_table *pasid_table;
 140         struct pasid_dir_entry *dir;
 141         struct pasid_entry *table;
 142         int i, max_pde;
 143
 144         info = dev->archdata.iommu;
 145         if (!info || !dev_is_pci(dev) || !info->pasid_table)
 146                 return;
 147
 148         pasid_table = info->pasid_table;
 149         device_detach_pasid_table(info, pasid_table);
 150
 151         if (!list_empty(&pasid_table->dev))
 152                 return;
 153
 154         /* Free scalable mode PASID directory tables: */
 155         dir = pasid_table->table;
 156         max_pde = pasid_table->max_pasid >> PASID_PDE_SHIFT;
 157         for (i = 0; i < max_pde; i++) {
 158                 table = get_pasid_table_from_pde(&dir[i]);
 159                 free_pgtable_page(table);
 160         }
 161
 162         free_pages((unsigned long)pasid_table->table, pasid_table->order);
 163         kfree(pasid_table);
 164 }
 165
 166 struct pasid_table *intel_pasid_get_table(struct device *dev)
 167 {
 168         struct device_domain_info *info;
 169
 170         info = dev->archdata.iommu;
 171         if (!info)
 172                 return NULL;
 173
 174         return info->pasid_table;
 175 }
 176
 177 int intel_pasid_get_dev_max_id(struct device *dev)
 178 {
 179         struct device_domain_info *info;
 180
 181         info = dev->archdata.iommu;
 182         if (!info || !info->pasid_table)
 183                 return 0;
 184
 185         return info->pasid_table->max_pasid;
 186 }
 187
 188 struct pasid_entry *intel_pasid_get_entry(struct device *dev, int pasid)
 189 {
 190         struct device_domain_info *info;
 191         struct pasid_table *pasid_table;
 192         struct pasid_dir_entry *dir;
 193         struct pasid_entry *entries;
 194         int dir_index, index;
 195
 196         pasid_table = intel_pasid_get_table(dev);
 197         if (WARN_ON(!pasid_table || pasid < 0 ||
 198                     pasid >= intel_pasid_get_dev_max_id(dev)))
 199                 return NULL;
 200
 201         dir = pasid_table->table;
 202         info = dev->archdata.iommu;
 203         dir_index = pasid >> PASID_PDE_SHIFT;
 204         index = pasid & PASID_PTE_MASK;
 205
 206         spin_lock(&pasid_lock);
 207         entries = get_pasid_table_from_pde(&dir[dir_index]);
 208         if (!entries) {
 209                 entries = alloc_pgtable_page(info->iommu->node);
 210                 if (!entries) {
 211                         spin_unlock(&pasid_lock);
 212                         return NULL;
 213                 }
 214
 215                 WRITE_ONCE(dir[dir_index].val,
 216                            (u64)virt_to_phys(entries) | PASID_PTE_PRESENT);
 217         }
 218         spin_unlock(&pasid_lock);
 219
 220         return &entries[index];
 221 }
 222
 223 /*
 224  * Interfaces for PASID table entry manipulation:
 225  */
 226 static inline void pasid_clear_entry(struct pasid_entry *pe)
 227 {
 228         WRITE_ONCE(pe->val[0], 0);
 229         WRITE_ONCE(pe->val[1], 0);
 230         WRITE_ONCE(pe->val[2], 0);
 231         WRITE_ONCE(pe->val[3], 0);
 232         WRITE_ONCE(pe->val[4], 0);
 233         WRITE_ONCE(pe->val[5], 0);
 234         WRITE_ONCE(pe->val[6], 0);
 235         WRITE_ONCE(pe->val[7], 0);
 236 }
 237
 238 static void intel_pasid_clear_entry(struct device *dev, int pasid)
 239 {
 240         struct pasid_entry *pe;
 241
 242         pe = intel_pasid_get_entry(dev, pasid);
 243         if (WARN_ON(!pe))
 244                 return;
 245
 246         pasid_clear_entry(pe);
 247 }
 248
 249 static inline void pasid_set_bits(u64 *ptr, u64 mask, u64 bits)
 250 {
 251         u64 old;
 252
 253         old = READ_ONCE(*ptr);
 254         WRITE_ONCE(*ptr, (old & ~mask) | bits);
 255 }
 256
 257 /*
 258  * Setup the DID(Domain Identifier) field (Bit 64~79) of scalable mode
 259  * PASID entry.
 260  */
 261 static inline void
 262 pasid_set_domain_id(struct pasid_entry *pe, u64 value)
 263 {
 264         pasid_set_bits(&pe->val[1], GENMASK_ULL(15, 0), value);
 265 }
 266
 267 /*
 268  * Get domain ID value of a scalable mode PASID entry.
 269  */
 270 static inline u16
 271 pasid_get_domain_id(struct pasid_entry *pe)
 272 {
 273         return (u16)(READ_ONCE(pe->val[1]) & GENMASK_ULL(15, 0));
 274 }
 275
 276 /*
 277  * Setup the SLPTPTR(Second Level Page Table Pointer) field (Bit 12~63)
 278  * of a scalable mode PASID entry.
 279  */
 280 static inline void
 281 pasid_set_slptr(struct pasid_entry *pe, u64 value)
 282 {
 283         pasid_set_bits(&pe->val[0], VTD_PAGE_MASK, value);
 284 }
 285
 286 /*
 287  * Setup the AW(Address Width) field (Bit 2~4) of a scalable mode PASID
 288  * entry.
 289  */
 290 static inline void
 291 pasid_set_address_width(struct pasid_entry *pe, u64 value)
 292 {
 293         pasid_set_bits(&pe->val[0], GENMASK_ULL(4, 2), value << 2);
 294 }
 295
 296 /*
 297  * Setup the PGTT(PASID Granular Translation Type) field (Bit 6~8)
 298  * of a scalable mode PASID entry.
 299  */
 300 static inline void
 301 pasid_set_translation_type(struct pasid_entry *pe, u64 value)
 302 {
 303         pasid_set_bits(&pe->val[0], GENMASK_ULL(8, 6), value << 6);
 304 }
 305
 306 /*
 307  * Enable fault processing by clearing the FPD(Fault Processing
 308  * Disable) field (Bit 1) of a scalable mode PASID entry.
 309  */
 310 static inline void pasid_set_fault_enable(struct pasid_entry *pe)
 311 {
 312         pasid_set_bits(&pe->val[0], 1 << 1, 0);
 313 }
 314
 315 /*
 316  * Setup the SRE(Supervisor Request Enable) field (Bit 128) of a
 317  * scalable mode PASID entry.
 318  */
 319 static inline void pasid_set_sre(struct pasid_entry *pe)
 320 {
 321         pasid_set_bits(&pe->val[2], 1 << 0, 1);
 322 }
 323
 324 /*
 325  * Setup the P(Present) field (Bit 0) of a scalable mode PASID
 326  * entry.
 327  */
 328 static inline void pasid_set_present(struct pasid_entry *pe)
 329 {
 330         pasid_set_bits(&pe->val[0], 1 << 0, 1);
 331 }
 332
 333 /*
 334  * Setup Page Walk Snoop bit (Bit 87) of a scalable mode PASID
 335  * entry.
 336  */
 337 static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value)
 338 {
 339         pasid_set_bits(&pe->val[1], 1 << 23, value << 23);
 340 }
 341
 342 /*
 343  * Setup the First Level Page table Pointer field (Bit 140~191)
 344  * of a scalable mode PASID entry.
 345  */
 346 static inline void
 347 pasid_set_flptr(struct pasid_entry *pe, u64 value)
 348 {
 349         pasid_set_bits(&pe->val[2], VTD_PAGE_MASK, value);
 350 }
 351
 352 /*
 353  * Setup the First Level Paging Mode field (Bit 130~131) of a
 354  * scalable mode PASID entry.
 355  */
 356 static inline void
 357 pasid_set_flpm(struct pasid_entry *pe, u64 value)
 358 {
 359         pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2);
 360 }
 361
 362 static void
 363 pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu,
 364                                     u16 did, int pasid)
 365 {
 366         struct qi_desc desc;
 367
 368         desc.qw0 = QI_PC_DID(did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
 369         desc.qw1 = 0;
 370         desc.qw2 = 0;
 371         desc.qw3 = 0;
 372
 373         qi_submit_sync(&desc, iommu);
 374 }
 375
 376 static void
 377 iotlb_invalidation_with_pasid(struct intel_iommu *iommu, u16 did, u32 pasid)
 378 {
 379         struct qi_desc desc;
 380
 381         desc.qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
 382                         QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
 383         desc.qw1 = 0;
 384         desc.qw2 = 0;
 385         desc.qw3 = 0;
 386
 387         qi_submit_sync(&desc, iommu);
 388 }
 389
 390 static void
 391 devtlb_invalidation_with_pasid(struct intel_iommu *iommu,
 392                                struct device *dev, int pasid)
 393 {
 394         struct device_domain_info *info;
 395         u16 sid, qdep, pfsid;
 396
 397         info = dev->archdata.iommu;
 398         if (!info || !info->ats_enabled)
 399                 return;
 400
 401         sid = info->bus << 8 | info->devfn;
 402         qdep = info->ats_qdep;
 403         pfsid = info->pfsid;
 404
 405         qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT);
 406 }
 407
 408 void intel_pasid_tear_down_entry(struct intel_iommu *iommu,
 409                                  struct device *dev, int pasid)
 410 {
 411         struct pasid_entry *pte;
 412         u16 did;
 413
 414         pte = intel_pasid_get_entry(dev, pasid);
 415         if (WARN_ON(!pte))
 416                 return;
 417
 418         did = pasid_get_domain_id(pte);
 419         intel_pasid_clear_entry(dev, pasid);
 420
 421         if (!ecap_coherent(iommu->ecap))
 422                 clflush_cache_range(pte, sizeof(*pte));
 423
 424         pasid_cache_invalidation_with_pasid(iommu, did, pasid);
 425         iotlb_invalidation_with_pasid(iommu, did, pasid);
 426
 427         /* Device IOTLB doesn't need to be flushed in caching mode. */
 428         if (!cap_caching_mode(iommu->cap))
 429                 devtlb_invalidation_with_pasid(iommu, dev, pasid);
 430 }
 431
 432 static void pasid_flush_caches(struct intel_iommu *iommu,
 433                                 struct pasid_entry *pte,
 434                                 int pasid, u16 did)
 435 {
 436         if (!ecap_coherent(iommu->ecap))
 437                 clflush_cache_range(pte, sizeof(*pte));
 438
 439         if (cap_caching_mode(iommu->cap)) {
 440                 pasid_cache_invalidation_with_pasid(iommu, did, pasid);
 441                 iotlb_invalidation_with_pasid(iommu, did, pasid);
 442         } else {
 443                 iommu_flush_write_buffer(iommu);
 444         }
 445 }
 446
 447 /*
 448  * Set up the scalable mode pasid table entry for first only
 449  * translation type.
 450  */
 451 int intel_pasid_setup_first_level(struct intel_iommu *iommu,
 452                                   struct device *dev, pgd_t *pgd,
 453                                   int pasid, u16 did, int flags)
 454 {
 455         struct pasid_entry *pte;
 456
 457         if (!ecap_flts(iommu->ecap)) {
 458                 pr_err("No first level translation support on %s\n",
 459                        iommu->name);
 460                 return -EINVAL;
 461         }
 462
 463         pte = intel_pasid_get_entry(dev, pasid);
 464         if (WARN_ON(!pte))
 465                 return -EINVAL;
 466
 467         pasid_clear_entry(pte);
 468
 469         /* Setup the first level page table pointer: */
 470         pasid_set_flptr(pte, (u64)__pa(pgd));
 471         if (flags & PASID_FLAG_SUPERVISOR_MODE) {
 472                 if (!ecap_srs(iommu->ecap)) {
 473                         pr_err("No supervisor request support on %s\n",
 474                                iommu->name);
 475                         return -EINVAL;
 476                 }
 477                 pasid_set_sre(pte);
 478         }
 479
 480         if (flags & PASID_FLAG_FL5LP) {
 481                 if (cap_5lp_support(iommu->cap)) {
 482                         pasid_set_flpm(pte, 1);
 483                 } else {
 484                         pr_err("No 5-level paging support for first-level\n");
 485                         pasid_clear_entry(pte);
 486                         return -EINVAL;
 487                 }
 488         }
 489
 490         pasid_set_domain_id(pte, did);
 491         pasid_set_address_width(pte, iommu->agaw);
 492         pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
 493
 494         /* Setup Present and PASID Granular Transfer Type: */
 495         pasid_set_translation_type(pte, 1);
 496         pasid_set_present(pte);
 497         pasid_flush_caches(iommu, pte, pasid, did);
 498
 499         return 0;
 500 }
 501
 502 /*
 503  * Set up the scalable mode pasid entry for second only translation type.
 504  */
 505 int intel_pasid_setup_second_level(struct intel_iommu *iommu,
 506                                    struct dmar_domain *domain,
 507                                    struct device *dev, int pasid)
 508 {
 509         struct pasid_entry *pte;
 510         struct dma_pte *pgd;
 511         u64 pgd_val;
 512         int agaw;
 513         u16 did;
 514
 515         /*
 516          * If hardware advertises no support for second level
 517          * translation, return directly.
 518          */
 519         if (!ecap_slts(iommu->ecap)) {
 520                 pr_err("No second level translation support on %s\n",
 521                        iommu->name);
 522                 return -EINVAL;
 523         }
 524
 525         /*
 526          * Skip top levels of page tables for iommu which has less agaw
 527          * than default. Unnecessary for PT mode.
 528          */
 529         pgd = domain->pgd;
 530         for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) {
 531                 pgd = phys_to_virt(dma_pte_addr(pgd));
 532                 if (!dma_pte_present(pgd)) {
 533                         dev_err(dev, "Invalid domain page table\n");
 534                         return -EINVAL;
 535                 }
 536         }
 537
 538         pgd_val = virt_to_phys(pgd);
 539         did = domain->iommu_did[iommu->seq_id];
 540
 541         pte = intel_pasid_get_entry(dev, pasid);
 542         if (!pte) {
 543                 dev_err(dev, "Failed to get pasid entry of PASID %d\n", pasid);
 544                 return -ENODEV;
 545         }
 546
 547         pasid_clear_entry(pte);
 548         pasid_set_domain_id(pte, did);
 549         pasid_set_slptr(pte, pgd_val);
 550         pasid_set_address_width(pte, agaw);
 551         pasid_set_translation_type(pte, 2);
 552         pasid_set_fault_enable(pte);
 553         pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
 554
 555         /*
 556          * Since it is a second level only translation setup, we should
 557          * set SRE bit as well (addresses are expected to be GPAs).
 558          */
 559         pasid_set_sre(pte);
 560         pasid_set_present(pte);
 561         pasid_flush_caches(iommu, pte, pasid, did);
 562
 563         return 0;
 564 }
 565
 566 /*
 567  * Set up the scalable mode pasid entry for passthrough translation type.
 568  */
 569 int intel_pasid_setup_pass_through(struct intel_iommu *iommu,
 570                                    struct dmar_domain *domain,
 571                                    struct device *dev, int pasid)
 572 {
 573         u16 did = FLPT_DEFAULT_DID;
 574         struct pasid_entry *pte;
 575
 576         pte = intel_pasid_get_entry(dev, pasid);
 577         if (!pte) {
 578                 dev_err(dev, "Failed to get pasid entry of PASID %d\n", pasid);
 579                 return -ENODEV;
 580         }
 581
 582         pasid_clear_entry(pte);
 583         pasid_set_domain_id(pte, did);
 584         pasid_set_address_width(pte, iommu->agaw);
 585         pasid_set_translation_type(pte, 4);
 586         pasid_set_fault_enable(pte);
 587         pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
 588
 589         /*
 590          * We should set SRE bit as well since the addresses are expected
 591          * to be GPAs.
 592          */
 593         pasid_set_sre(pte);
 594         pasid_set_present(pte);
 595         pasid_flush_caches(iommu, pte, pasid, did);
 596
 597         return 0;
 598 }