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Revert "tty: hvc: Fix data abort due to race in hvc_open"
[linux/fpc-iii.git] / drivers / mailbox / imx-mailbox.c
blob478308fb82cc6dd83aa760bdcb17a113c28ddfb2
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
4 */
5
6 #include <linux/clk.h>
7 #include <linux/firmware/imx/ipc.h>
8 #include <linux/interrupt.h>
9 #include <linux/io.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/mailbox_controller.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/slab.h>
16
17 #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
18 #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
19 #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
20 #define IMX_MU_xSR_BRDIP BIT(9)
21
22 /* General Purpose Interrupt Enable */
23 #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
24 /* Receive Interrupt Enable */
25 #define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
26 /* Transmit Interrupt Enable */
27 #define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
28 /* General Purpose Interrupt Request */
29 #define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
30
31 #define IMX_MU_CHANS 16
32 /* TX0/RX0/RXDB[0-3] */
33 #define IMX_MU_SCU_CHANS 6
34 #define IMX_MU_CHAN_NAME_SIZE 20
35
36 enum imx_mu_chan_type {
37 IMX_MU_TYPE_TX, /* Tx */
38 IMX_MU_TYPE_RX, /* Rx */
39 IMX_MU_TYPE_TXDB, /* Tx doorbell */
40 IMX_MU_TYPE_RXDB, /* Rx doorbell */
41 };
42
43 struct imx_sc_rpc_msg_max {
44 struct imx_sc_rpc_msg hdr;
45 u32 data[7];
46 };
47
48 struct imx_mu_con_priv {
49 unsigned int idx;
50 char irq_desc[IMX_MU_CHAN_NAME_SIZE];
51 enum imx_mu_chan_type type;
52 struct mbox_chan *chan;
53 struct tasklet_struct txdb_tasklet;
54 };
55
56 struct imx_mu_priv {
57 struct device *dev;
58 void __iomem *base;
59 spinlock_t xcr_lock; /* control register lock */
60
61 struct mbox_controller mbox;
62 struct mbox_chan mbox_chans[IMX_MU_CHANS];
63
64 struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
65 const struct imx_mu_dcfg *dcfg;
66 struct clk *clk;
67 int irq;
68
69 u32 xcr;
70
71 bool side_b;
72 };
73
74 struct imx_mu_dcfg {
75 int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
76 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
77 void (*init)(struct imx_mu_priv *priv);
78 u32 xTR[4]; /* Transmit Registers */
79 u32 xRR[4]; /* Receive Registers */
80 u32 xSR; /* Status Register */
81 u32 xCR; /* Control Register */
82 };
83
84 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
85 {
86 return container_of(mbox, struct imx_mu_priv, mbox);
87 }
88
89 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
90 {
91 iowrite32(val, priv->base + offs);
92 }
93
94 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
95 {
96 return ioread32(priv->base + offs);
97 }
98
99 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
100 {
101 unsigned long flags;
102 u32 val;
103
104 spin_lock_irqsave(&priv->xcr_lock, flags);
105 val = imx_mu_read(priv, priv->dcfg->xCR);
106 val &= ~clr;
107 val |= set;
108 imx_mu_write(priv, val, priv->dcfg->xCR);
109 spin_unlock_irqrestore(&priv->xcr_lock, flags);
110
111 return val;
112 }
113
114 static int imx_mu_generic_tx(struct imx_mu_priv *priv,
115 struct imx_mu_con_priv *cp,
116 void *data)
117 {
118 u32 *arg = data;
119
120 switch (cp->type) {
121 case IMX_MU_TYPE_TX:
122 imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
123 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
124 break;
125 case IMX_MU_TYPE_TXDB:
126 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
127 tasklet_schedule(&cp->txdb_tasklet);
128 break;
129 default:
130 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
131 return -EINVAL;
132 }
133
134 return 0;
135 }
136
137 static int imx_mu_generic_rx(struct imx_mu_priv *priv,
138 struct imx_mu_con_priv *cp)
139 {
140 u32 dat;
141
142 dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
143 mbox_chan_received_data(cp->chan, (void *)&dat);
144
145 return 0;
146 }
147
148 static int imx_mu_scu_tx(struct imx_mu_priv *priv,
149 struct imx_mu_con_priv *cp,
150 void *data)
151 {
152 struct imx_sc_rpc_msg_max *msg = data;
153 u32 *arg = data;
154 int i, ret;
155 u32 xsr;
156
157 switch (cp->type) {
158 case IMX_MU_TYPE_TX:
159 if (msg->hdr.size > sizeof(*msg)) {
160 /*
161 * The real message size can be different to
162 * struct imx_sc_rpc_msg_max size
163 */
164 dev_err(priv->dev, "Exceed max msg size (%zu) on TX, got: %i\n", sizeof(*msg), msg->hdr.size);
165 return -EINVAL;
166 }
167
168 for (i = 0; i < 4 && i < msg->hdr.size; i++)
169 imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
170 for (; i < msg->hdr.size; i++) {
171 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
172 xsr,
173 xsr & IMX_MU_xSR_TEn(i % 4),
174 0, 100);
175 if (ret) {
176 dev_err(priv->dev, "Send data index: %d timeout\n", i);
177 return ret;
178 }
179 imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
180 }
181
182 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
183 break;
184 default:
185 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
186 return -EINVAL;
187 }
188
189 return 0;
190 }
191
192 static int imx_mu_scu_rx(struct imx_mu_priv *priv,
193 struct imx_mu_con_priv *cp)
194 {
195 struct imx_sc_rpc_msg_max msg;
196 u32 *data = (u32 *)&msg;
197 int i, ret;
198 u32 xsr;
199
200 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
201 *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);
202
203 if (msg.hdr.size > sizeof(msg)) {
204 dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n",
205 sizeof(msg), msg.hdr.size);
206 return -EINVAL;
207 }
208
209 for (i = 1; i < msg.hdr.size; i++) {
210 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr,
211 xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);
212 if (ret) {
213 dev_err(priv->dev, "timeout read idx %d\n", i);
214 return ret;
215 }
216 *data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);
217 }
218
219 imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
220 mbox_chan_received_data(cp->chan, (void *)&msg);
221
222 return 0;
223 }
224
225 static void imx_mu_txdb_tasklet(unsigned long data)
226 {
227 struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
228
229 mbox_chan_txdone(cp->chan, 0);
230 }
231
232 static irqreturn_t imx_mu_isr(int irq, void *p)
233 {
234 struct mbox_chan *chan = p;
235 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
236 struct imx_mu_con_priv *cp = chan->con_priv;
237 u32 val, ctrl;
238
239 ctrl = imx_mu_read(priv, priv->dcfg->xCR);
240 val = imx_mu_read(priv, priv->dcfg->xSR);
241
242 switch (cp->type) {
243 case IMX_MU_TYPE_TX:
244 val &= IMX_MU_xSR_TEn(cp->idx) &
245 (ctrl & IMX_MU_xCR_TIEn(cp->idx));
246 break;
247 case IMX_MU_TYPE_RX:
248 val &= IMX_MU_xSR_RFn(cp->idx) &
249 (ctrl & IMX_MU_xCR_RIEn(cp->idx));
250 break;
251 case IMX_MU_TYPE_RXDB:
252 val &= IMX_MU_xSR_GIPn(cp->idx) &
253 (ctrl & IMX_MU_xCR_GIEn(cp->idx));
254 break;
255 default:
256 break;
257 }
258
259 if (!val)
260 return IRQ_NONE;
261
262 if (val == IMX_MU_xSR_TEn(cp->idx)) {
263 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
264 mbox_chan_txdone(chan, 0);
265 } else if (val == IMX_MU_xSR_RFn(cp->idx)) {
266 priv->dcfg->rx(priv, cp);
267 } else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
268 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
269 mbox_chan_received_data(chan, NULL);
270 } else {
271 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
272 return IRQ_NONE;
273 }
274
275 return IRQ_HANDLED;
276 }
277
278 static int imx_mu_send_data(struct mbox_chan *chan, void *data)
279 {
280 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
281 struct imx_mu_con_priv *cp = chan->con_priv;
282
283 return priv->dcfg->tx(priv, cp, data);
284 }
285
286 static int imx_mu_startup(struct mbox_chan *chan)
287 {
288 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
289 struct imx_mu_con_priv *cp = chan->con_priv;
290 int ret;
291
292 if (cp->type == IMX_MU_TYPE_TXDB) {
293 /* Tx doorbell don't have ACK support */
294 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
295 (unsigned long)cp);
296 return 0;
297 }
298
299 ret = request_irq(priv->irq, imx_mu_isr, IRQF_SHARED |
300 IRQF_NO_SUSPEND, cp->irq_desc, chan);
301 if (ret) {
302 dev_err(priv->dev,
303 "Unable to acquire IRQ %d\n", priv->irq);
304 return ret;
305 }
306
307 switch (cp->type) {
308 case IMX_MU_TYPE_RX:
309 imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0);
310 break;
311 case IMX_MU_TYPE_RXDB:
312 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0);
313 break;
314 default:
315 break;
316 }
317
318 return 0;
319 }
320
321 static void imx_mu_shutdown(struct mbox_chan *chan)
322 {
323 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
324 struct imx_mu_con_priv *cp = chan->con_priv;
325
326 if (cp->type == IMX_MU_TYPE_TXDB) {
327 tasklet_kill(&cp->txdb_tasklet);
328 return;
329 }
330
331 switch (cp->type) {
332 case IMX_MU_TYPE_TX:
333 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
334 break;
335 case IMX_MU_TYPE_RX:
336 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx));
337 break;
338 case IMX_MU_TYPE_RXDB:
339 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx));
340 break;
341 default:
342 break;
343 }
344
345 free_irq(priv->irq, chan);
346 }
347
348 static const struct mbox_chan_ops imx_mu_ops = {
349 .send_data = imx_mu_send_data,
350 .startup = imx_mu_startup,
351 .shutdown = imx_mu_shutdown,
352 };
353
354 static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox,
355 const struct of_phandle_args *sp)
356 {
357 u32 type, idx, chan;
358
359 if (sp->args_count != 2) {
360 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
361 return ERR_PTR(-EINVAL);
362 }
363
364 type = sp->args[0]; /* channel type */
365 idx = sp->args[1]; /* index */
366
367 switch (type) {
368 case IMX_MU_TYPE_TX:
369 case IMX_MU_TYPE_RX:
370 if (idx != 0)
371 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
372 chan = type;
373 break;
374 case IMX_MU_TYPE_RXDB:
375 chan = 2 + idx;
376 break;
377 default:
378 dev_err(mbox->dev, "Invalid chan type: %d\n", type);
379 return ERR_PTR(-EINVAL);
380 }
381
382 if (chan >= mbox->num_chans) {
383 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
384 return ERR_PTR(-EINVAL);
385 }
386
387 return &mbox->chans[chan];
388 }
389
390 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
391 const struct of_phandle_args *sp)
392 {
393 u32 type, idx, chan;
394
395 if (sp->args_count != 2) {
396 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
397 return ERR_PTR(-EINVAL);
398 }
399
400 type = sp->args[0]; /* channel type */
401 idx = sp->args[1]; /* index */
402 chan = type * 4 + idx;
403
404 if (chan >= mbox->num_chans) {
405 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
406 return ERR_PTR(-EINVAL);
407 }
408
409 return &mbox->chans[chan];
410 }
411
412 static void imx_mu_init_generic(struct imx_mu_priv *priv)
413 {
414 unsigned int i;
415
416 for (i = 0; i < IMX_MU_CHANS; i++) {
417 struct imx_mu_con_priv *cp = &priv->con_priv[i];
418
419 cp->idx = i % 4;
420 cp->type = i >> 2;
421 cp->chan = &priv->mbox_chans[i];
422 priv->mbox_chans[i].con_priv = cp;
423 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
424 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
425 }
426
427 priv->mbox.num_chans = IMX_MU_CHANS;
428 priv->mbox.of_xlate = imx_mu_xlate;
429
430 if (priv->side_b)
431 return;
432
433 /* Set default MU configuration */
434 imx_mu_write(priv, 0, priv->dcfg->xCR);
435 }
436
437 static void imx_mu_init_scu(struct imx_mu_priv *priv)
438 {
439 unsigned int i;
440
441 for (i = 0; i < IMX_MU_SCU_CHANS; i++) {
442 struct imx_mu_con_priv *cp = &priv->con_priv[i];
443
444 cp->idx = i < 2 ? 0 : i - 2;
445 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
446 cp->chan = &priv->mbox_chans[i];
447 priv->mbox_chans[i].con_priv = cp;
448 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
449 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
450 }
451
452 priv->mbox.num_chans = IMX_MU_SCU_CHANS;
453 priv->mbox.of_xlate = imx_mu_scu_xlate;
454
455 /* Set default MU configuration */
456 imx_mu_write(priv, 0, priv->dcfg->xCR);
457 }
458
459 static int imx_mu_probe(struct platform_device *pdev)
460 {
461 struct device *dev = &pdev->dev;
462 struct device_node *np = dev->of_node;
463 struct imx_mu_priv *priv;
464 const struct imx_mu_dcfg *dcfg;
465 int ret;
466
467 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
468 if (!priv)
469 return -ENOMEM;
470
471 priv->dev = dev;
472
473 priv->base = devm_platform_ioremap_resource(pdev, 0);
474 if (IS_ERR(priv->base))
475 return PTR_ERR(priv->base);
476
477 priv->irq = platform_get_irq(pdev, 0);
478 if (priv->irq < 0)
479 return priv->irq;
480
481 dcfg = of_device_get_match_data(dev);
482 if (!dcfg)
483 return -EINVAL;
484 priv->dcfg = dcfg;
485
486 priv->clk = devm_clk_get(dev, NULL);
487 if (IS_ERR(priv->clk)) {
488 if (PTR_ERR(priv->clk) != -ENOENT)
489 return PTR_ERR(priv->clk);
490
491 priv->clk = NULL;
492 }
493
494 ret = clk_prepare_enable(priv->clk);
495 if (ret) {
496 dev_err(dev, "Failed to enable clock\n");
497 return ret;
498 }
499
500 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
501
502 priv->dcfg->init(priv);
503
504 spin_lock_init(&priv->xcr_lock);
505
506 priv->mbox.dev = dev;
507 priv->mbox.ops = &imx_mu_ops;
508 priv->mbox.chans = priv->mbox_chans;
509 priv->mbox.txdone_irq = true;
510
511 platform_set_drvdata(pdev, priv);
512
513 return devm_mbox_controller_register(dev, &priv->mbox);
514 }
515
516 static int imx_mu_remove(struct platform_device *pdev)
517 {
518 struct imx_mu_priv *priv = platform_get_drvdata(pdev);
519
520 clk_disable_unprepare(priv->clk);
521
522 return 0;
523 }
524
525 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
526 .tx = imx_mu_generic_tx,
527 .rx = imx_mu_generic_rx,
528 .init = imx_mu_init_generic,
529 .xTR = {0x0, 0x4, 0x8, 0xc},
530 .xRR = {0x10, 0x14, 0x18, 0x1c},
531 .xSR = 0x20,
532 .xCR = 0x24,
533 };
534
535 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
536 .tx = imx_mu_generic_tx,
537 .rx = imx_mu_generic_rx,
538 .init = imx_mu_init_generic,
539 .xTR = {0x20, 0x24, 0x28, 0x2c},
540 .xRR = {0x40, 0x44, 0x48, 0x4c},
541 .xSR = 0x60,
542 .xCR = 0x64,
543 };
544
545 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
546 .tx = imx_mu_scu_tx,
547 .rx = imx_mu_scu_rx,
548 .init = imx_mu_init_scu,
549 .xTR = {0x0, 0x4, 0x8, 0xc},
550 .xRR = {0x10, 0x14, 0x18, 0x1c},
551 .xSR = 0x20,
552 .xCR = 0x24,
553 };
554
555 static const struct of_device_id imx_mu_dt_ids[] = {
556 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
557 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
558 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
559 { },
560 };
561 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
562
563 static int imx_mu_suspend_noirq(struct device *dev)
564 {
565 struct imx_mu_priv *priv = dev_get_drvdata(dev);
566
567 priv->xcr = imx_mu_read(priv, priv->dcfg->xCR);
568
569 return 0;
570 }
571
572 static int imx_mu_resume_noirq(struct device *dev)
573 {
574 struct imx_mu_priv *priv = dev_get_drvdata(dev);
575
576 /*
577 * ONLY restore MU when context lost, the TIE could
578 * be set during noirq resume as there is MU data
579 * communication going on, and restore the saved
580 * value will overwrite the TIE and cause MU data
581 * send failed, may lead to system freeze. This issue
582 * is observed by testing freeze mode suspend.
583 */
584 if (!imx_mu_read(priv, priv->dcfg->xCR))
585 imx_mu_write(priv, priv->xcr, priv->dcfg->xCR);
586
587 return 0;
588 }
589
590 static const struct dev_pm_ops imx_mu_pm_ops = {
591 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
592 imx_mu_resume_noirq)
593 };
594
595 static struct platform_driver imx_mu_driver = {
596 .probe = imx_mu_probe,
597 .remove = imx_mu_remove,
598 .driver = {
599 .name = "imx_mu",
600 .of_match_table = imx_mu_dt_ids,
601 .pm = &imx_mu_pm_ops,
602 },
603 };
604 module_platform_driver(imx_mu_driver);
605
606 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
607 MODULE_DESCRIPTION("Message Unit driver for i.MX");
608 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support