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Revert "tty: hvc: Fix data abort due to race in hvc_open"
[linux/fpc-iii.git] / drivers / tty / serial / 8250 / 8250_port.c
blob4d83c85a7389bd948391ef8ed2e5083d31fe4563
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Base port operations for 8250/16550-type serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 *
8 * A note about mapbase / membase
9 *
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/sysrq.h>
20 #include <linux/delay.h>
21 #include <linux/platform_device.h>
22 #include <linux/tty.h>
23 #include <linux/ratelimit.h>
24 #include <linux/tty_flip.h>
25 #include <linux/serial.h>
26 #include <linux/serial_8250.h>
27 #include <linux/nmi.h>
28 #include <linux/mutex.h>
29 #include <linux/slab.h>
30 #include <linux/uaccess.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/ktime.h>
33
34 #include <asm/io.h>
35 #include <asm/irq.h>
36
37 #include "8250.h"
38
39 /* Nuvoton NPCM timeout register */
40 #define UART_NPCM_TOR 7
41 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
42
43 /*
44 * Debugging.
45 */
46 #if 0
47 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
48 #else
49 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
50 #endif
51
52 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
53
54 /*
55 * Here we define the default xmit fifo size used for each type of UART.
56 */
57 static const struct serial8250_config uart_config[] = {
58 [PORT_UNKNOWN] = {
59 .name = "unknown",
60 .fifo_size = 1,
61 .tx_loadsz = 1,
62 },
63 [PORT_8250] = {
64 .name = "8250",
65 .fifo_size = 1,
66 .tx_loadsz = 1,
67 },
68 [PORT_16450] = {
69 .name = "16450",
70 .fifo_size = 1,
71 .tx_loadsz = 1,
72 },
73 [PORT_16550] = {
74 .name = "16550",
75 .fifo_size = 1,
76 .tx_loadsz = 1,
77 },
78 [PORT_16550A] = {
79 .name = "16550A",
80 .fifo_size = 16,
81 .tx_loadsz = 16,
82 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
83 .rxtrig_bytes = {1, 4, 8, 14},
84 .flags = UART_CAP_FIFO,
85 },
86 [PORT_CIRRUS] = {
87 .name = "Cirrus",
88 .fifo_size = 1,
89 .tx_loadsz = 1,
90 },
91 [PORT_16650] = {
92 .name = "ST16650",
93 .fifo_size = 1,
94 .tx_loadsz = 1,
95 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
96 },
97 [PORT_16650V2] = {
98 .name = "ST16650V2",
99 .fifo_size = 32,
100 .tx_loadsz = 16,
101 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
102 UART_FCR_T_TRIG_00,
103 .rxtrig_bytes = {8, 16, 24, 28},
104 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
105 },
106 [PORT_16750] = {
107 .name = "TI16750",
108 .fifo_size = 64,
109 .tx_loadsz = 64,
110 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
111 UART_FCR7_64BYTE,
112 .rxtrig_bytes = {1, 16, 32, 56},
113 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
114 },
115 [PORT_STARTECH] = {
116 .name = "Startech",
117 .fifo_size = 1,
118 .tx_loadsz = 1,
119 },
120 [PORT_16C950] = {
121 .name = "16C950/954",
122 .fifo_size = 128,
123 .tx_loadsz = 128,
124 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
125 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
126 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
127 },
128 [PORT_16654] = {
129 .name = "ST16654",
130 .fifo_size = 64,
131 .tx_loadsz = 32,
132 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
133 UART_FCR_T_TRIG_10,
134 .rxtrig_bytes = {8, 16, 56, 60},
135 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
136 },
137 [PORT_16850] = {
138 .name = "XR16850",
139 .fifo_size = 128,
140 .tx_loadsz = 128,
141 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
142 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
143 },
144 [PORT_RSA] = {
145 .name = "RSA",
146 .fifo_size = 2048,
147 .tx_loadsz = 2048,
148 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
149 .flags = UART_CAP_FIFO,
150 },
151 [PORT_NS16550A] = {
152 .name = "NS16550A",
153 .fifo_size = 16,
154 .tx_loadsz = 16,
155 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
156 .flags = UART_CAP_FIFO | UART_NATSEMI,
157 },
158 [PORT_XSCALE] = {
159 .name = "XScale",
160 .fifo_size = 32,
161 .tx_loadsz = 32,
162 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
163 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
164 },
165 [PORT_OCTEON] = {
166 .name = "OCTEON",
167 .fifo_size = 64,
168 .tx_loadsz = 64,
169 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
170 .flags = UART_CAP_FIFO,
171 },
172 [PORT_AR7] = {
173 .name = "AR7",
174 .fifo_size = 16,
175 .tx_loadsz = 16,
176 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
177 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
178 },
179 [PORT_U6_16550A] = {
180 .name = "U6_16550A",
181 .fifo_size = 64,
182 .tx_loadsz = 64,
183 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
184 .flags = UART_CAP_FIFO | UART_CAP_AFE,
185 },
186 [PORT_TEGRA] = {
187 .name = "Tegra",
188 .fifo_size = 32,
189 .tx_loadsz = 8,
190 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
191 UART_FCR_T_TRIG_01,
192 .rxtrig_bytes = {1, 4, 8, 14},
193 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
194 },
195 [PORT_XR17D15X] = {
196 .name = "XR17D15X",
197 .fifo_size = 64,
198 .tx_loadsz = 64,
199 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
200 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
201 UART_CAP_SLEEP,
202 },
203 [PORT_XR17V35X] = {
204 .name = "XR17V35X",
205 .fifo_size = 256,
206 .tx_loadsz = 256,
207 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
208 UART_FCR_T_TRIG_11,
209 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
210 UART_CAP_SLEEP,
211 },
212 [PORT_LPC3220] = {
213 .name = "LPC3220",
214 .fifo_size = 64,
215 .tx_loadsz = 32,
216 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
217 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
218 .flags = UART_CAP_FIFO,
219 },
220 [PORT_BRCM_TRUMANAGE] = {
221 .name = "TruManage",
222 .fifo_size = 1,
223 .tx_loadsz = 1024,
224 .flags = UART_CAP_HFIFO,
225 },
226 [PORT_8250_CIR] = {
227 .name = "CIR port"
228 },
229 [PORT_ALTR_16550_F32] = {
230 .name = "Altera 16550 FIFO32",
231 .fifo_size = 32,
232 .tx_loadsz = 32,
233 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
234 .rxtrig_bytes = {1, 8, 16, 30},
235 .flags = UART_CAP_FIFO | UART_CAP_AFE,
236 },
237 [PORT_ALTR_16550_F64] = {
238 .name = "Altera 16550 FIFO64",
239 .fifo_size = 64,
240 .tx_loadsz = 64,
241 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
242 .rxtrig_bytes = {1, 16, 32, 62},
243 .flags = UART_CAP_FIFO | UART_CAP_AFE,
244 },
245 [PORT_ALTR_16550_F128] = {
246 .name = "Altera 16550 FIFO128",
247 .fifo_size = 128,
248 .tx_loadsz = 128,
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
250 .rxtrig_bytes = {1, 32, 64, 126},
251 .flags = UART_CAP_FIFO | UART_CAP_AFE,
252 },
253 /*
254 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
255 * workaround of errata A-008006 which states that tx_loadsz should
256 * be configured less than Maximum supported fifo bytes.
257 */
258 [PORT_16550A_FSL64] = {
259 .name = "16550A_FSL64",
260 .fifo_size = 64,
261 .tx_loadsz = 63,
262 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
263 UART_FCR7_64BYTE,
264 .flags = UART_CAP_FIFO,
265 },
266 [PORT_RT2880] = {
267 .name = "Palmchip BK-3103",
268 .fifo_size = 16,
269 .tx_loadsz = 16,
270 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
271 .rxtrig_bytes = {1, 4, 8, 14},
272 .flags = UART_CAP_FIFO,
273 },
274 [PORT_DA830] = {
275 .name = "TI DA8xx/66AK2x",
276 .fifo_size = 16,
277 .tx_loadsz = 16,
278 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
279 UART_FCR_R_TRIG_10,
280 .rxtrig_bytes = {1, 4, 8, 14},
281 .flags = UART_CAP_FIFO | UART_CAP_AFE,
282 },
283 [PORT_MTK_BTIF] = {
284 .name = "MediaTek BTIF",
285 .fifo_size = 16,
286 .tx_loadsz = 16,
287 .fcr = UART_FCR_ENABLE_FIFO |
288 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
289 .flags = UART_CAP_FIFO,
290 },
291 [PORT_NPCM] = {
292 .name = "Nuvoton 16550",
293 .fifo_size = 16,
294 .tx_loadsz = 16,
295 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
296 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
297 .rxtrig_bytes = {1, 4, 8, 14},
298 .flags = UART_CAP_FIFO,
299 },
300 [PORT_SUNIX] = {
301 .name = "Sunix",
302 .fifo_size = 128,
303 .tx_loadsz = 128,
304 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
305 .rxtrig_bytes = {1, 32, 64, 112},
306 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
307 },
308 };
309
310 /* Uart divisor latch read */
311 static int default_serial_dl_read(struct uart_8250_port *up)
312 {
313 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
314 }
315
316 /* Uart divisor latch write */
317 static void default_serial_dl_write(struct uart_8250_port *up, int value)
318 {
319 serial_out(up, UART_DLL, value & 0xff);
320 serial_out(up, UART_DLM, value >> 8 & 0xff);
321 }
322
323 #ifdef CONFIG_SERIAL_8250_RT288X
324
325 /* Au1x00/RT288x UART hardware has a weird register layout */
326 static const s8 au_io_in_map[8] = {
327 0, /* UART_RX */
328 2, /* UART_IER */
329 3, /* UART_IIR */
330 5, /* UART_LCR */
331 6, /* UART_MCR */
332 7, /* UART_LSR */
333 8, /* UART_MSR */
334 -1, /* UART_SCR (unmapped) */
335 };
336
337 static const s8 au_io_out_map[8] = {
338 1, /* UART_TX */
339 2, /* UART_IER */
340 4, /* UART_FCR */
341 5, /* UART_LCR */
342 6, /* UART_MCR */
343 -1, /* UART_LSR (unmapped) */
344 -1, /* UART_MSR (unmapped) */
345 -1, /* UART_SCR (unmapped) */
346 };
347
348 unsigned int au_serial_in(struct uart_port *p, int offset)
349 {
350 if (offset >= ARRAY_SIZE(au_io_in_map))
351 return UINT_MAX;
352 offset = au_io_in_map[offset];
353 if (offset < 0)
354 return UINT_MAX;
355 return __raw_readl(p->membase + (offset << p->regshift));
356 }
357
358 void au_serial_out(struct uart_port *p, int offset, int value)
359 {
360 if (offset >= ARRAY_SIZE(au_io_out_map))
361 return;
362 offset = au_io_out_map[offset];
363 if (offset < 0)
364 return;
365 __raw_writel(value, p->membase + (offset << p->regshift));
366 }
367
368 /* Au1x00 haven't got a standard divisor latch */
369 static int au_serial_dl_read(struct uart_8250_port *up)
370 {
371 return __raw_readl(up->port.membase + 0x28);
372 }
373
374 static void au_serial_dl_write(struct uart_8250_port *up, int value)
375 {
376 __raw_writel(value, up->port.membase + 0x28);
377 }
378
379 #endif
380
381 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
382 {
383 offset = offset << p->regshift;
384 outb(p->hub6 - 1 + offset, p->iobase);
385 return inb(p->iobase + 1);
386 }
387
388 static void hub6_serial_out(struct uart_port *p, int offset, int value)
389 {
390 offset = offset << p->regshift;
391 outb(p->hub6 - 1 + offset, p->iobase);
392 outb(value, p->iobase + 1);
393 }
394
395 static unsigned int mem_serial_in(struct uart_port *p, int offset)
396 {
397 offset = offset << p->regshift;
398 return readb(p->membase + offset);
399 }
400
401 static void mem_serial_out(struct uart_port *p, int offset, int value)
402 {
403 offset = offset << p->regshift;
404 writeb(value, p->membase + offset);
405 }
406
407 static void mem16_serial_out(struct uart_port *p, int offset, int value)
408 {
409 offset = offset << p->regshift;
410 writew(value, p->membase + offset);
411 }
412
413 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
414 {
415 offset = offset << p->regshift;
416 return readw(p->membase + offset);
417 }
418
419 static void mem32_serial_out(struct uart_port *p, int offset, int value)
420 {
421 offset = offset << p->regshift;
422 writel(value, p->membase + offset);
423 }
424
425 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
426 {
427 offset = offset << p->regshift;
428 return readl(p->membase + offset);
429 }
430
431 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
432 {
433 offset = offset << p->regshift;
434 iowrite32be(value, p->membase + offset);
435 }
436
437 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
438 {
439 offset = offset << p->regshift;
440 return ioread32be(p->membase + offset);
441 }
442
443 static unsigned int io_serial_in(struct uart_port *p, int offset)
444 {
445 offset = offset << p->regshift;
446 return inb(p->iobase + offset);
447 }
448
449 static void io_serial_out(struct uart_port *p, int offset, int value)
450 {
451 offset = offset << p->regshift;
452 outb(value, p->iobase + offset);
453 }
454
455 static int serial8250_default_handle_irq(struct uart_port *port);
456
457 static void set_io_from_upio(struct uart_port *p)
458 {
459 struct uart_8250_port *up = up_to_u8250p(p);
460
461 up->dl_read = default_serial_dl_read;
462 up->dl_write = default_serial_dl_write;
463
464 switch (p->iotype) {
465 case UPIO_HUB6:
466 p->serial_in = hub6_serial_in;
467 p->serial_out = hub6_serial_out;
468 break;
469
470 case UPIO_MEM:
471 p->serial_in = mem_serial_in;
472 p->serial_out = mem_serial_out;
473 break;
474
475 case UPIO_MEM16:
476 p->serial_in = mem16_serial_in;
477 p->serial_out = mem16_serial_out;
478 break;
479
480 case UPIO_MEM32:
481 p->serial_in = mem32_serial_in;
482 p->serial_out = mem32_serial_out;
483 break;
484
485 case UPIO_MEM32BE:
486 p->serial_in = mem32be_serial_in;
487 p->serial_out = mem32be_serial_out;
488 break;
489
490 #ifdef CONFIG_SERIAL_8250_RT288X
491 case UPIO_AU:
492 p->serial_in = au_serial_in;
493 p->serial_out = au_serial_out;
494 up->dl_read = au_serial_dl_read;
495 up->dl_write = au_serial_dl_write;
496 break;
497 #endif
498
499 default:
500 p->serial_in = io_serial_in;
501 p->serial_out = io_serial_out;
502 break;
503 }
504 /* Remember loaded iotype */
505 up->cur_iotype = p->iotype;
506 p->handle_irq = serial8250_default_handle_irq;
507 }
508
509 static void
510 serial_port_out_sync(struct uart_port *p, int offset, int value)
511 {
512 switch (p->iotype) {
513 case UPIO_MEM:
514 case UPIO_MEM16:
515 case UPIO_MEM32:
516 case UPIO_MEM32BE:
517 case UPIO_AU:
518 p->serial_out(p, offset, value);
519 p->serial_in(p, UART_LCR); /* safe, no side-effects */
520 break;
521 default:
522 p->serial_out(p, offset, value);
523 }
524 }
525
526 /*
527 * For the 16C950
528 */
529 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
530 {
531 serial_out(up, UART_SCR, offset);
532 serial_out(up, UART_ICR, value);
533 }
534
535 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
536 {
537 unsigned int value;
538
539 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
540 serial_out(up, UART_SCR, offset);
541 value = serial_in(up, UART_ICR);
542 serial_icr_write(up, UART_ACR, up->acr);
543
544 return value;
545 }
546
547 /*
548 * FIFO support.
549 */
550 static void serial8250_clear_fifos(struct uart_8250_port *p)
551 {
552 if (p->capabilities & UART_CAP_FIFO) {
553 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
554 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
555 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
556 serial_out(p, UART_FCR, 0);
557 }
558 }
559
560 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
561 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
562
563 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
564 {
565 serial8250_clear_fifos(p);
566 serial_out(p, UART_FCR, p->fcr);
567 }
568 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
569
570 void serial8250_rpm_get(struct uart_8250_port *p)
571 {
572 if (!(p->capabilities & UART_CAP_RPM))
573 return;
574 pm_runtime_get_sync(p->port.dev);
575 }
576 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
577
578 void serial8250_rpm_put(struct uart_8250_port *p)
579 {
580 if (!(p->capabilities & UART_CAP_RPM))
581 return;
582 pm_runtime_mark_last_busy(p->port.dev);
583 pm_runtime_put_autosuspend(p->port.dev);
584 }
585 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
586
587 /**
588 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
589 * @p: uart_8250_port port instance
590 *
591 * The function is used to start rs485 software emulating on the
592 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
593 * transmission. The function is idempotent, so it is safe to call it
594 * multiple times.
595 *
596 * The caller MUST enable interrupt on empty shift register before
597 * calling serial8250_em485_init(). This interrupt is not a part of
598 * 8250 standard, but implementation defined.
599 *
600 * The function is supposed to be called from .rs485_config callback
601 * or from any other callback protected with p->port.lock spinlock.
602 *
603 * See also serial8250_em485_destroy()
604 *
605 * Return 0 - success, -errno - otherwise
606 */
607 static int serial8250_em485_init(struct uart_8250_port *p)
608 {
609 if (p->em485)
610 return 0;
611
612 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
613 if (!p->em485)
614 return -ENOMEM;
615
616 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
617 HRTIMER_MODE_REL);
618 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
619 HRTIMER_MODE_REL);
620 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
621 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
622 p->em485->port = p;
623 p->em485->active_timer = NULL;
624 p->em485->tx_stopped = true;
625
626 p->rs485_stop_tx(p);
627
628 return 0;
629 }
630
631 /**
632 * serial8250_em485_destroy() - put uart_8250_port into normal state
633 * @p: uart_8250_port port instance
634 *
635 * The function is used to stop rs485 software emulating on the
636 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
637 * call it multiple times.
638 *
639 * The function is supposed to be called from .rs485_config callback
640 * or from any other callback protected with p->port.lock spinlock.
641 *
642 * See also serial8250_em485_init()
643 */
644 void serial8250_em485_destroy(struct uart_8250_port *p)
645 {
646 if (!p->em485)
647 return;
648
649 hrtimer_cancel(&p->em485->start_tx_timer);
650 hrtimer_cancel(&p->em485->stop_tx_timer);
651
652 kfree(p->em485);
653 p->em485 = NULL;
654 }
655 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
656
657 /**
658 * serial8250_em485_config() - generic ->rs485_config() callback
659 * @port: uart port
660 * @rs485: rs485 settings
661 *
662 * Generic callback usable by 8250 uart drivers to activate rs485 settings
663 * if the uart is incapable of driving RTS as a Transmit Enable signal in
664 * hardware, relying on software emulation instead.
665 */
666 int serial8250_em485_config(struct uart_port *port, struct serial_rs485 *rs485)
667 {
668 struct uart_8250_port *up = up_to_u8250p(port);
669
670 /* pick sane settings if the user hasn't */
671 if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
672 !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
673 rs485->flags |= SER_RS485_RTS_ON_SEND;
674 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
675 }
676
677 /* clamp the delays to [0, 100ms] */
678 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
679 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
680
681 memset(rs485->padding, 0, sizeof(rs485->padding));
682 port->rs485 = *rs485;
683
684 /*
685 * Both serial8250_em485_init() and serial8250_em485_destroy()
686 * are idempotent.
687 */
688 if (rs485->flags & SER_RS485_ENABLED) {
689 int ret = serial8250_em485_init(up);
690
691 if (ret) {
692 rs485->flags &= ~SER_RS485_ENABLED;
693 port->rs485.flags &= ~SER_RS485_ENABLED;
694 }
695 return ret;
696 }
697
698 serial8250_em485_destroy(up);
699 return 0;
700 }
701 EXPORT_SYMBOL_GPL(serial8250_em485_config);
702
703 /*
704 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
705 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
706 * empty and the HW can idle again.
707 */
708 void serial8250_rpm_get_tx(struct uart_8250_port *p)
709 {
710 unsigned char rpm_active;
711
712 if (!(p->capabilities & UART_CAP_RPM))
713 return;
714
715 rpm_active = xchg(&p->rpm_tx_active, 1);
716 if (rpm_active)
717 return;
718 pm_runtime_get_sync(p->port.dev);
719 }
720 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
721
722 void serial8250_rpm_put_tx(struct uart_8250_port *p)
723 {
724 unsigned char rpm_active;
725
726 if (!(p->capabilities & UART_CAP_RPM))
727 return;
728
729 rpm_active = xchg(&p->rpm_tx_active, 0);
730 if (!rpm_active)
731 return;
732 pm_runtime_mark_last_busy(p->port.dev);
733 pm_runtime_put_autosuspend(p->port.dev);
734 }
735 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
736
737 /*
738 * IER sleep support. UARTs which have EFRs need the "extended
739 * capability" bit enabled. Note that on XR16C850s, we need to
740 * reset LCR to write to IER.
741 */
742 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
743 {
744 unsigned char lcr = 0, efr = 0;
745
746 serial8250_rpm_get(p);
747
748 if (p->capabilities & UART_CAP_SLEEP) {
749 if (p->capabilities & UART_CAP_EFR) {
750 lcr = serial_in(p, UART_LCR);
751 efr = serial_in(p, UART_EFR);
752 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
753 serial_out(p, UART_EFR, UART_EFR_ECB);
754 serial_out(p, UART_LCR, 0);
755 }
756 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
757 if (p->capabilities & UART_CAP_EFR) {
758 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
759 serial_out(p, UART_EFR, efr);
760 serial_out(p, UART_LCR, lcr);
761 }
762 }
763
764 serial8250_rpm_put(p);
765 }
766
767 #ifdef CONFIG_SERIAL_8250_RSA
768 /*
769 * Attempts to turn on the RSA FIFO. Returns zero on failure.
770 * We set the port uart clock rate if we succeed.
771 */
772 static int __enable_rsa(struct uart_8250_port *up)
773 {
774 unsigned char mode;
775 int result;
776
777 mode = serial_in(up, UART_RSA_MSR);
778 result = mode & UART_RSA_MSR_FIFO;
779
780 if (!result) {
781 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
782 mode = serial_in(up, UART_RSA_MSR);
783 result = mode & UART_RSA_MSR_FIFO;
784 }
785
786 if (result)
787 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
788
789 return result;
790 }
791
792 static void enable_rsa(struct uart_8250_port *up)
793 {
794 if (up->port.type == PORT_RSA) {
795 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
796 spin_lock_irq(&up->port.lock);
797 __enable_rsa(up);
798 spin_unlock_irq(&up->port.lock);
799 }
800 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
801 serial_out(up, UART_RSA_FRR, 0);
802 }
803 }
804
805 /*
806 * Attempts to turn off the RSA FIFO. Returns zero on failure.
807 * It is unknown why interrupts were disabled in here. However,
808 * the caller is expected to preserve this behaviour by grabbing
809 * the spinlock before calling this function.
810 */
811 static void disable_rsa(struct uart_8250_port *up)
812 {
813 unsigned char mode;
814 int result;
815
816 if (up->port.type == PORT_RSA &&
817 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
818 spin_lock_irq(&up->port.lock);
819
820 mode = serial_in(up, UART_RSA_MSR);
821 result = !(mode & UART_RSA_MSR_FIFO);
822
823 if (!result) {
824 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
825 mode = serial_in(up, UART_RSA_MSR);
826 result = !(mode & UART_RSA_MSR_FIFO);
827 }
828
829 if (result)
830 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
831 spin_unlock_irq(&up->port.lock);
832 }
833 }
834 #endif /* CONFIG_SERIAL_8250_RSA */
835
836 /*
837 * This is a quickie test to see how big the FIFO is.
838 * It doesn't work at all the time, more's the pity.
839 */
840 static int size_fifo(struct uart_8250_port *up)
841 {
842 unsigned char old_fcr, old_mcr, old_lcr;
843 unsigned short old_dl;
844 int count;
845
846 old_lcr = serial_in(up, UART_LCR);
847 serial_out(up, UART_LCR, 0);
848 old_fcr = serial_in(up, UART_FCR);
849 old_mcr = serial8250_in_MCR(up);
850 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
851 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
852 serial8250_out_MCR(up, UART_MCR_LOOP);
853 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
854 old_dl = serial_dl_read(up);
855 serial_dl_write(up, 0x0001);
856 serial_out(up, UART_LCR, 0x03);
857 for (count = 0; count < 256; count++)
858 serial_out(up, UART_TX, count);
859 mdelay(20);/* FIXME - schedule_timeout */
860 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
861 (count < 256); count++)
862 serial_in(up, UART_RX);
863 serial_out(up, UART_FCR, old_fcr);
864 serial8250_out_MCR(up, old_mcr);
865 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
866 serial_dl_write(up, old_dl);
867 serial_out(up, UART_LCR, old_lcr);
868
869 return count;
870 }
871
872 /*
873 * Read UART ID using the divisor method - set DLL and DLM to zero
874 * and the revision will be in DLL and device type in DLM. We
875 * preserve the device state across this.
876 */
877 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
878 {
879 unsigned char old_lcr;
880 unsigned int id, old_dl;
881
882 old_lcr = serial_in(p, UART_LCR);
883 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
884 old_dl = serial_dl_read(p);
885 serial_dl_write(p, 0);
886 id = serial_dl_read(p);
887 serial_dl_write(p, old_dl);
888
889 serial_out(p, UART_LCR, old_lcr);
890
891 return id;
892 }
893
894 /*
895 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
896 * When this function is called we know it is at least a StarTech
897 * 16650 V2, but it might be one of several StarTech UARTs, or one of
898 * its clones. (We treat the broken original StarTech 16650 V1 as a
899 * 16550, and why not? Startech doesn't seem to even acknowledge its
900 * existence.)
901 *
902 * What evil have men's minds wrought...
903 */
904 static void autoconfig_has_efr(struct uart_8250_port *up)
905 {
906 unsigned int id1, id2, id3, rev;
907
908 /*
909 * Everything with an EFR has SLEEP
910 */
911 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
912
913 /*
914 * First we check to see if it's an Oxford Semiconductor UART.
915 *
916 * If we have to do this here because some non-National
917 * Semiconductor clone chips lock up if you try writing to the
918 * LSR register (which serial_icr_read does)
919 */
920
921 /*
922 * Check for Oxford Semiconductor 16C950.
923 *
924 * EFR [4] must be set else this test fails.
925 *
926 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
927 * claims that it's needed for 952 dual UART's (which are not
928 * recommended for new designs).
929 */
930 up->acr = 0;
931 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
932 serial_out(up, UART_EFR, UART_EFR_ECB);
933 serial_out(up, UART_LCR, 0x00);
934 id1 = serial_icr_read(up, UART_ID1);
935 id2 = serial_icr_read(up, UART_ID2);
936 id3 = serial_icr_read(up, UART_ID3);
937 rev = serial_icr_read(up, UART_REV);
938
939 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
940
941 if (id1 == 0x16 && id2 == 0xC9 &&
942 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
943 up->port.type = PORT_16C950;
944
945 /*
946 * Enable work around for the Oxford Semiconductor 952 rev B
947 * chip which causes it to seriously miscalculate baud rates
948 * when DLL is 0.
949 */
950 if (id3 == 0x52 && rev == 0x01)
951 up->bugs |= UART_BUG_QUOT;
952 return;
953 }
954
955 /*
956 * We check for a XR16C850 by setting DLL and DLM to 0, and then
957 * reading back DLL and DLM. The chip type depends on the DLM
958 * value read back:
959 * 0x10 - XR16C850 and the DLL contains the chip revision.
960 * 0x12 - XR16C2850.
961 * 0x14 - XR16C854.
962 */
963 id1 = autoconfig_read_divisor_id(up);
964 DEBUG_AUTOCONF("850id=%04x ", id1);
965
966 id2 = id1 >> 8;
967 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
968 up->port.type = PORT_16850;
969 return;
970 }
971
972 /*
973 * It wasn't an XR16C850.
974 *
975 * We distinguish between the '654 and the '650 by counting
976 * how many bytes are in the FIFO. I'm using this for now,
977 * since that's the technique that was sent to me in the
978 * serial driver update, but I'm not convinced this works.
979 * I've had problems doing this in the past. -TYT
980 */
981 if (size_fifo(up) == 64)
982 up->port.type = PORT_16654;
983 else
984 up->port.type = PORT_16650V2;
985 }
986
987 /*
988 * We detected a chip without a FIFO. Only two fall into
989 * this category - the original 8250 and the 16450. The
990 * 16450 has a scratch register (accessible with LCR=0)
991 */
992 static void autoconfig_8250(struct uart_8250_port *up)
993 {
994 unsigned char scratch, status1, status2;
995
996 up->port.type = PORT_8250;
997
998 scratch = serial_in(up, UART_SCR);
999 serial_out(up, UART_SCR, 0xa5);
1000 status1 = serial_in(up, UART_SCR);
1001 serial_out(up, UART_SCR, 0x5a);
1002 status2 = serial_in(up, UART_SCR);
1003 serial_out(up, UART_SCR, scratch);
1004
1005 if (status1 == 0xa5 && status2 == 0x5a)
1006 up->port.type = PORT_16450;
1007 }
1008
1009 static int broken_efr(struct uart_8250_port *up)
1010 {
1011 /*
1012 * Exar ST16C2550 "A2" devices incorrectly detect as
1013 * having an EFR, and report an ID of 0x0201. See
1014 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1015 */
1016 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1017 return 1;
1018
1019 return 0;
1020 }
1021
1022 /*
1023 * We know that the chip has FIFOs. Does it have an EFR? The
1024 * EFR is located in the same register position as the IIR and
1025 * we know the top two bits of the IIR are currently set. The
1026 * EFR should contain zero. Try to read the EFR.
1027 */
1028 static void autoconfig_16550a(struct uart_8250_port *up)
1029 {
1030 unsigned char status1, status2;
1031 unsigned int iersave;
1032
1033 up->port.type = PORT_16550A;
1034 up->capabilities |= UART_CAP_FIFO;
1035
1036 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS))
1037 return;
1038
1039 /*
1040 * Check for presence of the EFR when DLAB is set.
1041 * Only ST16C650V1 UARTs pass this test.
1042 */
1043 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1044 if (serial_in(up, UART_EFR) == 0) {
1045 serial_out(up, UART_EFR, 0xA8);
1046 if (serial_in(up, UART_EFR) != 0) {
1047 DEBUG_AUTOCONF("EFRv1 ");
1048 up->port.type = PORT_16650;
1049 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1050 } else {
1051 serial_out(up, UART_LCR, 0);
1052 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1053 UART_FCR7_64BYTE);
1054 status1 = serial_in(up, UART_IIR) >> 5;
1055 serial_out(up, UART_FCR, 0);
1056 serial_out(up, UART_LCR, 0);
1057
1058 if (status1 == 7)
1059 up->port.type = PORT_16550A_FSL64;
1060 else
1061 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1062 }
1063 serial_out(up, UART_EFR, 0);
1064 return;
1065 }
1066
1067 /*
1068 * Maybe it requires 0xbf to be written to the LCR.
1069 * (other ST16C650V2 UARTs, TI16C752A, etc)
1070 */
1071 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1072 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1073 DEBUG_AUTOCONF("EFRv2 ");
1074 autoconfig_has_efr(up);
1075 return;
1076 }
1077
1078 /*
1079 * Check for a National Semiconductor SuperIO chip.
1080 * Attempt to switch to bank 2, read the value of the LOOP bit
1081 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1082 * switch back to bank 2, read it from EXCR1 again and check
1083 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1084 */
1085 serial_out(up, UART_LCR, 0);
1086 status1 = serial8250_in_MCR(up);
1087 serial_out(up, UART_LCR, 0xE0);
1088 status2 = serial_in(up, 0x02); /* EXCR1 */
1089
1090 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1091 serial_out(up, UART_LCR, 0);
1092 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1093 serial_out(up, UART_LCR, 0xE0);
1094 status2 = serial_in(up, 0x02); /* EXCR1 */
1095 serial_out(up, UART_LCR, 0);
1096 serial8250_out_MCR(up, status1);
1097
1098 if ((status2 ^ status1) & UART_MCR_LOOP) {
1099 unsigned short quot;
1100
1101 serial_out(up, UART_LCR, 0xE0);
1102
1103 quot = serial_dl_read(up);
1104 quot <<= 3;
1105
1106 if (ns16550a_goto_highspeed(up))
1107 serial_dl_write(up, quot);
1108
1109 serial_out(up, UART_LCR, 0);
1110
1111 up->port.uartclk = 921600*16;
1112 up->port.type = PORT_NS16550A;
1113 up->capabilities |= UART_NATSEMI;
1114 return;
1115 }
1116 }
1117
1118 /*
1119 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1120 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1121 * Try setting it with and without DLAB set. Cheap clones
1122 * set bit 5 without DLAB set.
1123 */
1124 serial_out(up, UART_LCR, 0);
1125 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1126 status1 = serial_in(up, UART_IIR) >> 5;
1127 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1128 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1129 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1130 status2 = serial_in(up, UART_IIR) >> 5;
1131 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1132 serial_out(up, UART_LCR, 0);
1133
1134 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1135
1136 if (status1 == 6 && status2 == 7) {
1137 up->port.type = PORT_16750;
1138 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1139 return;
1140 }
1141
1142 /*
1143 * Try writing and reading the UART_IER_UUE bit (b6).
1144 * If it works, this is probably one of the Xscale platform's
1145 * internal UARTs.
1146 * We're going to explicitly set the UUE bit to 0 before
1147 * trying to write and read a 1 just to make sure it's not
1148 * already a 1 and maybe locked there before we even start start.
1149 */
1150 iersave = serial_in(up, UART_IER);
1151 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1152 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1153 /*
1154 * OK it's in a known zero state, try writing and reading
1155 * without disturbing the current state of the other bits.
1156 */
1157 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1158 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1159 /*
1160 * It's an Xscale.
1161 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1162 */
1163 DEBUG_AUTOCONF("Xscale ");
1164 up->port.type = PORT_XSCALE;
1165 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1166 return;
1167 }
1168 } else {
1169 /*
1170 * If we got here we couldn't force the IER_UUE bit to 0.
1171 * Log it and continue.
1172 */
1173 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1174 }
1175 serial_out(up, UART_IER, iersave);
1176
1177 /*
1178 * We distinguish between 16550A and U6 16550A by counting
1179 * how many bytes are in the FIFO.
1180 */
1181 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1182 up->port.type = PORT_U6_16550A;
1183 up->capabilities |= UART_CAP_AFE;
1184 }
1185 }
1186
1187 /*
1188 * This routine is called by rs_init() to initialize a specific serial
1189 * port. It determines what type of UART chip this serial port is
1190 * using: 8250, 16450, 16550, 16550A. The important question is
1191 * whether or not this UART is a 16550A or not, since this will
1192 * determine whether or not we can use its FIFO features or not.
1193 */
1194 static void autoconfig(struct uart_8250_port *up)
1195 {
1196 unsigned char status1, scratch, scratch2, scratch3;
1197 unsigned char save_lcr, save_mcr;
1198 struct uart_port *port = &up->port;
1199 unsigned long flags;
1200 unsigned int old_capabilities;
1201
1202 if (!port->iobase && !port->mapbase && !port->membase)
1203 return;
1204
1205 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1206 port->name, port->iobase, port->membase);
1207
1208 /*
1209 * We really do need global IRQs disabled here - we're going to
1210 * be frobbing the chips IRQ enable register to see if it exists.
1211 */
1212 spin_lock_irqsave(&port->lock, flags);
1213
1214 up->capabilities = 0;
1215 up->bugs = 0;
1216
1217 if (!(port->flags & UPF_BUGGY_UART)) {
1218 /*
1219 * Do a simple existence test first; if we fail this,
1220 * there's no point trying anything else.
1221 *
1222 * 0x80 is used as a nonsense port to prevent against
1223 * false positives due to ISA bus float. The
1224 * assumption is that 0x80 is a non-existent port;
1225 * which should be safe since include/asm/io.h also
1226 * makes this assumption.
1227 *
1228 * Note: this is safe as long as MCR bit 4 is clear
1229 * and the device is in "PC" mode.
1230 */
1231 scratch = serial_in(up, UART_IER);
1232 serial_out(up, UART_IER, 0);
1233 #ifdef __i386__
1234 outb(0xff, 0x080);
1235 #endif
1236 /*
1237 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1238 * 16C754B) allow only to modify them if an EFR bit is set.
1239 */
1240 scratch2 = serial_in(up, UART_IER) & 0x0f;
1241 serial_out(up, UART_IER, 0x0F);
1242 #ifdef __i386__
1243 outb(0, 0x080);
1244 #endif
1245 scratch3 = serial_in(up, UART_IER) & 0x0f;
1246 serial_out(up, UART_IER, scratch);
1247 if (scratch2 != 0 || scratch3 != 0x0F) {
1248 /*
1249 * We failed; there's nothing here
1250 */
1251 spin_unlock_irqrestore(&port->lock, flags);
1252 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1253 scratch2, scratch3);
1254 goto out;
1255 }
1256 }
1257
1258 save_mcr = serial8250_in_MCR(up);
1259 save_lcr = serial_in(up, UART_LCR);
1260
1261 /*
1262 * Check to see if a UART is really there. Certain broken
1263 * internal modems based on the Rockwell chipset fail this
1264 * test, because they apparently don't implement the loopback
1265 * test mode. So this test is skipped on the COM 1 through
1266 * COM 4 ports. This *should* be safe, since no board
1267 * manufacturer would be stupid enough to design a board
1268 * that conflicts with COM 1-4 --- we hope!
1269 */
1270 if (!(port->flags & UPF_SKIP_TEST)) {
1271 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1272 status1 = serial_in(up, UART_MSR) & 0xF0;
1273 serial8250_out_MCR(up, save_mcr);
1274 if (status1 != 0x90) {
1275 spin_unlock_irqrestore(&port->lock, flags);
1276 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1277 status1);
1278 goto out;
1279 }
1280 }
1281
1282 /*
1283 * We're pretty sure there's a port here. Lets find out what
1284 * type of port it is. The IIR top two bits allows us to find
1285 * out if it's 8250 or 16450, 16550, 16550A or later. This
1286 * determines what we test for next.
1287 *
1288 * We also initialise the EFR (if any) to zero for later. The
1289 * EFR occupies the same register location as the FCR and IIR.
1290 */
1291 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1292 serial_out(up, UART_EFR, 0);
1293 serial_out(up, UART_LCR, 0);
1294
1295 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1296 scratch = serial_in(up, UART_IIR) >> 6;
1297
1298 switch (scratch) {
1299 case 0:
1300 autoconfig_8250(up);
1301 break;
1302 case 1:
1303 port->type = PORT_UNKNOWN;
1304 break;
1305 case 2:
1306 port->type = PORT_16550;
1307 break;
1308 case 3:
1309 autoconfig_16550a(up);
1310 break;
1311 }
1312
1313 #ifdef CONFIG_SERIAL_8250_RSA
1314 /*
1315 * Only probe for RSA ports if we got the region.
1316 */
1317 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1318 __enable_rsa(up))
1319 port->type = PORT_RSA;
1320 #endif
1321
1322 serial_out(up, UART_LCR, save_lcr);
1323
1324 port->fifosize = uart_config[up->port.type].fifo_size;
1325 old_capabilities = up->capabilities;
1326 up->capabilities = uart_config[port->type].flags;
1327 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1328
1329 if (port->type == PORT_UNKNOWN)
1330 goto out_lock;
1331
1332 /*
1333 * Reset the UART.
1334 */
1335 #ifdef CONFIG_SERIAL_8250_RSA
1336 if (port->type == PORT_RSA)
1337 serial_out(up, UART_RSA_FRR, 0);
1338 #endif
1339 serial8250_out_MCR(up, save_mcr);
1340 serial8250_clear_fifos(up);
1341 serial_in(up, UART_RX);
1342 if (up->capabilities & UART_CAP_UUE)
1343 serial_out(up, UART_IER, UART_IER_UUE);
1344 else
1345 serial_out(up, UART_IER, 0);
1346
1347 out_lock:
1348 spin_unlock_irqrestore(&port->lock, flags);
1349
1350 /*
1351 * Check if the device is a Fintek F81216A
1352 */
1353 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1354 fintek_8250_probe(up);
1355
1356 if (up->capabilities != old_capabilities) {
1357 dev_warn(port->dev, "detected caps %08x should be %08x\n",
1358 old_capabilities, up->capabilities);
1359 }
1360 out:
1361 DEBUG_AUTOCONF("iir=%d ", scratch);
1362 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1363 }
1364
1365 static void autoconfig_irq(struct uart_8250_port *up)
1366 {
1367 struct uart_port *port = &up->port;
1368 unsigned char save_mcr, save_ier;
1369 unsigned char save_ICP = 0;
1370 unsigned int ICP = 0;
1371 unsigned long irqs;
1372 int irq;
1373
1374 if (port->flags & UPF_FOURPORT) {
1375 ICP = (port->iobase & 0xfe0) | 0x1f;
1376 save_ICP = inb_p(ICP);
1377 outb_p(0x80, ICP);
1378 inb_p(ICP);
1379 }
1380
1381 if (uart_console(port))
1382 console_lock();
1383
1384 /* forget possible initially masked and pending IRQ */
1385 probe_irq_off(probe_irq_on());
1386 save_mcr = serial8250_in_MCR(up);
1387 save_ier = serial_in(up, UART_IER);
1388 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1389
1390 irqs = probe_irq_on();
1391 serial8250_out_MCR(up, 0);
1392 udelay(10);
1393 if (port->flags & UPF_FOURPORT) {
1394 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1395 } else {
1396 serial8250_out_MCR(up,
1397 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1398 }
1399 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1400 serial_in(up, UART_LSR);
1401 serial_in(up, UART_RX);
1402 serial_in(up, UART_IIR);
1403 serial_in(up, UART_MSR);
1404 serial_out(up, UART_TX, 0xFF);
1405 udelay(20);
1406 irq = probe_irq_off(irqs);
1407
1408 serial8250_out_MCR(up, save_mcr);
1409 serial_out(up, UART_IER, save_ier);
1410
1411 if (port->flags & UPF_FOURPORT)
1412 outb_p(save_ICP, ICP);
1413
1414 if (uart_console(port))
1415 console_unlock();
1416
1417 port->irq = (irq > 0) ? irq : 0;
1418 }
1419
1420 static void serial8250_stop_rx(struct uart_port *port)
1421 {
1422 struct uart_8250_port *up = up_to_u8250p(port);
1423
1424 serial8250_rpm_get(up);
1425
1426 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1427 up->port.read_status_mask &= ~UART_LSR_DR;
1428 serial_port_out(port, UART_IER, up->ier);
1429
1430 serial8250_rpm_put(up);
1431 }
1432
1433 /**
1434 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1435 * @up: uart 8250 port
1436 *
1437 * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1438 */
1439 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1440 {
1441 unsigned char mcr = serial8250_in_MCR(p);
1442
1443 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1444 mcr |= UART_MCR_RTS;
1445 else
1446 mcr &= ~UART_MCR_RTS;
1447 serial8250_out_MCR(p, mcr);
1448
1449 /*
1450 * Empty the RX FIFO, we are not interested in anything
1451 * received during the half-duplex transmission.
1452 * Enable previously disabled RX interrupts.
1453 */
1454 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1455 serial8250_clear_and_reinit_fifos(p);
1456
1457 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1458 serial_port_out(&p->port, UART_IER, p->ier);
1459 }
1460 }
1461 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1462
1463 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1464 {
1465 struct uart_8250_em485 *em485;
1466 struct uart_8250_port *p;
1467 unsigned long flags;
1468
1469 em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1470 p = em485->port;
1471
1472 serial8250_rpm_get(p);
1473 spin_lock_irqsave(&p->port.lock, flags);
1474 if (em485->active_timer == &em485->stop_tx_timer) {
1475 p->rs485_stop_tx(p);
1476 em485->active_timer = NULL;
1477 em485->tx_stopped = true;
1478 }
1479 spin_unlock_irqrestore(&p->port.lock, flags);
1480 serial8250_rpm_put(p);
1481 return HRTIMER_NORESTART;
1482 }
1483
1484 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1485 {
1486 long sec = msec / 1000;
1487 long nsec = (msec % 1000) * 1000000;
1488 ktime_t t = ktime_set(sec, nsec);
1489
1490 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1491 }
1492
1493 static void __stop_tx_rs485(struct uart_8250_port *p)
1494 {
1495 struct uart_8250_em485 *em485 = p->em485;
1496
1497 /*
1498 * rs485_stop_tx() is going to set RTS according to config
1499 * AND flush RX FIFO if required.
1500 */
1501 if (p->port.rs485.delay_rts_after_send > 0) {
1502 em485->active_timer = &em485->stop_tx_timer;
1503 start_hrtimer_ms(&em485->stop_tx_timer,
1504 p->port.rs485.delay_rts_after_send);
1505 } else {
1506 p->rs485_stop_tx(p);
1507 em485->active_timer = NULL;
1508 em485->tx_stopped = true;
1509 }
1510 }
1511
1512 static inline void __do_stop_tx(struct uart_8250_port *p)
1513 {
1514 if (serial8250_clear_THRI(p))
1515 serial8250_rpm_put_tx(p);
1516 }
1517
1518 static inline void __stop_tx(struct uart_8250_port *p)
1519 {
1520 struct uart_8250_em485 *em485 = p->em485;
1521
1522 if (em485) {
1523 unsigned char lsr = serial_in(p, UART_LSR);
1524 /*
1525 * To provide required timeing and allow FIFO transfer,
1526 * __stop_tx_rs485() must be called only when both FIFO and
1527 * shift register are empty. It is for device driver to enable
1528 * interrupt on TEMT.
1529 */
1530 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1531 return;
1532
1533 __stop_tx_rs485(p);
1534 }
1535 __do_stop_tx(p);
1536 }
1537
1538 static void serial8250_stop_tx(struct uart_port *port)
1539 {
1540 struct uart_8250_port *up = up_to_u8250p(port);
1541
1542 serial8250_rpm_get(up);
1543 __stop_tx(up);
1544
1545 /*
1546 * We really want to stop the transmitter from sending.
1547 */
1548 if (port->type == PORT_16C950) {
1549 up->acr |= UART_ACR_TXDIS;
1550 serial_icr_write(up, UART_ACR, up->acr);
1551 }
1552 serial8250_rpm_put(up);
1553 }
1554
1555 static inline void __start_tx(struct uart_port *port)
1556 {
1557 struct uart_8250_port *up = up_to_u8250p(port);
1558
1559 if (up->dma && !up->dma->tx_dma(up))
1560 return;
1561
1562 if (serial8250_set_THRI(up)) {
1563 if (up->bugs & UART_BUG_TXEN) {
1564 unsigned char lsr;
1565
1566 lsr = serial_in(up, UART_LSR);
1567 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1568 if (lsr & UART_LSR_THRE)
1569 serial8250_tx_chars(up);
1570 }
1571 }
1572
1573 /*
1574 * Re-enable the transmitter if we disabled it.
1575 */
1576 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1577 up->acr &= ~UART_ACR_TXDIS;
1578 serial_icr_write(up, UART_ACR, up->acr);
1579 }
1580 }
1581
1582 /**
1583 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1584 * @up: uart 8250 port
1585 *
1586 * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1587 * Assumes that setting the RTS bit in the MCR register means RTS is high.
1588 * (Some chips use inverse semantics.) Further assumes that reception is
1589 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1590 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1591 */
1592 void serial8250_em485_start_tx(struct uart_8250_port *up)
1593 {
1594 unsigned char mcr = serial8250_in_MCR(up);
1595
1596 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1597 serial8250_stop_rx(&up->port);
1598
1599 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1600 mcr |= UART_MCR_RTS;
1601 else
1602 mcr &= ~UART_MCR_RTS;
1603 serial8250_out_MCR(up, mcr);
1604 }
1605 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1606
1607 static inline void start_tx_rs485(struct uart_port *port)
1608 {
1609 struct uart_8250_port *up = up_to_u8250p(port);
1610 struct uart_8250_em485 *em485 = up->em485;
1611
1612 em485->active_timer = NULL;
1613
1614 if (em485->tx_stopped) {
1615 em485->tx_stopped = false;
1616
1617 up->rs485_start_tx(up);
1618
1619 if (up->port.rs485.delay_rts_before_send > 0) {
1620 em485->active_timer = &em485->start_tx_timer;
1621 start_hrtimer_ms(&em485->start_tx_timer,
1622 up->port.rs485.delay_rts_before_send);
1623 return;
1624 }
1625 }
1626
1627 __start_tx(port);
1628 }
1629
1630 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1631 {
1632 struct uart_8250_em485 *em485;
1633 struct uart_8250_port *p;
1634 unsigned long flags;
1635
1636 em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1637 p = em485->port;
1638
1639 spin_lock_irqsave(&p->port.lock, flags);
1640 if (em485->active_timer == &em485->start_tx_timer) {
1641 __start_tx(&p->port);
1642 em485->active_timer = NULL;
1643 }
1644 spin_unlock_irqrestore(&p->port.lock, flags);
1645 return HRTIMER_NORESTART;
1646 }
1647
1648 static void serial8250_start_tx(struct uart_port *port)
1649 {
1650 struct uart_8250_port *up = up_to_u8250p(port);
1651 struct uart_8250_em485 *em485 = up->em485;
1652
1653 serial8250_rpm_get_tx(up);
1654
1655 if (em485 &&
1656 em485->active_timer == &em485->start_tx_timer)
1657 return;
1658
1659 if (em485)
1660 start_tx_rs485(port);
1661 else
1662 __start_tx(port);
1663 }
1664
1665 static void serial8250_throttle(struct uart_port *port)
1666 {
1667 port->throttle(port);
1668 }
1669
1670 static void serial8250_unthrottle(struct uart_port *port)
1671 {
1672 port->unthrottle(port);
1673 }
1674
1675 static void serial8250_disable_ms(struct uart_port *port)
1676 {
1677 struct uart_8250_port *up = up_to_u8250p(port);
1678
1679 /* no MSR capabilities */
1680 if (up->bugs & UART_BUG_NOMSR)
1681 return;
1682
1683 mctrl_gpio_disable_ms(up->gpios);
1684
1685 up->ier &= ~UART_IER_MSI;
1686 serial_port_out(port, UART_IER, up->ier);
1687 }
1688
1689 static void serial8250_enable_ms(struct uart_port *port)
1690 {
1691 struct uart_8250_port *up = up_to_u8250p(port);
1692
1693 /* no MSR capabilities */
1694 if (up->bugs & UART_BUG_NOMSR)
1695 return;
1696
1697 mctrl_gpio_enable_ms(up->gpios);
1698
1699 up->ier |= UART_IER_MSI;
1700
1701 serial8250_rpm_get(up);
1702 serial_port_out(port, UART_IER, up->ier);
1703 serial8250_rpm_put(up);
1704 }
1705
1706 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1707 {
1708 struct uart_port *port = &up->port;
1709 unsigned char ch;
1710 char flag = TTY_NORMAL;
1711
1712 if (likely(lsr & UART_LSR_DR))
1713 ch = serial_in(up, UART_RX);
1714 else
1715 /*
1716 * Intel 82571 has a Serial Over Lan device that will
1717 * set UART_LSR_BI without setting UART_LSR_DR when
1718 * it receives a break. To avoid reading from the
1719 * receive buffer without UART_LSR_DR bit set, we
1720 * just force the read character to be 0
1721 */
1722 ch = 0;
1723
1724 port->icount.rx++;
1725
1726 lsr |= up->lsr_saved_flags;
1727 up->lsr_saved_flags = 0;
1728
1729 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1730 if (lsr & UART_LSR_BI) {
1731 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1732 port->icount.brk++;
1733 /*
1734 * We do the SysRQ and SAK checking
1735 * here because otherwise the break
1736 * may get masked by ignore_status_mask
1737 * or read_status_mask.
1738 */
1739 if (uart_handle_break(port))
1740 return;
1741 } else if (lsr & UART_LSR_PE)
1742 port->icount.parity++;
1743 else if (lsr & UART_LSR_FE)
1744 port->icount.frame++;
1745 if (lsr & UART_LSR_OE)
1746 port->icount.overrun++;
1747
1748 /*
1749 * Mask off conditions which should be ignored.
1750 */
1751 lsr &= port->read_status_mask;
1752
1753 if (lsr & UART_LSR_BI) {
1754 dev_dbg(port->dev, "handling break\n");
1755 flag = TTY_BREAK;
1756 } else if (lsr & UART_LSR_PE)
1757 flag = TTY_PARITY;
1758 else if (lsr & UART_LSR_FE)
1759 flag = TTY_FRAME;
1760 }
1761 if (uart_prepare_sysrq_char(port, ch))
1762 return;
1763
1764 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1765 }
1766 EXPORT_SYMBOL_GPL(serial8250_read_char);
1767
1768 /*
1769 * serial8250_rx_chars: processes according to the passed in LSR
1770 * value, and returns the remaining LSR bits not handled
1771 * by this Rx routine.
1772 */
1773 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1774 {
1775 struct uart_port *port = &up->port;
1776 int max_count = 256;
1777
1778 do {
1779 serial8250_read_char(up, lsr);
1780 if (--max_count == 0)
1781 break;
1782 lsr = serial_in(up, UART_LSR);
1783 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1784
1785 tty_flip_buffer_push(&port->state->port);
1786 return lsr;
1787 }
1788 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1789
1790 void serial8250_tx_chars(struct uart_8250_port *up)
1791 {
1792 struct uart_port *port = &up->port;
1793 struct circ_buf *xmit = &port->state->xmit;
1794 int count;
1795
1796 if (port->x_char) {
1797 serial_out(up, UART_TX, port->x_char);
1798 port->icount.tx++;
1799 port->x_char = 0;
1800 return;
1801 }
1802 if (uart_tx_stopped(port)) {
1803 serial8250_stop_tx(port);
1804 return;
1805 }
1806 if (uart_circ_empty(xmit)) {
1807 __stop_tx(up);
1808 return;
1809 }
1810
1811 count = up->tx_loadsz;
1812 do {
1813 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1814 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1815 port->icount.tx++;
1816 if (uart_circ_empty(xmit))
1817 break;
1818 if ((up->capabilities & UART_CAP_HFIFO) &&
1819 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1820 break;
1821 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1822 if ((up->capabilities & UART_CAP_MINI) &&
1823 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1824 break;
1825 } while (--count > 0);
1826
1827 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1828 uart_write_wakeup(port);
1829
1830 /*
1831 * With RPM enabled, we have to wait until the FIFO is empty before the
1832 * HW can go idle. So we get here once again with empty FIFO and disable
1833 * the interrupt and RPM in __stop_tx()
1834 */
1835 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1836 __stop_tx(up);
1837 }
1838 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1839
1840 /* Caller holds uart port lock */
1841 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1842 {
1843 struct uart_port *port = &up->port;
1844 unsigned int status = serial_in(up, UART_MSR);
1845
1846 status |= up->msr_saved_flags;
1847 up->msr_saved_flags = 0;
1848 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1849 port->state != NULL) {
1850 if (status & UART_MSR_TERI)
1851 port->icount.rng++;
1852 if (status & UART_MSR_DDSR)
1853 port->icount.dsr++;
1854 if (status & UART_MSR_DDCD)
1855 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1856 if (status & UART_MSR_DCTS)
1857 uart_handle_cts_change(port, status & UART_MSR_CTS);
1858
1859 wake_up_interruptible(&port->state->port.delta_msr_wait);
1860 }
1861
1862 return status;
1863 }
1864 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1865
1866 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1867 {
1868 switch (iir & 0x3f) {
1869 case UART_IIR_RX_TIMEOUT:
1870 serial8250_rx_dma_flush(up);
1871 /* fall-through */
1872 case UART_IIR_RLSI:
1873 return true;
1874 }
1875 return up->dma->rx_dma(up);
1876 }
1877
1878 /*
1879 * This handles the interrupt from one port.
1880 */
1881 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1882 {
1883 unsigned char status;
1884 unsigned long flags;
1885 struct uart_8250_port *up = up_to_u8250p(port);
1886 bool skip_rx = false;
1887
1888 if (iir & UART_IIR_NO_INT)
1889 return 0;
1890
1891 spin_lock_irqsave(&port->lock, flags);
1892
1893 status = serial_port_in(port, UART_LSR);
1894
1895 /*
1896 * If port is stopped and there are no error conditions in the
1897 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1898 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1899 * control when FIFO occupancy reaches preset threshold, thus
1900 * halting RX. This only works when auto HW flow control is
1901 * available.
1902 */
1903 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1904 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1905 !(port->read_status_mask & UART_LSR_DR))
1906 skip_rx = true;
1907
1908 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1909 if (!up->dma || handle_rx_dma(up, iir))
1910 status = serial8250_rx_chars(up, status);
1911 }
1912 serial8250_modem_status(up);
1913 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1914 (up->ier & UART_IER_THRI))
1915 serial8250_tx_chars(up);
1916
1917 uart_unlock_and_check_sysrq(port, flags);
1918 return 1;
1919 }
1920 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1921
1922 static int serial8250_default_handle_irq(struct uart_port *port)
1923 {
1924 struct uart_8250_port *up = up_to_u8250p(port);
1925 unsigned int iir;
1926 int ret;
1927
1928 serial8250_rpm_get(up);
1929
1930 iir = serial_port_in(port, UART_IIR);
1931 ret = serial8250_handle_irq(port, iir);
1932
1933 serial8250_rpm_put(up);
1934 return ret;
1935 }
1936
1937 /*
1938 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1939 * have a programmable TX threshold that triggers the THRE interrupt in
1940 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1941 * has space available. Load it up with tx_loadsz bytes.
1942 */
1943 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1944 {
1945 unsigned long flags;
1946 unsigned int iir = serial_port_in(port, UART_IIR);
1947
1948 /* TX Threshold IRQ triggered so load up FIFO */
1949 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1950 struct uart_8250_port *up = up_to_u8250p(port);
1951
1952 spin_lock_irqsave(&port->lock, flags);
1953 serial8250_tx_chars(up);
1954 spin_unlock_irqrestore(&port->lock, flags);
1955 }
1956
1957 iir = serial_port_in(port, UART_IIR);
1958 return serial8250_handle_irq(port, iir);
1959 }
1960
1961 static unsigned int serial8250_tx_empty(struct uart_port *port)
1962 {
1963 struct uart_8250_port *up = up_to_u8250p(port);
1964 unsigned long flags;
1965 unsigned int lsr;
1966
1967 serial8250_rpm_get(up);
1968
1969 spin_lock_irqsave(&port->lock, flags);
1970 lsr = serial_port_in(port, UART_LSR);
1971 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1972 spin_unlock_irqrestore(&port->lock, flags);
1973
1974 serial8250_rpm_put(up);
1975
1976 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1977 }
1978
1979 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1980 {
1981 struct uart_8250_port *up = up_to_u8250p(port);
1982 unsigned int status;
1983 unsigned int val;
1984
1985 serial8250_rpm_get(up);
1986 status = serial8250_modem_status(up);
1987 serial8250_rpm_put(up);
1988
1989 val = serial8250_MSR_to_TIOCM(status);
1990 if (up->gpios)
1991 return mctrl_gpio_get(up->gpios, &val);
1992
1993 return val;
1994 }
1995 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1996
1997 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1998 {
1999 if (port->get_mctrl)
2000 return port->get_mctrl(port);
2001 return serial8250_do_get_mctrl(port);
2002 }
2003
2004 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2005 {
2006 struct uart_8250_port *up = up_to_u8250p(port);
2007 unsigned char mcr;
2008
2009 if (port->rs485.flags & SER_RS485_ENABLED) {
2010 if (serial8250_in_MCR(up) & UART_MCR_RTS)
2011 mctrl |= TIOCM_RTS;
2012 else
2013 mctrl &= ~TIOCM_RTS;
2014 }
2015
2016 mcr = serial8250_TIOCM_to_MCR(mctrl);
2017
2018 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
2019
2020 serial8250_out_MCR(up, mcr);
2021 }
2022 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2023
2024 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2025 {
2026 if (port->set_mctrl)
2027 port->set_mctrl(port, mctrl);
2028 else
2029 serial8250_do_set_mctrl(port, mctrl);
2030 }
2031
2032 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2033 {
2034 struct uart_8250_port *up = up_to_u8250p(port);
2035 unsigned long flags;
2036
2037 serial8250_rpm_get(up);
2038 spin_lock_irqsave(&port->lock, flags);
2039 if (break_state == -1)
2040 up->lcr |= UART_LCR_SBC;
2041 else
2042 up->lcr &= ~UART_LCR_SBC;
2043 serial_port_out(port, UART_LCR, up->lcr);
2044 spin_unlock_irqrestore(&port->lock, flags);
2045 serial8250_rpm_put(up);
2046 }
2047
2048 /*
2049 * Wait for transmitter & holding register to empty
2050 */
2051 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2052 {
2053 unsigned int status, tmout = 10000;
2054
2055 /* Wait up to 10ms for the character(s) to be sent. */
2056 for (;;) {
2057 status = serial_in(up, UART_LSR);
2058
2059 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2060
2061 if ((status & bits) == bits)
2062 break;
2063 if (--tmout == 0)
2064 break;
2065 udelay(1);
2066 touch_nmi_watchdog();
2067 }
2068
2069 /* Wait up to 1s for flow control if necessary */
2070 if (up->port.flags & UPF_CONS_FLOW) {
2071 for (tmout = 1000000; tmout; tmout--) {
2072 unsigned int msr = serial_in(up, UART_MSR);
2073 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2074 if (msr & UART_MSR_CTS)
2075 break;
2076 udelay(1);
2077 touch_nmi_watchdog();
2078 }
2079 }
2080 }
2081
2082 #ifdef CONFIG_CONSOLE_POLL
2083 /*
2084 * Console polling routines for writing and reading from the uart while
2085 * in an interrupt or debug context.
2086 */
2087
2088 static int serial8250_get_poll_char(struct uart_port *port)
2089 {
2090 struct uart_8250_port *up = up_to_u8250p(port);
2091 unsigned char lsr;
2092 int status;
2093
2094 serial8250_rpm_get(up);
2095
2096 lsr = serial_port_in(port, UART_LSR);
2097
2098 if (!(lsr & UART_LSR_DR)) {
2099 status = NO_POLL_CHAR;
2100 goto out;
2101 }
2102
2103 status = serial_port_in(port, UART_RX);
2104 out:
2105 serial8250_rpm_put(up);
2106 return status;
2107 }
2108
2109
2110 static void serial8250_put_poll_char(struct uart_port *port,
2111 unsigned char c)
2112 {
2113 unsigned int ier;
2114 struct uart_8250_port *up = up_to_u8250p(port);
2115
2116 serial8250_rpm_get(up);
2117 /*
2118 * First save the IER then disable the interrupts
2119 */
2120 ier = serial_port_in(port, UART_IER);
2121 if (up->capabilities & UART_CAP_UUE)
2122 serial_port_out(port, UART_IER, UART_IER_UUE);
2123 else
2124 serial_port_out(port, UART_IER, 0);
2125
2126 wait_for_xmitr(up, BOTH_EMPTY);
2127 /*
2128 * Send the character out.
2129 */
2130 serial_port_out(port, UART_TX, c);
2131
2132 /*
2133 * Finally, wait for transmitter to become empty
2134 * and restore the IER
2135 */
2136 wait_for_xmitr(up, BOTH_EMPTY);
2137 serial_port_out(port, UART_IER, ier);
2138 serial8250_rpm_put(up);
2139 }
2140
2141 #endif /* CONFIG_CONSOLE_POLL */
2142
2143 int serial8250_do_startup(struct uart_port *port)
2144 {
2145 struct uart_8250_port *up = up_to_u8250p(port);
2146 unsigned long flags;
2147 unsigned char lsr, iir;
2148 int retval;
2149
2150 if (!port->fifosize)
2151 port->fifosize = uart_config[port->type].fifo_size;
2152 if (!up->tx_loadsz)
2153 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2154 if (!up->capabilities)
2155 up->capabilities = uart_config[port->type].flags;
2156 up->mcr = 0;
2157
2158 if (port->iotype != up->cur_iotype)
2159 set_io_from_upio(port);
2160
2161 serial8250_rpm_get(up);
2162 if (port->type == PORT_16C950) {
2163 /* Wake up and initialize UART */
2164 up->acr = 0;
2165 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2166 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2167 serial_port_out(port, UART_IER, 0);
2168 serial_port_out(port, UART_LCR, 0);
2169 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2170 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2171 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2172 serial_port_out(port, UART_LCR, 0);
2173 }
2174
2175 if (port->type == PORT_DA830) {
2176 /* Reset the port */
2177 serial_port_out(port, UART_IER, 0);
2178 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2179 mdelay(10);
2180
2181 /* Enable Tx, Rx and free run mode */
2182 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2183 UART_DA830_PWREMU_MGMT_UTRST |
2184 UART_DA830_PWREMU_MGMT_URRST |
2185 UART_DA830_PWREMU_MGMT_FREE);
2186 }
2187
2188 if (port->type == PORT_NPCM) {
2189 /*
2190 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2191 * register). Enable it, and set TIOC (timeout interrupt
2192 * comparator) to be 0x20 for correct operation.
2193 */
2194 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2195 }
2196
2197 #ifdef CONFIG_SERIAL_8250_RSA
2198 /*
2199 * If this is an RSA port, see if we can kick it up to the
2200 * higher speed clock.
2201 */
2202 enable_rsa(up);
2203 #endif
2204
2205 /*
2206 * Clear the FIFO buffers and disable them.
2207 * (they will be reenabled in set_termios())
2208 */
2209 serial8250_clear_fifos(up);
2210
2211 /*
2212 * Clear the interrupt registers.
2213 */
2214 serial_port_in(port, UART_LSR);
2215 serial_port_in(port, UART_RX);
2216 serial_port_in(port, UART_IIR);
2217 serial_port_in(port, UART_MSR);
2218
2219 /*
2220 * At this point, there's no way the LSR could still be 0xff;
2221 * if it is, then bail out, because there's likely no UART
2222 * here.
2223 */
2224 if (!(port->flags & UPF_BUGGY_UART) &&
2225 (serial_port_in(port, UART_LSR) == 0xff)) {
2226 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2227 retval = -ENODEV;
2228 goto out;
2229 }
2230
2231 /*
2232 * For a XR16C850, we need to set the trigger levels
2233 */
2234 if (port->type == PORT_16850) {
2235 unsigned char fctr;
2236
2237 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2238
2239 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2240 serial_port_out(port, UART_FCTR,
2241 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2242 serial_port_out(port, UART_TRG, UART_TRG_96);
2243 serial_port_out(port, UART_FCTR,
2244 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2245 serial_port_out(port, UART_TRG, UART_TRG_96);
2246
2247 serial_port_out(port, UART_LCR, 0);
2248 }
2249
2250 /*
2251 * For the Altera 16550 variants, set TX threshold trigger level.
2252 */
2253 if (((port->type == PORT_ALTR_16550_F32) ||
2254 (port->type == PORT_ALTR_16550_F64) ||
2255 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2256 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2257 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2258 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2259 } else {
2260 serial_port_out(port, UART_ALTR_AFR,
2261 UART_ALTR_EN_TXFIFO_LW);
2262 serial_port_out(port, UART_ALTR_TX_LOW,
2263 port->fifosize - up->tx_loadsz);
2264 port->handle_irq = serial8250_tx_threshold_handle_irq;
2265 }
2266 }
2267
2268 /* Check if we need to have shared IRQs */
2269 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2270 up->port.irqflags |= IRQF_SHARED;
2271
2272 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2273 unsigned char iir1;
2274 /*
2275 * Test for UARTs that do not reassert THRE when the
2276 * transmitter is idle and the interrupt has already
2277 * been cleared. Real 16550s should always reassert
2278 * this interrupt whenever the transmitter is idle and
2279 * the interrupt is enabled. Delays are necessary to
2280 * allow register changes to become visible.
2281 */
2282 spin_lock_irqsave(&port->lock, flags);
2283 if (up->port.irqflags & IRQF_SHARED)
2284 disable_irq_nosync(port->irq);
2285
2286 wait_for_xmitr(up, UART_LSR_THRE);
2287 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2288 udelay(1); /* allow THRE to set */
2289 iir1 = serial_port_in(port, UART_IIR);
2290 serial_port_out(port, UART_IER, 0);
2291 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2292 udelay(1); /* allow a working UART time to re-assert THRE */
2293 iir = serial_port_in(port, UART_IIR);
2294 serial_port_out(port, UART_IER, 0);
2295
2296 if (port->irqflags & IRQF_SHARED)
2297 enable_irq(port->irq);
2298 spin_unlock_irqrestore(&port->lock, flags);
2299
2300 /*
2301 * If the interrupt is not reasserted, or we otherwise
2302 * don't trust the iir, setup a timer to kick the UART
2303 * on a regular basis.
2304 */
2305 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2306 up->port.flags & UPF_BUG_THRE) {
2307 up->bugs |= UART_BUG_THRE;
2308 }
2309 }
2310
2311 retval = up->ops->setup_irq(up);
2312 if (retval)
2313 goto out;
2314
2315 /*
2316 * Now, initialize the UART
2317 */
2318 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2319
2320 spin_lock_irqsave(&port->lock, flags);
2321 if (up->port.flags & UPF_FOURPORT) {
2322 if (!up->port.irq)
2323 up->port.mctrl |= TIOCM_OUT1;
2324 } else
2325 /*
2326 * Most PC uarts need OUT2 raised to enable interrupts.
2327 */
2328 if (port->irq)
2329 up->port.mctrl |= TIOCM_OUT2;
2330
2331 serial8250_set_mctrl(port, port->mctrl);
2332
2333 /*
2334 * Serial over Lan (SoL) hack:
2335 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2336 * used for Serial Over Lan. Those chips take a longer time than a
2337 * normal serial device to signalize that a transmission data was
2338 * queued. Due to that, the above test generally fails. One solution
2339 * would be to delay the reading of iir. However, this is not
2340 * reliable, since the timeout is variable. So, let's just don't
2341 * test if we receive TX irq. This way, we'll never enable
2342 * UART_BUG_TXEN.
2343 */
2344 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2345 goto dont_test_tx_en;
2346
2347 /*
2348 * Do a quick test to see if we receive an interrupt when we enable
2349 * the TX irq.
2350 */
2351 serial_port_out(port, UART_IER, UART_IER_THRI);
2352 lsr = serial_port_in(port, UART_LSR);
2353 iir = serial_port_in(port, UART_IIR);
2354 serial_port_out(port, UART_IER, 0);
2355
2356 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2357 if (!(up->bugs & UART_BUG_TXEN)) {
2358 up->bugs |= UART_BUG_TXEN;
2359 dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2360 }
2361 } else {
2362 up->bugs &= ~UART_BUG_TXEN;
2363 }
2364
2365 dont_test_tx_en:
2366 spin_unlock_irqrestore(&port->lock, flags);
2367
2368 /*
2369 * Clear the interrupt registers again for luck, and clear the
2370 * saved flags to avoid getting false values from polling
2371 * routines or the previous session.
2372 */
2373 serial_port_in(port, UART_LSR);
2374 serial_port_in(port, UART_RX);
2375 serial_port_in(port, UART_IIR);
2376 serial_port_in(port, UART_MSR);
2377 up->lsr_saved_flags = 0;
2378 up->msr_saved_flags = 0;
2379
2380 /*
2381 * Request DMA channels for both RX and TX.
2382 */
2383 if (up->dma) {
2384 const char *msg = NULL;
2385
2386 if (uart_console(port))
2387 msg = "forbid DMA for kernel console";
2388 else if (serial8250_request_dma(up))
2389 msg = "failed to request DMA";
2390 if (msg) {
2391 dev_warn_ratelimited(port->dev, "%s\n", msg);
2392 up->dma = NULL;
2393 }
2394 }
2395
2396 /*
2397 * Set the IER shadow for rx interrupts but defer actual interrupt
2398 * enable until after the FIFOs are enabled; otherwise, an already-
2399 * active sender can swamp the interrupt handler with "too much work".
2400 */
2401 up->ier = UART_IER_RLSI | UART_IER_RDI;
2402
2403 if (port->flags & UPF_FOURPORT) {
2404 unsigned int icp;
2405 /*
2406 * Enable interrupts on the AST Fourport board
2407 */
2408 icp = (port->iobase & 0xfe0) | 0x01f;
2409 outb_p(0x80, icp);
2410 inb_p(icp);
2411 }
2412 retval = 0;
2413 out:
2414 serial8250_rpm_put(up);
2415 return retval;
2416 }
2417 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2418
2419 static int serial8250_startup(struct uart_port *port)
2420 {
2421 if (port->startup)
2422 return port->startup(port);
2423 return serial8250_do_startup(port);
2424 }
2425
2426 void serial8250_do_shutdown(struct uart_port *port)
2427 {
2428 struct uart_8250_port *up = up_to_u8250p(port);
2429 unsigned long flags;
2430
2431 serial8250_rpm_get(up);
2432 /*
2433 * Disable interrupts from this port
2434 */
2435 spin_lock_irqsave(&port->lock, flags);
2436 up->ier = 0;
2437 serial_port_out(port, UART_IER, 0);
2438 spin_unlock_irqrestore(&port->lock, flags);
2439
2440 synchronize_irq(port->irq);
2441
2442 if (up->dma)
2443 serial8250_release_dma(up);
2444
2445 spin_lock_irqsave(&port->lock, flags);
2446 if (port->flags & UPF_FOURPORT) {
2447 /* reset interrupts on the AST Fourport board */
2448 inb((port->iobase & 0xfe0) | 0x1f);
2449 port->mctrl |= TIOCM_OUT1;
2450 } else
2451 port->mctrl &= ~TIOCM_OUT2;
2452
2453 serial8250_set_mctrl(port, port->mctrl);
2454 spin_unlock_irqrestore(&port->lock, flags);
2455
2456 /*
2457 * Disable break condition and FIFOs
2458 */
2459 serial_port_out(port, UART_LCR,
2460 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2461 serial8250_clear_fifos(up);
2462
2463 #ifdef CONFIG_SERIAL_8250_RSA
2464 /*
2465 * Reset the RSA board back to 115kbps compat mode.
2466 */
2467 disable_rsa(up);
2468 #endif
2469
2470 /*
2471 * Read data port to reset things, and then unlink from
2472 * the IRQ chain.
2473 */
2474 serial_port_in(port, UART_RX);
2475 serial8250_rpm_put(up);
2476
2477 up->ops->release_irq(up);
2478 }
2479 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2480
2481 static void serial8250_shutdown(struct uart_port *port)
2482 {
2483 if (port->shutdown)
2484 port->shutdown(port);
2485 else
2486 serial8250_do_shutdown(port);
2487 }
2488
2489 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2490 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2491 unsigned int baud)
2492 {
2493 struct uart_port *port = &up->port;
2494
2495 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2496 }
2497
2498 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2499 unsigned int baud,
2500 unsigned int *frac)
2501 {
2502 struct uart_8250_port *up = up_to_u8250p(port);
2503 unsigned int quot;
2504
2505 /*
2506 * Handle magic divisors for baud rates above baud_base on
2507 * SMSC SuperIO chips.
2508 *
2509 */
2510 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2511 baud == (port->uartclk/4))
2512 quot = 0x8001;
2513 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2514 baud == (port->uartclk/8))
2515 quot = 0x8002;
2516 else if (up->port.type == PORT_NPCM)
2517 quot = npcm_get_divisor(up, baud);
2518 else
2519 quot = uart_get_divisor(port, baud);
2520
2521 /*
2522 * Oxford Semi 952 rev B workaround
2523 */
2524 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2525 quot++;
2526
2527 return quot;
2528 }
2529
2530 static unsigned int serial8250_get_divisor(struct uart_port *port,
2531 unsigned int baud,
2532 unsigned int *frac)
2533 {
2534 if (port->get_divisor)
2535 return port->get_divisor(port, baud, frac);
2536
2537 return serial8250_do_get_divisor(port, baud, frac);
2538 }
2539
2540 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2541 tcflag_t c_cflag)
2542 {
2543 unsigned char cval;
2544
2545 switch (c_cflag & CSIZE) {
2546 case CS5:
2547 cval = UART_LCR_WLEN5;
2548 break;
2549 case CS6:
2550 cval = UART_LCR_WLEN6;
2551 break;
2552 case CS7:
2553 cval = UART_LCR_WLEN7;
2554 break;
2555 default:
2556 case CS8:
2557 cval = UART_LCR_WLEN8;
2558 break;
2559 }
2560
2561 if (c_cflag & CSTOPB)
2562 cval |= UART_LCR_STOP;
2563 if (c_cflag & PARENB) {
2564 cval |= UART_LCR_PARITY;
2565 if (up->bugs & UART_BUG_PARITY)
2566 up->fifo_bug = true;
2567 }
2568 if (!(c_cflag & PARODD))
2569 cval |= UART_LCR_EPAR;
2570 #ifdef CMSPAR
2571 if (c_cflag & CMSPAR)
2572 cval |= UART_LCR_SPAR;
2573 #endif
2574
2575 return cval;
2576 }
2577
2578 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2579 unsigned int quot, unsigned int quot_frac)
2580 {
2581 struct uart_8250_port *up = up_to_u8250p(port);
2582
2583 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2584 if (is_omap1510_8250(up)) {
2585 if (baud == 115200) {
2586 quot = 1;
2587 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2588 } else
2589 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2590 }
2591
2592 /*
2593 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2594 * otherwise just set DLAB
2595 */
2596 if (up->capabilities & UART_NATSEMI)
2597 serial_port_out(port, UART_LCR, 0xe0);
2598 else
2599 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2600
2601 serial_dl_write(up, quot);
2602 }
2603 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2604
2605 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2606 unsigned int quot, unsigned int quot_frac)
2607 {
2608 if (port->set_divisor)
2609 port->set_divisor(port, baud, quot, quot_frac);
2610 else
2611 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2612 }
2613
2614 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2615 struct ktermios *termios,
2616 struct ktermios *old)
2617 {
2618 unsigned int tolerance = port->uartclk / 100;
2619
2620 /*
2621 * Ask the core to calculate the divisor for us.
2622 * Allow 1% tolerance at the upper limit so uart clks marginally
2623 * slower than nominal still match standard baud rates without
2624 * causing transmission errors.
2625 */
2626 return uart_get_baud_rate(port, termios, old,
2627 port->uartclk / 16 / UART_DIV_MAX,
2628 (port->uartclk + tolerance) / 16);
2629 }
2630
2631 void
2632 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2633 struct ktermios *old)
2634 {
2635 struct uart_8250_port *up = up_to_u8250p(port);
2636 unsigned char cval;
2637 unsigned long flags;
2638 unsigned int baud, quot, frac = 0;
2639
2640 if (up->capabilities & UART_CAP_MINI) {
2641 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2642 if ((termios->c_cflag & CSIZE) == CS5 ||
2643 (termios->c_cflag & CSIZE) == CS6)
2644 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2645 }
2646 cval = serial8250_compute_lcr(up, termios->c_cflag);
2647
2648 baud = serial8250_get_baud_rate(port, termios, old);
2649 quot = serial8250_get_divisor(port, baud, &frac);
2650
2651 /*
2652 * Ok, we're now changing the port state. Do it with
2653 * interrupts disabled.
2654 */
2655 serial8250_rpm_get(up);
2656 spin_lock_irqsave(&port->lock, flags);
2657
2658 up->lcr = cval; /* Save computed LCR */
2659
2660 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2661 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2662 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2663 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2664 up->fcr |= UART_FCR_TRIGGER_1;
2665 }
2666 }
2667
2668 /*
2669 * MCR-based auto flow control. When AFE is enabled, RTS will be
2670 * deasserted when the receive FIFO contains more characters than
2671 * the trigger, or the MCR RTS bit is cleared.
2672 */
2673 if (up->capabilities & UART_CAP_AFE) {
2674 up->mcr &= ~UART_MCR_AFE;
2675 if (termios->c_cflag & CRTSCTS)
2676 up->mcr |= UART_MCR_AFE;
2677 }
2678
2679 /*
2680 * Update the per-port timeout.
2681 */
2682 uart_update_timeout(port, termios->c_cflag, baud);
2683
2684 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2685 if (termios->c_iflag & INPCK)
2686 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2687 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2688 port->read_status_mask |= UART_LSR_BI;
2689
2690 /*
2691 * Characteres to ignore
2692 */
2693 port->ignore_status_mask = 0;
2694 if (termios->c_iflag & IGNPAR)
2695 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2696 if (termios->c_iflag & IGNBRK) {
2697 port->ignore_status_mask |= UART_LSR_BI;
2698 /*
2699 * If we're ignoring parity and break indicators,
2700 * ignore overruns too (for real raw support).
2701 */
2702 if (termios->c_iflag & IGNPAR)
2703 port->ignore_status_mask |= UART_LSR_OE;
2704 }
2705
2706 /*
2707 * ignore all characters if CREAD is not set
2708 */
2709 if ((termios->c_cflag & CREAD) == 0)
2710 port->ignore_status_mask |= UART_LSR_DR;
2711
2712 /*
2713 * CTS flow control flag and modem status interrupts
2714 */
2715 up->ier &= ~UART_IER_MSI;
2716 if (!(up->bugs & UART_BUG_NOMSR) &&
2717 UART_ENABLE_MS(&up->port, termios->c_cflag))
2718 up->ier |= UART_IER_MSI;
2719 if (up->capabilities & UART_CAP_UUE)
2720 up->ier |= UART_IER_UUE;
2721 if (up->capabilities & UART_CAP_RTOIE)
2722 up->ier |= UART_IER_RTOIE;
2723
2724 serial_port_out(port, UART_IER, up->ier);
2725
2726 if (up->capabilities & UART_CAP_EFR) {
2727 unsigned char efr = 0;
2728 /*
2729 * TI16C752/Startech hardware flow control. FIXME:
2730 * - TI16C752 requires control thresholds to be set.
2731 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2732 */
2733 if (termios->c_cflag & CRTSCTS)
2734 efr |= UART_EFR_CTS;
2735
2736 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2737 if (port->flags & UPF_EXAR_EFR)
2738 serial_port_out(port, UART_XR_EFR, efr);
2739 else
2740 serial_port_out(port, UART_EFR, efr);
2741 }
2742
2743 serial8250_set_divisor(port, baud, quot, frac);
2744
2745 /*
2746 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2747 * is written without DLAB set, this mode will be disabled.
2748 */
2749 if (port->type == PORT_16750)
2750 serial_port_out(port, UART_FCR, up->fcr);
2751
2752 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2753 if (port->type != PORT_16750) {
2754 /* emulated UARTs (Lucent Venus 167x) need two steps */
2755 if (up->fcr & UART_FCR_ENABLE_FIFO)
2756 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2757 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2758 }
2759 serial8250_set_mctrl(port, port->mctrl);
2760 spin_unlock_irqrestore(&port->lock, flags);
2761 serial8250_rpm_put(up);
2762
2763 /* Don't rewrite B0 */
2764 if (tty_termios_baud_rate(termios))
2765 tty_termios_encode_baud_rate(termios, baud, baud);
2766 }
2767 EXPORT_SYMBOL(serial8250_do_set_termios);
2768
2769 static void
2770 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2771 struct ktermios *old)
2772 {
2773 if (port->set_termios)
2774 port->set_termios(port, termios, old);
2775 else
2776 serial8250_do_set_termios(port, termios, old);
2777 }
2778
2779 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2780 {
2781 if (termios->c_line == N_PPS) {
2782 port->flags |= UPF_HARDPPS_CD;
2783 spin_lock_irq(&port->lock);
2784 serial8250_enable_ms(port);
2785 spin_unlock_irq(&port->lock);
2786 } else {
2787 port->flags &= ~UPF_HARDPPS_CD;
2788 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2789 spin_lock_irq(&port->lock);
2790 serial8250_disable_ms(port);
2791 spin_unlock_irq(&port->lock);
2792 }
2793 }
2794 }
2795 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2796
2797 static void
2798 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2799 {
2800 if (port->set_ldisc)
2801 port->set_ldisc(port, termios);
2802 else
2803 serial8250_do_set_ldisc(port, termios);
2804 }
2805
2806 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2807 unsigned int oldstate)
2808 {
2809 struct uart_8250_port *p = up_to_u8250p(port);
2810
2811 serial8250_set_sleep(p, state != 0);
2812 }
2813 EXPORT_SYMBOL(serial8250_do_pm);
2814
2815 static void
2816 serial8250_pm(struct uart_port *port, unsigned int state,
2817 unsigned int oldstate)
2818 {
2819 if (port->pm)
2820 port->pm(port, state, oldstate);
2821 else
2822 serial8250_do_pm(port, state, oldstate);
2823 }
2824
2825 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2826 {
2827 if (pt->port.mapsize)
2828 return pt->port.mapsize;
2829 if (pt->port.iotype == UPIO_AU) {
2830 if (pt->port.type == PORT_RT2880)
2831 return 0x100;
2832 return 0x1000;
2833 }
2834 if (is_omap1_8250(pt))
2835 return 0x16 << pt->port.regshift;
2836
2837 return 8 << pt->port.regshift;
2838 }
2839
2840 /*
2841 * Resource handling.
2842 */
2843 static int serial8250_request_std_resource(struct uart_8250_port *up)
2844 {
2845 unsigned int size = serial8250_port_size(up);
2846 struct uart_port *port = &up->port;
2847 int ret = 0;
2848
2849 switch (port->iotype) {
2850 case UPIO_AU:
2851 case UPIO_TSI:
2852 case UPIO_MEM32:
2853 case UPIO_MEM32BE:
2854 case UPIO_MEM16:
2855 case UPIO_MEM:
2856 if (!port->mapbase)
2857 break;
2858
2859 if (!request_mem_region(port->mapbase, size, "serial")) {
2860 ret = -EBUSY;
2861 break;
2862 }
2863
2864 if (port->flags & UPF_IOREMAP) {
2865 port->membase = ioremap(port->mapbase, size);
2866 if (!port->membase) {
2867 release_mem_region(port->mapbase, size);
2868 ret = -ENOMEM;
2869 }
2870 }
2871 break;
2872
2873 case UPIO_HUB6:
2874 case UPIO_PORT:
2875 if (!request_region(port->iobase, size, "serial"))
2876 ret = -EBUSY;
2877 break;
2878 }
2879 return ret;
2880 }
2881
2882 static void serial8250_release_std_resource(struct uart_8250_port *up)
2883 {
2884 unsigned int size = serial8250_port_size(up);
2885 struct uart_port *port = &up->port;
2886
2887 switch (port->iotype) {
2888 case UPIO_AU:
2889 case UPIO_TSI:
2890 case UPIO_MEM32:
2891 case UPIO_MEM32BE:
2892 case UPIO_MEM16:
2893 case UPIO_MEM:
2894 if (!port->mapbase)
2895 break;
2896
2897 if (port->flags & UPF_IOREMAP) {
2898 iounmap(port->membase);
2899 port->membase = NULL;
2900 }
2901
2902 release_mem_region(port->mapbase, size);
2903 break;
2904
2905 case UPIO_HUB6:
2906 case UPIO_PORT:
2907 release_region(port->iobase, size);
2908 break;
2909 }
2910 }
2911
2912 static void serial8250_release_port(struct uart_port *port)
2913 {
2914 struct uart_8250_port *up = up_to_u8250p(port);
2915
2916 serial8250_release_std_resource(up);
2917 }
2918
2919 static int serial8250_request_port(struct uart_port *port)
2920 {
2921 struct uart_8250_port *up = up_to_u8250p(port);
2922
2923 return serial8250_request_std_resource(up);
2924 }
2925
2926 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2927 {
2928 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2929 unsigned char bytes;
2930
2931 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2932
2933 return bytes ? bytes : -EOPNOTSUPP;
2934 }
2935
2936 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2937 {
2938 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2939 int i;
2940
2941 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2942 return -EOPNOTSUPP;
2943
2944 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2945 if (bytes < conf_type->rxtrig_bytes[i])
2946 /* Use the nearest lower value */
2947 return (--i) << UART_FCR_R_TRIG_SHIFT;
2948 }
2949
2950 return UART_FCR_R_TRIG_11;
2951 }
2952
2953 static int do_get_rxtrig(struct tty_port *port)
2954 {
2955 struct uart_state *state = container_of(port, struct uart_state, port);
2956 struct uart_port *uport = state->uart_port;
2957 struct uart_8250_port *up = up_to_u8250p(uport);
2958
2959 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2960 return -EINVAL;
2961
2962 return fcr_get_rxtrig_bytes(up);
2963 }
2964
2965 static int do_serial8250_get_rxtrig(struct tty_port *port)
2966 {
2967 int rxtrig_bytes;
2968
2969 mutex_lock(&port->mutex);
2970 rxtrig_bytes = do_get_rxtrig(port);
2971 mutex_unlock(&port->mutex);
2972
2973 return rxtrig_bytes;
2974 }
2975
2976 static ssize_t rx_trig_bytes_show(struct device *dev,
2977 struct device_attribute *attr, char *buf)
2978 {
2979 struct tty_port *port = dev_get_drvdata(dev);
2980 int rxtrig_bytes;
2981
2982 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2983 if (rxtrig_bytes < 0)
2984 return rxtrig_bytes;
2985
2986 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2987 }
2988
2989 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2990 {
2991 struct uart_state *state = container_of(port, struct uart_state, port);
2992 struct uart_port *uport = state->uart_port;
2993 struct uart_8250_port *up = up_to_u8250p(uport);
2994 int rxtrig;
2995
2996 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2997 up->fifo_bug)
2998 return -EINVAL;
2999
3000 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3001 if (rxtrig < 0)
3002 return rxtrig;
3003
3004 serial8250_clear_fifos(up);
3005 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3006 up->fcr |= (unsigned char)rxtrig;
3007 serial_out(up, UART_FCR, up->fcr);
3008 return 0;
3009 }
3010
3011 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3012 {
3013 int ret;
3014
3015 mutex_lock(&port->mutex);
3016 ret = do_set_rxtrig(port, bytes);
3017 mutex_unlock(&port->mutex);
3018
3019 return ret;
3020 }
3021
3022 static ssize_t rx_trig_bytes_store(struct device *dev,
3023 struct device_attribute *attr, const char *buf, size_t count)
3024 {
3025 struct tty_port *port = dev_get_drvdata(dev);
3026 unsigned char bytes;
3027 int ret;
3028
3029 if (!count)
3030 return -EINVAL;
3031
3032 ret = kstrtou8(buf, 10, &bytes);
3033 if (ret < 0)
3034 return ret;
3035
3036 ret = do_serial8250_set_rxtrig(port, bytes);
3037 if (ret < 0)
3038 return ret;
3039
3040 return count;
3041 }
3042
3043 static DEVICE_ATTR_RW(rx_trig_bytes);
3044
3045 static struct attribute *serial8250_dev_attrs[] = {
3046 &dev_attr_rx_trig_bytes.attr,
3047 NULL
3048 };
3049
3050 static struct attribute_group serial8250_dev_attr_group = {
3051 .attrs = serial8250_dev_attrs,
3052 };
3053
3054 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3055 {
3056 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3057
3058 if (conf_type->rxtrig_bytes[0])
3059 up->port.attr_group = &serial8250_dev_attr_group;
3060 }
3061
3062 static void serial8250_config_port(struct uart_port *port, int flags)
3063 {
3064 struct uart_8250_port *up = up_to_u8250p(port);
3065 int ret;
3066
3067 /*
3068 * Find the region that we can probe for. This in turn
3069 * tells us whether we can probe for the type of port.
3070 */
3071 ret = serial8250_request_std_resource(up);
3072 if (ret < 0)
3073 return;
3074
3075 if (port->iotype != up->cur_iotype)
3076 set_io_from_upio(port);
3077
3078 if (flags & UART_CONFIG_TYPE)
3079 autoconfig(up);
3080
3081 if (port->rs485.flags & SER_RS485_ENABLED)
3082 port->rs485_config(port, &port->rs485);
3083
3084 /* if access method is AU, it is a 16550 with a quirk */
3085 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3086 up->bugs |= UART_BUG_NOMSR;
3087
3088 /* HW bugs may trigger IRQ while IIR == NO_INT */
3089 if (port->type == PORT_TEGRA)
3090 up->bugs |= UART_BUG_NOMSR;
3091
3092 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3093 autoconfig_irq(up);
3094
3095 if (port->type == PORT_UNKNOWN)
3096 serial8250_release_std_resource(up);
3097
3098 register_dev_spec_attr_grp(up);
3099 up->fcr = uart_config[up->port.type].fcr;
3100 }
3101
3102 static int
3103 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3104 {
3105 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3106 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3107 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3108 ser->type == PORT_STARTECH)
3109 return -EINVAL;
3110 return 0;
3111 }
3112
3113 static const char *serial8250_type(struct uart_port *port)
3114 {
3115 int type = port->type;
3116
3117 if (type >= ARRAY_SIZE(uart_config))
3118 type = 0;
3119 return uart_config[type].name;
3120 }
3121
3122 static const struct uart_ops serial8250_pops = {
3123 .tx_empty = serial8250_tx_empty,
3124 .set_mctrl = serial8250_set_mctrl,
3125 .get_mctrl = serial8250_get_mctrl,
3126 .stop_tx = serial8250_stop_tx,
3127 .start_tx = serial8250_start_tx,
3128 .throttle = serial8250_throttle,
3129 .unthrottle = serial8250_unthrottle,
3130 .stop_rx = serial8250_stop_rx,
3131 .enable_ms = serial8250_enable_ms,
3132 .break_ctl = serial8250_break_ctl,
3133 .startup = serial8250_startup,
3134 .shutdown = serial8250_shutdown,
3135 .set_termios = serial8250_set_termios,
3136 .set_ldisc = serial8250_set_ldisc,
3137 .pm = serial8250_pm,
3138 .type = serial8250_type,
3139 .release_port = serial8250_release_port,
3140 .request_port = serial8250_request_port,
3141 .config_port = serial8250_config_port,
3142 .verify_port = serial8250_verify_port,
3143 #ifdef CONFIG_CONSOLE_POLL
3144 .poll_get_char = serial8250_get_poll_char,
3145 .poll_put_char = serial8250_put_poll_char,
3146 #endif
3147 };
3148
3149 void serial8250_init_port(struct uart_8250_port *up)
3150 {
3151 struct uart_port *port = &up->port;
3152
3153 spin_lock_init(&port->lock);
3154 port->ops = &serial8250_pops;
3155 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3156
3157 up->cur_iotype = 0xFF;
3158 }
3159 EXPORT_SYMBOL_GPL(serial8250_init_port);
3160
3161 void serial8250_set_defaults(struct uart_8250_port *up)
3162 {
3163 struct uart_port *port = &up->port;
3164
3165 if (up->port.flags & UPF_FIXED_TYPE) {
3166 unsigned int type = up->port.type;
3167
3168 if (!up->port.fifosize)
3169 up->port.fifosize = uart_config[type].fifo_size;
3170 if (!up->tx_loadsz)
3171 up->tx_loadsz = uart_config[type].tx_loadsz;
3172 if (!up->capabilities)
3173 up->capabilities = uart_config[type].flags;
3174 }
3175
3176 set_io_from_upio(port);
3177
3178 /* default dma handlers */
3179 if (up->dma) {
3180 if (!up->dma->tx_dma)
3181 up->dma->tx_dma = serial8250_tx_dma;
3182 if (!up->dma->rx_dma)
3183 up->dma->rx_dma = serial8250_rx_dma;
3184 }
3185 }
3186 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3187
3188 #ifdef CONFIG_SERIAL_8250_CONSOLE
3189
3190 static void serial8250_console_putchar(struct uart_port *port, int ch)
3191 {
3192 struct uart_8250_port *up = up_to_u8250p(port);
3193
3194 wait_for_xmitr(up, UART_LSR_THRE);
3195 serial_port_out(port, UART_TX, ch);
3196 }
3197
3198 /*
3199 * Restore serial console when h/w power-off detected
3200 */
3201 static void serial8250_console_restore(struct uart_8250_port *up)
3202 {
3203 struct uart_port *port = &up->port;
3204 struct ktermios termios;
3205 unsigned int baud, quot, frac = 0;
3206
3207 termios.c_cflag = port->cons->cflag;
3208 if (port->state->port.tty && termios.c_cflag == 0)
3209 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3210
3211 baud = serial8250_get_baud_rate(port, &termios, NULL);
3212 quot = serial8250_get_divisor(port, baud, &frac);
3213
3214 serial8250_set_divisor(port, baud, quot, frac);
3215 serial_port_out(port, UART_LCR, up->lcr);
3216 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3217 }
3218
3219 /*
3220 * Print a string to the serial port trying not to disturb
3221 * any possible real use of the port...
3222 *
3223 * The console_lock must be held when we get here.
3224 *
3225 * Doing runtime PM is really a bad idea for the kernel console.
3226 * Thus, we assume the function is called when device is powered up.
3227 */
3228 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3229 unsigned int count)
3230 {
3231 struct uart_8250_em485 *em485 = up->em485;
3232 struct uart_port *port = &up->port;
3233 unsigned long flags;
3234 unsigned int ier;
3235 int locked = 1;
3236
3237 touch_nmi_watchdog();
3238
3239 if (oops_in_progress)
3240 locked = spin_trylock_irqsave(&port->lock, flags);
3241 else
3242 spin_lock_irqsave(&port->lock, flags);
3243
3244 /*
3245 * First save the IER then disable the interrupts
3246 */
3247 ier = serial_port_in(port, UART_IER);
3248
3249 if (up->capabilities & UART_CAP_UUE)
3250 serial_port_out(port, UART_IER, UART_IER_UUE);
3251 else
3252 serial_port_out(port, UART_IER, 0);
3253
3254 /* check scratch reg to see if port powered off during system sleep */
3255 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3256 serial8250_console_restore(up);
3257 up->canary = 0;
3258 }
3259
3260 if (em485) {
3261 if (em485->tx_stopped)
3262 up->rs485_start_tx(up);
3263 mdelay(port->rs485.delay_rts_before_send);
3264 }
3265
3266 uart_console_write(port, s, count, serial8250_console_putchar);
3267
3268 /*
3269 * Finally, wait for transmitter to become empty
3270 * and restore the IER
3271 */
3272 wait_for_xmitr(up, BOTH_EMPTY);
3273
3274 if (em485) {
3275 mdelay(port->rs485.delay_rts_after_send);
3276 if (em485->tx_stopped)
3277 up->rs485_stop_tx(up);
3278 }
3279
3280 serial_port_out(port, UART_IER, ier);
3281
3282 /*
3283 * The receive handling will happen properly because the
3284 * receive ready bit will still be set; it is not cleared
3285 * on read. However, modem control will not, we must
3286 * call it if we have saved something in the saved flags
3287 * while processing with interrupts off.
3288 */
3289 if (up->msr_saved_flags)
3290 serial8250_modem_status(up);
3291
3292 if (locked)
3293 spin_unlock_irqrestore(&port->lock, flags);
3294 }
3295
3296 static unsigned int probe_baud(struct uart_port *port)
3297 {
3298 unsigned char lcr, dll, dlm;
3299 unsigned int quot;
3300
3301 lcr = serial_port_in(port, UART_LCR);
3302 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3303 dll = serial_port_in(port, UART_DLL);
3304 dlm = serial_port_in(port, UART_DLM);
3305 serial_port_out(port, UART_LCR, lcr);
3306
3307 quot = (dlm << 8) | dll;
3308 return (port->uartclk / 16) / quot;
3309 }
3310
3311 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3312 {
3313 int baud = 9600;
3314 int bits = 8;
3315 int parity = 'n';
3316 int flow = 'n';
3317 int ret;
3318
3319 if (!port->iobase && !port->membase)
3320 return -ENODEV;
3321
3322 if (options)
3323 uart_parse_options(options, &baud, &parity, &bits, &flow);
3324 else if (probe)
3325 baud = probe_baud(port);
3326
3327 ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3328 if (ret)
3329 return ret;
3330
3331 if (port->dev)
3332 pm_runtime_get_sync(port->dev);
3333
3334 return 0;
3335 }
3336
3337 int serial8250_console_exit(struct uart_port *port)
3338 {
3339 if (port->dev)
3340 pm_runtime_put_sync(port->dev);
3341
3342 return 0;
3343 }
3344
3345 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3346
3347 MODULE_LICENSE("GPL");
Linux with added FPC-III support