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Revert "tty: hvc: Fix data abort due to race in hvc_open"
[linux/fpc-iii.git] / drivers / tty / serial / amba-pl011.c
blob458fc3d9d48c2623a019cafda70c14ddbd71c8cd
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for AMBA serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 * Copyright (C) 2010 ST-Ericsson SA
10 *
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
13 * Note that although they do have CTS, DCD and DSR inputs, they do
14 * not have an RI input, nor do they have DTR or RTS outputs. If
15 * required, these have to be supplied via some other means (eg, GPIO)
16 * and hooked into this driver.
17 */
18
19 #include <linux/module.h>
20 #include <linux/ioport.h>
21 #include <linux/init.h>
22 #include <linux/console.h>
23 #include <linux/sysrq.h>
24 #include <linux/device.h>
25 #include <linux/tty.h>
26 #include <linux/tty_flip.h>
27 #include <linux/serial_core.h>
28 #include <linux/serial.h>
29 #include <linux/amba/bus.h>
30 #include <linux/amba/serial.h>
31 #include <linux/clk.h>
32 #include <linux/slab.h>
33 #include <linux/dmaengine.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/scatterlist.h>
36 #include <linux/delay.h>
37 #include <linux/types.h>
38 #include <linux/of.h>
39 #include <linux/of_device.h>
40 #include <linux/pinctrl/consumer.h>
41 #include <linux/sizes.h>
42 #include <linux/io.h>
43 #include <linux/acpi.h>
44
45 #include "amba-pl011.h"
46
47 #define UART_NR 14
48
49 #define SERIAL_AMBA_MAJOR 204
50 #define SERIAL_AMBA_MINOR 64
51 #define SERIAL_AMBA_NR UART_NR
52
53 #define AMBA_ISR_PASS_LIMIT 256
54
55 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
56 #define UART_DUMMY_DR_RX (1 << 16)
57
58 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
59 [REG_DR] = UART01x_DR,
60 [REG_FR] = UART01x_FR,
61 [REG_LCRH_RX] = UART011_LCRH,
62 [REG_LCRH_TX] = UART011_LCRH,
63 [REG_IBRD] = UART011_IBRD,
64 [REG_FBRD] = UART011_FBRD,
65 [REG_CR] = UART011_CR,
66 [REG_IFLS] = UART011_IFLS,
67 [REG_IMSC] = UART011_IMSC,
68 [REG_RIS] = UART011_RIS,
69 [REG_MIS] = UART011_MIS,
70 [REG_ICR] = UART011_ICR,
71 [REG_DMACR] = UART011_DMACR,
72 };
73
74 /* There is by now at least one vendor with differing details, so handle it */
75 struct vendor_data {
76 const u16 *reg_offset;
77 unsigned int ifls;
78 unsigned int fr_busy;
79 unsigned int fr_dsr;
80 unsigned int fr_cts;
81 unsigned int fr_ri;
82 unsigned int inv_fr;
83 bool access_32b;
84 bool oversampling;
85 bool dma_threshold;
86 bool cts_event_workaround;
87 bool always_enabled;
88 bool fixed_options;
89
90 unsigned int (*get_fifosize)(struct amba_device *dev);
91 };
92
93 static unsigned int get_fifosize_arm(struct amba_device *dev)
94 {
95 return amba_rev(dev) < 3 ? 16 : 32;
96 }
97
98 static struct vendor_data vendor_arm = {
99 .reg_offset = pl011_std_offsets,
100 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
101 .fr_busy = UART01x_FR_BUSY,
102 .fr_dsr = UART01x_FR_DSR,
103 .fr_cts = UART01x_FR_CTS,
104 .fr_ri = UART011_FR_RI,
105 .oversampling = false,
106 .dma_threshold = false,
107 .cts_event_workaround = false,
108 .always_enabled = false,
109 .fixed_options = false,
110 .get_fifosize = get_fifosize_arm,
111 };
112
113 static const struct vendor_data vendor_sbsa = {
114 .reg_offset = pl011_std_offsets,
115 .fr_busy = UART01x_FR_BUSY,
116 .fr_dsr = UART01x_FR_DSR,
117 .fr_cts = UART01x_FR_CTS,
118 .fr_ri = UART011_FR_RI,
119 .access_32b = true,
120 .oversampling = false,
121 .dma_threshold = false,
122 .cts_event_workaround = false,
123 .always_enabled = true,
124 .fixed_options = true,
125 };
126
127 #ifdef CONFIG_ACPI_SPCR_TABLE
128 static const struct vendor_data vendor_qdt_qdf2400_e44 = {
129 .reg_offset = pl011_std_offsets,
130 .fr_busy = UART011_FR_TXFE,
131 .fr_dsr = UART01x_FR_DSR,
132 .fr_cts = UART01x_FR_CTS,
133 .fr_ri = UART011_FR_RI,
134 .inv_fr = UART011_FR_TXFE,
135 .access_32b = true,
136 .oversampling = false,
137 .dma_threshold = false,
138 .cts_event_workaround = false,
139 .always_enabled = true,
140 .fixed_options = true,
141 };
142 #endif
143
144 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
145 [REG_DR] = UART01x_DR,
146 [REG_ST_DMAWM] = ST_UART011_DMAWM,
147 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
148 [REG_FR] = UART01x_FR,
149 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
150 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
151 [REG_IBRD] = UART011_IBRD,
152 [REG_FBRD] = UART011_FBRD,
153 [REG_CR] = UART011_CR,
154 [REG_IFLS] = UART011_IFLS,
155 [REG_IMSC] = UART011_IMSC,
156 [REG_RIS] = UART011_RIS,
157 [REG_MIS] = UART011_MIS,
158 [REG_ICR] = UART011_ICR,
159 [REG_DMACR] = UART011_DMACR,
160 [REG_ST_XFCR] = ST_UART011_XFCR,
161 [REG_ST_XON1] = ST_UART011_XON1,
162 [REG_ST_XON2] = ST_UART011_XON2,
163 [REG_ST_XOFF1] = ST_UART011_XOFF1,
164 [REG_ST_XOFF2] = ST_UART011_XOFF2,
165 [REG_ST_ITCR] = ST_UART011_ITCR,
166 [REG_ST_ITIP] = ST_UART011_ITIP,
167 [REG_ST_ABCR] = ST_UART011_ABCR,
168 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
169 };
170
171 static unsigned int get_fifosize_st(struct amba_device *dev)
172 {
173 return 64;
174 }
175
176 static struct vendor_data vendor_st = {
177 .reg_offset = pl011_st_offsets,
178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
179 .fr_busy = UART01x_FR_BUSY,
180 .fr_dsr = UART01x_FR_DSR,
181 .fr_cts = UART01x_FR_CTS,
182 .fr_ri = UART011_FR_RI,
183 .oversampling = true,
184 .dma_threshold = true,
185 .cts_event_workaround = true,
186 .always_enabled = false,
187 .fixed_options = false,
188 .get_fifosize = get_fifosize_st,
189 };
190
191 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
192 [REG_DR] = ZX_UART011_DR,
193 [REG_FR] = ZX_UART011_FR,
194 [REG_LCRH_RX] = ZX_UART011_LCRH,
195 [REG_LCRH_TX] = ZX_UART011_LCRH,
196 [REG_IBRD] = ZX_UART011_IBRD,
197 [REG_FBRD] = ZX_UART011_FBRD,
198 [REG_CR] = ZX_UART011_CR,
199 [REG_IFLS] = ZX_UART011_IFLS,
200 [REG_IMSC] = ZX_UART011_IMSC,
201 [REG_RIS] = ZX_UART011_RIS,
202 [REG_MIS] = ZX_UART011_MIS,
203 [REG_ICR] = ZX_UART011_ICR,
204 [REG_DMACR] = ZX_UART011_DMACR,
205 };
206
207 static unsigned int get_fifosize_zte(struct amba_device *dev)
208 {
209 return 16;
210 }
211
212 static struct vendor_data vendor_zte = {
213 .reg_offset = pl011_zte_offsets,
214 .access_32b = true,
215 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
216 .fr_busy = ZX_UART01x_FR_BUSY,
217 .fr_dsr = ZX_UART01x_FR_DSR,
218 .fr_cts = ZX_UART01x_FR_CTS,
219 .fr_ri = ZX_UART011_FR_RI,
220 .get_fifosize = get_fifosize_zte,
221 };
222
223 /* Deals with DMA transactions */
224
225 struct pl011_sgbuf {
226 struct scatterlist sg;
227 char *buf;
228 };
229
230 struct pl011_dmarx_data {
231 struct dma_chan *chan;
232 struct completion complete;
233 bool use_buf_b;
234 struct pl011_sgbuf sgbuf_a;
235 struct pl011_sgbuf sgbuf_b;
236 dma_cookie_t cookie;
237 bool running;
238 struct timer_list timer;
239 unsigned int last_residue;
240 unsigned long last_jiffies;
241 bool auto_poll_rate;
242 unsigned int poll_rate;
243 unsigned int poll_timeout;
244 };
245
246 struct pl011_dmatx_data {
247 struct dma_chan *chan;
248 struct scatterlist sg;
249 char *buf;
250 bool queued;
251 };
252
253 /*
254 * We wrap our port structure around the generic uart_port.
255 */
256 struct uart_amba_port {
257 struct uart_port port;
258 const u16 *reg_offset;
259 struct clk *clk;
260 const struct vendor_data *vendor;
261 unsigned int dmacr; /* dma control reg */
262 unsigned int im; /* interrupt mask */
263 unsigned int old_status;
264 unsigned int fifosize; /* vendor-specific */
265 unsigned int old_cr; /* state during shutdown */
266 unsigned int fixed_baud; /* vendor-set fixed baud rate */
267 char type[12];
268 #ifdef CONFIG_DMA_ENGINE
269 /* DMA stuff */
270 bool using_tx_dma;
271 bool using_rx_dma;
272 struct pl011_dmarx_data dmarx;
273 struct pl011_dmatx_data dmatx;
274 bool dma_probed;
275 #endif
276 };
277
278 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
279 unsigned int reg)
280 {
281 return uap->reg_offset[reg];
282 }
283
284 static unsigned int pl011_read(const struct uart_amba_port *uap,
285 unsigned int reg)
286 {
287 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
288
289 return (uap->port.iotype == UPIO_MEM32) ?
290 readl_relaxed(addr) : readw_relaxed(addr);
291 }
292
293 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
294 unsigned int reg)
295 {
296 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
297
298 if (uap->port.iotype == UPIO_MEM32)
299 writel_relaxed(val, addr);
300 else
301 writew_relaxed(val, addr);
302 }
303
304 /*
305 * Reads up to 256 characters from the FIFO or until it's empty and
306 * inserts them into the TTY layer. Returns the number of characters
307 * read from the FIFO.
308 */
309 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
310 {
311 u16 status;
312 unsigned int ch, flag, fifotaken;
313
314 for (fifotaken = 0; fifotaken != 256; fifotaken++) {
315 status = pl011_read(uap, REG_FR);
316 if (status & UART01x_FR_RXFE)
317 break;
318
319 /* Take chars from the FIFO and update status */
320 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
321 flag = TTY_NORMAL;
322 uap->port.icount.rx++;
323
324 if (unlikely(ch & UART_DR_ERROR)) {
325 if (ch & UART011_DR_BE) {
326 ch &= ~(UART011_DR_FE | UART011_DR_PE);
327 uap->port.icount.brk++;
328 if (uart_handle_break(&uap->port))
329 continue;
330 } else if (ch & UART011_DR_PE)
331 uap->port.icount.parity++;
332 else if (ch & UART011_DR_FE)
333 uap->port.icount.frame++;
334 if (ch & UART011_DR_OE)
335 uap->port.icount.overrun++;
336
337 ch &= uap->port.read_status_mask;
338
339 if (ch & UART011_DR_BE)
340 flag = TTY_BREAK;
341 else if (ch & UART011_DR_PE)
342 flag = TTY_PARITY;
343 else if (ch & UART011_DR_FE)
344 flag = TTY_FRAME;
345 }
346
347 if (uart_handle_sysrq_char(&uap->port, ch & 255))
348 continue;
349
350 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
351 }
352
353 return fifotaken;
354 }
355
356
357 /*
358 * All the DMA operation mode stuff goes inside this ifdef.
359 * This assumes that you have a generic DMA device interface,
360 * no custom DMA interfaces are supported.
361 */
362 #ifdef CONFIG_DMA_ENGINE
363
364 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
365
366 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
367 enum dma_data_direction dir)
368 {
369 dma_addr_t dma_addr;
370
371 sg->buf = dma_alloc_coherent(chan->device->dev,
372 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
373 if (!sg->buf)
374 return -ENOMEM;
375
376 sg_init_table(&sg->sg, 1);
377 sg_set_page(&sg->sg, phys_to_page(dma_addr),
378 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
379 sg_dma_address(&sg->sg) = dma_addr;
380 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
381
382 return 0;
383 }
384
385 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
386 enum dma_data_direction dir)
387 {
388 if (sg->buf) {
389 dma_free_coherent(chan->device->dev,
390 PL011_DMA_BUFFER_SIZE, sg->buf,
391 sg_dma_address(&sg->sg));
392 }
393 }
394
395 static void pl011_dma_probe(struct uart_amba_port *uap)
396 {
397 /* DMA is the sole user of the platform data right now */
398 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
399 struct device *dev = uap->port.dev;
400 struct dma_slave_config tx_conf = {
401 .dst_addr = uap->port.mapbase +
402 pl011_reg_to_offset(uap, REG_DR),
403 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
404 .direction = DMA_MEM_TO_DEV,
405 .dst_maxburst = uap->fifosize >> 1,
406 .device_fc = false,
407 };
408 struct dma_chan *chan;
409 dma_cap_mask_t mask;
410
411 uap->dma_probed = true;
412 chan = dma_request_chan(dev, "tx");
413 if (IS_ERR(chan)) {
414 if (PTR_ERR(chan) == -EPROBE_DEFER) {
415 uap->dma_probed = false;
416 return;
417 }
418
419 /* We need platform data */
420 if (!plat || !plat->dma_filter) {
421 dev_info(uap->port.dev, "no DMA platform data\n");
422 return;
423 }
424
425 /* Try to acquire a generic DMA engine slave TX channel */
426 dma_cap_zero(mask);
427 dma_cap_set(DMA_SLAVE, mask);
428
429 chan = dma_request_channel(mask, plat->dma_filter,
430 plat->dma_tx_param);
431 if (!chan) {
432 dev_err(uap->port.dev, "no TX DMA channel!\n");
433 return;
434 }
435 }
436
437 dmaengine_slave_config(chan, &tx_conf);
438 uap->dmatx.chan = chan;
439
440 dev_info(uap->port.dev, "DMA channel TX %s\n",
441 dma_chan_name(uap->dmatx.chan));
442
443 /* Optionally make use of an RX channel as well */
444 chan = dma_request_slave_channel(dev, "rx");
445
446 if (!chan && plat && plat->dma_rx_param) {
447 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
448
449 if (!chan) {
450 dev_err(uap->port.dev, "no RX DMA channel!\n");
451 return;
452 }
453 }
454
455 if (chan) {
456 struct dma_slave_config rx_conf = {
457 .src_addr = uap->port.mapbase +
458 pl011_reg_to_offset(uap, REG_DR),
459 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
460 .direction = DMA_DEV_TO_MEM,
461 .src_maxburst = uap->fifosize >> 2,
462 .device_fc = false,
463 };
464 struct dma_slave_caps caps;
465
466 /*
467 * Some DMA controllers provide information on their capabilities.
468 * If the controller does, check for suitable residue processing
469 * otherwise assime all is well.
470 */
471 if (0 == dma_get_slave_caps(chan, &caps)) {
472 if (caps.residue_granularity ==
473 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
474 dma_release_channel(chan);
475 dev_info(uap->port.dev,
476 "RX DMA disabled - no residue processing\n");
477 return;
478 }
479 }
480 dmaengine_slave_config(chan, &rx_conf);
481 uap->dmarx.chan = chan;
482
483 uap->dmarx.auto_poll_rate = false;
484 if (plat && plat->dma_rx_poll_enable) {
485 /* Set poll rate if specified. */
486 if (plat->dma_rx_poll_rate) {
487 uap->dmarx.auto_poll_rate = false;
488 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
489 } else {
490 /*
491 * 100 ms defaults to poll rate if not
492 * specified. This will be adjusted with
493 * the baud rate at set_termios.
494 */
495 uap->dmarx.auto_poll_rate = true;
496 uap->dmarx.poll_rate = 100;
497 }
498 /* 3 secs defaults poll_timeout if not specified. */
499 if (plat->dma_rx_poll_timeout)
500 uap->dmarx.poll_timeout =
501 plat->dma_rx_poll_timeout;
502 else
503 uap->dmarx.poll_timeout = 3000;
504 } else if (!plat && dev->of_node) {
505 uap->dmarx.auto_poll_rate = of_property_read_bool(
506 dev->of_node, "auto-poll");
507 if (uap->dmarx.auto_poll_rate) {
508 u32 x;
509
510 if (0 == of_property_read_u32(dev->of_node,
511 "poll-rate-ms", &x))
512 uap->dmarx.poll_rate = x;
513 else
514 uap->dmarx.poll_rate = 100;
515 if (0 == of_property_read_u32(dev->of_node,
516 "poll-timeout-ms", &x))
517 uap->dmarx.poll_timeout = x;
518 else
519 uap->dmarx.poll_timeout = 3000;
520 }
521 }
522 dev_info(uap->port.dev, "DMA channel RX %s\n",
523 dma_chan_name(uap->dmarx.chan));
524 }
525 }
526
527 static void pl011_dma_remove(struct uart_amba_port *uap)
528 {
529 if (uap->dmatx.chan)
530 dma_release_channel(uap->dmatx.chan);
531 if (uap->dmarx.chan)
532 dma_release_channel(uap->dmarx.chan);
533 }
534
535 /* Forward declare these for the refill routine */
536 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
537 static void pl011_start_tx_pio(struct uart_amba_port *uap);
538
539 /*
540 * The current DMA TX buffer has been sent.
541 * Try to queue up another DMA buffer.
542 */
543 static void pl011_dma_tx_callback(void *data)
544 {
545 struct uart_amba_port *uap = data;
546 struct pl011_dmatx_data *dmatx = &uap->dmatx;
547 unsigned long flags;
548 u16 dmacr;
549
550 spin_lock_irqsave(&uap->port.lock, flags);
551 if (uap->dmatx.queued)
552 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
553 DMA_TO_DEVICE);
554
555 dmacr = uap->dmacr;
556 uap->dmacr = dmacr & ~UART011_TXDMAE;
557 pl011_write(uap->dmacr, uap, REG_DMACR);
558
559 /*
560 * If TX DMA was disabled, it means that we've stopped the DMA for
561 * some reason (eg, XOFF received, or we want to send an X-char.)
562 *
563 * Note: we need to be careful here of a potential race between DMA
564 * and the rest of the driver - if the driver disables TX DMA while
565 * a TX buffer completing, we must update the tx queued status to
566 * get further refills (hence we check dmacr).
567 */
568 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
569 uart_circ_empty(&uap->port.state->xmit)) {
570 uap->dmatx.queued = false;
571 spin_unlock_irqrestore(&uap->port.lock, flags);
572 return;
573 }
574
575 if (pl011_dma_tx_refill(uap) <= 0)
576 /*
577 * We didn't queue a DMA buffer for some reason, but we
578 * have data pending to be sent. Re-enable the TX IRQ.
579 */
580 pl011_start_tx_pio(uap);
581
582 spin_unlock_irqrestore(&uap->port.lock, flags);
583 }
584
585 /*
586 * Try to refill the TX DMA buffer.
587 * Locking: called with port lock held and IRQs disabled.
588 * Returns:
589 * 1 if we queued up a TX DMA buffer.
590 * 0 if we didn't want to handle this by DMA
591 * <0 on error
592 */
593 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
594 {
595 struct pl011_dmatx_data *dmatx = &uap->dmatx;
596 struct dma_chan *chan = dmatx->chan;
597 struct dma_device *dma_dev = chan->device;
598 struct dma_async_tx_descriptor *desc;
599 struct circ_buf *xmit = &uap->port.state->xmit;
600 unsigned int count;
601
602 /*
603 * Try to avoid the overhead involved in using DMA if the
604 * transaction fits in the first half of the FIFO, by using
605 * the standard interrupt handling. This ensures that we
606 * issue a uart_write_wakeup() at the appropriate time.
607 */
608 count = uart_circ_chars_pending(xmit);
609 if (count < (uap->fifosize >> 1)) {
610 uap->dmatx.queued = false;
611 return 0;
612 }
613
614 /*
615 * Bodge: don't send the last character by DMA, as this
616 * will prevent XON from notifying us to restart DMA.
617 */
618 count -= 1;
619
620 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
621 if (count > PL011_DMA_BUFFER_SIZE)
622 count = PL011_DMA_BUFFER_SIZE;
623
624 if (xmit->tail < xmit->head)
625 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
626 else {
627 size_t first = UART_XMIT_SIZE - xmit->tail;
628 size_t second;
629
630 if (first > count)
631 first = count;
632 second = count - first;
633
634 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
635 if (second)
636 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
637 }
638
639 dmatx->sg.length = count;
640
641 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
642 uap->dmatx.queued = false;
643 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
644 return -EBUSY;
645 }
646
647 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
648 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
649 if (!desc) {
650 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
651 uap->dmatx.queued = false;
652 /*
653 * If DMA cannot be used right now, we complete this
654 * transaction via IRQ and let the TTY layer retry.
655 */
656 dev_dbg(uap->port.dev, "TX DMA busy\n");
657 return -EBUSY;
658 }
659
660 /* Some data to go along to the callback */
661 desc->callback = pl011_dma_tx_callback;
662 desc->callback_param = uap;
663
664 /* All errors should happen at prepare time */
665 dmaengine_submit(desc);
666
667 /* Fire the DMA transaction */
668 dma_dev->device_issue_pending(chan);
669
670 uap->dmacr |= UART011_TXDMAE;
671 pl011_write(uap->dmacr, uap, REG_DMACR);
672 uap->dmatx.queued = true;
673
674 /*
675 * Now we know that DMA will fire, so advance the ring buffer
676 * with the stuff we just dispatched.
677 */
678 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
679 uap->port.icount.tx += count;
680
681 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
682 uart_write_wakeup(&uap->port);
683
684 return 1;
685 }
686
687 /*
688 * We received a transmit interrupt without a pending X-char but with
689 * pending characters.
690 * Locking: called with port lock held and IRQs disabled.
691 * Returns:
692 * false if we want to use PIO to transmit
693 * true if we queued a DMA buffer
694 */
695 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
696 {
697 if (!uap->using_tx_dma)
698 return false;
699
700 /*
701 * If we already have a TX buffer queued, but received a
702 * TX interrupt, it will be because we've just sent an X-char.
703 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
704 */
705 if (uap->dmatx.queued) {
706 uap->dmacr |= UART011_TXDMAE;
707 pl011_write(uap->dmacr, uap, REG_DMACR);
708 uap->im &= ~UART011_TXIM;
709 pl011_write(uap->im, uap, REG_IMSC);
710 return true;
711 }
712
713 /*
714 * We don't have a TX buffer queued, so try to queue one.
715 * If we successfully queued a buffer, mask the TX IRQ.
716 */
717 if (pl011_dma_tx_refill(uap) > 0) {
718 uap->im &= ~UART011_TXIM;
719 pl011_write(uap->im, uap, REG_IMSC);
720 return true;
721 }
722 return false;
723 }
724
725 /*
726 * Stop the DMA transmit (eg, due to received XOFF).
727 * Locking: called with port lock held and IRQs disabled.
728 */
729 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
730 {
731 if (uap->dmatx.queued) {
732 uap->dmacr &= ~UART011_TXDMAE;
733 pl011_write(uap->dmacr, uap, REG_DMACR);
734 }
735 }
736
737 /*
738 * Try to start a DMA transmit, or in the case of an XON/OFF
739 * character queued for send, try to get that character out ASAP.
740 * Locking: called with port lock held and IRQs disabled.
741 * Returns:
742 * false if we want the TX IRQ to be enabled
743 * true if we have a buffer queued
744 */
745 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
746 {
747 u16 dmacr;
748
749 if (!uap->using_tx_dma)
750 return false;
751
752 if (!uap->port.x_char) {
753 /* no X-char, try to push chars out in DMA mode */
754 bool ret = true;
755
756 if (!uap->dmatx.queued) {
757 if (pl011_dma_tx_refill(uap) > 0) {
758 uap->im &= ~UART011_TXIM;
759 pl011_write(uap->im, uap, REG_IMSC);
760 } else
761 ret = false;
762 } else if (!(uap->dmacr & UART011_TXDMAE)) {
763 uap->dmacr |= UART011_TXDMAE;
764 pl011_write(uap->dmacr, uap, REG_DMACR);
765 }
766 return ret;
767 }
768
769 /*
770 * We have an X-char to send. Disable DMA to prevent it loading
771 * the TX fifo, and then see if we can stuff it into the FIFO.
772 */
773 dmacr = uap->dmacr;
774 uap->dmacr &= ~UART011_TXDMAE;
775 pl011_write(uap->dmacr, uap, REG_DMACR);
776
777 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
778 /*
779 * No space in the FIFO, so enable the transmit interrupt
780 * so we know when there is space. Note that once we've
781 * loaded the character, we should just re-enable DMA.
782 */
783 return false;
784 }
785
786 pl011_write(uap->port.x_char, uap, REG_DR);
787 uap->port.icount.tx++;
788 uap->port.x_char = 0;
789
790 /* Success - restore the DMA state */
791 uap->dmacr = dmacr;
792 pl011_write(dmacr, uap, REG_DMACR);
793
794 return true;
795 }
796
797 /*
798 * Flush the transmit buffer.
799 * Locking: called with port lock held and IRQs disabled.
800 */
801 static void pl011_dma_flush_buffer(struct uart_port *port)
802 __releases(&uap->port.lock)
803 __acquires(&uap->port.lock)
804 {
805 struct uart_amba_port *uap =
806 container_of(port, struct uart_amba_port, port);
807
808 if (!uap->using_tx_dma)
809 return;
810
811 dmaengine_terminate_async(uap->dmatx.chan);
812
813 if (uap->dmatx.queued) {
814 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
815 DMA_TO_DEVICE);
816 uap->dmatx.queued = false;
817 uap->dmacr &= ~UART011_TXDMAE;
818 pl011_write(uap->dmacr, uap, REG_DMACR);
819 }
820 }
821
822 static void pl011_dma_rx_callback(void *data);
823
824 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
825 {
826 struct dma_chan *rxchan = uap->dmarx.chan;
827 struct pl011_dmarx_data *dmarx = &uap->dmarx;
828 struct dma_async_tx_descriptor *desc;
829 struct pl011_sgbuf *sgbuf;
830
831 if (!rxchan)
832 return -EIO;
833
834 /* Start the RX DMA job */
835 sgbuf = uap->dmarx.use_buf_b ?
836 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
837 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
838 DMA_DEV_TO_MEM,
839 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
840 /*
841 * If the DMA engine is busy and cannot prepare a
842 * channel, no big deal, the driver will fall back
843 * to interrupt mode as a result of this error code.
844 */
845 if (!desc) {
846 uap->dmarx.running = false;
847 dmaengine_terminate_all(rxchan);
848 return -EBUSY;
849 }
850
851 /* Some data to go along to the callback */
852 desc->callback = pl011_dma_rx_callback;
853 desc->callback_param = uap;
854 dmarx->cookie = dmaengine_submit(desc);
855 dma_async_issue_pending(rxchan);
856
857 uap->dmacr |= UART011_RXDMAE;
858 pl011_write(uap->dmacr, uap, REG_DMACR);
859 uap->dmarx.running = true;
860
861 uap->im &= ~UART011_RXIM;
862 pl011_write(uap->im, uap, REG_IMSC);
863
864 return 0;
865 }
866
867 /*
868 * This is called when either the DMA job is complete, or
869 * the FIFO timeout interrupt occurred. This must be called
870 * with the port spinlock uap->port.lock held.
871 */
872 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
873 u32 pending, bool use_buf_b,
874 bool readfifo)
875 {
876 struct tty_port *port = &uap->port.state->port;
877 struct pl011_sgbuf *sgbuf = use_buf_b ?
878 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
879 int dma_count = 0;
880 u32 fifotaken = 0; /* only used for vdbg() */
881
882 struct pl011_dmarx_data *dmarx = &uap->dmarx;
883 int dmataken = 0;
884
885 if (uap->dmarx.poll_rate) {
886 /* The data can be taken by polling */
887 dmataken = sgbuf->sg.length - dmarx->last_residue;
888 /* Recalculate the pending size */
889 if (pending >= dmataken)
890 pending -= dmataken;
891 }
892
893 /* Pick the remain data from the DMA */
894 if (pending) {
895
896 /*
897 * First take all chars in the DMA pipe, then look in the FIFO.
898 * Note that tty_insert_flip_buf() tries to take as many chars
899 * as it can.
900 */
901 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
902 pending);
903
904 uap->port.icount.rx += dma_count;
905 if (dma_count < pending)
906 dev_warn(uap->port.dev,
907 "couldn't insert all characters (TTY is full?)\n");
908 }
909
910 /* Reset the last_residue for Rx DMA poll */
911 if (uap->dmarx.poll_rate)
912 dmarx->last_residue = sgbuf->sg.length;
913
914 /*
915 * Only continue with trying to read the FIFO if all DMA chars have
916 * been taken first.
917 */
918 if (dma_count == pending && readfifo) {
919 /* Clear any error flags */
920 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
921 UART011_FEIS, uap, REG_ICR);
922
923 /*
924 * If we read all the DMA'd characters, and we had an
925 * incomplete buffer, that could be due to an rx error, or
926 * maybe we just timed out. Read any pending chars and check
927 * the error status.
928 *
929 * Error conditions will only occur in the FIFO, these will
930 * trigger an immediate interrupt and stop the DMA job, so we
931 * will always find the error in the FIFO, never in the DMA
932 * buffer.
933 */
934 fifotaken = pl011_fifo_to_tty(uap);
935 }
936
937 spin_unlock(&uap->port.lock);
938 dev_vdbg(uap->port.dev,
939 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
940 dma_count, fifotaken);
941 tty_flip_buffer_push(port);
942 spin_lock(&uap->port.lock);
943 }
944
945 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
946 {
947 struct pl011_dmarx_data *dmarx = &uap->dmarx;
948 struct dma_chan *rxchan = dmarx->chan;
949 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
950 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
951 size_t pending;
952 struct dma_tx_state state;
953 enum dma_status dmastat;
954
955 /*
956 * Pause the transfer so we can trust the current counter,
957 * do this before we pause the PL011 block, else we may
958 * overflow the FIFO.
959 */
960 if (dmaengine_pause(rxchan))
961 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
962 dmastat = rxchan->device->device_tx_status(rxchan,
963 dmarx->cookie, &state);
964 if (dmastat != DMA_PAUSED)
965 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
966
967 /* Disable RX DMA - incoming data will wait in the FIFO */
968 uap->dmacr &= ~UART011_RXDMAE;
969 pl011_write(uap->dmacr, uap, REG_DMACR);
970 uap->dmarx.running = false;
971
972 pending = sgbuf->sg.length - state.residue;
973 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
974 /* Then we terminate the transfer - we now know our residue */
975 dmaengine_terminate_all(rxchan);
976
977 /*
978 * This will take the chars we have so far and insert
979 * into the framework.
980 */
981 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
982
983 /* Switch buffer & re-trigger DMA job */
984 dmarx->use_buf_b = !dmarx->use_buf_b;
985 if (pl011_dma_rx_trigger_dma(uap)) {
986 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
987 "fall back to interrupt mode\n");
988 uap->im |= UART011_RXIM;
989 pl011_write(uap->im, uap, REG_IMSC);
990 }
991 }
992
993 static void pl011_dma_rx_callback(void *data)
994 {
995 struct uart_amba_port *uap = data;
996 struct pl011_dmarx_data *dmarx = &uap->dmarx;
997 struct dma_chan *rxchan = dmarx->chan;
998 bool lastbuf = dmarx->use_buf_b;
999 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1000 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1001 size_t pending;
1002 struct dma_tx_state state;
1003 int ret;
1004
1005 /*
1006 * This completion interrupt occurs typically when the
1007 * RX buffer is totally stuffed but no timeout has yet
1008 * occurred. When that happens, we just want the RX
1009 * routine to flush out the secondary DMA buffer while
1010 * we immediately trigger the next DMA job.
1011 */
1012 spin_lock_irq(&uap->port.lock);
1013 /*
1014 * Rx data can be taken by the UART interrupts during
1015 * the DMA irq handler. So we check the residue here.
1016 */
1017 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1018 pending = sgbuf->sg.length - state.residue;
1019 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1020 /* Then we terminate the transfer - we now know our residue */
1021 dmaengine_terminate_all(rxchan);
1022
1023 uap->dmarx.running = false;
1024 dmarx->use_buf_b = !lastbuf;
1025 ret = pl011_dma_rx_trigger_dma(uap);
1026
1027 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1028 spin_unlock_irq(&uap->port.lock);
1029 /*
1030 * Do this check after we picked the DMA chars so we don't
1031 * get some IRQ immediately from RX.
1032 */
1033 if (ret) {
1034 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1035 "fall back to interrupt mode\n");
1036 uap->im |= UART011_RXIM;
1037 pl011_write(uap->im, uap, REG_IMSC);
1038 }
1039 }
1040
1041 /*
1042 * Stop accepting received characters, when we're shutting down or
1043 * suspending this port.
1044 * Locking: called with port lock held and IRQs disabled.
1045 */
1046 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1047 {
1048 /* FIXME. Just disable the DMA enable */
1049 uap->dmacr &= ~UART011_RXDMAE;
1050 pl011_write(uap->dmacr, uap, REG_DMACR);
1051 }
1052
1053 /*
1054 * Timer handler for Rx DMA polling.
1055 * Every polling, It checks the residue in the dma buffer and transfer
1056 * data to the tty. Also, last_residue is updated for the next polling.
1057 */
1058 static void pl011_dma_rx_poll(struct timer_list *t)
1059 {
1060 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
1061 struct tty_port *port = &uap->port.state->port;
1062 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1063 struct dma_chan *rxchan = uap->dmarx.chan;
1064 unsigned long flags = 0;
1065 unsigned int dmataken = 0;
1066 unsigned int size = 0;
1067 struct pl011_sgbuf *sgbuf;
1068 int dma_count;
1069 struct dma_tx_state state;
1070
1071 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1072 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1073 if (likely(state.residue < dmarx->last_residue)) {
1074 dmataken = sgbuf->sg.length - dmarx->last_residue;
1075 size = dmarx->last_residue - state.residue;
1076 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1077 size);
1078 if (dma_count == size)
1079 dmarx->last_residue = state.residue;
1080 dmarx->last_jiffies = jiffies;
1081 }
1082 tty_flip_buffer_push(port);
1083
1084 /*
1085 * If no data is received in poll_timeout, the driver will fall back
1086 * to interrupt mode. We will retrigger DMA at the first interrupt.
1087 */
1088 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1089 > uap->dmarx.poll_timeout) {
1090
1091 spin_lock_irqsave(&uap->port.lock, flags);
1092 pl011_dma_rx_stop(uap);
1093 uap->im |= UART011_RXIM;
1094 pl011_write(uap->im, uap, REG_IMSC);
1095 spin_unlock_irqrestore(&uap->port.lock, flags);
1096
1097 uap->dmarx.running = false;
1098 dmaengine_terminate_all(rxchan);
1099 del_timer(&uap->dmarx.timer);
1100 } else {
1101 mod_timer(&uap->dmarx.timer,
1102 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1103 }
1104 }
1105
1106 static void pl011_dma_startup(struct uart_amba_port *uap)
1107 {
1108 int ret;
1109
1110 if (!uap->dma_probed)
1111 pl011_dma_probe(uap);
1112
1113 if (!uap->dmatx.chan)
1114 return;
1115
1116 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1117 if (!uap->dmatx.buf) {
1118 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1119 uap->port.fifosize = uap->fifosize;
1120 return;
1121 }
1122
1123 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1124
1125 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1126 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1127 uap->using_tx_dma = true;
1128
1129 if (!uap->dmarx.chan)
1130 goto skip_rx;
1131
1132 /* Allocate and map DMA RX buffers */
1133 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1134 DMA_FROM_DEVICE);
1135 if (ret) {
1136 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1137 "RX buffer A", ret);
1138 goto skip_rx;
1139 }
1140
1141 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1142 DMA_FROM_DEVICE);
1143 if (ret) {
1144 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1145 "RX buffer B", ret);
1146 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1147 DMA_FROM_DEVICE);
1148 goto skip_rx;
1149 }
1150
1151 uap->using_rx_dma = true;
1152
1153 skip_rx:
1154 /* Turn on DMA error (RX/TX will be enabled on demand) */
1155 uap->dmacr |= UART011_DMAONERR;
1156 pl011_write(uap->dmacr, uap, REG_DMACR);
1157
1158 /*
1159 * ST Micro variants has some specific dma burst threshold
1160 * compensation. Set this to 16 bytes, so burst will only
1161 * be issued above/below 16 bytes.
1162 */
1163 if (uap->vendor->dma_threshold)
1164 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1165 uap, REG_ST_DMAWM);
1166
1167 if (uap->using_rx_dma) {
1168 if (pl011_dma_rx_trigger_dma(uap))
1169 dev_dbg(uap->port.dev, "could not trigger initial "
1170 "RX DMA job, fall back to interrupt mode\n");
1171 if (uap->dmarx.poll_rate) {
1172 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
1173 mod_timer(&uap->dmarx.timer,
1174 jiffies +
1175 msecs_to_jiffies(uap->dmarx.poll_rate));
1176 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1177 uap->dmarx.last_jiffies = jiffies;
1178 }
1179 }
1180 }
1181
1182 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1183 {
1184 if (!(uap->using_tx_dma || uap->using_rx_dma))
1185 return;
1186
1187 /* Disable RX and TX DMA */
1188 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1189 cpu_relax();
1190
1191 spin_lock_irq(&uap->port.lock);
1192 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1193 pl011_write(uap->dmacr, uap, REG_DMACR);
1194 spin_unlock_irq(&uap->port.lock);
1195
1196 if (uap->using_tx_dma) {
1197 /* In theory, this should already be done by pl011_dma_flush_buffer */
1198 dmaengine_terminate_all(uap->dmatx.chan);
1199 if (uap->dmatx.queued) {
1200 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1201 DMA_TO_DEVICE);
1202 uap->dmatx.queued = false;
1203 }
1204
1205 kfree(uap->dmatx.buf);
1206 uap->using_tx_dma = false;
1207 }
1208
1209 if (uap->using_rx_dma) {
1210 dmaengine_terminate_all(uap->dmarx.chan);
1211 /* Clean up the RX DMA */
1212 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1213 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1214 if (uap->dmarx.poll_rate)
1215 del_timer_sync(&uap->dmarx.timer);
1216 uap->using_rx_dma = false;
1217 }
1218 }
1219
1220 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1221 {
1222 return uap->using_rx_dma;
1223 }
1224
1225 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1226 {
1227 return uap->using_rx_dma && uap->dmarx.running;
1228 }
1229
1230 #else
1231 /* Blank functions if the DMA engine is not available */
1232 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1233 {
1234 }
1235
1236 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1237 {
1238 }
1239
1240 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1241 {
1242 }
1243
1244 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1245 {
1246 return false;
1247 }
1248
1249 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1250 {
1251 }
1252
1253 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1254 {
1255 return false;
1256 }
1257
1258 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1259 {
1260 }
1261
1262 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1263 {
1264 }
1265
1266 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1267 {
1268 return -EIO;
1269 }
1270
1271 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1272 {
1273 return false;
1274 }
1275
1276 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1277 {
1278 return false;
1279 }
1280
1281 #define pl011_dma_flush_buffer NULL
1282 #endif
1283
1284 static void pl011_stop_tx(struct uart_port *port)
1285 {
1286 struct uart_amba_port *uap =
1287 container_of(port, struct uart_amba_port, port);
1288
1289 uap->im &= ~UART011_TXIM;
1290 pl011_write(uap->im, uap, REG_IMSC);
1291 pl011_dma_tx_stop(uap);
1292 }
1293
1294 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1295
1296 /* Start TX with programmed I/O only (no DMA) */
1297 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1298 {
1299 if (pl011_tx_chars(uap, false)) {
1300 uap->im |= UART011_TXIM;
1301 pl011_write(uap->im, uap, REG_IMSC);
1302 }
1303 }
1304
1305 static void pl011_start_tx(struct uart_port *port)
1306 {
1307 struct uart_amba_port *uap =
1308 container_of(port, struct uart_amba_port, port);
1309
1310 if (!pl011_dma_tx_start(uap))
1311 pl011_start_tx_pio(uap);
1312 }
1313
1314 static void pl011_stop_rx(struct uart_port *port)
1315 {
1316 struct uart_amba_port *uap =
1317 container_of(port, struct uart_amba_port, port);
1318
1319 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1320 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1321 pl011_write(uap->im, uap, REG_IMSC);
1322
1323 pl011_dma_rx_stop(uap);
1324 }
1325
1326 static void pl011_enable_ms(struct uart_port *port)
1327 {
1328 struct uart_amba_port *uap =
1329 container_of(port, struct uart_amba_port, port);
1330
1331 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1332 pl011_write(uap->im, uap, REG_IMSC);
1333 }
1334
1335 static void pl011_rx_chars(struct uart_amba_port *uap)
1336 __releases(&uap->port.lock)
1337 __acquires(&uap->port.lock)
1338 {
1339 pl011_fifo_to_tty(uap);
1340
1341 spin_unlock(&uap->port.lock);
1342 tty_flip_buffer_push(&uap->port.state->port);
1343 /*
1344 * If we were temporarily out of DMA mode for a while,
1345 * attempt to switch back to DMA mode again.
1346 */
1347 if (pl011_dma_rx_available(uap)) {
1348 if (pl011_dma_rx_trigger_dma(uap)) {
1349 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1350 "fall back to interrupt mode again\n");
1351 uap->im |= UART011_RXIM;
1352 pl011_write(uap->im, uap, REG_IMSC);
1353 } else {
1354 #ifdef CONFIG_DMA_ENGINE
1355 /* Start Rx DMA poll */
1356 if (uap->dmarx.poll_rate) {
1357 uap->dmarx.last_jiffies = jiffies;
1358 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1359 mod_timer(&uap->dmarx.timer,
1360 jiffies +
1361 msecs_to_jiffies(uap->dmarx.poll_rate));
1362 }
1363 #endif
1364 }
1365 }
1366 spin_lock(&uap->port.lock);
1367 }
1368
1369 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1370 bool from_irq)
1371 {
1372 if (unlikely(!from_irq) &&
1373 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1374 return false; /* unable to transmit character */
1375
1376 pl011_write(c, uap, REG_DR);
1377 uap->port.icount.tx++;
1378
1379 return true;
1380 }
1381
1382 /* Returns true if tx interrupts have to be (kept) enabled */
1383 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1384 {
1385 struct circ_buf *xmit = &uap->port.state->xmit;
1386 int count = uap->fifosize >> 1;
1387
1388 if (uap->port.x_char) {
1389 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1390 return true;
1391 uap->port.x_char = 0;
1392 --count;
1393 }
1394 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1395 pl011_stop_tx(&uap->port);
1396 return false;
1397 }
1398
1399 /* If we are using DMA mode, try to send some characters. */
1400 if (pl011_dma_tx_irq(uap))
1401 return true;
1402
1403 do {
1404 if (likely(from_irq) && count-- == 0)
1405 break;
1406
1407 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1408 break;
1409
1410 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1411 } while (!uart_circ_empty(xmit));
1412
1413 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1414 uart_write_wakeup(&uap->port);
1415
1416 if (uart_circ_empty(xmit)) {
1417 pl011_stop_tx(&uap->port);
1418 return false;
1419 }
1420 return true;
1421 }
1422
1423 static void pl011_modem_status(struct uart_amba_port *uap)
1424 {
1425 unsigned int status, delta;
1426
1427 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1428
1429 delta = status ^ uap->old_status;
1430 uap->old_status = status;
1431
1432 if (!delta)
1433 return;
1434
1435 if (delta & UART01x_FR_DCD)
1436 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1437
1438 if (delta & uap->vendor->fr_dsr)
1439 uap->port.icount.dsr++;
1440
1441 if (delta & uap->vendor->fr_cts)
1442 uart_handle_cts_change(&uap->port,
1443 status & uap->vendor->fr_cts);
1444
1445 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1446 }
1447
1448 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1449 {
1450 if (!uap->vendor->cts_event_workaround)
1451 return;
1452
1453 /* workaround to make sure that all bits are unlocked.. */
1454 pl011_write(0x00, uap, REG_ICR);
1455
1456 /*
1457 * WA: introduce 26ns(1 uart clk) delay before W1C;
1458 * single apb access will incur 2 pclk(133.12Mhz) delay,
1459 * so add 2 dummy reads
1460 */
1461 pl011_read(uap, REG_ICR);
1462 pl011_read(uap, REG_ICR);
1463 }
1464
1465 static irqreturn_t pl011_int(int irq, void *dev_id)
1466 {
1467 struct uart_amba_port *uap = dev_id;
1468 unsigned long flags;
1469 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1470 int handled = 0;
1471
1472 spin_lock_irqsave(&uap->port.lock, flags);
1473 status = pl011_read(uap, REG_RIS) & uap->im;
1474 if (status) {
1475 do {
1476 check_apply_cts_event_workaround(uap);
1477
1478 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1479 UART011_RXIS),
1480 uap, REG_ICR);
1481
1482 if (status & (UART011_RTIS|UART011_RXIS)) {
1483 if (pl011_dma_rx_running(uap))
1484 pl011_dma_rx_irq(uap);
1485 else
1486 pl011_rx_chars(uap);
1487 }
1488 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1489 UART011_CTSMIS|UART011_RIMIS))
1490 pl011_modem_status(uap);
1491 if (status & UART011_TXIS)
1492 pl011_tx_chars(uap, true);
1493
1494 if (pass_counter-- == 0)
1495 break;
1496
1497 status = pl011_read(uap, REG_RIS) & uap->im;
1498 } while (status != 0);
1499 handled = 1;
1500 }
1501
1502 spin_unlock_irqrestore(&uap->port.lock, flags);
1503
1504 return IRQ_RETVAL(handled);
1505 }
1506
1507 static unsigned int pl011_tx_empty(struct uart_port *port)
1508 {
1509 struct uart_amba_port *uap =
1510 container_of(port, struct uart_amba_port, port);
1511
1512 /* Allow feature register bits to be inverted to work around errata */
1513 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1514
1515 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1516 0 : TIOCSER_TEMT;
1517 }
1518
1519 static unsigned int pl011_get_mctrl(struct uart_port *port)
1520 {
1521 struct uart_amba_port *uap =
1522 container_of(port, struct uart_amba_port, port);
1523 unsigned int result = 0;
1524 unsigned int status = pl011_read(uap, REG_FR);
1525
1526 #define TIOCMBIT(uartbit, tiocmbit) \
1527 if (status & uartbit) \
1528 result |= tiocmbit
1529
1530 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1531 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1532 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1533 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1534 #undef TIOCMBIT
1535 return result;
1536 }
1537
1538 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1539 {
1540 struct uart_amba_port *uap =
1541 container_of(port, struct uart_amba_port, port);
1542 unsigned int cr;
1543
1544 cr = pl011_read(uap, REG_CR);
1545
1546 #define TIOCMBIT(tiocmbit, uartbit) \
1547 if (mctrl & tiocmbit) \
1548 cr |= uartbit; \
1549 else \
1550 cr &= ~uartbit
1551
1552 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1553 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1554 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1555 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1556 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1557
1558 if (port->status & UPSTAT_AUTORTS) {
1559 /* We need to disable auto-RTS if we want to turn RTS off */
1560 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1561 }
1562 #undef TIOCMBIT
1563
1564 pl011_write(cr, uap, REG_CR);
1565 }
1566
1567 static void pl011_break_ctl(struct uart_port *port, int break_state)
1568 {
1569 struct uart_amba_port *uap =
1570 container_of(port, struct uart_amba_port, port);
1571 unsigned long flags;
1572 unsigned int lcr_h;
1573
1574 spin_lock_irqsave(&uap->port.lock, flags);
1575 lcr_h = pl011_read(uap, REG_LCRH_TX);
1576 if (break_state == -1)
1577 lcr_h |= UART01x_LCRH_BRK;
1578 else
1579 lcr_h &= ~UART01x_LCRH_BRK;
1580 pl011_write(lcr_h, uap, REG_LCRH_TX);
1581 spin_unlock_irqrestore(&uap->port.lock, flags);
1582 }
1583
1584 #ifdef CONFIG_CONSOLE_POLL
1585
1586 static void pl011_quiesce_irqs(struct uart_port *port)
1587 {
1588 struct uart_amba_port *uap =
1589 container_of(port, struct uart_amba_port, port);
1590
1591 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1592 /*
1593 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1594 * we simply mask it. start_tx() will unmask it.
1595 *
1596 * Note we can race with start_tx(), and if the race happens, the
1597 * polling user might get another interrupt just after we clear it.
1598 * But it should be OK and can happen even w/o the race, e.g.
1599 * controller immediately got some new data and raised the IRQ.
1600 *
1601 * And whoever uses polling routines assumes that it manages the device
1602 * (including tx queue), so we're also fine with start_tx()'s caller
1603 * side.
1604 */
1605 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1606 REG_IMSC);
1607 }
1608
1609 static int pl011_get_poll_char(struct uart_port *port)
1610 {
1611 struct uart_amba_port *uap =
1612 container_of(port, struct uart_amba_port, port);
1613 unsigned int status;
1614
1615 /*
1616 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1617 * debugger.
1618 */
1619 pl011_quiesce_irqs(port);
1620
1621 status = pl011_read(uap, REG_FR);
1622 if (status & UART01x_FR_RXFE)
1623 return NO_POLL_CHAR;
1624
1625 return pl011_read(uap, REG_DR);
1626 }
1627
1628 static void pl011_put_poll_char(struct uart_port *port,
1629 unsigned char ch)
1630 {
1631 struct uart_amba_port *uap =
1632 container_of(port, struct uart_amba_port, port);
1633
1634 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1635 cpu_relax();
1636
1637 pl011_write(ch, uap, REG_DR);
1638 }
1639
1640 #endif /* CONFIG_CONSOLE_POLL */
1641
1642 static int pl011_hwinit(struct uart_port *port)
1643 {
1644 struct uart_amba_port *uap =
1645 container_of(port, struct uart_amba_port, port);
1646 int retval;
1647
1648 /* Optionaly enable pins to be muxed in and configured */
1649 pinctrl_pm_select_default_state(port->dev);
1650
1651 /*
1652 * Try to enable the clock producer.
1653 */
1654 retval = clk_prepare_enable(uap->clk);
1655 if (retval)
1656 return retval;
1657
1658 uap->port.uartclk = clk_get_rate(uap->clk);
1659
1660 /* Clear pending error and receive interrupts */
1661 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1662 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1663 uap, REG_ICR);
1664
1665 /*
1666 * Save interrupts enable mask, and enable RX interrupts in case if
1667 * the interrupt is used for NMI entry.
1668 */
1669 uap->im = pl011_read(uap, REG_IMSC);
1670 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1671
1672 if (dev_get_platdata(uap->port.dev)) {
1673 struct amba_pl011_data *plat;
1674
1675 plat = dev_get_platdata(uap->port.dev);
1676 if (plat->init)
1677 plat->init();
1678 }
1679 return 0;
1680 }
1681
1682 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1683 {
1684 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1685 pl011_reg_to_offset(uap, REG_LCRH_TX);
1686 }
1687
1688 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1689 {
1690 pl011_write(lcr_h, uap, REG_LCRH_RX);
1691 if (pl011_split_lcrh(uap)) {
1692 int i;
1693 /*
1694 * Wait 10 PCLKs before writing LCRH_TX register,
1695 * to get this delay write read only register 10 times
1696 */
1697 for (i = 0; i < 10; ++i)
1698 pl011_write(0xff, uap, REG_MIS);
1699 pl011_write(lcr_h, uap, REG_LCRH_TX);
1700 }
1701 }
1702
1703 static int pl011_allocate_irq(struct uart_amba_port *uap)
1704 {
1705 pl011_write(uap->im, uap, REG_IMSC);
1706
1707 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
1708 }
1709
1710 /*
1711 * Enable interrupts, only timeouts when using DMA
1712 * if initial RX DMA job failed, start in interrupt mode
1713 * as well.
1714 */
1715 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1716 {
1717 unsigned int i;
1718
1719 spin_lock_irq(&uap->port.lock);
1720
1721 /* Clear out any spuriously appearing RX interrupts */
1722 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1723
1724 /*
1725 * RXIS is asserted only when the RX FIFO transitions from below
1726 * to above the trigger threshold. If the RX FIFO is already
1727 * full to the threshold this can't happen and RXIS will now be
1728 * stuck off. Drain the RX FIFO explicitly to fix this:
1729 */
1730 for (i = 0; i < uap->fifosize * 2; ++i) {
1731 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1732 break;
1733
1734 pl011_read(uap, REG_DR);
1735 }
1736
1737 uap->im = UART011_RTIM;
1738 if (!pl011_dma_rx_running(uap))
1739 uap->im |= UART011_RXIM;
1740 pl011_write(uap->im, uap, REG_IMSC);
1741 spin_unlock_irq(&uap->port.lock);
1742 }
1743
1744 static int pl011_startup(struct uart_port *port)
1745 {
1746 struct uart_amba_port *uap =
1747 container_of(port, struct uart_amba_port, port);
1748 unsigned int cr;
1749 int retval;
1750
1751 retval = pl011_hwinit(port);
1752 if (retval)
1753 goto clk_dis;
1754
1755 retval = pl011_allocate_irq(uap);
1756 if (retval)
1757 goto clk_dis;
1758
1759 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1760
1761 spin_lock_irq(&uap->port.lock);
1762
1763 /* restore RTS and DTR */
1764 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1765 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1766 pl011_write(cr, uap, REG_CR);
1767
1768 spin_unlock_irq(&uap->port.lock);
1769
1770 /*
1771 * initialise the old status of the modem signals
1772 */
1773 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1774
1775 /* Startup DMA */
1776 pl011_dma_startup(uap);
1777
1778 pl011_enable_interrupts(uap);
1779
1780 return 0;
1781
1782 clk_dis:
1783 clk_disable_unprepare(uap->clk);
1784 return retval;
1785 }
1786
1787 static int sbsa_uart_startup(struct uart_port *port)
1788 {
1789 struct uart_amba_port *uap =
1790 container_of(port, struct uart_amba_port, port);
1791 int retval;
1792
1793 retval = pl011_hwinit(port);
1794 if (retval)
1795 return retval;
1796
1797 retval = pl011_allocate_irq(uap);
1798 if (retval)
1799 return retval;
1800
1801 /* The SBSA UART does not support any modem status lines. */
1802 uap->old_status = 0;
1803
1804 pl011_enable_interrupts(uap);
1805
1806 return 0;
1807 }
1808
1809 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1810 unsigned int lcrh)
1811 {
1812 unsigned long val;
1813
1814 val = pl011_read(uap, lcrh);
1815 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1816 pl011_write(val, uap, lcrh);
1817 }
1818
1819 /*
1820 * disable the port. It should not disable RTS and DTR.
1821 * Also RTS and DTR state should be preserved to restore
1822 * it during startup().
1823 */
1824 static void pl011_disable_uart(struct uart_amba_port *uap)
1825 {
1826 unsigned int cr;
1827
1828 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1829 spin_lock_irq(&uap->port.lock);
1830 cr = pl011_read(uap, REG_CR);
1831 uap->old_cr = cr;
1832 cr &= UART011_CR_RTS | UART011_CR_DTR;
1833 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1834 pl011_write(cr, uap, REG_CR);
1835 spin_unlock_irq(&uap->port.lock);
1836
1837 /*
1838 * disable break condition and fifos
1839 */
1840 pl011_shutdown_channel(uap, REG_LCRH_RX);
1841 if (pl011_split_lcrh(uap))
1842 pl011_shutdown_channel(uap, REG_LCRH_TX);
1843 }
1844
1845 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1846 {
1847 spin_lock_irq(&uap->port.lock);
1848
1849 /* mask all interrupts and clear all pending ones */
1850 uap->im = 0;
1851 pl011_write(uap->im, uap, REG_IMSC);
1852 pl011_write(0xffff, uap, REG_ICR);
1853
1854 spin_unlock_irq(&uap->port.lock);
1855 }
1856
1857 static void pl011_shutdown(struct uart_port *port)
1858 {
1859 struct uart_amba_port *uap =
1860 container_of(port, struct uart_amba_port, port);
1861
1862 pl011_disable_interrupts(uap);
1863
1864 pl011_dma_shutdown(uap);
1865
1866 free_irq(uap->port.irq, uap);
1867
1868 pl011_disable_uart(uap);
1869
1870 /*
1871 * Shut down the clock producer
1872 */
1873 clk_disable_unprepare(uap->clk);
1874 /* Optionally let pins go into sleep states */
1875 pinctrl_pm_select_sleep_state(port->dev);
1876
1877 if (dev_get_platdata(uap->port.dev)) {
1878 struct amba_pl011_data *plat;
1879
1880 plat = dev_get_platdata(uap->port.dev);
1881 if (plat->exit)
1882 plat->exit();
1883 }
1884
1885 if (uap->port.ops->flush_buffer)
1886 uap->port.ops->flush_buffer(port);
1887 }
1888
1889 static void sbsa_uart_shutdown(struct uart_port *port)
1890 {
1891 struct uart_amba_port *uap =
1892 container_of(port, struct uart_amba_port, port);
1893
1894 pl011_disable_interrupts(uap);
1895
1896 free_irq(uap->port.irq, uap);
1897
1898 if (uap->port.ops->flush_buffer)
1899 uap->port.ops->flush_buffer(port);
1900 }
1901
1902 static void
1903 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1904 {
1905 port->read_status_mask = UART011_DR_OE | 255;
1906 if (termios->c_iflag & INPCK)
1907 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1908 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1909 port->read_status_mask |= UART011_DR_BE;
1910
1911 /*
1912 * Characters to ignore
1913 */
1914 port->ignore_status_mask = 0;
1915 if (termios->c_iflag & IGNPAR)
1916 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1917 if (termios->c_iflag & IGNBRK) {
1918 port->ignore_status_mask |= UART011_DR_BE;
1919 /*
1920 * If we're ignoring parity and break indicators,
1921 * ignore overruns too (for real raw support).
1922 */
1923 if (termios->c_iflag & IGNPAR)
1924 port->ignore_status_mask |= UART011_DR_OE;
1925 }
1926
1927 /*
1928 * Ignore all characters if CREAD is not set.
1929 */
1930 if ((termios->c_cflag & CREAD) == 0)
1931 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1932 }
1933
1934 static void
1935 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1936 struct ktermios *old)
1937 {
1938 struct uart_amba_port *uap =
1939 container_of(port, struct uart_amba_port, port);
1940 unsigned int lcr_h, old_cr;
1941 unsigned long flags;
1942 unsigned int baud, quot, clkdiv;
1943
1944 if (uap->vendor->oversampling)
1945 clkdiv = 8;
1946 else
1947 clkdiv = 16;
1948
1949 /*
1950 * Ask the core to calculate the divisor for us.
1951 */
1952 baud = uart_get_baud_rate(port, termios, old, 0,
1953 port->uartclk / clkdiv);
1954 #ifdef CONFIG_DMA_ENGINE
1955 /*
1956 * Adjust RX DMA polling rate with baud rate if not specified.
1957 */
1958 if (uap->dmarx.auto_poll_rate)
1959 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1960 #endif
1961
1962 if (baud > port->uartclk/16)
1963 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1964 else
1965 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1966
1967 switch (termios->c_cflag & CSIZE) {
1968 case CS5:
1969 lcr_h = UART01x_LCRH_WLEN_5;
1970 break;
1971 case CS6:
1972 lcr_h = UART01x_LCRH_WLEN_6;
1973 break;
1974 case CS7:
1975 lcr_h = UART01x_LCRH_WLEN_7;
1976 break;
1977 default: // CS8
1978 lcr_h = UART01x_LCRH_WLEN_8;
1979 break;
1980 }
1981 if (termios->c_cflag & CSTOPB)
1982 lcr_h |= UART01x_LCRH_STP2;
1983 if (termios->c_cflag & PARENB) {
1984 lcr_h |= UART01x_LCRH_PEN;
1985 if (!(termios->c_cflag & PARODD))
1986 lcr_h |= UART01x_LCRH_EPS;
1987 if (termios->c_cflag & CMSPAR)
1988 lcr_h |= UART011_LCRH_SPS;
1989 }
1990 if (uap->fifosize > 1)
1991 lcr_h |= UART01x_LCRH_FEN;
1992
1993 spin_lock_irqsave(&port->lock, flags);
1994
1995 /*
1996 * Update the per-port timeout.
1997 */
1998 uart_update_timeout(port, termios->c_cflag, baud);
1999
2000 pl011_setup_status_masks(port, termios);
2001
2002 if (UART_ENABLE_MS(port, termios->c_cflag))
2003 pl011_enable_ms(port);
2004
2005 /* first, disable everything */
2006 old_cr = pl011_read(uap, REG_CR);
2007 pl011_write(0, uap, REG_CR);
2008
2009 if (termios->c_cflag & CRTSCTS) {
2010 if (old_cr & UART011_CR_RTS)
2011 old_cr |= UART011_CR_RTSEN;
2012
2013 old_cr |= UART011_CR_CTSEN;
2014 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
2015 } else {
2016 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2017 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
2018 }
2019
2020 if (uap->vendor->oversampling) {
2021 if (baud > port->uartclk / 16)
2022 old_cr |= ST_UART011_CR_OVSFACT;
2023 else
2024 old_cr &= ~ST_UART011_CR_OVSFACT;
2025 }
2026
2027 /*
2028 * Workaround for the ST Micro oversampling variants to
2029 * increase the bitrate slightly, by lowering the divisor,
2030 * to avoid delayed sampling of start bit at high speeds,
2031 * else we see data corruption.
2032 */
2033 if (uap->vendor->oversampling) {
2034 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2035 quot -= 1;
2036 else if ((baud > 3250000) && (quot > 2))
2037 quot -= 2;
2038 }
2039 /* Set baud rate */
2040 pl011_write(quot & 0x3f, uap, REG_FBRD);
2041 pl011_write(quot >> 6, uap, REG_IBRD);
2042
2043 /*
2044 * ----------v----------v----------v----------v-----
2045 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2046 * REG_FBRD & REG_IBRD.
2047 * ----------^----------^----------^----------^-----
2048 */
2049 pl011_write_lcr_h(uap, lcr_h);
2050 pl011_write(old_cr, uap, REG_CR);
2051
2052 spin_unlock_irqrestore(&port->lock, flags);
2053 }
2054
2055 static void
2056 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2057 struct ktermios *old)
2058 {
2059 struct uart_amba_port *uap =
2060 container_of(port, struct uart_amba_port, port);
2061 unsigned long flags;
2062
2063 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2064
2065 /* The SBSA UART only supports 8n1 without hardware flow control. */
2066 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2067 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2068 termios->c_cflag |= CS8 | CLOCAL;
2069
2070 spin_lock_irqsave(&port->lock, flags);
2071 uart_update_timeout(port, CS8, uap->fixed_baud);
2072 pl011_setup_status_masks(port, termios);
2073 spin_unlock_irqrestore(&port->lock, flags);
2074 }
2075
2076 static const char *pl011_type(struct uart_port *port)
2077 {
2078 struct uart_amba_port *uap =
2079 container_of(port, struct uart_amba_port, port);
2080 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2081 }
2082
2083 /*
2084 * Release the memory region(s) being used by 'port'
2085 */
2086 static void pl011_release_port(struct uart_port *port)
2087 {
2088 release_mem_region(port->mapbase, SZ_4K);
2089 }
2090
2091 /*
2092 * Request the memory region(s) being used by 'port'
2093 */
2094 static int pl011_request_port(struct uart_port *port)
2095 {
2096 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
2097 != NULL ? 0 : -EBUSY;
2098 }
2099
2100 /*
2101 * Configure/autoconfigure the port.
2102 */
2103 static void pl011_config_port(struct uart_port *port, int flags)
2104 {
2105 if (flags & UART_CONFIG_TYPE) {
2106 port->type = PORT_AMBA;
2107 pl011_request_port(port);
2108 }
2109 }
2110
2111 /*
2112 * verify the new serial_struct (for TIOCSSERIAL).
2113 */
2114 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2115 {
2116 int ret = 0;
2117 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2118 ret = -EINVAL;
2119 if (ser->irq < 0 || ser->irq >= nr_irqs)
2120 ret = -EINVAL;
2121 if (ser->baud_base < 9600)
2122 ret = -EINVAL;
2123 return ret;
2124 }
2125
2126 static const struct uart_ops amba_pl011_pops = {
2127 .tx_empty = pl011_tx_empty,
2128 .set_mctrl = pl011_set_mctrl,
2129 .get_mctrl = pl011_get_mctrl,
2130 .stop_tx = pl011_stop_tx,
2131 .start_tx = pl011_start_tx,
2132 .stop_rx = pl011_stop_rx,
2133 .enable_ms = pl011_enable_ms,
2134 .break_ctl = pl011_break_ctl,
2135 .startup = pl011_startup,
2136 .shutdown = pl011_shutdown,
2137 .flush_buffer = pl011_dma_flush_buffer,
2138 .set_termios = pl011_set_termios,
2139 .type = pl011_type,
2140 .release_port = pl011_release_port,
2141 .request_port = pl011_request_port,
2142 .config_port = pl011_config_port,
2143 .verify_port = pl011_verify_port,
2144 #ifdef CONFIG_CONSOLE_POLL
2145 .poll_init = pl011_hwinit,
2146 .poll_get_char = pl011_get_poll_char,
2147 .poll_put_char = pl011_put_poll_char,
2148 #endif
2149 };
2150
2151 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2152 {
2153 }
2154
2155 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2156 {
2157 return 0;
2158 }
2159
2160 static const struct uart_ops sbsa_uart_pops = {
2161 .tx_empty = pl011_tx_empty,
2162 .set_mctrl = sbsa_uart_set_mctrl,
2163 .get_mctrl = sbsa_uart_get_mctrl,
2164 .stop_tx = pl011_stop_tx,
2165 .start_tx = pl011_start_tx,
2166 .stop_rx = pl011_stop_rx,
2167 .startup = sbsa_uart_startup,
2168 .shutdown = sbsa_uart_shutdown,
2169 .set_termios = sbsa_uart_set_termios,
2170 .type = pl011_type,
2171 .release_port = pl011_release_port,
2172 .request_port = pl011_request_port,
2173 .config_port = pl011_config_port,
2174 .verify_port = pl011_verify_port,
2175 #ifdef CONFIG_CONSOLE_POLL
2176 .poll_init = pl011_hwinit,
2177 .poll_get_char = pl011_get_poll_char,
2178 .poll_put_char = pl011_put_poll_char,
2179 #endif
2180 };
2181
2182 static struct uart_amba_port *amba_ports[UART_NR];
2183
2184 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2185
2186 static void pl011_console_putchar(struct uart_port *port, int ch)
2187 {
2188 struct uart_amba_port *uap =
2189 container_of(port, struct uart_amba_port, port);
2190
2191 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2192 cpu_relax();
2193 pl011_write(ch, uap, REG_DR);
2194 }
2195
2196 static void
2197 pl011_console_write(struct console *co, const char *s, unsigned int count)
2198 {
2199 struct uart_amba_port *uap = amba_ports[co->index];
2200 unsigned int old_cr = 0, new_cr;
2201 unsigned long flags;
2202 int locked = 1;
2203
2204 clk_enable(uap->clk);
2205
2206 local_irq_save(flags);
2207 if (uap->port.sysrq)
2208 locked = 0;
2209 else if (oops_in_progress)
2210 locked = spin_trylock(&uap->port.lock);
2211 else
2212 spin_lock(&uap->port.lock);
2213
2214 /*
2215 * First save the CR then disable the interrupts
2216 */
2217 if (!uap->vendor->always_enabled) {
2218 old_cr = pl011_read(uap, REG_CR);
2219 new_cr = old_cr & ~UART011_CR_CTSEN;
2220 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2221 pl011_write(new_cr, uap, REG_CR);
2222 }
2223
2224 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2225
2226 /*
2227 * Finally, wait for transmitter to become empty and restore the
2228 * TCR. Allow feature register bits to be inverted to work around
2229 * errata.
2230 */
2231 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2232 & uap->vendor->fr_busy)
2233 cpu_relax();
2234 if (!uap->vendor->always_enabled)
2235 pl011_write(old_cr, uap, REG_CR);
2236
2237 if (locked)
2238 spin_unlock(&uap->port.lock);
2239 local_irq_restore(flags);
2240
2241 clk_disable(uap->clk);
2242 }
2243
2244 static void __init
2245 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2246 int *parity, int *bits)
2247 {
2248 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2249 unsigned int lcr_h, ibrd, fbrd;
2250
2251 lcr_h = pl011_read(uap, REG_LCRH_TX);
2252
2253 *parity = 'n';
2254 if (lcr_h & UART01x_LCRH_PEN) {
2255 if (lcr_h & UART01x_LCRH_EPS)
2256 *parity = 'e';
2257 else
2258 *parity = 'o';
2259 }
2260
2261 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2262 *bits = 7;
2263 else
2264 *bits = 8;
2265
2266 ibrd = pl011_read(uap, REG_IBRD);
2267 fbrd = pl011_read(uap, REG_FBRD);
2268
2269 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2270
2271 if (uap->vendor->oversampling) {
2272 if (pl011_read(uap, REG_CR)
2273 & ST_UART011_CR_OVSFACT)
2274 *baud *= 2;
2275 }
2276 }
2277 }
2278
2279 static int __init pl011_console_setup(struct console *co, char *options)
2280 {
2281 struct uart_amba_port *uap;
2282 int baud = 38400;
2283 int bits = 8;
2284 int parity = 'n';
2285 int flow = 'n';
2286 int ret;
2287
2288 /*
2289 * Check whether an invalid uart number has been specified, and
2290 * if so, search for the first available port that does have
2291 * console support.
2292 */
2293 if (co->index >= UART_NR)
2294 co->index = 0;
2295 uap = amba_ports[co->index];
2296 if (!uap)
2297 return -ENODEV;
2298
2299 /* Allow pins to be muxed in and configured */
2300 pinctrl_pm_select_default_state(uap->port.dev);
2301
2302 ret = clk_prepare(uap->clk);
2303 if (ret)
2304 return ret;
2305
2306 if (dev_get_platdata(uap->port.dev)) {
2307 struct amba_pl011_data *plat;
2308
2309 plat = dev_get_platdata(uap->port.dev);
2310 if (plat->init)
2311 plat->init();
2312 }
2313
2314 uap->port.uartclk = clk_get_rate(uap->clk);
2315
2316 if (uap->vendor->fixed_options) {
2317 baud = uap->fixed_baud;
2318 } else {
2319 if (options)
2320 uart_parse_options(options,
2321 &baud, &parity, &bits, &flow);
2322 else
2323 pl011_console_get_options(uap, &baud, &parity, &bits);
2324 }
2325
2326 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2327 }
2328
2329 /**
2330 * pl011_console_match - non-standard console matching
2331 * @co: registering console
2332 * @name: name from console command line
2333 * @idx: index from console command line
2334 * @options: ptr to option string from console command line
2335 *
2336 * Only attempts to match console command lines of the form:
2337 * console=pl011,mmio|mmio32,<addr>[,<options>]
2338 * console=pl011,0x<addr>[,<options>]
2339 * This form is used to register an initial earlycon boot console and
2340 * replace it with the amba_console at pl011 driver init.
2341 *
2342 * Performs console setup for a match (as required by interface)
2343 * If no <options> are specified, then assume the h/w is already setup.
2344 *
2345 * Returns 0 if console matches; otherwise non-zero to use default matching
2346 */
2347 static int __init pl011_console_match(struct console *co, char *name, int idx,
2348 char *options)
2349 {
2350 unsigned char iotype;
2351 resource_size_t addr;
2352 int i;
2353
2354 /*
2355 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2356 * have a distinct console name, so make sure we check for that.
2357 * The actual implementation of the erratum occurs in the probe
2358 * function.
2359 */
2360 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
2361 return -ENODEV;
2362
2363 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2364 return -ENODEV;
2365
2366 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2367 return -ENODEV;
2368
2369 /* try to match the port specified on the command line */
2370 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2371 struct uart_port *port;
2372
2373 if (!amba_ports[i])
2374 continue;
2375
2376 port = &amba_ports[i]->port;
2377
2378 if (port->mapbase != addr)
2379 continue;
2380
2381 co->index = i;
2382 port->cons = co;
2383 return pl011_console_setup(co, options);
2384 }
2385
2386 return -ENODEV;
2387 }
2388
2389 static struct uart_driver amba_reg;
2390 static struct console amba_console = {
2391 .name = "ttyAMA",
2392 .write = pl011_console_write,
2393 .device = uart_console_device,
2394 .setup = pl011_console_setup,
2395 .match = pl011_console_match,
2396 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2397 .index = -1,
2398 .data = &amba_reg,
2399 };
2400
2401 #define AMBA_CONSOLE (&amba_console)
2402
2403 static void qdf2400_e44_putc(struct uart_port *port, int c)
2404 {
2405 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2406 cpu_relax();
2407 writel(c, port->membase + UART01x_DR);
2408 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2409 cpu_relax();
2410 }
2411
2412 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2413 {
2414 struct earlycon_device *dev = con->data;
2415
2416 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2417 }
2418
2419 static void pl011_putc(struct uart_port *port, int c)
2420 {
2421 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2422 cpu_relax();
2423 if (port->iotype == UPIO_MEM32)
2424 writel(c, port->membase + UART01x_DR);
2425 else
2426 writeb(c, port->membase + UART01x_DR);
2427 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2428 cpu_relax();
2429 }
2430
2431 static void pl011_early_write(struct console *con, const char *s, unsigned n)
2432 {
2433 struct earlycon_device *dev = con->data;
2434
2435 uart_console_write(&dev->port, s, n, pl011_putc);
2436 }
2437
2438 /*
2439 * On non-ACPI systems, earlycon is enabled by specifying
2440 * "earlycon=pl011,<address>" on the kernel command line.
2441 *
2442 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2443 * by specifying only "earlycon" on the command line. Because it requires
2444 * SPCR, the console starts after ACPI is parsed, which is later than a
2445 * traditional early console.
2446 *
2447 * To get the traditional early console that starts before ACPI is parsed,
2448 * specify the full "earlycon=pl011,<address>" option.
2449 */
2450 static int __init pl011_early_console_setup(struct earlycon_device *device,
2451 const char *opt)
2452 {
2453 if (!device->port.membase)
2454 return -ENODEV;
2455
2456 device->con->write = pl011_early_write;
2457
2458 return 0;
2459 }
2460 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2461 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2462
2463 /*
2464 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2465 * Erratum 44, traditional earlycon can be enabled by specifying
2466 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2467 *
2468 * Alternatively, you can just specify "earlycon", and the early console
2469 * will be enabled with the information from the SPCR table. In this
2470 * case, the SPCR code will detect the need for the E44 work-around,
2471 * and set the console name to "qdf2400_e44".
2472 */
2473 static int __init
2474 qdf2400_e44_early_console_setup(struct earlycon_device *device,
2475 const char *opt)
2476 {
2477 if (!device->port.membase)
2478 return -ENODEV;
2479
2480 device->con->write = qdf2400_e44_early_write;
2481 return 0;
2482 }
2483 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
2484
2485 #else
2486 #define AMBA_CONSOLE NULL
2487 #endif
2488
2489 static struct uart_driver amba_reg = {
2490 .owner = THIS_MODULE,
2491 .driver_name = "ttyAMA",
2492 .dev_name = "ttyAMA",
2493 .major = SERIAL_AMBA_MAJOR,
2494 .minor = SERIAL_AMBA_MINOR,
2495 .nr = UART_NR,
2496 .cons = AMBA_CONSOLE,
2497 };
2498
2499 static int pl011_probe_dt_alias(int index, struct device *dev)
2500 {
2501 struct device_node *np;
2502 static bool seen_dev_with_alias = false;
2503 static bool seen_dev_without_alias = false;
2504 int ret = index;
2505
2506 if (!IS_ENABLED(CONFIG_OF))
2507 return ret;
2508
2509 np = dev->of_node;
2510 if (!np)
2511 return ret;
2512
2513 ret = of_alias_get_id(np, "serial");
2514 if (ret < 0) {
2515 seen_dev_without_alias = true;
2516 ret = index;
2517 } else {
2518 seen_dev_with_alias = true;
2519 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2520 dev_warn(dev, "requested serial port %d not available.\n", ret);
2521 ret = index;
2522 }
2523 }
2524
2525 if (seen_dev_with_alias && seen_dev_without_alias)
2526 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2527
2528 return ret;
2529 }
2530
2531 /* unregisters the driver also if no more ports are left */
2532 static void pl011_unregister_port(struct uart_amba_port *uap)
2533 {
2534 int i;
2535 bool busy = false;
2536
2537 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2538 if (amba_ports[i] == uap)
2539 amba_ports[i] = NULL;
2540 else if (amba_ports[i])
2541 busy = true;
2542 }
2543 pl011_dma_remove(uap);
2544 if (!busy)
2545 uart_unregister_driver(&amba_reg);
2546 }
2547
2548 static int pl011_find_free_port(void)
2549 {
2550 int i;
2551
2552 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2553 if (amba_ports[i] == NULL)
2554 return i;
2555
2556 return -EBUSY;
2557 }
2558
2559 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2560 struct resource *mmiobase, int index)
2561 {
2562 void __iomem *base;
2563
2564 base = devm_ioremap_resource(dev, mmiobase);
2565 if (IS_ERR(base))
2566 return PTR_ERR(base);
2567
2568 index = pl011_probe_dt_alias(index, dev);
2569
2570 uap->old_cr = 0;
2571 uap->port.dev = dev;
2572 uap->port.mapbase = mmiobase->start;
2573 uap->port.membase = base;
2574 uap->port.fifosize = uap->fifosize;
2575 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);
2576 uap->port.flags = UPF_BOOT_AUTOCONF;
2577 uap->port.line = index;
2578 spin_lock_init(&uap->port.lock);
2579
2580 amba_ports[index] = uap;
2581
2582 return 0;
2583 }
2584
2585 static int pl011_register_port(struct uart_amba_port *uap)
2586 {
2587 int ret;
2588
2589 /* Ensure interrupts from this UART are masked and cleared */
2590 pl011_write(0, uap, REG_IMSC);
2591 pl011_write(0xffff, uap, REG_ICR);
2592
2593 if (!amba_reg.state) {
2594 ret = uart_register_driver(&amba_reg);
2595 if (ret < 0) {
2596 dev_err(uap->port.dev,
2597 "Failed to register AMBA-PL011 driver\n");
2598 return ret;
2599 }
2600 }
2601
2602 ret = uart_add_one_port(&amba_reg, &uap->port);
2603 if (ret)
2604 pl011_unregister_port(uap);
2605
2606 return ret;
2607 }
2608
2609 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2610 {
2611 struct uart_amba_port *uap;
2612 struct vendor_data *vendor = id->data;
2613 int portnr, ret;
2614
2615 portnr = pl011_find_free_port();
2616 if (portnr < 0)
2617 return portnr;
2618
2619 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2620 GFP_KERNEL);
2621 if (!uap)
2622 return -ENOMEM;
2623
2624 uap->clk = devm_clk_get(&dev->dev, NULL);
2625 if (IS_ERR(uap->clk))
2626 return PTR_ERR(uap->clk);
2627
2628 uap->reg_offset = vendor->reg_offset;
2629 uap->vendor = vendor;
2630 uap->fifosize = vendor->get_fifosize(dev);
2631 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2632 uap->port.irq = dev->irq[0];
2633 uap->port.ops = &amba_pl011_pops;
2634
2635 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2636
2637 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2638 if (ret)
2639 return ret;
2640
2641 amba_set_drvdata(dev, uap);
2642
2643 return pl011_register_port(uap);
2644 }
2645
2646 static int pl011_remove(struct amba_device *dev)
2647 {
2648 struct uart_amba_port *uap = amba_get_drvdata(dev);
2649
2650 uart_remove_one_port(&amba_reg, &uap->port);
2651 pl011_unregister_port(uap);
2652 return 0;
2653 }
2654
2655 #ifdef CONFIG_PM_SLEEP
2656 static int pl011_suspend(struct device *dev)
2657 {
2658 struct uart_amba_port *uap = dev_get_drvdata(dev);
2659
2660 if (!uap)
2661 return -EINVAL;
2662
2663 return uart_suspend_port(&amba_reg, &uap->port);
2664 }
2665
2666 static int pl011_resume(struct device *dev)
2667 {
2668 struct uart_amba_port *uap = dev_get_drvdata(dev);
2669
2670 if (!uap)
2671 return -EINVAL;
2672
2673 return uart_resume_port(&amba_reg, &uap->port);
2674 }
2675 #endif
2676
2677 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2678
2679 static int sbsa_uart_probe(struct platform_device *pdev)
2680 {
2681 struct uart_amba_port *uap;
2682 struct resource *r;
2683 int portnr, ret;
2684 int baudrate;
2685
2686 /*
2687 * Check the mandatory baud rate parameter in the DT node early
2688 * so that we can easily exit with the error.
2689 */
2690 if (pdev->dev.of_node) {
2691 struct device_node *np = pdev->dev.of_node;
2692
2693 ret = of_property_read_u32(np, "current-speed", &baudrate);
2694 if (ret)
2695 return ret;
2696 } else {
2697 baudrate = 115200;
2698 }
2699
2700 portnr = pl011_find_free_port();
2701 if (portnr < 0)
2702 return portnr;
2703
2704 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2705 GFP_KERNEL);
2706 if (!uap)
2707 return -ENOMEM;
2708
2709 ret = platform_get_irq(pdev, 0);
2710 if (ret < 0)
2711 return ret;
2712 uap->port.irq = ret;
2713
2714 #ifdef CONFIG_ACPI_SPCR_TABLE
2715 if (qdf2400_e44_present) {
2716 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
2717 uap->vendor = &vendor_qdt_qdf2400_e44;
2718 } else
2719 #endif
2720 uap->vendor = &vendor_sbsa;
2721
2722 uap->reg_offset = uap->vendor->reg_offset;
2723 uap->fifosize = 32;
2724 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2725 uap->port.ops = &sbsa_uart_pops;
2726 uap->fixed_baud = baudrate;
2727
2728 snprintf(uap->type, sizeof(uap->type), "SBSA");
2729
2730 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2731
2732 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2733 if (ret)
2734 return ret;
2735
2736 platform_set_drvdata(pdev, uap);
2737
2738 return pl011_register_port(uap);
2739 }
2740
2741 static int sbsa_uart_remove(struct platform_device *pdev)
2742 {
2743 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2744
2745 uart_remove_one_port(&amba_reg, &uap->port);
2746 pl011_unregister_port(uap);
2747 return 0;
2748 }
2749
2750 static const struct of_device_id sbsa_uart_of_match[] = {
2751 { .compatible = "arm,sbsa-uart", },
2752 {},
2753 };
2754 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2755
2756 static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2757 { "ARMH0011", 0 },
2758 {},
2759 };
2760 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2761
2762 static struct platform_driver arm_sbsa_uart_platform_driver = {
2763 .probe = sbsa_uart_probe,
2764 .remove = sbsa_uart_remove,
2765 .driver = {
2766 .name = "sbsa-uart",
2767 .pm = &pl011_dev_pm_ops,
2768 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2769 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2770 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2771 },
2772 };
2773
2774 static const struct amba_id pl011_ids[] = {
2775 {
2776 .id = 0x00041011,
2777 .mask = 0x000fffff,
2778 .data = &vendor_arm,
2779 },
2780 {
2781 .id = 0x00380802,
2782 .mask = 0x00ffffff,
2783 .data = &vendor_st,
2784 },
2785 {
2786 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2787 .mask = 0x00ffffff,
2788 .data = &vendor_zte,
2789 },
2790 { 0, 0 },
2791 };
2792
2793 MODULE_DEVICE_TABLE(amba, pl011_ids);
2794
2795 static struct amba_driver pl011_driver = {
2796 .drv = {
2797 .name = "uart-pl011",
2798 .pm = &pl011_dev_pm_ops,
2799 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2800 },
2801 .id_table = pl011_ids,
2802 .probe = pl011_probe,
2803 .remove = pl011_remove,
2804 };
2805
2806 static int __init pl011_init(void)
2807 {
2808 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2809
2810 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2811 pr_warn("could not register SBSA UART platform driver\n");
2812 return amba_driver_register(&pl011_driver);
2813 }
2814
2815 static void __exit pl011_exit(void)
2816 {
2817 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2818 amba_driver_unregister(&pl011_driver);
2819 }
2820
2821 /*
2822 * While this can be a module, if builtin it's most likely the console
2823 * So let's leave module_exit but move module_init to an earlier place
2824 */
2825 arch_initcall(pl011_init);
2826 module_exit(pl011_exit);
2827
2828 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2829 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2830 MODULE_LICENSE("GPL");
Linux with added FPC-III support