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Revert "tty: hvc: Fix data abort due to race in hvc_open"
[linux/fpc-iii.git] / drivers / tty / serial / imx.c
blobd5979a8bdc406fc9198838c8c264104b01abd23b
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/module.h>
12 #include <linux/ioport.h>
13 #include <linux/init.h>
14 #include <linux/console.h>
15 #include <linux/sysrq.h>
16 #include <linux/platform_device.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/rational.h>
25 #include <linux/slab.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/io.h>
29 #include <linux/dma-mapping.h>
30
31 #include <asm/irq.h>
32 #include <linux/platform_data/serial-imx.h>
33 #include <linux/platform_data/dma-imx.h>
34
35 #include "serial_mctrl_gpio.h"
36
37 /* Register definitions */
38 #define URXD0 0x0 /* Receiver Register */
39 #define URTX0 0x40 /* Transmitter Register */
40 #define UCR1 0x80 /* Control Register 1 */
41 #define UCR2 0x84 /* Control Register 2 */
42 #define UCR3 0x88 /* Control Register 3 */
43 #define UCR4 0x8c /* Control Register 4 */
44 #define UFCR 0x90 /* FIFO Control Register */
45 #define USR1 0x94 /* Status Register 1 */
46 #define USR2 0x98 /* Status Register 2 */
47 #define UESC 0x9c /* Escape Character Register */
48 #define UTIM 0xa0 /* Escape Timer Register */
49 #define UBIR 0xa4 /* BRM Incremental Register */
50 #define UBMR 0xa8 /* BRM Modulator Register */
51 #define UBRC 0xac /* Baud Rate Count Register */
52 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
53 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55
56 /* UART Control Register Bit Fields.*/
57 #define URXD_DUMMY_READ (1<<16)
58 #define URXD_CHARRDY (1<<15)
59 #define URXD_ERR (1<<14)
60 #define URXD_OVRRUN (1<<13)
61 #define URXD_FRMERR (1<<12)
62 #define URXD_BRK (1<<11)
63 #define URXD_PRERR (1<<10)
64 #define URXD_RX_DATA (0xFF<<0)
65 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
66 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
67 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
68 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
69 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
71 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
72 #define UCR1_IREN (1<<7) /* Infrared interface enable */
73 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
74 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
75 #define UCR1_SNDBRK (1<<4) /* Send break */
76 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
77 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
79 #define UCR1_DOZE (1<<1) /* Doze */
80 #define UCR1_UARTEN (1<<0) /* UART enabled */
81 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
82 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
83 #define UCR2_CTSC (1<<13) /* CTS pin control */
84 #define UCR2_CTS (1<<12) /* Clear to send */
85 #define UCR2_ESCEN (1<<11) /* Escape enable */
86 #define UCR2_PREN (1<<8) /* Parity enable */
87 #define UCR2_PROE (1<<7) /* Parity odd/even */
88 #define UCR2_STPB (1<<6) /* Stop */
89 #define UCR2_WS (1<<5) /* Word size */
90 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
91 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
92 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
93 #define UCR2_RXEN (1<<1) /* Receiver enabled */
94 #define UCR2_SRST (1<<0) /* SW reset */
95 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
96 #define UCR3_PARERREN (1<<12) /* Parity enable */
97 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
98 #define UCR3_DSR (1<<10) /* Data set ready */
99 #define UCR3_DCD (1<<9) /* Data carrier detect */
100 #define UCR3_RI (1<<8) /* Ring indicator */
101 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
102 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
103 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
104 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
105 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
106 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
107 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
108 #define UCR3_BPEN (1<<0) /* Preset registers enable */
109 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
110 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
111 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
112 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
113 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
114 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
115 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
116 #define UCR4_IRSC (1<<5) /* IR special case */
117 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
118 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
119 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
120 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
121 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
122 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
123 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
124 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
125 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
126 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
127 #define USR1_RTSS (1<<14) /* RTS pin status */
128 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
129 #define USR1_RTSD (1<<12) /* RTS delta */
130 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
131 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
132 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
133 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
134 #define USR1_DTRD (1<<7) /* DTR Delta */
135 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
136 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
137 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
138 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
139 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
140 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
141 #define USR2_IDLE (1<<12) /* Idle condition */
142 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
143 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
144 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
145 #define USR2_WAKE (1<<7) /* Wake */
146 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
147 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
148 #define USR2_TXDC (1<<3) /* Transmitter complete */
149 #define USR2_BRCD (1<<2) /* Break condition */
150 #define USR2_ORE (1<<1) /* Overrun error */
151 #define USR2_RDR (1<<0) /* Recv data ready */
152 #define UTS_FRCPERR (1<<13) /* Force parity error */
153 #define UTS_LOOP (1<<12) /* Loop tx and rx */
154 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
155 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
156 #define UTS_TXFULL (1<<4) /* TxFIFO full */
157 #define UTS_RXFULL (1<<3) /* RxFIFO full */
158 #define UTS_SOFTRST (1<<0) /* Software reset */
159
160 /* We've been assigned a range on the "Low-density serial ports" major */
161 #define SERIAL_IMX_MAJOR 207
162 #define MINOR_START 16
163 #define DEV_NAME "ttymxc"
164
165 /*
166 * This determines how often we check the modem status signals
167 * for any change. They generally aren't connected to an IRQ
168 * so we have to poll them. We also check immediately before
169 * filling the TX fifo incase CTS has been dropped.
170 */
171 #define MCTRL_TIMEOUT (250*HZ/1000)
172
173 #define DRIVER_NAME "IMX-uart"
174
175 #define UART_NR 8
176
177 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
178 enum imx_uart_type {
179 IMX1_UART,
180 IMX21_UART,
181 IMX53_UART,
182 IMX6Q_UART,
183 };
184
185 /* device type dependent stuff */
186 struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189 };
190
191 struct imx_port {
192 struct uart_port port;
193 struct timer_list timer;
194 unsigned int old_status;
195 unsigned int have_rtscts:1;
196 unsigned int have_rtsgpio:1;
197 unsigned int dte_mode:1;
198 unsigned int inverted_tx:1;
199 unsigned int inverted_rx:1;
200 struct clk *clk_ipg;
201 struct clk *clk_per;
202 const struct imx_uart_data *devdata;
203
204 struct mctrl_gpios *gpios;
205
206 /* shadow registers */
207 unsigned int ucr1;
208 unsigned int ucr2;
209 unsigned int ucr3;
210 unsigned int ucr4;
211 unsigned int ufcr;
212
213 /* DMA fields */
214 unsigned int dma_is_enabled:1;
215 unsigned int dma_is_rxing:1;
216 unsigned int dma_is_txing:1;
217 struct dma_chan *dma_chan_rx, *dma_chan_tx;
218 struct scatterlist rx_sgl, tx_sgl[2];
219 void *rx_buf;
220 struct circ_buf rx_ring;
221 unsigned int rx_periods;
222 dma_cookie_t rx_cookie;
223 unsigned int tx_bytes;
224 unsigned int dma_tx_nents;
225 unsigned int saved_reg[10];
226 bool context_saved;
227 };
228
229 struct imx_port_ucrs {
230 unsigned int ucr1;
231 unsigned int ucr2;
232 unsigned int ucr3;
233 };
234
235 static struct imx_uart_data imx_uart_devdata[] = {
236 [IMX1_UART] = {
237 .uts_reg = IMX1_UTS,
238 .devtype = IMX1_UART,
239 },
240 [IMX21_UART] = {
241 .uts_reg = IMX21_UTS,
242 .devtype = IMX21_UART,
243 },
244 [IMX53_UART] = {
245 .uts_reg = IMX21_UTS,
246 .devtype = IMX53_UART,
247 },
248 [IMX6Q_UART] = {
249 .uts_reg = IMX21_UTS,
250 .devtype = IMX6Q_UART,
251 },
252 };
253
254 static const struct platform_device_id imx_uart_devtype[] = {
255 {
256 .name = "imx1-uart",
257 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
258 }, {
259 .name = "imx21-uart",
260 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
261 }, {
262 .name = "imx53-uart",
263 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
264 }, {
265 .name = "imx6q-uart",
266 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
267 }, {
268 /* sentinel */
269 }
270 };
271 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
272
273 static const struct of_device_id imx_uart_dt_ids[] = {
274 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
275 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
276 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
277 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
278 { /* sentinel */ }
279 };
280 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
281
282 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
283 {
284 switch (offset) {
285 case UCR1:
286 sport->ucr1 = val;
287 break;
288 case UCR2:
289 sport->ucr2 = val;
290 break;
291 case UCR3:
292 sport->ucr3 = val;
293 break;
294 case UCR4:
295 sport->ucr4 = val;
296 break;
297 case UFCR:
298 sport->ufcr = val;
299 break;
300 default:
301 break;
302 }
303 writel(val, sport->port.membase + offset);
304 }
305
306 static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
307 {
308 switch (offset) {
309 case UCR1:
310 return sport->ucr1;
311 break;
312 case UCR2:
313 /*
314 * UCR2_SRST is the only bit in the cached registers that might
315 * differ from the value that was last written. As it only
316 * automatically becomes one after being cleared, reread
317 * conditionally.
318 */
319 if (!(sport->ucr2 & UCR2_SRST))
320 sport->ucr2 = readl(sport->port.membase + offset);
321 return sport->ucr2;
322 break;
323 case UCR3:
324 return sport->ucr3;
325 break;
326 case UCR4:
327 return sport->ucr4;
328 break;
329 case UFCR:
330 return sport->ufcr;
331 break;
332 default:
333 return readl(sport->port.membase + offset);
334 }
335 }
336
337 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
338 {
339 return sport->devdata->uts_reg;
340 }
341
342 static inline int imx_uart_is_imx1(struct imx_port *sport)
343 {
344 return sport->devdata->devtype == IMX1_UART;
345 }
346
347 static inline int imx_uart_is_imx21(struct imx_port *sport)
348 {
349 return sport->devdata->devtype == IMX21_UART;
350 }
351
352 static inline int imx_uart_is_imx53(struct imx_port *sport)
353 {
354 return sport->devdata->devtype == IMX53_UART;
355 }
356
357 static inline int imx_uart_is_imx6q(struct imx_port *sport)
358 {
359 return sport->devdata->devtype == IMX6Q_UART;
360 }
361 /*
362 * Save and restore functions for UCR1, UCR2 and UCR3 registers
363 */
364 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
365 static void imx_uart_ucrs_save(struct imx_port *sport,
366 struct imx_port_ucrs *ucr)
367 {
368 /* save control registers */
369 ucr->ucr1 = imx_uart_readl(sport, UCR1);
370 ucr->ucr2 = imx_uart_readl(sport, UCR2);
371 ucr->ucr3 = imx_uart_readl(sport, UCR3);
372 }
373
374 static void imx_uart_ucrs_restore(struct imx_port *sport,
375 struct imx_port_ucrs *ucr)
376 {
377 /* restore control registers */
378 imx_uart_writel(sport, ucr->ucr1, UCR1);
379 imx_uart_writel(sport, ucr->ucr2, UCR2);
380 imx_uart_writel(sport, ucr->ucr3, UCR3);
381 }
382 #endif
383
384 /* called with port.lock taken and irqs caller dependent */
385 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
386 {
387 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
388
389 sport->port.mctrl |= TIOCM_RTS;
390 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
391 }
392
393 /* called with port.lock taken and irqs caller dependent */
394 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
395 {
396 *ucr2 &= ~UCR2_CTSC;
397 *ucr2 |= UCR2_CTS;
398
399 sport->port.mctrl &= ~TIOCM_RTS;
400 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
401 }
402
403 /* called with port.lock taken and irqs off */
404 static void imx_uart_start_rx(struct uart_port *port)
405 {
406 struct imx_port *sport = (struct imx_port *)port;
407 unsigned int ucr1, ucr2;
408
409 ucr1 = imx_uart_readl(sport, UCR1);
410 ucr2 = imx_uart_readl(sport, UCR2);
411
412 ucr2 |= UCR2_RXEN;
413
414 if (sport->dma_is_enabled) {
415 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
416 } else {
417 ucr1 |= UCR1_RRDYEN;
418 ucr2 |= UCR2_ATEN;
419 }
420
421 /* Write UCR2 first as it includes RXEN */
422 imx_uart_writel(sport, ucr2, UCR2);
423 imx_uart_writel(sport, ucr1, UCR1);
424 }
425
426 /* called with port.lock taken and irqs off */
427 static void imx_uart_stop_tx(struct uart_port *port)
428 {
429 struct imx_port *sport = (struct imx_port *)port;
430 u32 ucr1;
431
432 /*
433 * We are maybe in the SMP context, so if the DMA TX thread is running
434 * on other cpu, we have to wait for it to finish.
435 */
436 if (sport->dma_is_txing)
437 return;
438
439 ucr1 = imx_uart_readl(sport, UCR1);
440 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
441
442 /* in rs485 mode disable transmitter if shifter is empty */
443 if (port->rs485.flags & SER_RS485_ENABLED &&
444 imx_uart_readl(sport, USR2) & USR2_TXDC) {
445 u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4;
446 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
447 imx_uart_rts_active(sport, &ucr2);
448 else
449 imx_uart_rts_inactive(sport, &ucr2);
450 imx_uart_writel(sport, ucr2, UCR2);
451
452 imx_uart_start_rx(port);
453
454 ucr4 = imx_uart_readl(sport, UCR4);
455 ucr4 &= ~UCR4_TCEN;
456 imx_uart_writel(sport, ucr4, UCR4);
457 }
458 }
459
460 /* called with port.lock taken and irqs off */
461 static void imx_uart_stop_rx(struct uart_port *port)
462 {
463 struct imx_port *sport = (struct imx_port *)port;
464 u32 ucr1, ucr2;
465
466 ucr1 = imx_uart_readl(sport, UCR1);
467 ucr2 = imx_uart_readl(sport, UCR2);
468
469 if (sport->dma_is_enabled) {
470 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
471 } else {
472 ucr1 &= ~UCR1_RRDYEN;
473 ucr2 &= ~UCR2_ATEN;
474 }
475 imx_uart_writel(sport, ucr1, UCR1);
476
477 ucr2 &= ~UCR2_RXEN;
478 imx_uart_writel(sport, ucr2, UCR2);
479 }
480
481 /* called with port.lock taken and irqs off */
482 static void imx_uart_enable_ms(struct uart_port *port)
483 {
484 struct imx_port *sport = (struct imx_port *)port;
485
486 mod_timer(&sport->timer, jiffies);
487
488 mctrl_gpio_enable_ms(sport->gpios);
489 }
490
491 static void imx_uart_dma_tx(struct imx_port *sport);
492
493 /* called with port.lock taken and irqs off */
494 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
495 {
496 struct circ_buf *xmit = &sport->port.state->xmit;
497
498 if (sport->port.x_char) {
499 /* Send next char */
500 imx_uart_writel(sport, sport->port.x_char, URTX0);
501 sport->port.icount.tx++;
502 sport->port.x_char = 0;
503 return;
504 }
505
506 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
507 imx_uart_stop_tx(&sport->port);
508 return;
509 }
510
511 if (sport->dma_is_enabled) {
512 u32 ucr1;
513 /*
514 * We've just sent a X-char Ensure the TX DMA is enabled
515 * and the TX IRQ is disabled.
516 **/
517 ucr1 = imx_uart_readl(sport, UCR1);
518 ucr1 &= ~UCR1_TRDYEN;
519 if (sport->dma_is_txing) {
520 ucr1 |= UCR1_TXDMAEN;
521 imx_uart_writel(sport, ucr1, UCR1);
522 } else {
523 imx_uart_writel(sport, ucr1, UCR1);
524 imx_uart_dma_tx(sport);
525 }
526
527 return;
528 }
529
530 while (!uart_circ_empty(xmit) &&
531 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
532 /* send xmit->buf[xmit->tail]
533 * out the port here */
534 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
535 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
536 sport->port.icount.tx++;
537 }
538
539 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
540 uart_write_wakeup(&sport->port);
541
542 if (uart_circ_empty(xmit))
543 imx_uart_stop_tx(&sport->port);
544 }
545
546 static void imx_uart_dma_tx_callback(void *data)
547 {
548 struct imx_port *sport = data;
549 struct scatterlist *sgl = &sport->tx_sgl[0];
550 struct circ_buf *xmit = &sport->port.state->xmit;
551 unsigned long flags;
552 u32 ucr1;
553
554 spin_lock_irqsave(&sport->port.lock, flags);
555
556 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
557
558 ucr1 = imx_uart_readl(sport, UCR1);
559 ucr1 &= ~UCR1_TXDMAEN;
560 imx_uart_writel(sport, ucr1, UCR1);
561
562 /* update the stat */
563 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
564 sport->port.icount.tx += sport->tx_bytes;
565
566 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
567
568 sport->dma_is_txing = 0;
569
570 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
571 uart_write_wakeup(&sport->port);
572
573 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
574 imx_uart_dma_tx(sport);
575 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
576 u32 ucr4 = imx_uart_readl(sport, UCR4);
577 ucr4 |= UCR4_TCEN;
578 imx_uart_writel(sport, ucr4, UCR4);
579 }
580
581 spin_unlock_irqrestore(&sport->port.lock, flags);
582 }
583
584 /* called with port.lock taken and irqs off */
585 static void imx_uart_dma_tx(struct imx_port *sport)
586 {
587 struct circ_buf *xmit = &sport->port.state->xmit;
588 struct scatterlist *sgl = sport->tx_sgl;
589 struct dma_async_tx_descriptor *desc;
590 struct dma_chan *chan = sport->dma_chan_tx;
591 struct device *dev = sport->port.dev;
592 u32 ucr1, ucr4;
593 int ret;
594
595 if (sport->dma_is_txing)
596 return;
597
598 ucr4 = imx_uart_readl(sport, UCR4);
599 ucr4 &= ~UCR4_TCEN;
600 imx_uart_writel(sport, ucr4, UCR4);
601
602 sport->tx_bytes = uart_circ_chars_pending(xmit);
603
604 if (xmit->tail < xmit->head || xmit->head == 0) {
605 sport->dma_tx_nents = 1;
606 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
607 } else {
608 sport->dma_tx_nents = 2;
609 sg_init_table(sgl, 2);
610 sg_set_buf(sgl, xmit->buf + xmit->tail,
611 UART_XMIT_SIZE - xmit->tail);
612 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
613 }
614
615 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
616 if (ret == 0) {
617 dev_err(dev, "DMA mapping error for TX.\n");
618 return;
619 }
620 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
621 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
622 if (!desc) {
623 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
624 DMA_TO_DEVICE);
625 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
626 return;
627 }
628 desc->callback = imx_uart_dma_tx_callback;
629 desc->callback_param = sport;
630
631 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
632 uart_circ_chars_pending(xmit));
633
634 ucr1 = imx_uart_readl(sport, UCR1);
635 ucr1 |= UCR1_TXDMAEN;
636 imx_uart_writel(sport, ucr1, UCR1);
637
638 /* fire it */
639 sport->dma_is_txing = 1;
640 dmaengine_submit(desc);
641 dma_async_issue_pending(chan);
642 return;
643 }
644
645 /* called with port.lock taken and irqs off */
646 static void imx_uart_start_tx(struct uart_port *port)
647 {
648 struct imx_port *sport = (struct imx_port *)port;
649 u32 ucr1;
650
651 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
652 return;
653
654 if (port->rs485.flags & SER_RS485_ENABLED) {
655 u32 ucr2;
656
657 ucr2 = imx_uart_readl(sport, UCR2);
658 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
659 imx_uart_rts_active(sport, &ucr2);
660 else
661 imx_uart_rts_inactive(sport, &ucr2);
662 imx_uart_writel(sport, ucr2, UCR2);
663
664 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
665 imx_uart_stop_rx(port);
666
667 /*
668 * Enable transmitter and shifter empty irq only if DMA is off.
669 * In the DMA case this is done in the tx-callback.
670 */
671 if (!sport->dma_is_enabled) {
672 u32 ucr4 = imx_uart_readl(sport, UCR4);
673 ucr4 |= UCR4_TCEN;
674 imx_uart_writel(sport, ucr4, UCR4);
675 }
676 }
677
678 if (!sport->dma_is_enabled) {
679 ucr1 = imx_uart_readl(sport, UCR1);
680 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
681 }
682
683 if (sport->dma_is_enabled) {
684 if (sport->port.x_char) {
685 /* We have X-char to send, so enable TX IRQ and
686 * disable TX DMA to let TX interrupt to send X-char */
687 ucr1 = imx_uart_readl(sport, UCR1);
688 ucr1 &= ~UCR1_TXDMAEN;
689 ucr1 |= UCR1_TRDYEN;
690 imx_uart_writel(sport, ucr1, UCR1);
691 return;
692 }
693
694 if (!uart_circ_empty(&port->state->xmit) &&
695 !uart_tx_stopped(port))
696 imx_uart_dma_tx(sport);
697 return;
698 }
699 }
700
701 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
702 {
703 struct imx_port *sport = dev_id;
704 u32 usr1;
705
706 imx_uart_writel(sport, USR1_RTSD, USR1);
707 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
708 uart_handle_cts_change(&sport->port, !!usr1);
709 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
710
711 return IRQ_HANDLED;
712 }
713
714 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
715 {
716 struct imx_port *sport = dev_id;
717 irqreturn_t ret;
718
719 spin_lock(&sport->port.lock);
720
721 ret = __imx_uart_rtsint(irq, dev_id);
722
723 spin_unlock(&sport->port.lock);
724
725 return ret;
726 }
727
728 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
729 {
730 struct imx_port *sport = dev_id;
731
732 spin_lock(&sport->port.lock);
733 imx_uart_transmit_buffer(sport);
734 spin_unlock(&sport->port.lock);
735 return IRQ_HANDLED;
736 }
737
738 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
739 {
740 struct imx_port *sport = dev_id;
741 unsigned int rx, flg, ignored = 0;
742 struct tty_port *port = &sport->port.state->port;
743
744 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
745 u32 usr2;
746
747 flg = TTY_NORMAL;
748 sport->port.icount.rx++;
749
750 rx = imx_uart_readl(sport, URXD0);
751
752 usr2 = imx_uart_readl(sport, USR2);
753 if (usr2 & USR2_BRCD) {
754 imx_uart_writel(sport, USR2_BRCD, USR2);
755 if (uart_handle_break(&sport->port))
756 continue;
757 }
758
759 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
760 continue;
761
762 if (unlikely(rx & URXD_ERR)) {
763 if (rx & URXD_BRK)
764 sport->port.icount.brk++;
765 else if (rx & URXD_PRERR)
766 sport->port.icount.parity++;
767 else if (rx & URXD_FRMERR)
768 sport->port.icount.frame++;
769 if (rx & URXD_OVRRUN)
770 sport->port.icount.overrun++;
771
772 if (rx & sport->port.ignore_status_mask) {
773 if (++ignored > 100)
774 goto out;
775 continue;
776 }
777
778 rx &= (sport->port.read_status_mask | 0xFF);
779
780 if (rx & URXD_BRK)
781 flg = TTY_BREAK;
782 else if (rx & URXD_PRERR)
783 flg = TTY_PARITY;
784 else if (rx & URXD_FRMERR)
785 flg = TTY_FRAME;
786 if (rx & URXD_OVRRUN)
787 flg = TTY_OVERRUN;
788
789 sport->port.sysrq = 0;
790 }
791
792 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
793 goto out;
794
795 if (tty_insert_flip_char(port, rx, flg) == 0)
796 sport->port.icount.buf_overrun++;
797 }
798
799 out:
800 tty_flip_buffer_push(port);
801
802 return IRQ_HANDLED;
803 }
804
805 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
806 {
807 struct imx_port *sport = dev_id;
808 irqreturn_t ret;
809
810 spin_lock(&sport->port.lock);
811
812 ret = __imx_uart_rxint(irq, dev_id);
813
814 spin_unlock(&sport->port.lock);
815
816 return ret;
817 }
818
819 static void imx_uart_clear_rx_errors(struct imx_port *sport);
820
821 /*
822 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
823 */
824 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
825 {
826 unsigned int tmp = TIOCM_DSR;
827 unsigned usr1 = imx_uart_readl(sport, USR1);
828 unsigned usr2 = imx_uart_readl(sport, USR2);
829
830 if (usr1 & USR1_RTSS)
831 tmp |= TIOCM_CTS;
832
833 /* in DCE mode DCDIN is always 0 */
834 if (!(usr2 & USR2_DCDIN))
835 tmp |= TIOCM_CAR;
836
837 if (sport->dte_mode)
838 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
839 tmp |= TIOCM_RI;
840
841 return tmp;
842 }
843
844 /*
845 * Handle any change of modem status signal since we were last called.
846 */
847 static void imx_uart_mctrl_check(struct imx_port *sport)
848 {
849 unsigned int status, changed;
850
851 status = imx_uart_get_hwmctrl(sport);
852 changed = status ^ sport->old_status;
853
854 if (changed == 0)
855 return;
856
857 sport->old_status = status;
858
859 if (changed & TIOCM_RI && status & TIOCM_RI)
860 sport->port.icount.rng++;
861 if (changed & TIOCM_DSR)
862 sport->port.icount.dsr++;
863 if (changed & TIOCM_CAR)
864 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
865 if (changed & TIOCM_CTS)
866 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
867
868 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
869 }
870
871 static irqreturn_t imx_uart_int(int irq, void *dev_id)
872 {
873 struct imx_port *sport = dev_id;
874 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
875 irqreturn_t ret = IRQ_NONE;
876
877 spin_lock(&sport->port.lock);
878
879 usr1 = imx_uart_readl(sport, USR1);
880 usr2 = imx_uart_readl(sport, USR2);
881 ucr1 = imx_uart_readl(sport, UCR1);
882 ucr2 = imx_uart_readl(sport, UCR2);
883 ucr3 = imx_uart_readl(sport, UCR3);
884 ucr4 = imx_uart_readl(sport, UCR4);
885
886 /*
887 * Even if a condition is true that can trigger an irq only handle it if
888 * the respective irq source is enabled. This prevents some undesired
889 * actions, for example if a character that sits in the RX FIFO and that
890 * should be fetched via DMA is tried to be fetched using PIO. Or the
891 * receiver is currently off and so reading from URXD0 results in an
892 * exception. So just mask the (raw) status bits for disabled irqs.
893 */
894 if ((ucr1 & UCR1_RRDYEN) == 0)
895 usr1 &= ~USR1_RRDY;
896 if ((ucr2 & UCR2_ATEN) == 0)
897 usr1 &= ~USR1_AGTIM;
898 if ((ucr1 & UCR1_TRDYEN) == 0)
899 usr1 &= ~USR1_TRDY;
900 if ((ucr4 & UCR4_TCEN) == 0)
901 usr2 &= ~USR2_TXDC;
902 if ((ucr3 & UCR3_DTRDEN) == 0)
903 usr1 &= ~USR1_DTRD;
904 if ((ucr1 & UCR1_RTSDEN) == 0)
905 usr1 &= ~USR1_RTSD;
906 if ((ucr3 & UCR3_AWAKEN) == 0)
907 usr1 &= ~USR1_AWAKE;
908 if ((ucr4 & UCR4_OREN) == 0)
909 usr2 &= ~USR2_ORE;
910
911 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
912 __imx_uart_rxint(irq, dev_id);
913 ret = IRQ_HANDLED;
914 }
915
916 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
917 imx_uart_transmit_buffer(sport);
918 ret = IRQ_HANDLED;
919 }
920
921 if (usr1 & USR1_DTRD) {
922 imx_uart_writel(sport, USR1_DTRD, USR1);
923
924 imx_uart_mctrl_check(sport);
925
926 ret = IRQ_HANDLED;
927 }
928
929 if (usr1 & USR1_RTSD) {
930 __imx_uart_rtsint(irq, dev_id);
931 ret = IRQ_HANDLED;
932 }
933
934 if (usr1 & USR1_AWAKE) {
935 imx_uart_writel(sport, USR1_AWAKE, USR1);
936 ret = IRQ_HANDLED;
937 }
938
939 if (usr2 & USR2_ORE) {
940 sport->port.icount.overrun++;
941 imx_uart_writel(sport, USR2_ORE, USR2);
942 ret = IRQ_HANDLED;
943 }
944
945 spin_unlock(&sport->port.lock);
946
947 return ret;
948 }
949
950 /*
951 * Return TIOCSER_TEMT when transmitter is not busy.
952 */
953 static unsigned int imx_uart_tx_empty(struct uart_port *port)
954 {
955 struct imx_port *sport = (struct imx_port *)port;
956 unsigned int ret;
957
958 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
959
960 /* If the TX DMA is working, return 0. */
961 if (sport->dma_is_txing)
962 ret = 0;
963
964 return ret;
965 }
966
967 /* called with port.lock taken and irqs off */
968 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
969 {
970 struct imx_port *sport = (struct imx_port *)port;
971 unsigned int ret = imx_uart_get_hwmctrl(sport);
972
973 mctrl_gpio_get(sport->gpios, &ret);
974
975 return ret;
976 }
977
978 /* called with port.lock taken and irqs off */
979 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
980 {
981 struct imx_port *sport = (struct imx_port *)port;
982 u32 ucr3, uts;
983
984 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
985 u32 ucr2;
986
987 /*
988 * Turn off autoRTS if RTS is lowered and restore autoRTS
989 * setting if RTS is raised.
990 */
991 ucr2 = imx_uart_readl(sport, UCR2);
992 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
993 if (mctrl & TIOCM_RTS) {
994 ucr2 |= UCR2_CTS;
995 /*
996 * UCR2_IRTS is unset if and only if the port is
997 * configured for CRTSCTS, so we use inverted UCR2_IRTS
998 * to get the state to restore to.
999 */
1000 if (!(ucr2 & UCR2_IRTS))
1001 ucr2 |= UCR2_CTSC;
1002 }
1003 imx_uart_writel(sport, ucr2, UCR2);
1004 }
1005
1006 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1007 if (!(mctrl & TIOCM_DTR))
1008 ucr3 |= UCR3_DSR;
1009 imx_uart_writel(sport, ucr3, UCR3);
1010
1011 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1012 if (mctrl & TIOCM_LOOP)
1013 uts |= UTS_LOOP;
1014 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1015
1016 mctrl_gpio_set(sport->gpios, mctrl);
1017 }
1018
1019 /*
1020 * Interrupts always disabled.
1021 */
1022 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1023 {
1024 struct imx_port *sport = (struct imx_port *)port;
1025 unsigned long flags;
1026 u32 ucr1;
1027
1028 spin_lock_irqsave(&sport->port.lock, flags);
1029
1030 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1031
1032 if (break_state != 0)
1033 ucr1 |= UCR1_SNDBRK;
1034
1035 imx_uart_writel(sport, ucr1, UCR1);
1036
1037 spin_unlock_irqrestore(&sport->port.lock, flags);
1038 }
1039
1040 /*
1041 * This is our per-port timeout handler, for checking the
1042 * modem status signals.
1043 */
1044 static void imx_uart_timeout(struct timer_list *t)
1045 {
1046 struct imx_port *sport = from_timer(sport, t, timer);
1047 unsigned long flags;
1048
1049 if (sport->port.state) {
1050 spin_lock_irqsave(&sport->port.lock, flags);
1051 imx_uart_mctrl_check(sport);
1052 spin_unlock_irqrestore(&sport->port.lock, flags);
1053
1054 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1055 }
1056 }
1057
1058 /*
1059 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1060 * [1] the RX DMA buffer is full.
1061 * [2] the aging timer expires
1062 *
1063 * Condition [2] is triggered when a character has been sitting in the FIFO
1064 * for at least 8 byte durations.
1065 */
1066 static void imx_uart_dma_rx_callback(void *data)
1067 {
1068 struct imx_port *sport = data;
1069 struct dma_chan *chan = sport->dma_chan_rx;
1070 struct scatterlist *sgl = &sport->rx_sgl;
1071 struct tty_port *port = &sport->port.state->port;
1072 struct dma_tx_state state;
1073 struct circ_buf *rx_ring = &sport->rx_ring;
1074 enum dma_status status;
1075 unsigned int w_bytes = 0;
1076 unsigned int r_bytes;
1077 unsigned int bd_size;
1078
1079 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1080
1081 if (status == DMA_ERROR) {
1082 imx_uart_clear_rx_errors(sport);
1083 return;
1084 }
1085
1086 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1087
1088 /*
1089 * The state-residue variable represents the empty space
1090 * relative to the entire buffer. Taking this in consideration
1091 * the head is always calculated base on the buffer total
1092 * length - DMA transaction residue. The UART script from the
1093 * SDMA firmware will jump to the next buffer descriptor,
1094 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1095 * Taking this in consideration the tail is always at the
1096 * beginning of the buffer descriptor that contains the head.
1097 */
1098
1099 /* Calculate the head */
1100 rx_ring->head = sg_dma_len(sgl) - state.residue;
1101
1102 /* Calculate the tail. */
1103 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1104 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1105
1106 if (rx_ring->head <= sg_dma_len(sgl) &&
1107 rx_ring->head > rx_ring->tail) {
1108
1109 /* Move data from tail to head */
1110 r_bytes = rx_ring->head - rx_ring->tail;
1111
1112 /* CPU claims ownership of RX DMA buffer */
1113 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1114 DMA_FROM_DEVICE);
1115
1116 w_bytes = tty_insert_flip_string(port,
1117 sport->rx_buf + rx_ring->tail, r_bytes);
1118
1119 /* UART retrieves ownership of RX DMA buffer */
1120 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1121 DMA_FROM_DEVICE);
1122
1123 if (w_bytes != r_bytes)
1124 sport->port.icount.buf_overrun++;
1125
1126 sport->port.icount.rx += w_bytes;
1127 } else {
1128 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1129 WARN_ON(rx_ring->head <= rx_ring->tail);
1130 }
1131 }
1132
1133 if (w_bytes) {
1134 tty_flip_buffer_push(port);
1135 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1136 }
1137 }
1138
1139 /* RX DMA buffer periods */
1140 #define RX_DMA_PERIODS 16
1141 #define RX_BUF_SIZE (RX_DMA_PERIODS * PAGE_SIZE / 4)
1142
1143 static int imx_uart_start_rx_dma(struct imx_port *sport)
1144 {
1145 struct scatterlist *sgl = &sport->rx_sgl;
1146 struct dma_chan *chan = sport->dma_chan_rx;
1147 struct device *dev = sport->port.dev;
1148 struct dma_async_tx_descriptor *desc;
1149 int ret;
1150
1151 sport->rx_ring.head = 0;
1152 sport->rx_ring.tail = 0;
1153 sport->rx_periods = RX_DMA_PERIODS;
1154
1155 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1156 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1157 if (ret == 0) {
1158 dev_err(dev, "DMA mapping error for RX.\n");
1159 return -EINVAL;
1160 }
1161
1162 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1163 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1164 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1165
1166 if (!desc) {
1167 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1168 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1169 return -EINVAL;
1170 }
1171 desc->callback = imx_uart_dma_rx_callback;
1172 desc->callback_param = sport;
1173
1174 dev_dbg(dev, "RX: prepare for the DMA.\n");
1175 sport->dma_is_rxing = 1;
1176 sport->rx_cookie = dmaengine_submit(desc);
1177 dma_async_issue_pending(chan);
1178 return 0;
1179 }
1180
1181 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1182 {
1183 struct tty_port *port = &sport->port.state->port;
1184 u32 usr1, usr2;
1185
1186 usr1 = imx_uart_readl(sport, USR1);
1187 usr2 = imx_uart_readl(sport, USR2);
1188
1189 if (usr2 & USR2_BRCD) {
1190 sport->port.icount.brk++;
1191 imx_uart_writel(sport, USR2_BRCD, USR2);
1192 uart_handle_break(&sport->port);
1193 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1194 sport->port.icount.buf_overrun++;
1195 tty_flip_buffer_push(port);
1196 } else {
1197 if (usr1 & USR1_FRAMERR) {
1198 sport->port.icount.frame++;
1199 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1200 } else if (usr1 & USR1_PARITYERR) {
1201 sport->port.icount.parity++;
1202 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1203 }
1204 }
1205
1206 if (usr2 & USR2_ORE) {
1207 sport->port.icount.overrun++;
1208 imx_uart_writel(sport, USR2_ORE, USR2);
1209 }
1210
1211 }
1212
1213 #define TXTL_DEFAULT 2 /* reset default */
1214 #define RXTL_DEFAULT 1 /* reset default */
1215 #define TXTL_DMA 8 /* DMA burst setting */
1216 #define RXTL_DMA 9 /* DMA burst setting */
1217
1218 static void imx_uart_setup_ufcr(struct imx_port *sport,
1219 unsigned char txwl, unsigned char rxwl)
1220 {
1221 unsigned int val;
1222
1223 /* set receiver / transmitter trigger level */
1224 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1225 val |= txwl << UFCR_TXTL_SHF | rxwl;
1226 imx_uart_writel(sport, val, UFCR);
1227 }
1228
1229 static void imx_uart_dma_exit(struct imx_port *sport)
1230 {
1231 if (sport->dma_chan_rx) {
1232 dmaengine_terminate_sync(sport->dma_chan_rx);
1233 dma_release_channel(sport->dma_chan_rx);
1234 sport->dma_chan_rx = NULL;
1235 sport->rx_cookie = -EINVAL;
1236 kfree(sport->rx_buf);
1237 sport->rx_buf = NULL;
1238 }
1239
1240 if (sport->dma_chan_tx) {
1241 dmaengine_terminate_sync(sport->dma_chan_tx);
1242 dma_release_channel(sport->dma_chan_tx);
1243 sport->dma_chan_tx = NULL;
1244 }
1245 }
1246
1247 static int imx_uart_dma_init(struct imx_port *sport)
1248 {
1249 struct dma_slave_config slave_config = {};
1250 struct device *dev = sport->port.dev;
1251 int ret;
1252
1253 /* Prepare for RX : */
1254 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1255 if (!sport->dma_chan_rx) {
1256 dev_dbg(dev, "cannot get the DMA channel.\n");
1257 ret = -EINVAL;
1258 goto err;
1259 }
1260
1261 slave_config.direction = DMA_DEV_TO_MEM;
1262 slave_config.src_addr = sport->port.mapbase + URXD0;
1263 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1264 /* one byte less than the watermark level to enable the aging timer */
1265 slave_config.src_maxburst = RXTL_DMA - 1;
1266 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1267 if (ret) {
1268 dev_err(dev, "error in RX dma configuration.\n");
1269 goto err;
1270 }
1271
1272 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
1273 if (!sport->rx_buf) {
1274 ret = -ENOMEM;
1275 goto err;
1276 }
1277 sport->rx_ring.buf = sport->rx_buf;
1278
1279 /* Prepare for TX : */
1280 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1281 if (!sport->dma_chan_tx) {
1282 dev_err(dev, "cannot get the TX DMA channel!\n");
1283 ret = -EINVAL;
1284 goto err;
1285 }
1286
1287 slave_config.direction = DMA_MEM_TO_DEV;
1288 slave_config.dst_addr = sport->port.mapbase + URTX0;
1289 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1290 slave_config.dst_maxburst = TXTL_DMA;
1291 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1292 if (ret) {
1293 dev_err(dev, "error in TX dma configuration.");
1294 goto err;
1295 }
1296
1297 return 0;
1298 err:
1299 imx_uart_dma_exit(sport);
1300 return ret;
1301 }
1302
1303 static void imx_uart_enable_dma(struct imx_port *sport)
1304 {
1305 u32 ucr1;
1306
1307 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1308
1309 /* set UCR1 */
1310 ucr1 = imx_uart_readl(sport, UCR1);
1311 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1312 imx_uart_writel(sport, ucr1, UCR1);
1313
1314 sport->dma_is_enabled = 1;
1315 }
1316
1317 static void imx_uart_disable_dma(struct imx_port *sport)
1318 {
1319 u32 ucr1;
1320
1321 /* clear UCR1 */
1322 ucr1 = imx_uart_readl(sport, UCR1);
1323 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1324 imx_uart_writel(sport, ucr1, UCR1);
1325
1326 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1327
1328 sport->dma_is_enabled = 0;
1329 }
1330
1331 /* half the RX buffer size */
1332 #define CTSTL 16
1333
1334 static int imx_uart_startup(struct uart_port *port)
1335 {
1336 struct imx_port *sport = (struct imx_port *)port;
1337 int retval, i;
1338 unsigned long flags;
1339 int dma_is_inited = 0;
1340 u32 ucr1, ucr2, ucr3, ucr4;
1341
1342 retval = clk_prepare_enable(sport->clk_per);
1343 if (retval)
1344 return retval;
1345 retval = clk_prepare_enable(sport->clk_ipg);
1346 if (retval) {
1347 clk_disable_unprepare(sport->clk_per);
1348 return retval;
1349 }
1350
1351 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1352
1353 /* disable the DREN bit (Data Ready interrupt enable) before
1354 * requesting IRQs
1355 */
1356 ucr4 = imx_uart_readl(sport, UCR4);
1357
1358 /* set the trigger level for CTS */
1359 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1360 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1361
1362 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1363
1364 /* Can we enable the DMA support? */
1365 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1366 dma_is_inited = 1;
1367
1368 spin_lock_irqsave(&sport->port.lock, flags);
1369 /* Reset fifo's and state machines */
1370 i = 100;
1371
1372 ucr2 = imx_uart_readl(sport, UCR2);
1373 ucr2 &= ~UCR2_SRST;
1374 imx_uart_writel(sport, ucr2, UCR2);
1375
1376 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1377 udelay(1);
1378
1379 /*
1380 * Finally, clear and enable interrupts
1381 */
1382 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1383 imx_uart_writel(sport, USR2_ORE, USR2);
1384
1385 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1386 ucr1 |= UCR1_UARTEN;
1387 if (sport->have_rtscts)
1388 ucr1 |= UCR1_RTSDEN;
1389
1390 imx_uart_writel(sport, ucr1, UCR1);
1391
1392 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1393 if (!sport->dma_is_enabled)
1394 ucr4 |= UCR4_OREN;
1395 if (sport->inverted_rx)
1396 ucr4 |= UCR4_INVR;
1397 imx_uart_writel(sport, ucr4, UCR4);
1398
1399 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1400 /*
1401 * configure tx polarity before enabling tx
1402 */
1403 if (sport->inverted_tx)
1404 ucr3 |= UCR3_INVT;
1405
1406 if (!imx_uart_is_imx1(sport)) {
1407 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1408
1409 if (sport->dte_mode)
1410 /* disable broken interrupts */
1411 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1412 }
1413 imx_uart_writel(sport, ucr3, UCR3);
1414
1415 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1416 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1417 if (!sport->have_rtscts)
1418 ucr2 |= UCR2_IRTS;
1419 /*
1420 * make sure the edge sensitive RTS-irq is disabled,
1421 * we're using RTSD instead.
1422 */
1423 if (!imx_uart_is_imx1(sport))
1424 ucr2 &= ~UCR2_RTSEN;
1425 imx_uart_writel(sport, ucr2, UCR2);
1426
1427 /*
1428 * Enable modem status interrupts
1429 */
1430 imx_uart_enable_ms(&sport->port);
1431
1432 if (dma_is_inited) {
1433 imx_uart_enable_dma(sport);
1434 imx_uart_start_rx_dma(sport);
1435 } else {
1436 ucr1 = imx_uart_readl(sport, UCR1);
1437 ucr1 |= UCR1_RRDYEN;
1438 imx_uart_writel(sport, ucr1, UCR1);
1439
1440 ucr2 = imx_uart_readl(sport, UCR2);
1441 ucr2 |= UCR2_ATEN;
1442 imx_uart_writel(sport, ucr2, UCR2);
1443 }
1444
1445 spin_unlock_irqrestore(&sport->port.lock, flags);
1446
1447 return 0;
1448 }
1449
1450 static void imx_uart_shutdown(struct uart_port *port)
1451 {
1452 struct imx_port *sport = (struct imx_port *)port;
1453 unsigned long flags;
1454 u32 ucr1, ucr2, ucr4;
1455
1456 if (sport->dma_is_enabled) {
1457 dmaengine_terminate_sync(sport->dma_chan_tx);
1458 if (sport->dma_is_txing) {
1459 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1460 sport->dma_tx_nents, DMA_TO_DEVICE);
1461 sport->dma_is_txing = 0;
1462 }
1463 dmaengine_terminate_sync(sport->dma_chan_rx);
1464 if (sport->dma_is_rxing) {
1465 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1466 1, DMA_FROM_DEVICE);
1467 sport->dma_is_rxing = 0;
1468 }
1469
1470 spin_lock_irqsave(&sport->port.lock, flags);
1471 imx_uart_stop_tx(port);
1472 imx_uart_stop_rx(port);
1473 imx_uart_disable_dma(sport);
1474 spin_unlock_irqrestore(&sport->port.lock, flags);
1475 imx_uart_dma_exit(sport);
1476 }
1477
1478 mctrl_gpio_disable_ms(sport->gpios);
1479
1480 spin_lock_irqsave(&sport->port.lock, flags);
1481 ucr2 = imx_uart_readl(sport, UCR2);
1482 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1483 imx_uart_writel(sport, ucr2, UCR2);
1484
1485 ucr4 = imx_uart_readl(sport, UCR4);
1486 ucr4 &= ~UCR4_OREN;
1487 imx_uart_writel(sport, ucr4, UCR4);
1488 spin_unlock_irqrestore(&sport->port.lock, flags);
1489
1490 /*
1491 * Stop our timer.
1492 */
1493 del_timer_sync(&sport->timer);
1494
1495 /*
1496 * Disable all interrupts, port and break condition.
1497 */
1498
1499 spin_lock_irqsave(&sport->port.lock, flags);
1500 ucr1 = imx_uart_readl(sport, UCR1);
1501 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1502
1503 imx_uart_writel(sport, ucr1, UCR1);
1504 spin_unlock_irqrestore(&sport->port.lock, flags);
1505
1506 clk_disable_unprepare(sport->clk_per);
1507 clk_disable_unprepare(sport->clk_ipg);
1508 }
1509
1510 /* called with port.lock taken and irqs off */
1511 static void imx_uart_flush_buffer(struct uart_port *port)
1512 {
1513 struct imx_port *sport = (struct imx_port *)port;
1514 struct scatterlist *sgl = &sport->tx_sgl[0];
1515 u32 ucr2;
1516 int i = 100, ubir, ubmr, uts;
1517
1518 if (!sport->dma_chan_tx)
1519 return;
1520
1521 sport->tx_bytes = 0;
1522 dmaengine_terminate_all(sport->dma_chan_tx);
1523 if (sport->dma_is_txing) {
1524 u32 ucr1;
1525
1526 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1527 DMA_TO_DEVICE);
1528 ucr1 = imx_uart_readl(sport, UCR1);
1529 ucr1 &= ~UCR1_TXDMAEN;
1530 imx_uart_writel(sport, ucr1, UCR1);
1531 sport->dma_is_txing = 0;
1532 }
1533
1534 /*
1535 * According to the Reference Manual description of the UART SRST bit:
1536 *
1537 * "Reset the transmit and receive state machines,
1538 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1539 * and UTS[6-3]".
1540 *
1541 * We don't need to restore the old values from USR1, USR2, URXD and
1542 * UTXD. UBRC is read only, so only save/restore the other three
1543 * registers.
1544 */
1545 ubir = imx_uart_readl(sport, UBIR);
1546 ubmr = imx_uart_readl(sport, UBMR);
1547 uts = imx_uart_readl(sport, IMX21_UTS);
1548
1549 ucr2 = imx_uart_readl(sport, UCR2);
1550 ucr2 &= ~UCR2_SRST;
1551 imx_uart_writel(sport, ucr2, UCR2);
1552
1553 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1554 udelay(1);
1555
1556 /* Restore the registers */
1557 imx_uart_writel(sport, ubir, UBIR);
1558 imx_uart_writel(sport, ubmr, UBMR);
1559 imx_uart_writel(sport, uts, IMX21_UTS);
1560 }
1561
1562 static void
1563 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1564 struct ktermios *old)
1565 {
1566 struct imx_port *sport = (struct imx_port *)port;
1567 unsigned long flags;
1568 u32 ucr2, old_ucr2, ufcr;
1569 unsigned int baud, quot;
1570 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1571 unsigned long div;
1572 unsigned long num, denom, old_ubir, old_ubmr;
1573 uint64_t tdiv64;
1574
1575 /*
1576 * We only support CS7 and CS8.
1577 */
1578 while ((termios->c_cflag & CSIZE) != CS7 &&
1579 (termios->c_cflag & CSIZE) != CS8) {
1580 termios->c_cflag &= ~CSIZE;
1581 termios->c_cflag |= old_csize;
1582 old_csize = CS8;
1583 }
1584
1585 del_timer_sync(&sport->timer);
1586
1587 /*
1588 * Ask the core to calculate the divisor for us.
1589 */
1590 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1591 quot = uart_get_divisor(port, baud);
1592
1593 spin_lock_irqsave(&sport->port.lock, flags);
1594
1595 /*
1596 * Read current UCR2 and save it for future use, then clear all the bits
1597 * except those we will or may need to preserve.
1598 */
1599 old_ucr2 = imx_uart_readl(sport, UCR2);
1600 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1601
1602 ucr2 |= UCR2_SRST | UCR2_IRTS;
1603 if ((termios->c_cflag & CSIZE) == CS8)
1604 ucr2 |= UCR2_WS;
1605
1606 if (!sport->have_rtscts)
1607 termios->c_cflag &= ~CRTSCTS;
1608
1609 if (port->rs485.flags & SER_RS485_ENABLED) {
1610 /*
1611 * RTS is mandatory for rs485 operation, so keep
1612 * it under manual control and keep transmitter
1613 * disabled.
1614 */
1615 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1616 imx_uart_rts_active(sport, &ucr2);
1617 else
1618 imx_uart_rts_inactive(sport, &ucr2);
1619
1620 } else if (termios->c_cflag & CRTSCTS) {
1621 /*
1622 * Only let receiver control RTS output if we were not requested
1623 * to have RTS inactive (which then should take precedence).
1624 */
1625 if (ucr2 & UCR2_CTS)
1626 ucr2 |= UCR2_CTSC;
1627 }
1628
1629 if (termios->c_cflag & CRTSCTS)
1630 ucr2 &= ~UCR2_IRTS;
1631
1632 if (termios->c_cflag & CSTOPB)
1633 ucr2 |= UCR2_STPB;
1634 if (termios->c_cflag & PARENB) {
1635 ucr2 |= UCR2_PREN;
1636 if (termios->c_cflag & PARODD)
1637 ucr2 |= UCR2_PROE;
1638 }
1639
1640 sport->port.read_status_mask = 0;
1641 if (termios->c_iflag & INPCK)
1642 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1643 if (termios->c_iflag & (BRKINT | PARMRK))
1644 sport->port.read_status_mask |= URXD_BRK;
1645
1646 /*
1647 * Characters to ignore
1648 */
1649 sport->port.ignore_status_mask = 0;
1650 if (termios->c_iflag & IGNPAR)
1651 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1652 if (termios->c_iflag & IGNBRK) {
1653 sport->port.ignore_status_mask |= URXD_BRK;
1654 /*
1655 * If we're ignoring parity and break indicators,
1656 * ignore overruns too (for real raw support).
1657 */
1658 if (termios->c_iflag & IGNPAR)
1659 sport->port.ignore_status_mask |= URXD_OVRRUN;
1660 }
1661
1662 if ((termios->c_cflag & CREAD) == 0)
1663 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1664
1665 /*
1666 * Update the per-port timeout.
1667 */
1668 uart_update_timeout(port, termios->c_cflag, baud);
1669
1670 /* custom-baudrate handling */
1671 div = sport->port.uartclk / (baud * 16);
1672 if (baud == 38400 && quot != div)
1673 baud = sport->port.uartclk / (quot * 16);
1674
1675 div = sport->port.uartclk / (baud * 16);
1676 if (div > 7)
1677 div = 7;
1678 if (!div)
1679 div = 1;
1680
1681 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1682 1 << 16, 1 << 16, &num, &denom);
1683
1684 tdiv64 = sport->port.uartclk;
1685 tdiv64 *= num;
1686 do_div(tdiv64, denom * 16 * div);
1687 tty_termios_encode_baud_rate(termios,
1688 (speed_t)tdiv64, (speed_t)tdiv64);
1689
1690 num -= 1;
1691 denom -= 1;
1692
1693 ufcr = imx_uart_readl(sport, UFCR);
1694 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1695 imx_uart_writel(sport, ufcr, UFCR);
1696
1697 /*
1698 * Two registers below should always be written both and in this
1699 * particular order. One consequence is that we need to check if any of
1700 * them changes and then update both. We do need the check for change
1701 * as even writing the same values seem to "restart"
1702 * transmission/receiving logic in the hardware, that leads to data
1703 * breakage even when rate doesn't in fact change. E.g., user switches
1704 * RTS/CTS handshake and suddenly gets broken bytes.
1705 */
1706 old_ubir = imx_uart_readl(sport, UBIR);
1707 old_ubmr = imx_uart_readl(sport, UBMR);
1708 if (old_ubir != num || old_ubmr != denom) {
1709 imx_uart_writel(sport, num, UBIR);
1710 imx_uart_writel(sport, denom, UBMR);
1711 }
1712
1713 if (!imx_uart_is_imx1(sport))
1714 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1715 IMX21_ONEMS);
1716
1717 imx_uart_writel(sport, ucr2, UCR2);
1718
1719 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1720 imx_uart_enable_ms(&sport->port);
1721
1722 spin_unlock_irqrestore(&sport->port.lock, flags);
1723 }
1724
1725 static const char *imx_uart_type(struct uart_port *port)
1726 {
1727 struct imx_port *sport = (struct imx_port *)port;
1728
1729 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1730 }
1731
1732 /*
1733 * Configure/autoconfigure the port.
1734 */
1735 static void imx_uart_config_port(struct uart_port *port, int flags)
1736 {
1737 struct imx_port *sport = (struct imx_port *)port;
1738
1739 if (flags & UART_CONFIG_TYPE)
1740 sport->port.type = PORT_IMX;
1741 }
1742
1743 /*
1744 * Verify the new serial_struct (for TIOCSSERIAL).
1745 * The only change we allow are to the flags and type, and
1746 * even then only between PORT_IMX and PORT_UNKNOWN
1747 */
1748 static int
1749 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1750 {
1751 struct imx_port *sport = (struct imx_port *)port;
1752 int ret = 0;
1753
1754 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1755 ret = -EINVAL;
1756 if (sport->port.irq != ser->irq)
1757 ret = -EINVAL;
1758 if (ser->io_type != UPIO_MEM)
1759 ret = -EINVAL;
1760 if (sport->port.uartclk / 16 != ser->baud_base)
1761 ret = -EINVAL;
1762 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1763 ret = -EINVAL;
1764 if (sport->port.iobase != ser->port)
1765 ret = -EINVAL;
1766 if (ser->hub6 != 0)
1767 ret = -EINVAL;
1768 return ret;
1769 }
1770
1771 #if defined(CONFIG_CONSOLE_POLL)
1772
1773 static int imx_uart_poll_init(struct uart_port *port)
1774 {
1775 struct imx_port *sport = (struct imx_port *)port;
1776 unsigned long flags;
1777 u32 ucr1, ucr2;
1778 int retval;
1779
1780 retval = clk_prepare_enable(sport->clk_ipg);
1781 if (retval)
1782 return retval;
1783 retval = clk_prepare_enable(sport->clk_per);
1784 if (retval)
1785 clk_disable_unprepare(sport->clk_ipg);
1786
1787 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1788
1789 spin_lock_irqsave(&sport->port.lock, flags);
1790
1791 /*
1792 * Be careful about the order of enabling bits here. First enable the
1793 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1794 * This prevents that a character that already sits in the RX fifo is
1795 * triggering an irq but the try to fetch it from there results in an
1796 * exception because UARTEN or RXEN is still off.
1797 */
1798 ucr1 = imx_uart_readl(sport, UCR1);
1799 ucr2 = imx_uart_readl(sport, UCR2);
1800
1801 if (imx_uart_is_imx1(sport))
1802 ucr1 |= IMX1_UCR1_UARTCLKEN;
1803
1804 ucr1 |= UCR1_UARTEN;
1805 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1806
1807 ucr2 |= UCR2_RXEN;
1808 ucr2 &= ~UCR2_ATEN;
1809
1810 imx_uart_writel(sport, ucr1, UCR1);
1811 imx_uart_writel(sport, ucr2, UCR2);
1812
1813 /* now enable irqs */
1814 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1815 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1816
1817 spin_unlock_irqrestore(&sport->port.lock, flags);
1818
1819 return 0;
1820 }
1821
1822 static int imx_uart_poll_get_char(struct uart_port *port)
1823 {
1824 struct imx_port *sport = (struct imx_port *)port;
1825 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1826 return NO_POLL_CHAR;
1827
1828 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1829 }
1830
1831 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1832 {
1833 struct imx_port *sport = (struct imx_port *)port;
1834 unsigned int status;
1835
1836 /* drain */
1837 do {
1838 status = imx_uart_readl(sport, USR1);
1839 } while (~status & USR1_TRDY);
1840
1841 /* write */
1842 imx_uart_writel(sport, c, URTX0);
1843
1844 /* flush */
1845 do {
1846 status = imx_uart_readl(sport, USR2);
1847 } while (~status & USR2_TXDC);
1848 }
1849 #endif
1850
1851 /* called with port.lock taken and irqs off or from .probe without locking */
1852 static int imx_uart_rs485_config(struct uart_port *port,
1853 struct serial_rs485 *rs485conf)
1854 {
1855 struct imx_port *sport = (struct imx_port *)port;
1856 u32 ucr2;
1857
1858 /* unimplemented */
1859 rs485conf->delay_rts_before_send = 0;
1860 rs485conf->delay_rts_after_send = 0;
1861
1862 /* RTS is required to control the transmitter */
1863 if (!sport->have_rtscts && !sport->have_rtsgpio)
1864 rs485conf->flags &= ~SER_RS485_ENABLED;
1865
1866 if (rs485conf->flags & SER_RS485_ENABLED) {
1867 /* Enable receiver if low-active RTS signal is requested */
1868 if (sport->have_rtscts && !sport->have_rtsgpio &&
1869 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1870 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1871
1872 /* disable transmitter */
1873 ucr2 = imx_uart_readl(sport, UCR2);
1874 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1875 imx_uart_rts_active(sport, &ucr2);
1876 else
1877 imx_uart_rts_inactive(sport, &ucr2);
1878 imx_uart_writel(sport, ucr2, UCR2);
1879 }
1880
1881 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1882 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1883 rs485conf->flags & SER_RS485_RX_DURING_TX)
1884 imx_uart_start_rx(port);
1885
1886 port->rs485 = *rs485conf;
1887
1888 return 0;
1889 }
1890
1891 static const struct uart_ops imx_uart_pops = {
1892 .tx_empty = imx_uart_tx_empty,
1893 .set_mctrl = imx_uart_set_mctrl,
1894 .get_mctrl = imx_uart_get_mctrl,
1895 .stop_tx = imx_uart_stop_tx,
1896 .start_tx = imx_uart_start_tx,
1897 .stop_rx = imx_uart_stop_rx,
1898 .enable_ms = imx_uart_enable_ms,
1899 .break_ctl = imx_uart_break_ctl,
1900 .startup = imx_uart_startup,
1901 .shutdown = imx_uart_shutdown,
1902 .flush_buffer = imx_uart_flush_buffer,
1903 .set_termios = imx_uart_set_termios,
1904 .type = imx_uart_type,
1905 .config_port = imx_uart_config_port,
1906 .verify_port = imx_uart_verify_port,
1907 #if defined(CONFIG_CONSOLE_POLL)
1908 .poll_init = imx_uart_poll_init,
1909 .poll_get_char = imx_uart_poll_get_char,
1910 .poll_put_char = imx_uart_poll_put_char,
1911 #endif
1912 };
1913
1914 static struct imx_port *imx_uart_ports[UART_NR];
1915
1916 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1917 static void imx_uart_console_putchar(struct uart_port *port, int ch)
1918 {
1919 struct imx_port *sport = (struct imx_port *)port;
1920
1921 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1922 barrier();
1923
1924 imx_uart_writel(sport, ch, URTX0);
1925 }
1926
1927 /*
1928 * Interrupts are disabled on entering
1929 */
1930 static void
1931 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1932 {
1933 struct imx_port *sport = imx_uart_ports[co->index];
1934 struct imx_port_ucrs old_ucr;
1935 unsigned int ucr1;
1936 unsigned long flags = 0;
1937 int locked = 1;
1938 int retval;
1939
1940 retval = clk_enable(sport->clk_per);
1941 if (retval)
1942 return;
1943 retval = clk_enable(sport->clk_ipg);
1944 if (retval) {
1945 clk_disable(sport->clk_per);
1946 return;
1947 }
1948
1949 if (sport->port.sysrq)
1950 locked = 0;
1951 else if (oops_in_progress)
1952 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1953 else
1954 spin_lock_irqsave(&sport->port.lock, flags);
1955
1956 /*
1957 * First, save UCR1/2/3 and then disable interrupts
1958 */
1959 imx_uart_ucrs_save(sport, &old_ucr);
1960 ucr1 = old_ucr.ucr1;
1961
1962 if (imx_uart_is_imx1(sport))
1963 ucr1 |= IMX1_UCR1_UARTCLKEN;
1964 ucr1 |= UCR1_UARTEN;
1965 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1966
1967 imx_uart_writel(sport, ucr1, UCR1);
1968
1969 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
1970
1971 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
1972
1973 /*
1974 * Finally, wait for transmitter to become empty
1975 * and restore UCR1/2/3
1976 */
1977 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
1978
1979 imx_uart_ucrs_restore(sport, &old_ucr);
1980
1981 if (locked)
1982 spin_unlock_irqrestore(&sport->port.lock, flags);
1983
1984 clk_disable(sport->clk_ipg);
1985 clk_disable(sport->clk_per);
1986 }
1987
1988 /*
1989 * If the port was already initialised (eg, by a boot loader),
1990 * try to determine the current setup.
1991 */
1992 static void __init
1993 imx_uart_console_get_options(struct imx_port *sport, int *baud,
1994 int *parity, int *bits)
1995 {
1996
1997 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
1998 /* ok, the port was enabled */
1999 unsigned int ucr2, ubir, ubmr, uartclk;
2000 unsigned int baud_raw;
2001 unsigned int ucfr_rfdiv;
2002
2003 ucr2 = imx_uart_readl(sport, UCR2);
2004
2005 *parity = 'n';
2006 if (ucr2 & UCR2_PREN) {
2007 if (ucr2 & UCR2_PROE)
2008 *parity = 'o';
2009 else
2010 *parity = 'e';
2011 }
2012
2013 if (ucr2 & UCR2_WS)
2014 *bits = 8;
2015 else
2016 *bits = 7;
2017
2018 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2019 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2020
2021 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2022 if (ucfr_rfdiv == 6)
2023 ucfr_rfdiv = 7;
2024 else
2025 ucfr_rfdiv = 6 - ucfr_rfdiv;
2026
2027 uartclk = clk_get_rate(sport->clk_per);
2028 uartclk /= ucfr_rfdiv;
2029
2030 { /*
2031 * The next code provides exact computation of
2032 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2033 * without need of float support or long long division,
2034 * which would be required to prevent 32bit arithmetic overflow
2035 */
2036 unsigned int mul = ubir + 1;
2037 unsigned int div = 16 * (ubmr + 1);
2038 unsigned int rem = uartclk % div;
2039
2040 baud_raw = (uartclk / div) * mul;
2041 baud_raw += (rem * mul + div / 2) / div;
2042 *baud = (baud_raw + 50) / 100 * 100;
2043 }
2044
2045 if (*baud != baud_raw)
2046 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2047 baud_raw, *baud);
2048 }
2049 }
2050
2051 static int __init
2052 imx_uart_console_setup(struct console *co, char *options)
2053 {
2054 struct imx_port *sport;
2055 int baud = 9600;
2056 int bits = 8;
2057 int parity = 'n';
2058 int flow = 'n';
2059 int retval;
2060
2061 /*
2062 * Check whether an invalid uart number has been specified, and
2063 * if so, search for the first available port that does have
2064 * console support.
2065 */
2066 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2067 co->index = 0;
2068 sport = imx_uart_ports[co->index];
2069 if (sport == NULL)
2070 return -ENODEV;
2071
2072 /* For setting the registers, we only need to enable the ipg clock. */
2073 retval = clk_prepare_enable(sport->clk_ipg);
2074 if (retval)
2075 goto error_console;
2076
2077 if (options)
2078 uart_parse_options(options, &baud, &parity, &bits, &flow);
2079 else
2080 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2081
2082 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2083
2084 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2085
2086 clk_disable(sport->clk_ipg);
2087 if (retval) {
2088 clk_unprepare(sport->clk_ipg);
2089 goto error_console;
2090 }
2091
2092 retval = clk_prepare(sport->clk_per);
2093 if (retval)
2094 clk_unprepare(sport->clk_ipg);
2095
2096 error_console:
2097 return retval;
2098 }
2099
2100 static struct uart_driver imx_uart_uart_driver;
2101 static struct console imx_uart_console = {
2102 .name = DEV_NAME,
2103 .write = imx_uart_console_write,
2104 .device = uart_console_device,
2105 .setup = imx_uart_console_setup,
2106 .flags = CON_PRINTBUFFER,
2107 .index = -1,
2108 .data = &imx_uart_uart_driver,
2109 };
2110
2111 #define IMX_CONSOLE &imx_uart_console
2112
2113 #ifdef CONFIG_OF
2114 static void imx_uart_console_early_putchar(struct uart_port *port, int ch)
2115 {
2116 struct imx_port *sport = (struct imx_port *)port;
2117
2118 while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL)
2119 cpu_relax();
2120
2121 imx_uart_writel(sport, ch, URTX0);
2122 }
2123
2124 static void imx_uart_console_early_write(struct console *con, const char *s,
2125 unsigned count)
2126 {
2127 struct earlycon_device *dev = con->data;
2128
2129 uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar);
2130 }
2131
2132 static int __init
2133 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
2134 {
2135 if (!dev->port.membase)
2136 return -ENODEV;
2137
2138 dev->con->write = imx_uart_console_early_write;
2139
2140 return 0;
2141 }
2142 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
2143 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
2144 #endif
2145
2146 #else
2147 #define IMX_CONSOLE NULL
2148 #endif
2149
2150 static struct uart_driver imx_uart_uart_driver = {
2151 .owner = THIS_MODULE,
2152 .driver_name = DRIVER_NAME,
2153 .dev_name = DEV_NAME,
2154 .major = SERIAL_IMX_MAJOR,
2155 .minor = MINOR_START,
2156 .nr = ARRAY_SIZE(imx_uart_ports),
2157 .cons = IMX_CONSOLE,
2158 };
2159
2160 #ifdef CONFIG_OF
2161 /*
2162 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2163 * could successfully get all information from dt or a negative errno.
2164 */
2165 static int imx_uart_probe_dt(struct imx_port *sport,
2166 struct platform_device *pdev)
2167 {
2168 struct device_node *np = pdev->dev.of_node;
2169 int ret;
2170
2171 sport->devdata = of_device_get_match_data(&pdev->dev);
2172 if (!sport->devdata)
2173 /* no device tree device */
2174 return 1;
2175
2176 ret = of_alias_get_id(np, "serial");
2177 if (ret < 0) {
2178 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2179 return ret;
2180 }
2181 sport->port.line = ret;
2182
2183 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2184 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2185 sport->have_rtscts = 1;
2186
2187 if (of_get_property(np, "fsl,dte-mode", NULL))
2188 sport->dte_mode = 1;
2189
2190 if (of_get_property(np, "rts-gpios", NULL))
2191 sport->have_rtsgpio = 1;
2192
2193 if (of_get_property(np, "fsl,inverted-tx", NULL))
2194 sport->inverted_tx = 1;
2195
2196 if (of_get_property(np, "fsl,inverted-rx", NULL))
2197 sport->inverted_rx = 1;
2198
2199 return 0;
2200 }
2201 #else
2202 static inline int imx_uart_probe_dt(struct imx_port *sport,
2203 struct platform_device *pdev)
2204 {
2205 return 1;
2206 }
2207 #endif
2208
2209 static void imx_uart_probe_pdata(struct imx_port *sport,
2210 struct platform_device *pdev)
2211 {
2212 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2213
2214 sport->port.line = pdev->id;
2215 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
2216
2217 if (!pdata)
2218 return;
2219
2220 if (pdata->flags & IMXUART_HAVE_RTSCTS)
2221 sport->have_rtscts = 1;
2222 }
2223
2224 static int imx_uart_probe(struct platform_device *pdev)
2225 {
2226 struct imx_port *sport;
2227 void __iomem *base;
2228 int ret = 0;
2229 u32 ucr1;
2230 struct resource *res;
2231 int txirq, rxirq, rtsirq;
2232
2233 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2234 if (!sport)
2235 return -ENOMEM;
2236
2237 ret = imx_uart_probe_dt(sport, pdev);
2238 if (ret > 0)
2239 imx_uart_probe_pdata(sport, pdev);
2240 else if (ret < 0)
2241 return ret;
2242
2243 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2244 dev_err(&pdev->dev, "serial%d out of range\n",
2245 sport->port.line);
2246 return -EINVAL;
2247 }
2248
2249 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2250 base = devm_ioremap_resource(&pdev->dev, res);
2251 if (IS_ERR(base))
2252 return PTR_ERR(base);
2253
2254 rxirq = platform_get_irq(pdev, 0);
2255 txirq = platform_get_irq_optional(pdev, 1);
2256 rtsirq = platform_get_irq_optional(pdev, 2);
2257
2258 sport->port.dev = &pdev->dev;
2259 sport->port.mapbase = res->start;
2260 sport->port.membase = base;
2261 sport->port.type = PORT_IMX,
2262 sport->port.iotype = UPIO_MEM;
2263 sport->port.irq = rxirq;
2264 sport->port.fifosize = 32;
2265 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2266 sport->port.ops = &imx_uart_pops;
2267 sport->port.rs485_config = imx_uart_rs485_config;
2268 sport->port.flags = UPF_BOOT_AUTOCONF;
2269 timer_setup(&sport->timer, imx_uart_timeout, 0);
2270
2271 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2272 if (IS_ERR(sport->gpios))
2273 return PTR_ERR(sport->gpios);
2274
2275 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2276 if (IS_ERR(sport->clk_ipg)) {
2277 ret = PTR_ERR(sport->clk_ipg);
2278 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2279 return ret;
2280 }
2281
2282 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2283 if (IS_ERR(sport->clk_per)) {
2284 ret = PTR_ERR(sport->clk_per);
2285 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2286 return ret;
2287 }
2288
2289 sport->port.uartclk = clk_get_rate(sport->clk_per);
2290
2291 /* For register access, we only need to enable the ipg clock. */
2292 ret = clk_prepare_enable(sport->clk_ipg);
2293 if (ret) {
2294 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2295 return ret;
2296 }
2297
2298 /* initialize shadow register values */
2299 sport->ucr1 = readl(sport->port.membase + UCR1);
2300 sport->ucr2 = readl(sport->port.membase + UCR2);
2301 sport->ucr3 = readl(sport->port.membase + UCR3);
2302 sport->ucr4 = readl(sport->port.membase + UCR4);
2303 sport->ufcr = readl(sport->port.membase + UFCR);
2304
2305 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
2306
2307 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2308 (!sport->have_rtscts && !sport->have_rtsgpio))
2309 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2310
2311 /*
2312 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2313 * signal cannot be set low during transmission in case the
2314 * receiver is off (limitation of the i.MX UART IP).
2315 */
2316 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2317 sport->have_rtscts && !sport->have_rtsgpio &&
2318 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2319 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2320 dev_err(&pdev->dev,
2321 "low-active RTS not possible when receiver is off, enabling receiver\n");
2322
2323 imx_uart_rs485_config(&sport->port, &sport->port.rs485);
2324
2325 /* Disable interrupts before requesting them */
2326 ucr1 = imx_uart_readl(sport, UCR1);
2327 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2328 UCR1_TRDYEN | UCR1_RTSDEN);
2329 imx_uart_writel(sport, ucr1, UCR1);
2330
2331 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2332 /*
2333 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2334 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2335 * and DCD (when they are outputs) or enables the respective
2336 * irqs. So set this bit early, i.e. before requesting irqs.
2337 */
2338 u32 ufcr = imx_uart_readl(sport, UFCR);
2339 if (!(ufcr & UFCR_DCEDTE))
2340 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2341
2342 /*
2343 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2344 * enabled later because they cannot be cleared
2345 * (confirmed on i.MX25) which makes them unusable.
2346 */
2347 imx_uart_writel(sport,
2348 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2349 UCR3);
2350
2351 } else {
2352 u32 ucr3 = UCR3_DSR;
2353 u32 ufcr = imx_uart_readl(sport, UFCR);
2354 if (ufcr & UFCR_DCEDTE)
2355 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2356
2357 if (!imx_uart_is_imx1(sport))
2358 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2359 imx_uart_writel(sport, ucr3, UCR3);
2360 }
2361
2362 clk_disable_unprepare(sport->clk_ipg);
2363
2364 /*
2365 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2366 * chips only have one interrupt.
2367 */
2368 if (txirq > 0) {
2369 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2370 dev_name(&pdev->dev), sport);
2371 if (ret) {
2372 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2373 ret);
2374 return ret;
2375 }
2376
2377 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2378 dev_name(&pdev->dev), sport);
2379 if (ret) {
2380 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2381 ret);
2382 return ret;
2383 }
2384
2385 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2386 dev_name(&pdev->dev), sport);
2387 if (ret) {
2388 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2389 ret);
2390 return ret;
2391 }
2392 } else {
2393 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2394 dev_name(&pdev->dev), sport);
2395 if (ret) {
2396 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2397 return ret;
2398 }
2399 }
2400
2401 /* We need to initialize lock even for non-registered console */
2402 spin_lock_init(&sport->port.lock);
2403
2404 imx_uart_ports[sport->port.line] = sport;
2405
2406 platform_set_drvdata(pdev, sport);
2407
2408 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2409 }
2410
2411 static int imx_uart_remove(struct platform_device *pdev)
2412 {
2413 struct imx_port *sport = platform_get_drvdata(pdev);
2414
2415 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2416 }
2417
2418 static void imx_uart_restore_context(struct imx_port *sport)
2419 {
2420 unsigned long flags;
2421
2422 spin_lock_irqsave(&sport->port.lock, flags);
2423 if (!sport->context_saved) {
2424 spin_unlock_irqrestore(&sport->port.lock, flags);
2425 return;
2426 }
2427
2428 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2429 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2430 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2431 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2432 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2433 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2434 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2435 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2436 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2437 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2438 sport->context_saved = false;
2439 spin_unlock_irqrestore(&sport->port.lock, flags);
2440 }
2441
2442 static void imx_uart_save_context(struct imx_port *sport)
2443 {
2444 unsigned long flags;
2445
2446 /* Save necessary regs */
2447 spin_lock_irqsave(&sport->port.lock, flags);
2448 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2449 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2450 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2451 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2452 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2453 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2454 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2455 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2456 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2457 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2458 sport->context_saved = true;
2459 spin_unlock_irqrestore(&sport->port.lock, flags);
2460 }
2461
2462 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2463 {
2464 u32 ucr3;
2465
2466 ucr3 = imx_uart_readl(sport, UCR3);
2467 if (on) {
2468 imx_uart_writel(sport, USR1_AWAKE, USR1);
2469 ucr3 |= UCR3_AWAKEN;
2470 } else {
2471 ucr3 &= ~UCR3_AWAKEN;
2472 }
2473 imx_uart_writel(sport, ucr3, UCR3);
2474
2475 if (sport->have_rtscts) {
2476 u32 ucr1 = imx_uart_readl(sport, UCR1);
2477 if (on)
2478 ucr1 |= UCR1_RTSDEN;
2479 else
2480 ucr1 &= ~UCR1_RTSDEN;
2481 imx_uart_writel(sport, ucr1, UCR1);
2482 }
2483 }
2484
2485 static int imx_uart_suspend_noirq(struct device *dev)
2486 {
2487 struct imx_port *sport = dev_get_drvdata(dev);
2488
2489 imx_uart_save_context(sport);
2490
2491 clk_disable(sport->clk_ipg);
2492
2493 pinctrl_pm_select_sleep_state(dev);
2494
2495 return 0;
2496 }
2497
2498 static int imx_uart_resume_noirq(struct device *dev)
2499 {
2500 struct imx_port *sport = dev_get_drvdata(dev);
2501 int ret;
2502
2503 pinctrl_pm_select_default_state(dev);
2504
2505 ret = clk_enable(sport->clk_ipg);
2506 if (ret)
2507 return ret;
2508
2509 imx_uart_restore_context(sport);
2510
2511 return 0;
2512 }
2513
2514 static int imx_uart_suspend(struct device *dev)
2515 {
2516 struct imx_port *sport = dev_get_drvdata(dev);
2517 int ret;
2518
2519 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2520 disable_irq(sport->port.irq);
2521
2522 ret = clk_prepare_enable(sport->clk_ipg);
2523 if (ret)
2524 return ret;
2525
2526 /* enable wakeup from i.MX UART */
2527 imx_uart_enable_wakeup(sport, true);
2528
2529 return 0;
2530 }
2531
2532 static int imx_uart_resume(struct device *dev)
2533 {
2534 struct imx_port *sport = dev_get_drvdata(dev);
2535
2536 /* disable wakeup from i.MX UART */
2537 imx_uart_enable_wakeup(sport, false);
2538
2539 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2540 enable_irq(sport->port.irq);
2541
2542 clk_disable_unprepare(sport->clk_ipg);
2543
2544 return 0;
2545 }
2546
2547 static int imx_uart_freeze(struct device *dev)
2548 {
2549 struct imx_port *sport = dev_get_drvdata(dev);
2550
2551 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2552
2553 return clk_prepare_enable(sport->clk_ipg);
2554 }
2555
2556 static int imx_uart_thaw(struct device *dev)
2557 {
2558 struct imx_port *sport = dev_get_drvdata(dev);
2559
2560 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2561
2562 clk_disable_unprepare(sport->clk_ipg);
2563
2564 return 0;
2565 }
2566
2567 static const struct dev_pm_ops imx_uart_pm_ops = {
2568 .suspend_noirq = imx_uart_suspend_noirq,
2569 .resume_noirq = imx_uart_resume_noirq,
2570 .freeze_noirq = imx_uart_suspend_noirq,
2571 .restore_noirq = imx_uart_resume_noirq,
2572 .suspend = imx_uart_suspend,
2573 .resume = imx_uart_resume,
2574 .freeze = imx_uart_freeze,
2575 .thaw = imx_uart_thaw,
2576 .restore = imx_uart_thaw,
2577 };
2578
2579 static struct platform_driver imx_uart_platform_driver = {
2580 .probe = imx_uart_probe,
2581 .remove = imx_uart_remove,
2582
2583 .id_table = imx_uart_devtype,
2584 .driver = {
2585 .name = "imx-uart",
2586 .of_match_table = imx_uart_dt_ids,
2587 .pm = &imx_uart_pm_ops,
2588 },
2589 };
2590
2591 static int __init imx_uart_init(void)
2592 {
2593 int ret = uart_register_driver(&imx_uart_uart_driver);
2594
2595 if (ret)
2596 return ret;
2597
2598 ret = platform_driver_register(&imx_uart_platform_driver);
2599 if (ret != 0)
2600 uart_unregister_driver(&imx_uart_uart_driver);
2601
2602 return ret;
2603 }
2604
2605 static void __exit imx_uart_exit(void)
2606 {
2607 platform_driver_unregister(&imx_uart_platform_driver);
2608 uart_unregister_driver(&imx_uart_uart_driver);
2609 }
2610
2611 module_init(imx_uart_init);
2612 module_exit(imx_uart_exit);
2613
2614 MODULE_AUTHOR("Sascha Hauer");
2615 MODULE_DESCRIPTION("IMX generic serial port driver");
2616 MODULE_LICENSE("GPL");
2617 MODULE_ALIAS("platform:imx-uart");
Linux with added FPC-III support