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Revert "tty: hvc: Fix data abort due to race in hvc_open"
[linux/fpc-iii.git] / drivers / tty / serial / omap-serial.c
blobf7d6b3c9ea45902dab8af5f636d985d5420df546
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for OMAP-UART controller.
4 * Based on drivers/serial/8250.c
5 *
6 * Copyright (C) 2010 Texas Instruments.
7 *
8 * Authors:
9 * Govindraj R <govindraj.raja@ti.com>
10 * Thara Gopinath <thara@ti.com>
11 *
12 * Note: This driver is made separate from 8250 driver as we cannot
13 * over load 8250 driver with omap platform specific configuration for
14 * features like DMA, it makes easier to implement features like DMA and
15 * hardware flow control and software flow control configuration with
16 * this driver as required for the omap-platform.
17 */
18
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/console.h>
22 #include <linux/serial_reg.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/tty.h>
26 #include <linux/tty_flip.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/clk.h>
30 #include <linux/serial_core.h>
31 #include <linux/irq.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/pm_wakeirq.h>
34 #include <linux/of.h>
35 #include <linux/of_irq.h>
36 #include <linux/gpio.h>
37 #include <linux/of_gpio.h>
38 #include <linux/platform_data/serial-omap.h>
39
40 #define OMAP_MAX_HSUART_PORTS 10
41
42 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
43
44 #define OMAP_UART_REV_42 0x0402
45 #define OMAP_UART_REV_46 0x0406
46 #define OMAP_UART_REV_52 0x0502
47 #define OMAP_UART_REV_63 0x0603
48
49 #define OMAP_UART_TX_WAKEUP_EN BIT(7)
50
51 /* Feature flags */
52 #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
53
54 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
55 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
56
57 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
58
59 /* SCR register bitmasks */
60 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
61 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
62 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
63
64 /* FCR register bitmasks */
65 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
66 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
67
68 /* MVR register bitmasks */
69 #define OMAP_UART_MVR_SCHEME_SHIFT 30
70
71 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
72 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
73 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
74
75 #define OMAP_UART_MVR_MAJ_MASK 0x700
76 #define OMAP_UART_MVR_MAJ_SHIFT 8
77 #define OMAP_UART_MVR_MIN_MASK 0x3f
78
79 #define OMAP_UART_DMA_CH_FREE -1
80
81 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
82 #define OMAP_MODE13X_SPEED 230400
83
84 /* WER = 0x7F
85 * Enable module level wakeup in WER reg
86 */
87 #define OMAP_UART_WER_MOD_WKUP 0x7F
88
89 /* Enable XON/XOFF flow control on output */
90 #define OMAP_UART_SW_TX 0x08
91
92 /* Enable XON/XOFF flow control on input */
93 #define OMAP_UART_SW_RX 0x02
94
95 #define OMAP_UART_SW_CLR 0xF0
96
97 #define OMAP_UART_TCR_TRIG 0x0F
98
99 struct uart_omap_dma {
100 u8 uart_dma_tx;
101 u8 uart_dma_rx;
102 int rx_dma_channel;
103 int tx_dma_channel;
104 dma_addr_t rx_buf_dma_phys;
105 dma_addr_t tx_buf_dma_phys;
106 unsigned int uart_base;
107 /*
108 * Buffer for rx dma. It is not required for tx because the buffer
109 * comes from port structure.
110 */
111 unsigned char *rx_buf;
112 unsigned int prev_rx_dma_pos;
113 int tx_buf_size;
114 int tx_dma_used;
115 int rx_dma_used;
116 spinlock_t tx_lock;
117 spinlock_t rx_lock;
118 /* timer to poll activity on rx dma */
119 struct timer_list rx_timer;
120 unsigned int rx_buf_size;
121 unsigned int rx_poll_rate;
122 unsigned int rx_timeout;
123 };
124
125 struct uart_omap_port {
126 struct uart_port port;
127 struct uart_omap_dma uart_dma;
128 struct device *dev;
129 int wakeirq;
130
131 unsigned char ier;
132 unsigned char lcr;
133 unsigned char mcr;
134 unsigned char fcr;
135 unsigned char efr;
136 unsigned char dll;
137 unsigned char dlh;
138 unsigned char mdr1;
139 unsigned char scr;
140 unsigned char wer;
141
142 int use_dma;
143 /*
144 * Some bits in registers are cleared on a read, so they must
145 * be saved whenever the register is read, but the bits will not
146 * be immediately processed.
147 */
148 unsigned int lsr_break_flag;
149 unsigned char msr_saved_flags;
150 char name[20];
151 unsigned long port_activity;
152 int context_loss_cnt;
153 u32 errata;
154 u32 features;
155
156 int rts_gpio;
157
158 struct pm_qos_request pm_qos_request;
159 u32 latency;
160 u32 calc_latency;
161 struct work_struct qos_work;
162 bool is_suspending;
163 };
164
165 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
166
167 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
168
169 /* Forward declaration of functions */
170 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
171
172 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
173 {
174 offset <<= up->port.regshift;
175 return readw(up->port.membase + offset);
176 }
177
178 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
179 {
180 offset <<= up->port.regshift;
181 writew(value, up->port.membase + offset);
182 }
183
184 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
185 {
186 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
187 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
188 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
189 serial_out(up, UART_FCR, 0);
190 }
191
192 #ifdef CONFIG_PM
193 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
194 {
195 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
196
197 if (!pdata || !pdata->get_context_loss_count)
198 return -EINVAL;
199
200 return pdata->get_context_loss_count(up->dev);
201 }
202
203 /* REVISIT: Remove this when omap3 boots in device tree only mode */
204 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
205 {
206 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
207
208 if (!pdata || !pdata->enable_wakeup)
209 return;
210
211 pdata->enable_wakeup(up->dev, enable);
212 }
213 #endif /* CONFIG_PM */
214
215 /*
216 * Calculate the absolute difference between the desired and actual baud
217 * rate for the given mode.
218 */
219 static inline int calculate_baud_abs_diff(struct uart_port *port,
220 unsigned int baud, unsigned int mode)
221 {
222 unsigned int n = port->uartclk / (mode * baud);
223 int abs_diff;
224
225 if (n == 0)
226 n = 1;
227
228 abs_diff = baud - (port->uartclk / (mode * n));
229 if (abs_diff < 0)
230 abs_diff = -abs_diff;
231
232 return abs_diff;
233 }
234
235 /*
236 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
237 * @port: uart port info
238 * @baud: baudrate for which mode needs to be determined
239 *
240 * Returns true if baud rate is MODE16X and false if MODE13X
241 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
242 * and Error Rates" determines modes not for all common baud rates.
243 * E.g. for 1000000 baud rate mode must be 16x, but according to that
244 * table it's determined as 13x.
245 */
246 static bool
247 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
248 {
249 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
250 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
251
252 return (abs_diff_13 >= abs_diff_16);
253 }
254
255 /*
256 * serial_omap_get_divisor - calculate divisor value
257 * @port: uart port info
258 * @baud: baudrate for which divisor needs to be calculated.
259 */
260 static unsigned int
261 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
262 {
263 unsigned int mode;
264
265 if (!serial_omap_baud_is_mode16(port, baud))
266 mode = 13;
267 else
268 mode = 16;
269 return port->uartclk/(mode * baud);
270 }
271
272 static void serial_omap_enable_ms(struct uart_port *port)
273 {
274 struct uart_omap_port *up = to_uart_omap_port(port);
275
276 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
277
278 pm_runtime_get_sync(up->dev);
279 up->ier |= UART_IER_MSI;
280 serial_out(up, UART_IER, up->ier);
281 pm_runtime_mark_last_busy(up->dev);
282 pm_runtime_put_autosuspend(up->dev);
283 }
284
285 static void serial_omap_stop_tx(struct uart_port *port)
286 {
287 struct uart_omap_port *up = to_uart_omap_port(port);
288 int res;
289
290 pm_runtime_get_sync(up->dev);
291
292 /* Handle RS-485 */
293 if (port->rs485.flags & SER_RS485_ENABLED) {
294 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
295 /* THR interrupt is fired when both TX FIFO and TX
296 * shift register are empty. This means there's nothing
297 * left to transmit now, so make sure the THR interrupt
298 * is fired when TX FIFO is below the trigger level,
299 * disable THR interrupts and toggle the RS-485 GPIO
300 * data direction pin if needed.
301 */
302 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
303 serial_out(up, UART_OMAP_SCR, up->scr);
304 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
305 1 : 0;
306 if (gpio_get_value(up->rts_gpio) != res) {
307 if (port->rs485.delay_rts_after_send > 0)
308 mdelay(
309 port->rs485.delay_rts_after_send);
310 gpio_set_value(up->rts_gpio, res);
311 }
312 } else {
313 /* We're asked to stop, but there's still stuff in the
314 * UART FIFO, so make sure the THR interrupt is fired
315 * when both TX FIFO and TX shift register are empty.
316 * The next THR interrupt (if no transmission is started
317 * in the meantime) will indicate the end of a
318 * transmission. Therefore we _don't_ disable THR
319 * interrupts in this situation.
320 */
321 up->scr |= OMAP_UART_SCR_TX_EMPTY;
322 serial_out(up, UART_OMAP_SCR, up->scr);
323 return;
324 }
325 }
326
327 if (up->ier & UART_IER_THRI) {
328 up->ier &= ~UART_IER_THRI;
329 serial_out(up, UART_IER, up->ier);
330 }
331
332 if ((port->rs485.flags & SER_RS485_ENABLED) &&
333 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
334 /*
335 * Empty the RX FIFO, we are not interested in anything
336 * received during the half-duplex transmission.
337 */
338 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
339 /* Re-enable RX interrupts */
340 up->ier |= UART_IER_RLSI | UART_IER_RDI;
341 up->port.read_status_mask |= UART_LSR_DR;
342 serial_out(up, UART_IER, up->ier);
343 }
344
345 pm_runtime_mark_last_busy(up->dev);
346 pm_runtime_put_autosuspend(up->dev);
347 }
348
349 static void serial_omap_stop_rx(struct uart_port *port)
350 {
351 struct uart_omap_port *up = to_uart_omap_port(port);
352
353 pm_runtime_get_sync(up->dev);
354 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
355 up->port.read_status_mask &= ~UART_LSR_DR;
356 serial_out(up, UART_IER, up->ier);
357 pm_runtime_mark_last_busy(up->dev);
358 pm_runtime_put_autosuspend(up->dev);
359 }
360
361 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
362 {
363 struct circ_buf *xmit = &up->port.state->xmit;
364 int count;
365
366 if (up->port.x_char) {
367 serial_out(up, UART_TX, up->port.x_char);
368 up->port.icount.tx++;
369 up->port.x_char = 0;
370 return;
371 }
372 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
373 serial_omap_stop_tx(&up->port);
374 return;
375 }
376 count = up->port.fifosize / 4;
377 do {
378 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
379 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
380 up->port.icount.tx++;
381 if (uart_circ_empty(xmit))
382 break;
383 } while (--count > 0);
384
385 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
386 uart_write_wakeup(&up->port);
387
388 if (uart_circ_empty(xmit))
389 serial_omap_stop_tx(&up->port);
390 }
391
392 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
393 {
394 if (!(up->ier & UART_IER_THRI)) {
395 up->ier |= UART_IER_THRI;
396 serial_out(up, UART_IER, up->ier);
397 }
398 }
399
400 static void serial_omap_start_tx(struct uart_port *port)
401 {
402 struct uart_omap_port *up = to_uart_omap_port(port);
403 int res;
404
405 pm_runtime_get_sync(up->dev);
406
407 /* Handle RS-485 */
408 if (port->rs485.flags & SER_RS485_ENABLED) {
409 /* Fire THR interrupts when FIFO is below trigger level */
410 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
411 serial_out(up, UART_OMAP_SCR, up->scr);
412
413 /* if rts not already enabled */
414 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
415 if (gpio_get_value(up->rts_gpio) != res) {
416 gpio_set_value(up->rts_gpio, res);
417 if (port->rs485.delay_rts_before_send > 0)
418 mdelay(port->rs485.delay_rts_before_send);
419 }
420 }
421
422 if ((port->rs485.flags & SER_RS485_ENABLED) &&
423 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
424 serial_omap_stop_rx(port);
425
426 serial_omap_enable_ier_thri(up);
427 pm_runtime_mark_last_busy(up->dev);
428 pm_runtime_put_autosuspend(up->dev);
429 }
430
431 static void serial_omap_throttle(struct uart_port *port)
432 {
433 struct uart_omap_port *up = to_uart_omap_port(port);
434 unsigned long flags;
435
436 pm_runtime_get_sync(up->dev);
437 spin_lock_irqsave(&up->port.lock, flags);
438 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
439 serial_out(up, UART_IER, up->ier);
440 spin_unlock_irqrestore(&up->port.lock, flags);
441 pm_runtime_mark_last_busy(up->dev);
442 pm_runtime_put_autosuspend(up->dev);
443 }
444
445 static void serial_omap_unthrottle(struct uart_port *port)
446 {
447 struct uart_omap_port *up = to_uart_omap_port(port);
448 unsigned long flags;
449
450 pm_runtime_get_sync(up->dev);
451 spin_lock_irqsave(&up->port.lock, flags);
452 up->ier |= UART_IER_RLSI | UART_IER_RDI;
453 serial_out(up, UART_IER, up->ier);
454 spin_unlock_irqrestore(&up->port.lock, flags);
455 pm_runtime_mark_last_busy(up->dev);
456 pm_runtime_put_autosuspend(up->dev);
457 }
458
459 static unsigned int check_modem_status(struct uart_omap_port *up)
460 {
461 unsigned int status;
462
463 status = serial_in(up, UART_MSR);
464 status |= up->msr_saved_flags;
465 up->msr_saved_flags = 0;
466 if ((status & UART_MSR_ANY_DELTA) == 0)
467 return status;
468
469 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
470 up->port.state != NULL) {
471 if (status & UART_MSR_TERI)
472 up->port.icount.rng++;
473 if (status & UART_MSR_DDSR)
474 up->port.icount.dsr++;
475 if (status & UART_MSR_DDCD)
476 uart_handle_dcd_change
477 (&up->port, status & UART_MSR_DCD);
478 if (status & UART_MSR_DCTS)
479 uart_handle_cts_change
480 (&up->port, status & UART_MSR_CTS);
481 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
482 }
483
484 return status;
485 }
486
487 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
488 {
489 unsigned int flag;
490
491 /*
492 * Read one data character out to avoid stalling the receiver according
493 * to the table 23-246 of the omap4 TRM.
494 */
495 if (likely(lsr & UART_LSR_DR))
496 serial_in(up, UART_RX);
497
498 up->port.icount.rx++;
499 flag = TTY_NORMAL;
500
501 if (lsr & UART_LSR_BI) {
502 flag = TTY_BREAK;
503 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
504 up->port.icount.brk++;
505 /*
506 * We do the SysRQ and SAK checking
507 * here because otherwise the break
508 * may get masked by ignore_status_mask
509 * or read_status_mask.
510 */
511 if (uart_handle_break(&up->port))
512 return;
513
514 }
515
516 if (lsr & UART_LSR_PE) {
517 flag = TTY_PARITY;
518 up->port.icount.parity++;
519 }
520
521 if (lsr & UART_LSR_FE) {
522 flag = TTY_FRAME;
523 up->port.icount.frame++;
524 }
525
526 if (lsr & UART_LSR_OE)
527 up->port.icount.overrun++;
528
529 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
530 if (up->port.line == up->port.cons->index) {
531 /* Recover the break flag from console xmit */
532 lsr |= up->lsr_break_flag;
533 }
534 #endif
535 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
536 }
537
538 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
539 {
540 unsigned char ch = 0;
541 unsigned int flag;
542
543 if (!(lsr & UART_LSR_DR))
544 return;
545
546 ch = serial_in(up, UART_RX);
547 flag = TTY_NORMAL;
548 up->port.icount.rx++;
549
550 if (uart_handle_sysrq_char(&up->port, ch))
551 return;
552
553 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
554 }
555
556 /**
557 * serial_omap_irq() - This handles the interrupt from one port
558 * @irq: uart port irq number
559 * @dev_id: uart port info
560 */
561 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
562 {
563 struct uart_omap_port *up = dev_id;
564 unsigned int iir, lsr;
565 unsigned int type;
566 irqreturn_t ret = IRQ_NONE;
567 int max_count = 256;
568
569 spin_lock(&up->port.lock);
570 pm_runtime_get_sync(up->dev);
571
572 do {
573 iir = serial_in(up, UART_IIR);
574 if (iir & UART_IIR_NO_INT)
575 break;
576
577 ret = IRQ_HANDLED;
578 lsr = serial_in(up, UART_LSR);
579
580 /* extract IRQ type from IIR register */
581 type = iir & 0x3e;
582
583 switch (type) {
584 case UART_IIR_MSI:
585 check_modem_status(up);
586 break;
587 case UART_IIR_THRI:
588 transmit_chars(up, lsr);
589 break;
590 case UART_IIR_RX_TIMEOUT:
591 /* FALLTHROUGH */
592 case UART_IIR_RDI:
593 serial_omap_rdi(up, lsr);
594 break;
595 case UART_IIR_RLSI:
596 serial_omap_rlsi(up, lsr);
597 break;
598 case UART_IIR_CTS_RTS_DSR:
599 /* simply try again */
600 break;
601 case UART_IIR_XOFF:
602 /* FALLTHROUGH */
603 default:
604 break;
605 }
606 } while (max_count--);
607
608 spin_unlock(&up->port.lock);
609
610 tty_flip_buffer_push(&up->port.state->port);
611
612 pm_runtime_mark_last_busy(up->dev);
613 pm_runtime_put_autosuspend(up->dev);
614 up->port_activity = jiffies;
615
616 return ret;
617 }
618
619 static unsigned int serial_omap_tx_empty(struct uart_port *port)
620 {
621 struct uart_omap_port *up = to_uart_omap_port(port);
622 unsigned long flags = 0;
623 unsigned int ret = 0;
624
625 pm_runtime_get_sync(up->dev);
626 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
627 spin_lock_irqsave(&up->port.lock, flags);
628 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
629 spin_unlock_irqrestore(&up->port.lock, flags);
630 pm_runtime_mark_last_busy(up->dev);
631 pm_runtime_put_autosuspend(up->dev);
632 return ret;
633 }
634
635 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
636 {
637 struct uart_omap_port *up = to_uart_omap_port(port);
638 unsigned int status;
639 unsigned int ret = 0;
640
641 pm_runtime_get_sync(up->dev);
642 status = check_modem_status(up);
643 pm_runtime_mark_last_busy(up->dev);
644 pm_runtime_put_autosuspend(up->dev);
645
646 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
647
648 if (status & UART_MSR_DCD)
649 ret |= TIOCM_CAR;
650 if (status & UART_MSR_RI)
651 ret |= TIOCM_RNG;
652 if (status & UART_MSR_DSR)
653 ret |= TIOCM_DSR;
654 if (status & UART_MSR_CTS)
655 ret |= TIOCM_CTS;
656 return ret;
657 }
658
659 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
660 {
661 struct uart_omap_port *up = to_uart_omap_port(port);
662 unsigned char mcr = 0, old_mcr, lcr;
663
664 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
665 if (mctrl & TIOCM_RTS)
666 mcr |= UART_MCR_RTS;
667 if (mctrl & TIOCM_DTR)
668 mcr |= UART_MCR_DTR;
669 if (mctrl & TIOCM_OUT1)
670 mcr |= UART_MCR_OUT1;
671 if (mctrl & TIOCM_OUT2)
672 mcr |= UART_MCR_OUT2;
673 if (mctrl & TIOCM_LOOP)
674 mcr |= UART_MCR_LOOP;
675
676 pm_runtime_get_sync(up->dev);
677 old_mcr = serial_in(up, UART_MCR);
678 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
679 UART_MCR_DTR | UART_MCR_RTS);
680 up->mcr = old_mcr | mcr;
681 serial_out(up, UART_MCR, up->mcr);
682
683 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
684 lcr = serial_in(up, UART_LCR);
685 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
686 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
687 up->efr |= UART_EFR_RTS;
688 else
689 up->efr &= ~UART_EFR_RTS;
690 serial_out(up, UART_EFR, up->efr);
691 serial_out(up, UART_LCR, lcr);
692
693 pm_runtime_mark_last_busy(up->dev);
694 pm_runtime_put_autosuspend(up->dev);
695 }
696
697 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
698 {
699 struct uart_omap_port *up = to_uart_omap_port(port);
700 unsigned long flags = 0;
701
702 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
703 pm_runtime_get_sync(up->dev);
704 spin_lock_irqsave(&up->port.lock, flags);
705 if (break_state == -1)
706 up->lcr |= UART_LCR_SBC;
707 else
708 up->lcr &= ~UART_LCR_SBC;
709 serial_out(up, UART_LCR, up->lcr);
710 spin_unlock_irqrestore(&up->port.lock, flags);
711 pm_runtime_mark_last_busy(up->dev);
712 pm_runtime_put_autosuspend(up->dev);
713 }
714
715 static int serial_omap_startup(struct uart_port *port)
716 {
717 struct uart_omap_port *up = to_uart_omap_port(port);
718 unsigned long flags = 0;
719 int retval;
720
721 /*
722 * Allocate the IRQ
723 */
724 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
725 up->name, up);
726 if (retval)
727 return retval;
728
729 /* Optional wake-up IRQ */
730 if (up->wakeirq) {
731 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
732 if (retval) {
733 free_irq(up->port.irq, up);
734 return retval;
735 }
736 }
737
738 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
739
740 pm_runtime_get_sync(up->dev);
741 /*
742 * Clear the FIFO buffers and disable them.
743 * (they will be reenabled in set_termios())
744 */
745 serial_omap_clear_fifos(up);
746
747 /*
748 * Clear the interrupt registers.
749 */
750 (void) serial_in(up, UART_LSR);
751 if (serial_in(up, UART_LSR) & UART_LSR_DR)
752 (void) serial_in(up, UART_RX);
753 (void) serial_in(up, UART_IIR);
754 (void) serial_in(up, UART_MSR);
755
756 /*
757 * Now, initialize the UART
758 */
759 serial_out(up, UART_LCR, UART_LCR_WLEN8);
760 spin_lock_irqsave(&up->port.lock, flags);
761 /*
762 * Most PC uarts need OUT2 raised to enable interrupts.
763 */
764 up->port.mctrl |= TIOCM_OUT2;
765 serial_omap_set_mctrl(&up->port, up->port.mctrl);
766 spin_unlock_irqrestore(&up->port.lock, flags);
767
768 up->msr_saved_flags = 0;
769 /*
770 * Finally, enable interrupts. Note: Modem status interrupts
771 * are set via set_termios(), which will be occurring imminently
772 * anyway, so we don't enable them here.
773 */
774 up->ier = UART_IER_RLSI | UART_IER_RDI;
775 serial_out(up, UART_IER, up->ier);
776
777 /* Enable module level wake up */
778 up->wer = OMAP_UART_WER_MOD_WKUP;
779 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
780 up->wer |= OMAP_UART_TX_WAKEUP_EN;
781
782 serial_out(up, UART_OMAP_WER, up->wer);
783
784 pm_runtime_mark_last_busy(up->dev);
785 pm_runtime_put_autosuspend(up->dev);
786 up->port_activity = jiffies;
787 return 0;
788 }
789
790 static void serial_omap_shutdown(struct uart_port *port)
791 {
792 struct uart_omap_port *up = to_uart_omap_port(port);
793 unsigned long flags = 0;
794
795 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
796
797 pm_runtime_get_sync(up->dev);
798 /*
799 * Disable interrupts from this port
800 */
801 up->ier = 0;
802 serial_out(up, UART_IER, 0);
803
804 spin_lock_irqsave(&up->port.lock, flags);
805 up->port.mctrl &= ~TIOCM_OUT2;
806 serial_omap_set_mctrl(&up->port, up->port.mctrl);
807 spin_unlock_irqrestore(&up->port.lock, flags);
808
809 /*
810 * Disable break condition and FIFOs
811 */
812 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
813 serial_omap_clear_fifos(up);
814
815 /*
816 * Read data port to reset things, and then free the irq
817 */
818 if (serial_in(up, UART_LSR) & UART_LSR_DR)
819 (void) serial_in(up, UART_RX);
820
821 pm_runtime_mark_last_busy(up->dev);
822 pm_runtime_put_autosuspend(up->dev);
823 free_irq(up->port.irq, up);
824 dev_pm_clear_wake_irq(up->dev);
825 }
826
827 static void serial_omap_uart_qos_work(struct work_struct *work)
828 {
829 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
830 qos_work);
831
832 cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
833 }
834
835 static void
836 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
837 struct ktermios *old)
838 {
839 struct uart_omap_port *up = to_uart_omap_port(port);
840 unsigned char cval = 0;
841 unsigned long flags = 0;
842 unsigned int baud, quot;
843
844 switch (termios->c_cflag & CSIZE) {
845 case CS5:
846 cval = UART_LCR_WLEN5;
847 break;
848 case CS6:
849 cval = UART_LCR_WLEN6;
850 break;
851 case CS7:
852 cval = UART_LCR_WLEN7;
853 break;
854 default:
855 case CS8:
856 cval = UART_LCR_WLEN8;
857 break;
858 }
859
860 if (termios->c_cflag & CSTOPB)
861 cval |= UART_LCR_STOP;
862 if (termios->c_cflag & PARENB)
863 cval |= UART_LCR_PARITY;
864 if (!(termios->c_cflag & PARODD))
865 cval |= UART_LCR_EPAR;
866 if (termios->c_cflag & CMSPAR)
867 cval |= UART_LCR_SPAR;
868
869 /*
870 * Ask the core to calculate the divisor for us.
871 */
872
873 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
874 quot = serial_omap_get_divisor(port, baud);
875
876 /* calculate wakeup latency constraint */
877 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
878 up->latency = up->calc_latency;
879 schedule_work(&up->qos_work);
880
881 up->dll = quot & 0xff;
882 up->dlh = quot >> 8;
883 up->mdr1 = UART_OMAP_MDR1_DISABLE;
884
885 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
886 UART_FCR_ENABLE_FIFO;
887
888 /*
889 * Ok, we're now changing the port state. Do it with
890 * interrupts disabled.
891 */
892 pm_runtime_get_sync(up->dev);
893 spin_lock_irqsave(&up->port.lock, flags);
894
895 /*
896 * Update the per-port timeout.
897 */
898 uart_update_timeout(port, termios->c_cflag, baud);
899
900 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
901 if (termios->c_iflag & INPCK)
902 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
903 if (termios->c_iflag & (BRKINT | PARMRK))
904 up->port.read_status_mask |= UART_LSR_BI;
905
906 /*
907 * Characters to ignore
908 */
909 up->port.ignore_status_mask = 0;
910 if (termios->c_iflag & IGNPAR)
911 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
912 if (termios->c_iflag & IGNBRK) {
913 up->port.ignore_status_mask |= UART_LSR_BI;
914 /*
915 * If we're ignoring parity and break indicators,
916 * ignore overruns too (for real raw support).
917 */
918 if (termios->c_iflag & IGNPAR)
919 up->port.ignore_status_mask |= UART_LSR_OE;
920 }
921
922 /*
923 * ignore all characters if CREAD is not set
924 */
925 if ((termios->c_cflag & CREAD) == 0)
926 up->port.ignore_status_mask |= UART_LSR_DR;
927
928 /*
929 * Modem status interrupts
930 */
931 up->ier &= ~UART_IER_MSI;
932 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
933 up->ier |= UART_IER_MSI;
934 serial_out(up, UART_IER, up->ier);
935 serial_out(up, UART_LCR, cval); /* reset DLAB */
936 up->lcr = cval;
937 up->scr = 0;
938
939 /* FIFOs and DMA Settings */
940
941 /* FCR can be changed only when the
942 * baud clock is not running
943 * DLL_REG and DLH_REG set to 0.
944 */
945 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
946 serial_out(up, UART_DLL, 0);
947 serial_out(up, UART_DLM, 0);
948 serial_out(up, UART_LCR, 0);
949
950 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
951
952 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
953 up->efr &= ~UART_EFR_SCD;
954 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
955
956 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
957 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
958 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
959 /* FIFO ENABLE, DMA MODE */
960
961 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
962 /*
963 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
964 * sets Enables the granularity of 1 for TRIGGER RX
965 * level. Along with setting RX FIFO trigger level
966 * to 1 (as noted below, 16 characters) and TLR[3:0]
967 * to zero this will result RX FIFO threshold level
968 * to 1 character, instead of 16 as noted in comment
969 * below.
970 */
971
972 /* Set receive FIFO threshold to 16 characters and
973 * transmit FIFO threshold to 32 spaces
974 */
975 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
976 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
977 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
978 UART_FCR_ENABLE_FIFO;
979
980 serial_out(up, UART_FCR, up->fcr);
981 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
982
983 serial_out(up, UART_OMAP_SCR, up->scr);
984
985 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
986 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
987 serial_out(up, UART_MCR, up->mcr);
988 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
989 serial_out(up, UART_EFR, up->efr);
990 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
991
992 /* Protocol, Baud Rate, and Interrupt Settings */
993
994 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
995 serial_omap_mdr1_errataset(up, up->mdr1);
996 else
997 serial_out(up, UART_OMAP_MDR1, up->mdr1);
998
999 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1000 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1001
1002 serial_out(up, UART_LCR, 0);
1003 serial_out(up, UART_IER, 0);
1004 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1005
1006 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
1007 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
1008
1009 serial_out(up, UART_LCR, 0);
1010 serial_out(up, UART_IER, up->ier);
1011 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1012
1013 serial_out(up, UART_EFR, up->efr);
1014 serial_out(up, UART_LCR, cval);
1015
1016 if (!serial_omap_baud_is_mode16(port, baud))
1017 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1018 else
1019 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1020
1021 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1022 serial_omap_mdr1_errataset(up, up->mdr1);
1023 else
1024 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1025
1026 /* Configure flow control */
1027 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1028
1029 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1030 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1031 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1032
1033 /* Enable access to TCR/TLR */
1034 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1035 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1036 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1037
1038 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1039
1040 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1041
1042 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1043 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
1044 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1045 up->efr |= UART_EFR_CTS;
1046 } else {
1047 /* Disable AUTORTS and AUTOCTS */
1048 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1049 }
1050
1051 if (up->port.flags & UPF_SOFT_FLOW) {
1052 /* clear SW control mode bits */
1053 up->efr &= OMAP_UART_SW_CLR;
1054
1055 /*
1056 * IXON Flag:
1057 * Enable XON/XOFF flow control on input.
1058 * Receiver compares XON1, XOFF1.
1059 */
1060 if (termios->c_iflag & IXON)
1061 up->efr |= OMAP_UART_SW_RX;
1062
1063 /*
1064 * IXOFF Flag:
1065 * Enable XON/XOFF flow control on output.
1066 * Transmit XON1, XOFF1
1067 */
1068 if (termios->c_iflag & IXOFF) {
1069 up->port.status |= UPSTAT_AUTOXOFF;
1070 up->efr |= OMAP_UART_SW_TX;
1071 }
1072
1073 /*
1074 * IXANY Flag:
1075 * Enable any character to restart output.
1076 * Operation resumes after receiving any
1077 * character after recognition of the XOFF character
1078 */
1079 if (termios->c_iflag & IXANY)
1080 up->mcr |= UART_MCR_XONANY;
1081 else
1082 up->mcr &= ~UART_MCR_XONANY;
1083 }
1084 serial_out(up, UART_MCR, up->mcr);
1085 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1086 serial_out(up, UART_EFR, up->efr);
1087 serial_out(up, UART_LCR, up->lcr);
1088
1089 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1090
1091 spin_unlock_irqrestore(&up->port.lock, flags);
1092 pm_runtime_mark_last_busy(up->dev);
1093 pm_runtime_put_autosuspend(up->dev);
1094 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1095 }
1096
1097 static void
1098 serial_omap_pm(struct uart_port *port, unsigned int state,
1099 unsigned int oldstate)
1100 {
1101 struct uart_omap_port *up = to_uart_omap_port(port);
1102 unsigned char efr;
1103
1104 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1105
1106 pm_runtime_get_sync(up->dev);
1107 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1108 efr = serial_in(up, UART_EFR);
1109 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1110 serial_out(up, UART_LCR, 0);
1111
1112 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1113 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1114 serial_out(up, UART_EFR, efr);
1115 serial_out(up, UART_LCR, 0);
1116
1117 pm_runtime_mark_last_busy(up->dev);
1118 pm_runtime_put_autosuspend(up->dev);
1119 }
1120
1121 static void serial_omap_release_port(struct uart_port *port)
1122 {
1123 dev_dbg(port->dev, "serial_omap_release_port+\n");
1124 }
1125
1126 static int serial_omap_request_port(struct uart_port *port)
1127 {
1128 dev_dbg(port->dev, "serial_omap_request_port+\n");
1129 return 0;
1130 }
1131
1132 static void serial_omap_config_port(struct uart_port *port, int flags)
1133 {
1134 struct uart_omap_port *up = to_uart_omap_port(port);
1135
1136 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1137 up->port.line);
1138 up->port.type = PORT_OMAP;
1139 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1140 }
1141
1142 static int
1143 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1144 {
1145 /* we don't want the core code to modify any port params */
1146 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1147 return -EINVAL;
1148 }
1149
1150 static const char *
1151 serial_omap_type(struct uart_port *port)
1152 {
1153 struct uart_omap_port *up = to_uart_omap_port(port);
1154
1155 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1156 return up->name;
1157 }
1158
1159 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1160
1161 static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1162 {
1163 unsigned int status, tmout = 10000;
1164
1165 /* Wait up to 10ms for the character(s) to be sent. */
1166 do {
1167 status = serial_in(up, UART_LSR);
1168
1169 if (status & UART_LSR_BI)
1170 up->lsr_break_flag = UART_LSR_BI;
1171
1172 if (--tmout == 0)
1173 break;
1174 udelay(1);
1175 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1176
1177 /* Wait up to 1s for flow control if necessary */
1178 if (up->port.flags & UPF_CONS_FLOW) {
1179 tmout = 1000000;
1180 for (tmout = 1000000; tmout; tmout--) {
1181 unsigned int msr = serial_in(up, UART_MSR);
1182
1183 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1184 if (msr & UART_MSR_CTS)
1185 break;
1186
1187 udelay(1);
1188 }
1189 }
1190 }
1191
1192 #ifdef CONFIG_CONSOLE_POLL
1193
1194 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1195 {
1196 struct uart_omap_port *up = to_uart_omap_port(port);
1197
1198 pm_runtime_get_sync(up->dev);
1199 wait_for_xmitr(up);
1200 serial_out(up, UART_TX, ch);
1201 pm_runtime_mark_last_busy(up->dev);
1202 pm_runtime_put_autosuspend(up->dev);
1203 }
1204
1205 static int serial_omap_poll_get_char(struct uart_port *port)
1206 {
1207 struct uart_omap_port *up = to_uart_omap_port(port);
1208 unsigned int status;
1209
1210 pm_runtime_get_sync(up->dev);
1211 status = serial_in(up, UART_LSR);
1212 if (!(status & UART_LSR_DR)) {
1213 status = NO_POLL_CHAR;
1214 goto out;
1215 }
1216
1217 status = serial_in(up, UART_RX);
1218
1219 out:
1220 pm_runtime_mark_last_busy(up->dev);
1221 pm_runtime_put_autosuspend(up->dev);
1222
1223 return status;
1224 }
1225
1226 #endif /* CONFIG_CONSOLE_POLL */
1227
1228 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1229
1230 #ifdef CONFIG_SERIAL_EARLYCON
1231 static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
1232 {
1233 offset <<= port->regshift;
1234 return readw(port->membase + offset);
1235 }
1236
1237 static void omap_serial_early_out(struct uart_port *port, int offset,
1238 int value)
1239 {
1240 offset <<= port->regshift;
1241 writew(value, port->membase + offset);
1242 }
1243
1244 static void omap_serial_early_putc(struct uart_port *port, int c)
1245 {
1246 unsigned int status;
1247
1248 for (;;) {
1249 status = omap_serial_early_in(port, UART_LSR);
1250 if ((status & BOTH_EMPTY) == BOTH_EMPTY)
1251 break;
1252 cpu_relax();
1253 }
1254 omap_serial_early_out(port, UART_TX, c);
1255 }
1256
1257 static void early_omap_serial_write(struct console *console, const char *s,
1258 unsigned int count)
1259 {
1260 struct earlycon_device *device = console->data;
1261 struct uart_port *port = &device->port;
1262
1263 uart_console_write(port, s, count, omap_serial_early_putc);
1264 }
1265
1266 static int __init early_omap_serial_setup(struct earlycon_device *device,
1267 const char *options)
1268 {
1269 struct uart_port *port = &device->port;
1270
1271 if (!(device->port.membase || device->port.iobase))
1272 return -ENODEV;
1273
1274 port->regshift = 2;
1275 device->con->write = early_omap_serial_write;
1276 return 0;
1277 }
1278
1279 OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
1280 OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
1281 OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
1282 #endif /* CONFIG_SERIAL_EARLYCON */
1283
1284 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1285
1286 static struct uart_driver serial_omap_reg;
1287
1288 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1289 {
1290 struct uart_omap_port *up = to_uart_omap_port(port);
1291
1292 wait_for_xmitr(up);
1293 serial_out(up, UART_TX, ch);
1294 }
1295
1296 static void
1297 serial_omap_console_write(struct console *co, const char *s,
1298 unsigned int count)
1299 {
1300 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1301 unsigned long flags;
1302 unsigned int ier;
1303 int locked = 1;
1304
1305 pm_runtime_get_sync(up->dev);
1306
1307 local_irq_save(flags);
1308 if (up->port.sysrq)
1309 locked = 0;
1310 else if (oops_in_progress)
1311 locked = spin_trylock(&up->port.lock);
1312 else
1313 spin_lock(&up->port.lock);
1314
1315 /*
1316 * First save the IER then disable the interrupts
1317 */
1318 ier = serial_in(up, UART_IER);
1319 serial_out(up, UART_IER, 0);
1320
1321 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1322
1323 /*
1324 * Finally, wait for transmitter to become empty
1325 * and restore the IER
1326 */
1327 wait_for_xmitr(up);
1328 serial_out(up, UART_IER, ier);
1329 /*
1330 * The receive handling will happen properly because the
1331 * receive ready bit will still be set; it is not cleared
1332 * on read. However, modem control will not, we must
1333 * call it if we have saved something in the saved flags
1334 * while processing with interrupts off.
1335 */
1336 if (up->msr_saved_flags)
1337 check_modem_status(up);
1338
1339 pm_runtime_mark_last_busy(up->dev);
1340 pm_runtime_put_autosuspend(up->dev);
1341 if (locked)
1342 spin_unlock(&up->port.lock);
1343 local_irq_restore(flags);
1344 }
1345
1346 static int __init
1347 serial_omap_console_setup(struct console *co, char *options)
1348 {
1349 struct uart_omap_port *up;
1350 int baud = 115200;
1351 int bits = 8;
1352 int parity = 'n';
1353 int flow = 'n';
1354
1355 if (serial_omap_console_ports[co->index] == NULL)
1356 return -ENODEV;
1357 up = serial_omap_console_ports[co->index];
1358
1359 if (options)
1360 uart_parse_options(options, &baud, &parity, &bits, &flow);
1361
1362 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1363 }
1364
1365 static struct console serial_omap_console = {
1366 .name = OMAP_SERIAL_NAME,
1367 .write = serial_omap_console_write,
1368 .device = uart_console_device,
1369 .setup = serial_omap_console_setup,
1370 .flags = CON_PRINTBUFFER,
1371 .index = -1,
1372 .data = &serial_omap_reg,
1373 };
1374
1375 static void serial_omap_add_console_port(struct uart_omap_port *up)
1376 {
1377 serial_omap_console_ports[up->port.line] = up;
1378 }
1379
1380 #define OMAP_CONSOLE (&serial_omap_console)
1381
1382 #else
1383
1384 #define OMAP_CONSOLE NULL
1385
1386 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1387 {}
1388
1389 #endif
1390
1391 /* Enable or disable the rs485 support */
1392 static int
1393 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
1394 {
1395 struct uart_omap_port *up = to_uart_omap_port(port);
1396 unsigned int mode;
1397 int val;
1398
1399 pm_runtime_get_sync(up->dev);
1400
1401 /* Disable interrupts from this port */
1402 mode = up->ier;
1403 up->ier = 0;
1404 serial_out(up, UART_IER, 0);
1405
1406 /* Clamp the delays to [0, 100ms] */
1407 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
1408 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
1409
1410 /* store new config */
1411 port->rs485 = *rs485;
1412
1413 /*
1414 * Just as a precaution, only allow rs485
1415 * to be enabled if the gpio pin is valid
1416 */
1417 if (gpio_is_valid(up->rts_gpio)) {
1418 /* enable / disable rts */
1419 val = (port->rs485.flags & SER_RS485_ENABLED) ?
1420 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1421 val = (port->rs485.flags & val) ? 1 : 0;
1422 gpio_set_value(up->rts_gpio, val);
1423 } else
1424 port->rs485.flags &= ~SER_RS485_ENABLED;
1425
1426 /* Enable interrupts */
1427 up->ier = mode;
1428 serial_out(up, UART_IER, up->ier);
1429
1430 /* If RS-485 is disabled, make sure the THR interrupt is fired when
1431 * TX FIFO is below the trigger level.
1432 */
1433 if (!(port->rs485.flags & SER_RS485_ENABLED) &&
1434 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1435 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1436 serial_out(up, UART_OMAP_SCR, up->scr);
1437 }
1438
1439 pm_runtime_mark_last_busy(up->dev);
1440 pm_runtime_put_autosuspend(up->dev);
1441
1442 return 0;
1443 }
1444
1445 static const struct uart_ops serial_omap_pops = {
1446 .tx_empty = serial_omap_tx_empty,
1447 .set_mctrl = serial_omap_set_mctrl,
1448 .get_mctrl = serial_omap_get_mctrl,
1449 .stop_tx = serial_omap_stop_tx,
1450 .start_tx = serial_omap_start_tx,
1451 .throttle = serial_omap_throttle,
1452 .unthrottle = serial_omap_unthrottle,
1453 .stop_rx = serial_omap_stop_rx,
1454 .enable_ms = serial_omap_enable_ms,
1455 .break_ctl = serial_omap_break_ctl,
1456 .startup = serial_omap_startup,
1457 .shutdown = serial_omap_shutdown,
1458 .set_termios = serial_omap_set_termios,
1459 .pm = serial_omap_pm,
1460 .type = serial_omap_type,
1461 .release_port = serial_omap_release_port,
1462 .request_port = serial_omap_request_port,
1463 .config_port = serial_omap_config_port,
1464 .verify_port = serial_omap_verify_port,
1465 #ifdef CONFIG_CONSOLE_POLL
1466 .poll_put_char = serial_omap_poll_put_char,
1467 .poll_get_char = serial_omap_poll_get_char,
1468 #endif
1469 };
1470
1471 static struct uart_driver serial_omap_reg = {
1472 .owner = THIS_MODULE,
1473 .driver_name = "OMAP-SERIAL",
1474 .dev_name = OMAP_SERIAL_NAME,
1475 .nr = OMAP_MAX_HSUART_PORTS,
1476 .cons = OMAP_CONSOLE,
1477 };
1478
1479 #ifdef CONFIG_PM_SLEEP
1480 static int serial_omap_prepare(struct device *dev)
1481 {
1482 struct uart_omap_port *up = dev_get_drvdata(dev);
1483
1484 up->is_suspending = true;
1485
1486 return 0;
1487 }
1488
1489 static void serial_omap_complete(struct device *dev)
1490 {
1491 struct uart_omap_port *up = dev_get_drvdata(dev);
1492
1493 up->is_suspending = false;
1494 }
1495
1496 static int serial_omap_suspend(struct device *dev)
1497 {
1498 struct uart_omap_port *up = dev_get_drvdata(dev);
1499
1500 uart_suspend_port(&serial_omap_reg, &up->port);
1501 flush_work(&up->qos_work);
1502
1503 if (device_may_wakeup(dev))
1504 serial_omap_enable_wakeup(up, true);
1505 else
1506 serial_omap_enable_wakeup(up, false);
1507
1508 return 0;
1509 }
1510
1511 static int serial_omap_resume(struct device *dev)
1512 {
1513 struct uart_omap_port *up = dev_get_drvdata(dev);
1514
1515 if (device_may_wakeup(dev))
1516 serial_omap_enable_wakeup(up, false);
1517
1518 uart_resume_port(&serial_omap_reg, &up->port);
1519
1520 return 0;
1521 }
1522 #else
1523 #define serial_omap_prepare NULL
1524 #define serial_omap_complete NULL
1525 #endif /* CONFIG_PM_SLEEP */
1526
1527 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1528 {
1529 u32 mvr, scheme;
1530 u16 revision, major, minor;
1531
1532 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1533
1534 /* Check revision register scheme */
1535 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1536
1537 switch (scheme) {
1538 case 0: /* Legacy Scheme: OMAP2/3 */
1539 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1540 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1541 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1542 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1543 break;
1544 case 1:
1545 /* New Scheme: OMAP4+ */
1546 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1547 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1548 OMAP_UART_MVR_MAJ_SHIFT;
1549 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1550 break;
1551 default:
1552 dev_warn(up->dev,
1553 "Unknown %s revision, defaulting to highest\n",
1554 up->name);
1555 /* highest possible revision */
1556 major = 0xff;
1557 minor = 0xff;
1558 }
1559
1560 /* normalize revision for the driver */
1561 revision = UART_BUILD_REVISION(major, minor);
1562
1563 switch (revision) {
1564 case OMAP_UART_REV_46:
1565 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1566 UART_ERRATA_i291_DMA_FORCEIDLE);
1567 break;
1568 case OMAP_UART_REV_52:
1569 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1570 UART_ERRATA_i291_DMA_FORCEIDLE);
1571 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1572 break;
1573 case OMAP_UART_REV_63:
1574 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1575 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1576 break;
1577 default:
1578 break;
1579 }
1580 }
1581
1582 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1583 {
1584 struct omap_uart_port_info *omap_up_info;
1585
1586 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1587 if (!omap_up_info)
1588 return NULL; /* out of memory */
1589
1590 of_property_read_u32(dev->of_node, "clock-frequency",
1591 &omap_up_info->uartclk);
1592
1593 omap_up_info->flags = UPF_BOOT_AUTOCONF;
1594
1595 return omap_up_info;
1596 }
1597
1598 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1599 struct device_node *np)
1600 {
1601 struct serial_rs485 *rs485conf = &up->port.rs485;
1602 int ret;
1603
1604 rs485conf->flags = 0;
1605 up->rts_gpio = -EINVAL;
1606
1607 if (!np)
1608 return 0;
1609
1610 uart_get_rs485_mode(up->dev, rs485conf);
1611
1612 if (of_property_read_bool(np, "rs485-rts-active-high")) {
1613 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1614 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1615 } else {
1616 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1617 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1618 }
1619
1620 /* check for tx enable gpio */
1621 up->rts_gpio = of_get_named_gpio(np, "rts-gpio", 0);
1622 if (gpio_is_valid(up->rts_gpio)) {
1623 ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial");
1624 if (ret < 0)
1625 return ret;
1626 ret = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ? 1 : 0;
1627 ret = gpio_direction_output(up->rts_gpio, ret);
1628 if (ret < 0)
1629 return ret;
1630 } else if (up->rts_gpio == -EPROBE_DEFER) {
1631 return -EPROBE_DEFER;
1632 } else {
1633 up->rts_gpio = -EINVAL;
1634 }
1635
1636 return 0;
1637 }
1638
1639 static int serial_omap_probe(struct platform_device *pdev)
1640 {
1641 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1642 struct uart_omap_port *up;
1643 struct resource *mem;
1644 void __iomem *base;
1645 int uartirq = 0;
1646 int wakeirq = 0;
1647 int ret;
1648
1649 /* The optional wakeirq may be specified in the board dts file */
1650 if (pdev->dev.of_node) {
1651 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1652 if (!uartirq)
1653 return -EPROBE_DEFER;
1654 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1655 omap_up_info = of_get_uart_port_info(&pdev->dev);
1656 pdev->dev.platform_data = omap_up_info;
1657 } else {
1658 uartirq = platform_get_irq(pdev, 0);
1659 if (uartirq < 0)
1660 return -EPROBE_DEFER;
1661 }
1662
1663 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1664 if (!up)
1665 return -ENOMEM;
1666
1667 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1668 base = devm_ioremap_resource(&pdev->dev, mem);
1669 if (IS_ERR(base))
1670 return PTR_ERR(base);
1671
1672 up->dev = &pdev->dev;
1673 up->port.dev = &pdev->dev;
1674 up->port.type = PORT_OMAP;
1675 up->port.iotype = UPIO_MEM;
1676 up->port.irq = uartirq;
1677 up->port.regshift = 2;
1678 up->port.fifosize = 64;
1679 up->port.ops = &serial_omap_pops;
1680 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
1681
1682 if (pdev->dev.of_node)
1683 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1684 else
1685 ret = pdev->id;
1686
1687 if (ret < 0) {
1688 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1689 ret);
1690 goto err_port_line;
1691 }
1692 up->port.line = ret;
1693
1694 if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1695 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
1696 OMAP_MAX_HSUART_PORTS);
1697 ret = -ENXIO;
1698 goto err_port_line;
1699 }
1700
1701 up->wakeirq = wakeirq;
1702 if (!up->wakeirq)
1703 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1704 up->port.line);
1705
1706 ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1707 if (ret < 0)
1708 goto err_rs485;
1709
1710 sprintf(up->name, "OMAP UART%d", up->port.line);
1711 up->port.mapbase = mem->start;
1712 up->port.membase = base;
1713 up->port.flags = omap_up_info->flags;
1714 up->port.uartclk = omap_up_info->uartclk;
1715 up->port.rs485_config = serial_omap_config_rs485;
1716 if (!up->port.uartclk) {
1717 up->port.uartclk = DEFAULT_CLK_SPEED;
1718 dev_warn(&pdev->dev,
1719 "No clock speed specified: using default: %d\n",
1720 DEFAULT_CLK_SPEED);
1721 }
1722
1723 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1724 up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1725 cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
1726 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1727
1728 platform_set_drvdata(pdev, up);
1729 if (omap_up_info->autosuspend_timeout == 0)
1730 omap_up_info->autosuspend_timeout = -1;
1731
1732 device_init_wakeup(up->dev, true);
1733 pm_runtime_use_autosuspend(&pdev->dev);
1734 pm_runtime_set_autosuspend_delay(&pdev->dev,
1735 omap_up_info->autosuspend_timeout);
1736
1737 pm_runtime_irq_safe(&pdev->dev);
1738 pm_runtime_enable(&pdev->dev);
1739
1740 pm_runtime_get_sync(&pdev->dev);
1741
1742 omap_serial_fill_features_erratas(up);
1743
1744 ui[up->port.line] = up;
1745 serial_omap_add_console_port(up);
1746
1747 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1748 if (ret != 0)
1749 goto err_add_port;
1750
1751 pm_runtime_mark_last_busy(up->dev);
1752 pm_runtime_put_autosuspend(up->dev);
1753 return 0;
1754
1755 err_add_port:
1756 pm_runtime_dont_use_autosuspend(&pdev->dev);
1757 pm_runtime_put_sync(&pdev->dev);
1758 pm_runtime_disable(&pdev->dev);
1759 cpu_latency_qos_remove_request(&up->pm_qos_request);
1760 device_init_wakeup(up->dev, false);
1761 err_rs485:
1762 err_port_line:
1763 return ret;
1764 }
1765
1766 static int serial_omap_remove(struct platform_device *dev)
1767 {
1768 struct uart_omap_port *up = platform_get_drvdata(dev);
1769
1770 pm_runtime_get_sync(up->dev);
1771
1772 uart_remove_one_port(&serial_omap_reg, &up->port);
1773
1774 pm_runtime_dont_use_autosuspend(up->dev);
1775 pm_runtime_put_sync(up->dev);
1776 pm_runtime_disable(up->dev);
1777 cpu_latency_qos_remove_request(&up->pm_qos_request);
1778 device_init_wakeup(&dev->dev, false);
1779
1780 return 0;
1781 }
1782
1783 /*
1784 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1785 * The access to uart register after MDR1 Access
1786 * causes UART to corrupt data.
1787 *
1788 * Need a delay =
1789 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1790 * give 10 times as much
1791 */
1792 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1793 {
1794 u8 timeout = 255;
1795
1796 serial_out(up, UART_OMAP_MDR1, mdr1);
1797 udelay(2);
1798 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1799 UART_FCR_CLEAR_RCVR);
1800 /*
1801 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1802 * TX_FIFO_E bit is 1.
1803 */
1804 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1805 (UART_LSR_THRE | UART_LSR_DR))) {
1806 timeout--;
1807 if (!timeout) {
1808 /* Should *never* happen. we warn and carry on */
1809 dev_crit(up->dev, "Errata i202: timedout %x\n",
1810 serial_in(up, UART_LSR));
1811 break;
1812 }
1813 udelay(1);
1814 }
1815 }
1816
1817 #ifdef CONFIG_PM
1818 static void serial_omap_restore_context(struct uart_omap_port *up)
1819 {
1820 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1821 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1822 else
1823 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1824
1825 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1826 serial_out(up, UART_EFR, UART_EFR_ECB);
1827 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1828 serial_out(up, UART_IER, 0x0);
1829 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1830 serial_out(up, UART_DLL, up->dll);
1831 serial_out(up, UART_DLM, up->dlh);
1832 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1833 serial_out(up, UART_IER, up->ier);
1834 serial_out(up, UART_FCR, up->fcr);
1835 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1836 serial_out(up, UART_MCR, up->mcr);
1837 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1838 serial_out(up, UART_OMAP_SCR, up->scr);
1839 serial_out(up, UART_EFR, up->efr);
1840 serial_out(up, UART_LCR, up->lcr);
1841 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1842 serial_omap_mdr1_errataset(up, up->mdr1);
1843 else
1844 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1845 serial_out(up, UART_OMAP_WER, up->wer);
1846 }
1847
1848 static int serial_omap_runtime_suspend(struct device *dev)
1849 {
1850 struct uart_omap_port *up = dev_get_drvdata(dev);
1851
1852 if (!up)
1853 return -EINVAL;
1854
1855 /*
1856 * When using 'no_console_suspend', the console UART must not be
1857 * suspended. Since driver suspend is managed by runtime suspend,
1858 * preventing runtime suspend (by returning error) will keep device
1859 * active during suspend.
1860 */
1861 if (up->is_suspending && !console_suspend_enabled &&
1862 uart_console(&up->port))
1863 return -EBUSY;
1864
1865 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1866
1867 serial_omap_enable_wakeup(up, true);
1868
1869 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1870 schedule_work(&up->qos_work);
1871
1872 return 0;
1873 }
1874
1875 static int serial_omap_runtime_resume(struct device *dev)
1876 {
1877 struct uart_omap_port *up = dev_get_drvdata(dev);
1878
1879 int loss_cnt = serial_omap_get_context_loss_count(up);
1880
1881 serial_omap_enable_wakeup(up, false);
1882
1883 if (loss_cnt < 0) {
1884 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1885 loss_cnt);
1886 serial_omap_restore_context(up);
1887 } else if (up->context_loss_cnt != loss_cnt) {
1888 serial_omap_restore_context(up);
1889 }
1890 up->latency = up->calc_latency;
1891 schedule_work(&up->qos_work);
1892
1893 return 0;
1894 }
1895 #endif
1896
1897 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1898 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1899 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1900 serial_omap_runtime_resume, NULL)
1901 .prepare = serial_omap_prepare,
1902 .complete = serial_omap_complete,
1903 };
1904
1905 #if defined(CONFIG_OF)
1906 static const struct of_device_id omap_serial_of_match[] = {
1907 { .compatible = "ti,omap2-uart" },
1908 { .compatible = "ti,omap3-uart" },
1909 { .compatible = "ti,omap4-uart" },
1910 {},
1911 };
1912 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1913 #endif
1914
1915 static struct platform_driver serial_omap_driver = {
1916 .probe = serial_omap_probe,
1917 .remove = serial_omap_remove,
1918 .driver = {
1919 .name = OMAP_SERIAL_DRIVER_NAME,
1920 .pm = &serial_omap_dev_pm_ops,
1921 .of_match_table = of_match_ptr(omap_serial_of_match),
1922 },
1923 };
1924
1925 static int __init serial_omap_init(void)
1926 {
1927 int ret;
1928
1929 ret = uart_register_driver(&serial_omap_reg);
1930 if (ret != 0)
1931 return ret;
1932 ret = platform_driver_register(&serial_omap_driver);
1933 if (ret != 0)
1934 uart_unregister_driver(&serial_omap_reg);
1935 return ret;
1936 }
1937
1938 static void __exit serial_omap_exit(void)
1939 {
1940 platform_driver_unregister(&serial_omap_driver);
1941 uart_unregister_driver(&serial_omap_reg);
1942 }
1943
1944 module_init(serial_omap_init);
1945 module_exit(serial_omap_exit);
1946
1947 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1948 MODULE_LICENSE("GPL");
1949 MODULE_AUTHOR("Texas Instruments Inc");
Linux with added FPC-III support