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Revert "tty: hvc: Fix data abort due to race in hvc_open"
[linux/fpc-iii.git] / drivers / tty / serial / qcom_geni_serial.c
blob6119090ce045d726e54015c989f11e19473bb492
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4 #include <linux/clk.h>
5 #include <linux/console.h>
6 #include <linux/io.h>
7 #include <linux/iopoll.h>
8 #include <linux/irq.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/pm_wakeirq.h>
15 #include <linux/qcom-geni-se.h>
16 #include <linux/serial.h>
17 #include <linux/serial_core.h>
18 #include <linux/slab.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21
22 /* UART specific GENI registers */
23 #define SE_UART_LOOPBACK_CFG 0x22c
24 #define SE_UART_IO_MACRO_CTRL 0x240
25 #define SE_UART_TX_TRANS_CFG 0x25c
26 #define SE_UART_TX_WORD_LEN 0x268
27 #define SE_UART_TX_STOP_BIT_LEN 0x26c
28 #define SE_UART_TX_TRANS_LEN 0x270
29 #define SE_UART_RX_TRANS_CFG 0x280
30 #define SE_UART_RX_WORD_LEN 0x28c
31 #define SE_UART_RX_STALE_CNT 0x294
32 #define SE_UART_TX_PARITY_CFG 0x2a4
33 #define SE_UART_RX_PARITY_CFG 0x2a8
34 #define SE_UART_MANUAL_RFR 0x2ac
35
36 /* SE_UART_TRANS_CFG */
37 #define UART_TX_PAR_EN BIT(0)
38 #define UART_CTS_MASK BIT(1)
39
40 /* SE_UART_TX_WORD_LEN */
41 #define TX_WORD_LEN_MSK GENMASK(9, 0)
42
43 /* SE_UART_TX_STOP_BIT_LEN */
44 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
45 #define TX_STOP_BIT_LEN_1 0
46 #define TX_STOP_BIT_LEN_1_5 1
47 #define TX_STOP_BIT_LEN_2 2
48
49 /* SE_UART_TX_TRANS_LEN */
50 #define TX_TRANS_LEN_MSK GENMASK(23, 0)
51
52 /* SE_UART_RX_TRANS_CFG */
53 #define UART_RX_INS_STATUS_BIT BIT(2)
54 #define UART_RX_PAR_EN BIT(3)
55
56 /* SE_UART_RX_WORD_LEN */
57 #define RX_WORD_LEN_MASK GENMASK(9, 0)
58
59 /* SE_UART_RX_STALE_CNT */
60 #define RX_STALE_CNT GENMASK(23, 0)
61
62 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
63 #define PAR_CALC_EN BIT(0)
64 #define PAR_MODE_MSK GENMASK(2, 1)
65 #define PAR_MODE_SHFT 1
66 #define PAR_EVEN 0x00
67 #define PAR_ODD 0x01
68 #define PAR_SPACE 0x10
69 #define PAR_MARK 0x11
70
71 /* SE_UART_MANUAL_RFR register fields */
72 #define UART_MANUAL_RFR_EN BIT(31)
73 #define UART_RFR_NOT_READY BIT(1)
74 #define UART_RFR_READY BIT(0)
75
76 /* UART M_CMD OP codes */
77 #define UART_START_TX 0x1
78 #define UART_START_BREAK 0x4
79 #define UART_STOP_BREAK 0x5
80 /* UART S_CMD OP codes */
81 #define UART_START_READ 0x1
82 #define UART_PARAM 0x1
83
84 #define UART_OVERSAMPLING 32
85 #define STALE_TIMEOUT 16
86 #define DEFAULT_BITS_PER_CHAR 10
87 #define GENI_UART_CONS_PORTS 1
88 #define GENI_UART_PORTS 3
89 #define DEF_FIFO_DEPTH_WORDS 16
90 #define DEF_TX_WM 2
91 #define DEF_FIFO_WIDTH_BITS 32
92 #define UART_RX_WM 2
93
94 /* SE_UART_LOOPBACK_CFG */
95 #define RX_TX_SORTED BIT(0)
96 #define CTS_RTS_SORTED BIT(1)
97 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED)
98
99 /* UART pin swap value */
100 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0)
101 #define IO_MACRO_IO0_SEL 0x3
102 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4)
103 #define IO_MACRO_IO2_IO3_SWAP 0x4640
104
105 #ifdef CONFIG_CONSOLE_POLL
106 #define CONSOLE_RX_BYTES_PW 1
107 #else
108 #define CONSOLE_RX_BYTES_PW 4
109 #endif
110
111 struct qcom_geni_serial_port {
112 struct uart_port uport;
113 struct geni_se se;
114 const char *name;
115 u32 tx_fifo_depth;
116 u32 tx_fifo_width;
117 u32 rx_fifo_depth;
118 bool setup;
119 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
120 unsigned int baud;
121 unsigned int tx_bytes_pw;
122 unsigned int rx_bytes_pw;
123 void *rx_fifo;
124 u32 loopback;
125 bool brk;
126
127 unsigned int tx_remaining;
128 int wakeup_irq;
129 bool rx_tx_swap;
130 bool cts_rts_swap;
131 };
132
133 static const struct uart_ops qcom_geni_console_pops;
134 static const struct uart_ops qcom_geni_uart_pops;
135 static struct uart_driver qcom_geni_console_driver;
136 static struct uart_driver qcom_geni_uart_driver;
137 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
138 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
139 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
140 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
141 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
142
143 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
144 32000000, 48000000, 64000000, 80000000,
145 96000000, 100000000, 102400000,
146 112000000, 120000000, 128000000};
147
148 #define to_dev_port(ptr, member) \
149 container_of(ptr, struct qcom_geni_serial_port, member)
150
151 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
152 [0] = {
153 .uport = {
154 .iotype = UPIO_MEM,
155 .ops = &qcom_geni_uart_pops,
156 .flags = UPF_BOOT_AUTOCONF,
157 .line = 0,
158 },
159 },
160 [1] = {
161 .uport = {
162 .iotype = UPIO_MEM,
163 .ops = &qcom_geni_uart_pops,
164 .flags = UPF_BOOT_AUTOCONF,
165 .line = 1,
166 },
167 },
168 [2] = {
169 .uport = {
170 .iotype = UPIO_MEM,
171 .ops = &qcom_geni_uart_pops,
172 .flags = UPF_BOOT_AUTOCONF,
173 .line = 2,
174 },
175 },
176 };
177
178 static struct qcom_geni_serial_port qcom_geni_console_port = {
179 .uport = {
180 .iotype = UPIO_MEM,
181 .ops = &qcom_geni_console_pops,
182 .flags = UPF_BOOT_AUTOCONF,
183 .line = 0,
184 },
185 };
186
187 static int qcom_geni_serial_request_port(struct uart_port *uport)
188 {
189 struct platform_device *pdev = to_platform_device(uport->dev);
190 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
191
192 uport->membase = devm_platform_ioremap_resource(pdev, 0);
193 if (IS_ERR(uport->membase))
194 return PTR_ERR(uport->membase);
195 port->se.base = uport->membase;
196 return 0;
197 }
198
199 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
200 {
201 if (cfg_flags & UART_CONFIG_TYPE) {
202 uport->type = PORT_MSM;
203 qcom_geni_serial_request_port(uport);
204 }
205 }
206
207 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
208 {
209 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
210 u32 geni_ios;
211
212 if (uart_console(uport)) {
213 mctrl |= TIOCM_CTS;
214 } else {
215 geni_ios = readl(uport->membase + SE_GENI_IOS);
216 if (!(geni_ios & IO2_DATA_IN))
217 mctrl |= TIOCM_CTS;
218 }
219
220 return mctrl;
221 }
222
223 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
224 unsigned int mctrl)
225 {
226 u32 uart_manual_rfr = 0;
227 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
228
229 if (uart_console(uport))
230 return;
231
232 if (mctrl & TIOCM_LOOP)
233 port->loopback = RX_TX_CTS_RTS_SORTED;
234
235 if (!(mctrl & TIOCM_RTS))
236 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
237 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
238 }
239
240 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
241 {
242 return "MSM";
243 }
244
245 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
246 {
247 struct qcom_geni_serial_port *port;
248 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
249
250 if (line < 0 || line >= nr_ports)
251 return ERR_PTR(-ENXIO);
252
253 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
254 return port;
255 }
256
257 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
258 int offset, int field, bool set)
259 {
260 u32 reg;
261 struct qcom_geni_serial_port *port;
262 unsigned int baud;
263 unsigned int fifo_bits;
264 unsigned long timeout_us = 20000;
265
266 if (uport->private_data) {
267 port = to_dev_port(uport, uport);
268 baud = port->baud;
269 if (!baud)
270 baud = 115200;
271 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
272 /*
273 * Total polling iterations based on FIFO worth of bytes to be
274 * sent at current baud. Add a little fluff to the wait.
275 */
276 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
277 }
278
279 /*
280 * Use custom implementation instead of readl_poll_atomic since ktimer
281 * is not ready at the time of early console.
282 */
283 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
284 while (timeout_us) {
285 reg = readl(uport->membase + offset);
286 if ((bool)(reg & field) == set)
287 return true;
288 udelay(10);
289 timeout_us -= 10;
290 }
291 return false;
292 }
293
294 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
295 {
296 u32 m_cmd;
297
298 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
299 m_cmd = UART_START_TX << M_OPCODE_SHFT;
300 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
301 }
302
303 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
304 {
305 int done;
306 u32 irq_clear = M_CMD_DONE_EN;
307
308 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
309 M_CMD_DONE_EN, true);
310 if (!done) {
311 writel(M_GENI_CMD_ABORT, uport->membase +
312 SE_GENI_M_CMD_CTRL_REG);
313 irq_clear |= M_CMD_ABORT_EN;
314 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
315 M_CMD_ABORT_EN, true);
316 }
317 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
318 }
319
320 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
321 {
322 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
323
324 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
325 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
326 S_GENI_CMD_ABORT, false);
327 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
328 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
329 }
330
331 #ifdef CONFIG_CONSOLE_POLL
332 static int qcom_geni_serial_get_char(struct uart_port *uport)
333 {
334 u32 rx_fifo;
335 u32 status;
336
337 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
338 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
339
340 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
341 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
342
343 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
344 if (!(status & RX_FIFO_WC_MSK))
345 return NO_POLL_CHAR;
346
347 rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
348 return rx_fifo & 0xff;
349 }
350
351 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
352 unsigned char c)
353 {
354 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
355 qcom_geni_serial_setup_tx(uport, 1);
356 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
357 M_TX_FIFO_WATERMARK_EN, true));
358 writel(c, uport->membase + SE_GENI_TX_FIFOn);
359 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
360 qcom_geni_serial_poll_tx_done(uport);
361 }
362 #endif
363
364 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
365 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
366 {
367 writel(ch, uport->membase + SE_GENI_TX_FIFOn);
368 }
369
370 static void
371 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
372 unsigned int count)
373 {
374 int i;
375 u32 bytes_to_send = count;
376
377 for (i = 0; i < count; i++) {
378 /*
379 * uart_console_write() adds a carriage return for each newline.
380 * Account for additional bytes to be written.
381 */
382 if (s[i] == '\n')
383 bytes_to_send++;
384 }
385
386 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
387 qcom_geni_serial_setup_tx(uport, bytes_to_send);
388 for (i = 0; i < count; ) {
389 size_t chars_to_write = 0;
390 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
391
392 /*
393 * If the WM bit never set, then the Tx state machine is not
394 * in a valid state, so break, cancel/abort any existing
395 * command. Unfortunately the current data being written is
396 * lost.
397 */
398 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
399 M_TX_FIFO_WATERMARK_EN, true))
400 break;
401 chars_to_write = min_t(size_t, count - i, avail / 2);
402 uart_console_write(uport, s + i, chars_to_write,
403 qcom_geni_serial_wr_char);
404 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
405 SE_GENI_M_IRQ_CLEAR);
406 i += chars_to_write;
407 }
408 qcom_geni_serial_poll_tx_done(uport);
409 }
410
411 static void qcom_geni_serial_console_write(struct console *co, const char *s,
412 unsigned int count)
413 {
414 struct uart_port *uport;
415 struct qcom_geni_serial_port *port;
416 bool locked = true;
417 unsigned long flags;
418 u32 geni_status;
419 u32 irq_en;
420
421 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
422
423 port = get_port_from_line(co->index, true);
424 if (IS_ERR(port))
425 return;
426
427 uport = &port->uport;
428 if (oops_in_progress)
429 locked = spin_trylock_irqsave(&uport->lock, flags);
430 else
431 spin_lock_irqsave(&uport->lock, flags);
432
433 geni_status = readl(uport->membase + SE_GENI_STATUS);
434
435 /* Cancel the current write to log the fault */
436 if (!locked) {
437 geni_se_cancel_m_cmd(&port->se);
438 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
439 M_CMD_CANCEL_EN, true)) {
440 geni_se_abort_m_cmd(&port->se);
441 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
442 M_CMD_ABORT_EN, true);
443 writel(M_CMD_ABORT_EN, uport->membase +
444 SE_GENI_M_IRQ_CLEAR);
445 }
446 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
447 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
448 /*
449 * It seems we can't interrupt existing transfers if all data
450 * has been sent, in which case we need to look for done first.
451 */
452 qcom_geni_serial_poll_tx_done(uport);
453
454 if (uart_circ_chars_pending(&uport->state->xmit)) {
455 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
456 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
457 uport->membase + SE_GENI_M_IRQ_EN);
458 }
459 }
460
461 __qcom_geni_serial_console_write(uport, s, count);
462
463 if (port->tx_remaining)
464 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
465
466 if (locked)
467 spin_unlock_irqrestore(&uport->lock, flags);
468 }
469
470 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
471 {
472 u32 i;
473 unsigned char buf[sizeof(u32)];
474 struct tty_port *tport;
475 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
476
477 tport = &uport->state->port;
478 for (i = 0; i < bytes; ) {
479 int c;
480 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
481
482 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
483 i += chunk;
484 if (drop)
485 continue;
486
487 for (c = 0; c < chunk; c++) {
488 int sysrq;
489
490 uport->icount.rx++;
491 if (port->brk && buf[c] == 0) {
492 port->brk = false;
493 if (uart_handle_break(uport))
494 continue;
495 }
496
497 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
498
499 if (!sysrq)
500 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
501 }
502 }
503 if (!drop)
504 tty_flip_buffer_push(tport);
505 return 0;
506 }
507 #else
508 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
509 {
510 return -EPERM;
511 }
512
513 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
514
515 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
516 {
517 struct tty_port *tport;
518 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
519 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
520 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
521 int ret;
522
523 tport = &uport->state->port;
524 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
525 if (drop)
526 return 0;
527
528 ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
529 if (ret != bytes) {
530 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
531 __func__, ret, bytes);
532 WARN_ON_ONCE(1);
533 }
534 uport->icount.rx += ret;
535 tty_flip_buffer_push(tport);
536 return ret;
537 }
538
539 static void qcom_geni_serial_start_tx(struct uart_port *uport)
540 {
541 u32 irq_en;
542 u32 status;
543
544 status = readl(uport->membase + SE_GENI_STATUS);
545 if (status & M_GENI_CMD_ACTIVE)
546 return;
547
548 if (!qcom_geni_serial_tx_empty(uport))
549 return;
550
551 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
552 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
553
554 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
555 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
556 }
557
558 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
559 {
560 u32 irq_en;
561 u32 status;
562 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
563
564 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
565 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
566 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
567 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
568 status = readl(uport->membase + SE_GENI_STATUS);
569 /* Possible stop tx is called multiple times. */
570 if (!(status & M_GENI_CMD_ACTIVE))
571 return;
572
573 geni_se_cancel_m_cmd(&port->se);
574 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
575 M_CMD_CANCEL_EN, true)) {
576 geni_se_abort_m_cmd(&port->se);
577 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
578 M_CMD_ABORT_EN, true);
579 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
580 }
581 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
582 }
583
584 static void qcom_geni_serial_start_rx(struct uart_port *uport)
585 {
586 u32 irq_en;
587 u32 status;
588 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
589
590 status = readl(uport->membase + SE_GENI_STATUS);
591 if (status & S_GENI_CMD_ACTIVE)
592 qcom_geni_serial_stop_rx(uport);
593
594 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
595
596 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
597 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
598 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
599
600 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
601 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
602 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
603 }
604
605 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
606 {
607 u32 irq_en;
608 u32 status;
609 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
610 u32 s_irq_status;
611
612 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
613 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
614 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
615
616 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
617 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
618 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
619
620 status = readl(uport->membase + SE_GENI_STATUS);
621 /* Possible stop rx is called multiple times. */
622 if (!(status & S_GENI_CMD_ACTIVE))
623 return;
624
625 geni_se_cancel_s_cmd(&port->se);
626 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
627 S_CMD_CANCEL_EN, true);
628 /*
629 * If timeout occurs secondary engine remains active
630 * and Abort sequence is executed.
631 */
632 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
633 /* Flush the Rx buffer */
634 if (s_irq_status & S_RX_FIFO_LAST_EN)
635 qcom_geni_serial_handle_rx(uport, true);
636 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
637
638 status = readl(uport->membase + SE_GENI_STATUS);
639 if (status & S_GENI_CMD_ACTIVE)
640 qcom_geni_serial_abort_rx(uport);
641 }
642
643 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
644 {
645 u32 status;
646 u32 word_cnt;
647 u32 last_word_byte_cnt;
648 u32 last_word_partial;
649 u32 total_bytes;
650 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
651
652 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
653 word_cnt = status & RX_FIFO_WC_MSK;
654 last_word_partial = status & RX_LAST;
655 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
656 RX_LAST_BYTE_VALID_SHFT;
657
658 if (!word_cnt)
659 return;
660 total_bytes = port->rx_bytes_pw * (word_cnt - 1);
661 if (last_word_partial && last_word_byte_cnt)
662 total_bytes += last_word_byte_cnt;
663 else
664 total_bytes += port->rx_bytes_pw;
665 port->handle_rx(uport, total_bytes, drop);
666 }
667
668 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
669 bool active)
670 {
671 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
672 struct circ_buf *xmit = &uport->state->xmit;
673 size_t avail;
674 size_t remaining;
675 size_t pending;
676 int i;
677 u32 status;
678 u32 irq_en;
679 unsigned int chunk;
680 int tail;
681
682 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
683
684 /* Complete the current tx command before taking newly added data */
685 if (active)
686 pending = port->tx_remaining;
687 else
688 pending = uart_circ_chars_pending(xmit);
689
690 /* All data has been transmitted and acknowledged as received */
691 if (!pending && !status && done) {
692 qcom_geni_serial_stop_tx(uport);
693 goto out_write_wakeup;
694 }
695
696 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
697 avail *= port->tx_bytes_pw;
698
699 tail = xmit->tail;
700 chunk = min(avail, pending);
701 if (!chunk)
702 goto out_write_wakeup;
703
704 if (!port->tx_remaining) {
705 qcom_geni_serial_setup_tx(uport, pending);
706 port->tx_remaining = pending;
707
708 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
709 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
710 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
711 uport->membase + SE_GENI_M_IRQ_EN);
712 }
713
714 remaining = chunk;
715 for (i = 0; i < chunk; ) {
716 unsigned int tx_bytes;
717 u8 buf[sizeof(u32)];
718 int c;
719
720 memset(buf, 0, ARRAY_SIZE(buf));
721 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
722
723 for (c = 0; c < tx_bytes ; c++) {
724 buf[c] = xmit->buf[tail++];
725 tail &= UART_XMIT_SIZE - 1;
726 }
727
728 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
729
730 i += tx_bytes;
731 uport->icount.tx += tx_bytes;
732 remaining -= tx_bytes;
733 port->tx_remaining -= tx_bytes;
734 }
735
736 xmit->tail = tail;
737
738 /*
739 * The tx fifo watermark is level triggered and latched. Though we had
740 * cleared it in qcom_geni_serial_isr it will have already reasserted
741 * so we must clear it again here after our writes.
742 */
743 writel(M_TX_FIFO_WATERMARK_EN,
744 uport->membase + SE_GENI_M_IRQ_CLEAR);
745
746 out_write_wakeup:
747 if (!port->tx_remaining) {
748 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
749 if (irq_en & M_TX_FIFO_WATERMARK_EN)
750 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
751 uport->membase + SE_GENI_M_IRQ_EN);
752 }
753
754 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
755 uart_write_wakeup(uport);
756 }
757
758 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
759 {
760 u32 m_irq_en;
761 u32 m_irq_status;
762 u32 s_irq_status;
763 u32 geni_status;
764 struct uart_port *uport = dev;
765 unsigned long flags;
766 bool drop_rx = false;
767 struct tty_port *tport = &uport->state->port;
768 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
769
770 if (uport->suspended)
771 return IRQ_NONE;
772
773 spin_lock_irqsave(&uport->lock, flags);
774 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
775 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
776 geni_status = readl(uport->membase + SE_GENI_STATUS);
777 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
778 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
779 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
780
781 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
782 goto out_unlock;
783
784 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
785 uport->icount.overrun++;
786 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
787 }
788
789 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
790 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
791 geni_status & M_GENI_CMD_ACTIVE);
792
793 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
794 if (s_irq_status & S_GP_IRQ_0_EN)
795 uport->icount.parity++;
796 drop_rx = true;
797 } else if (s_irq_status & S_GP_IRQ_2_EN ||
798 s_irq_status & S_GP_IRQ_3_EN) {
799 uport->icount.brk++;
800 port->brk = true;
801 }
802
803 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
804 s_irq_status & S_RX_FIFO_LAST_EN)
805 qcom_geni_serial_handle_rx(uport, drop_rx);
806
807 out_unlock:
808 uart_unlock_and_check_sysrq(uport, flags);
809
810 return IRQ_HANDLED;
811 }
812
813 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
814 {
815 struct uart_port *uport;
816
817 uport = &port->uport;
818 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
819 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
820 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
821 uport->fifosize =
822 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
823 }
824
825
826 static void qcom_geni_serial_shutdown(struct uart_port *uport)
827 {
828 disable_irq(uport->irq);
829 }
830
831 static int qcom_geni_serial_port_setup(struct uart_port *uport)
832 {
833 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
834 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
835 u32 proto;
836 u32 pin_swap;
837
838 if (uart_console(uport)) {
839 port->tx_bytes_pw = 1;
840 port->rx_bytes_pw = CONSOLE_RX_BYTES_PW;
841 } else {
842 port->tx_bytes_pw = 4;
843 port->rx_bytes_pw = 4;
844 }
845
846 proto = geni_se_read_proto(&port->se);
847 if (proto != GENI_SE_UART) {
848 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
849 return -ENXIO;
850 }
851
852 qcom_geni_serial_stop_rx(uport);
853
854 get_tx_fifo_size(port);
855
856 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
857
858 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
859 if (port->rx_tx_swap) {
860 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
861 pin_swap |= IO_MACRO_IO2_IO3_SWAP;
862 }
863 if (port->cts_rts_swap) {
864 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
865 pin_swap |= IO_MACRO_IO0_SEL;
866 }
867 /* Configure this register if RX-TX, CTS-RTS pins are swapped */
868 if (port->rx_tx_swap || port->cts_rts_swap)
869 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
870
871 /*
872 * Make an unconditional cancel on the main sequencer to reset
873 * it else we could end up in data loss scenarios.
874 */
875 if (uart_console(uport))
876 qcom_geni_serial_poll_tx_done(uport);
877 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
878 false, true, false);
879 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
880 false, false, true);
881 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
882 geni_se_select_mode(&port->se, GENI_SE_FIFO);
883 port->setup = true;
884
885 return 0;
886 }
887
888 static int qcom_geni_serial_startup(struct uart_port *uport)
889 {
890 int ret;
891 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
892
893 if (!port->setup) {
894 ret = qcom_geni_serial_port_setup(uport);
895 if (ret)
896 return ret;
897 }
898 enable_irq(uport->irq);
899
900 return 0;
901 }
902
903 static unsigned long get_clk_cfg(unsigned long clk_freq)
904 {
905 int i;
906
907 for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
908 if (!(root_freq[i] % clk_freq))
909 return root_freq[i];
910 }
911 return 0;
912 }
913
914 static unsigned long get_clk_div_rate(unsigned int baud,
915 unsigned int sampling_rate, unsigned int *clk_div)
916 {
917 unsigned long ser_clk;
918 unsigned long desired_clk;
919
920 desired_clk = baud * sampling_rate;
921 ser_clk = get_clk_cfg(desired_clk);
922 if (!ser_clk) {
923 pr_err("%s: Can't find matching DFS entry for baud %d\n",
924 __func__, baud);
925 return ser_clk;
926 }
927
928 *clk_div = ser_clk / desired_clk;
929 return ser_clk;
930 }
931
932 static void qcom_geni_serial_set_termios(struct uart_port *uport,
933 struct ktermios *termios, struct ktermios *old)
934 {
935 unsigned int baud;
936 u32 bits_per_char;
937 u32 tx_trans_cfg;
938 u32 tx_parity_cfg;
939 u32 rx_trans_cfg;
940 u32 rx_parity_cfg;
941 u32 stop_bit_len;
942 unsigned int clk_div;
943 u32 ser_clk_cfg;
944 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
945 unsigned long clk_rate;
946 u32 ver, sampling_rate;
947
948 qcom_geni_serial_stop_rx(uport);
949 /* baud rate */
950 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
951 port->baud = baud;
952
953 sampling_rate = UART_OVERSAMPLING;
954 /* Sampling rate is halved for IP versions >= 2.5 */
955 ver = geni_se_get_qup_hw_version(&port->se);
956 if (GENI_SE_VERSION_MAJOR(ver) >= 2 && GENI_SE_VERSION_MINOR(ver) >= 5)
957 sampling_rate /= 2;
958
959 clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
960 if (!clk_rate)
961 goto out_restart_rx;
962
963 uport->uartclk = clk_rate;
964 clk_set_rate(port->se.clk, clk_rate);
965 ser_clk_cfg = SER_CLK_EN;
966 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
967
968 /* parity */
969 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
970 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
971 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
972 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
973 if (termios->c_cflag & PARENB) {
974 tx_trans_cfg |= UART_TX_PAR_EN;
975 rx_trans_cfg |= UART_RX_PAR_EN;
976 tx_parity_cfg |= PAR_CALC_EN;
977 rx_parity_cfg |= PAR_CALC_EN;
978 if (termios->c_cflag & PARODD) {
979 tx_parity_cfg |= PAR_ODD;
980 rx_parity_cfg |= PAR_ODD;
981 } else if (termios->c_cflag & CMSPAR) {
982 tx_parity_cfg |= PAR_SPACE;
983 rx_parity_cfg |= PAR_SPACE;
984 } else {
985 tx_parity_cfg |= PAR_EVEN;
986 rx_parity_cfg |= PAR_EVEN;
987 }
988 } else {
989 tx_trans_cfg &= ~UART_TX_PAR_EN;
990 rx_trans_cfg &= ~UART_RX_PAR_EN;
991 tx_parity_cfg &= ~PAR_CALC_EN;
992 rx_parity_cfg &= ~PAR_CALC_EN;
993 }
994
995 /* bits per char */
996 switch (termios->c_cflag & CSIZE) {
997 case CS5:
998 bits_per_char = 5;
999 break;
1000 case CS6:
1001 bits_per_char = 6;
1002 break;
1003 case CS7:
1004 bits_per_char = 7;
1005 break;
1006 case CS8:
1007 default:
1008 bits_per_char = 8;
1009 break;
1010 }
1011
1012 /* stop bits */
1013 if (termios->c_cflag & CSTOPB)
1014 stop_bit_len = TX_STOP_BIT_LEN_2;
1015 else
1016 stop_bit_len = TX_STOP_BIT_LEN_1;
1017
1018 /* flow control, clear the CTS_MASK bit if using flow control. */
1019 if (termios->c_cflag & CRTSCTS)
1020 tx_trans_cfg &= ~UART_CTS_MASK;
1021 else
1022 tx_trans_cfg |= UART_CTS_MASK;
1023
1024 if (baud)
1025 uart_update_timeout(uport, termios->c_cflag, baud);
1026
1027 if (!uart_console(uport))
1028 writel(port->loopback,
1029 uport->membase + SE_UART_LOOPBACK_CFG);
1030 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1031 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1032 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1033 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1034 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1035 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1036 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1037 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1038 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1039 out_restart_rx:
1040 qcom_geni_serial_start_rx(uport);
1041 }
1042
1043 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1044 {
1045 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1046 }
1047
1048 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1049 static int __init qcom_geni_console_setup(struct console *co, char *options)
1050 {
1051 struct uart_port *uport;
1052 struct qcom_geni_serial_port *port;
1053 int baud = 9600;
1054 int bits = 8;
1055 int parity = 'n';
1056 int flow = 'n';
1057 int ret;
1058
1059 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1060 return -ENXIO;
1061
1062 port = get_port_from_line(co->index, true);
1063 if (IS_ERR(port)) {
1064 pr_err("Invalid line %d\n", co->index);
1065 return PTR_ERR(port);
1066 }
1067
1068 uport = &port->uport;
1069
1070 if (unlikely(!uport->membase))
1071 return -ENXIO;
1072
1073 if (!port->setup) {
1074 ret = qcom_geni_serial_port_setup(uport);
1075 if (ret)
1076 return ret;
1077 }
1078
1079 if (options)
1080 uart_parse_options(options, &baud, &parity, &bits, &flow);
1081
1082 return uart_set_options(uport, co, baud, parity, bits, flow);
1083 }
1084
1085 static void qcom_geni_serial_earlycon_write(struct console *con,
1086 const char *s, unsigned int n)
1087 {
1088 struct earlycon_device *dev = con->data;
1089
1090 __qcom_geni_serial_console_write(&dev->port, s, n);
1091 }
1092
1093 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1094 const char *opt)
1095 {
1096 struct uart_port *uport = &dev->port;
1097 u32 tx_trans_cfg;
1098 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
1099 u32 rx_trans_cfg = 0;
1100 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
1101 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
1102 u32 bits_per_char;
1103 struct geni_se se;
1104
1105 if (!uport->membase)
1106 return -EINVAL;
1107
1108 memset(&se, 0, sizeof(se));
1109 se.base = uport->membase;
1110 if (geni_se_read_proto(&se) != GENI_SE_UART)
1111 return -ENXIO;
1112 /*
1113 * Ignore Flow control.
1114 * n = 8.
1115 */
1116 tx_trans_cfg = UART_CTS_MASK;
1117 bits_per_char = BITS_PER_BYTE;
1118
1119 /*
1120 * Make an unconditional cancel on the main sequencer to reset
1121 * it else we could end up in data loss scenarios.
1122 */
1123 qcom_geni_serial_poll_tx_done(uport);
1124 qcom_geni_serial_abort_rx(uport);
1125 geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
1126 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1127 geni_se_select_mode(&se, GENI_SE_FIFO);
1128
1129 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1130 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1131 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1132 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1133 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1134 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1135 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1136
1137 dev->con->write = qcom_geni_serial_earlycon_write;
1138 dev->con->setup = NULL;
1139 return 0;
1140 }
1141 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1142 qcom_geni_serial_earlycon_setup);
1143
1144 static int __init console_register(struct uart_driver *drv)
1145 {
1146 return uart_register_driver(drv);
1147 }
1148
1149 static void console_unregister(struct uart_driver *drv)
1150 {
1151 uart_unregister_driver(drv);
1152 }
1153
1154 static struct console cons_ops = {
1155 .name = "ttyMSM",
1156 .write = qcom_geni_serial_console_write,
1157 .device = uart_console_device,
1158 .setup = qcom_geni_console_setup,
1159 .flags = CON_PRINTBUFFER,
1160 .index = -1,
1161 .data = &qcom_geni_console_driver,
1162 };
1163
1164 static struct uart_driver qcom_geni_console_driver = {
1165 .owner = THIS_MODULE,
1166 .driver_name = "qcom_geni_console",
1167 .dev_name = "ttyMSM",
1168 .nr = GENI_UART_CONS_PORTS,
1169 .cons = &cons_ops,
1170 };
1171 #else
1172 static int console_register(struct uart_driver *drv)
1173 {
1174 return 0;
1175 }
1176
1177 static void console_unregister(struct uart_driver *drv)
1178 {
1179 }
1180 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1181
1182 static struct uart_driver qcom_geni_uart_driver = {
1183 .owner = THIS_MODULE,
1184 .driver_name = "qcom_geni_uart",
1185 .dev_name = "ttyHS",
1186 .nr = GENI_UART_PORTS,
1187 };
1188
1189 static void qcom_geni_serial_pm(struct uart_port *uport,
1190 unsigned int new_state, unsigned int old_state)
1191 {
1192 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1193
1194 /* If we've never been called, treat it as off */
1195 if (old_state == UART_PM_STATE_UNDEFINED)
1196 old_state = UART_PM_STATE_OFF;
1197
1198 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
1199 geni_se_resources_on(&port->se);
1200 else if (new_state == UART_PM_STATE_OFF &&
1201 old_state == UART_PM_STATE_ON)
1202 geni_se_resources_off(&port->se);
1203 }
1204
1205 static const struct uart_ops qcom_geni_console_pops = {
1206 .tx_empty = qcom_geni_serial_tx_empty,
1207 .stop_tx = qcom_geni_serial_stop_tx,
1208 .start_tx = qcom_geni_serial_start_tx,
1209 .stop_rx = qcom_geni_serial_stop_rx,
1210 .set_termios = qcom_geni_serial_set_termios,
1211 .startup = qcom_geni_serial_startup,
1212 .request_port = qcom_geni_serial_request_port,
1213 .config_port = qcom_geni_serial_config_port,
1214 .shutdown = qcom_geni_serial_shutdown,
1215 .type = qcom_geni_serial_get_type,
1216 .set_mctrl = qcom_geni_serial_set_mctrl,
1217 .get_mctrl = qcom_geni_serial_get_mctrl,
1218 #ifdef CONFIG_CONSOLE_POLL
1219 .poll_get_char = qcom_geni_serial_get_char,
1220 .poll_put_char = qcom_geni_serial_poll_put_char,
1221 #endif
1222 .pm = qcom_geni_serial_pm,
1223 };
1224
1225 static const struct uart_ops qcom_geni_uart_pops = {
1226 .tx_empty = qcom_geni_serial_tx_empty,
1227 .stop_tx = qcom_geni_serial_stop_tx,
1228 .start_tx = qcom_geni_serial_start_tx,
1229 .stop_rx = qcom_geni_serial_stop_rx,
1230 .set_termios = qcom_geni_serial_set_termios,
1231 .startup = qcom_geni_serial_startup,
1232 .request_port = qcom_geni_serial_request_port,
1233 .config_port = qcom_geni_serial_config_port,
1234 .shutdown = qcom_geni_serial_shutdown,
1235 .type = qcom_geni_serial_get_type,
1236 .set_mctrl = qcom_geni_serial_set_mctrl,
1237 .get_mctrl = qcom_geni_serial_get_mctrl,
1238 .pm = qcom_geni_serial_pm,
1239 };
1240
1241 static int qcom_geni_serial_probe(struct platform_device *pdev)
1242 {
1243 int ret = 0;
1244 int line = -1;
1245 struct qcom_geni_serial_port *port;
1246 struct uart_port *uport;
1247 struct resource *res;
1248 int irq;
1249 bool console = false;
1250 struct uart_driver *drv;
1251
1252 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1253 console = true;
1254
1255 if (console) {
1256 drv = &qcom_geni_console_driver;
1257 line = of_alias_get_id(pdev->dev.of_node, "serial");
1258 } else {
1259 drv = &qcom_geni_uart_driver;
1260 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1261 }
1262
1263 port = get_port_from_line(line, console);
1264 if (IS_ERR(port)) {
1265 dev_err(&pdev->dev, "Invalid line %d\n", line);
1266 return PTR_ERR(port);
1267 }
1268
1269 uport = &port->uport;
1270 /* Don't allow 2 drivers to access the same port */
1271 if (uport->private_data)
1272 return -ENODEV;
1273
1274 uport->dev = &pdev->dev;
1275 port->se.dev = &pdev->dev;
1276 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1277 port->se.clk = devm_clk_get(&pdev->dev, "se");
1278 if (IS_ERR(port->se.clk)) {
1279 ret = PTR_ERR(port->se.clk);
1280 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1281 return ret;
1282 }
1283
1284 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1285 if (!res)
1286 return -EINVAL;
1287 uport->mapbase = res->start;
1288
1289 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1290 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1291 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1292
1293 if (!console) {
1294 port->rx_fifo = devm_kcalloc(uport->dev,
1295 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
1296 if (!port->rx_fifo)
1297 return -ENOMEM;
1298 }
1299
1300 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1301 "qcom_geni_serial_%s%d",
1302 uart_console(uport) ? "console" : "uart", uport->line);
1303 if (!port->name)
1304 return -ENOMEM;
1305
1306 irq = platform_get_irq(pdev, 0);
1307 if (irq < 0)
1308 return irq;
1309 uport->irq = irq;
1310 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1311
1312 if (!console)
1313 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1314
1315 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1316 port->rx_tx_swap = true;
1317
1318 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1319 port->cts_rts_swap = true;
1320
1321 uport->private_data = drv;
1322 platform_set_drvdata(pdev, port);
1323 port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1324
1325 ret = uart_add_one_port(drv, uport);
1326 if (ret)
1327 return ret;
1328
1329 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1330 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1331 IRQF_TRIGGER_HIGH, port->name, uport);
1332 if (ret) {
1333 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1334 uart_remove_one_port(drv, uport);
1335 return ret;
1336 }
1337
1338 /*
1339 * Set pm_runtime status as ACTIVE so that wakeup_irq gets
1340 * enabled/disabled from dev_pm_arm_wake_irq during system
1341 * suspend/resume respectively.
1342 */
1343 pm_runtime_set_active(&pdev->dev);
1344
1345 if (port->wakeup_irq > 0) {
1346 device_init_wakeup(&pdev->dev, true);
1347 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1348 port->wakeup_irq);
1349 if (ret) {
1350 device_init_wakeup(&pdev->dev, false);
1351 uart_remove_one_port(drv, uport);
1352 return ret;
1353 }
1354 }
1355
1356 return 0;
1357 }
1358
1359 static int qcom_geni_serial_remove(struct platform_device *pdev)
1360 {
1361 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1362 struct uart_driver *drv = port->uport.private_data;
1363
1364 dev_pm_clear_wake_irq(&pdev->dev);
1365 device_init_wakeup(&pdev->dev, false);
1366 uart_remove_one_port(drv, &port->uport);
1367
1368 return 0;
1369 }
1370
1371 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1372 {
1373 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1374 struct uart_port *uport = &port->uport;
1375
1376 return uart_suspend_port(uport->private_data, uport);
1377 }
1378
1379 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1380 {
1381 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1382 struct uart_port *uport = &port->uport;
1383
1384 return uart_resume_port(uport->private_data, uport);
1385 }
1386
1387 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1388 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1389 qcom_geni_serial_sys_resume)
1390 };
1391
1392 static const struct of_device_id qcom_geni_serial_match_table[] = {
1393 { .compatible = "qcom,geni-debug-uart", },
1394 { .compatible = "qcom,geni-uart", },
1395 {}
1396 };
1397 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1398
1399 static struct platform_driver qcom_geni_serial_platform_driver = {
1400 .remove = qcom_geni_serial_remove,
1401 .probe = qcom_geni_serial_probe,
1402 .driver = {
1403 .name = "qcom_geni_serial",
1404 .of_match_table = qcom_geni_serial_match_table,
1405 .pm = &qcom_geni_serial_pm_ops,
1406 },
1407 };
1408
1409 static int __init qcom_geni_serial_init(void)
1410 {
1411 int ret;
1412
1413 ret = console_register(&qcom_geni_console_driver);
1414 if (ret)
1415 return ret;
1416
1417 ret = uart_register_driver(&qcom_geni_uart_driver);
1418 if (ret) {
1419 console_unregister(&qcom_geni_console_driver);
1420 return ret;
1421 }
1422
1423 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1424 if (ret) {
1425 console_unregister(&qcom_geni_console_driver);
1426 uart_unregister_driver(&qcom_geni_uart_driver);
1427 }
1428 return ret;
1429 }
1430 module_init(qcom_geni_serial_init);
1431
1432 static void __exit qcom_geni_serial_exit(void)
1433 {
1434 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1435 console_unregister(&qcom_geni_console_driver);
1436 uart_unregister_driver(&qcom_geni_uart_driver);
1437 }
1438 module_exit(qcom_geni_serial_exit);
1439
1440 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1441 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support