1 #ifndef __ASM_POWERPC_CPUTABLE_H
2 #define __ASM_POWERPC_CPUTABLE_H
4 #include <asm/asm-compat.h>
6 #define PPC_FEATURE_32 0x80000000
7 #define PPC_FEATURE_64 0x40000000
8 #define PPC_FEATURE_601_INSTR 0x20000000
9 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10 #define PPC_FEATURE_HAS_FPU 0x08000000
11 #define PPC_FEATURE_HAS_MMU 0x04000000
12 #define PPC_FEATURE_HAS_4xxMAC 0x02000000
13 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14 #define PPC_FEATURE_HAS_SPE 0x00800000
15 #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16 #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
17 #define PPC_FEATURE_NO_TB 0x00100000
18 #define PPC_FEATURE_POWER4 0x00080000
19 #define PPC_FEATURE_POWER5 0x00040000
20 #define PPC_FEATURE_POWER5_PLUS 0x00020000
21 #define PPC_FEATURE_CELL 0x00010000
22 #define PPC_FEATURE_BOOKE 0x00008000
23 #define PPC_FEATURE_SMT 0x00004000
24 #define PPC_FEATURE_ICACHE_SNOOP 0x00002000
25 #define PPC_FEATURE_ARCH_2_05 0x00001000
30 /* This structure can grow, it's real size is used by head.S code
31 * via the mkdefs mechanism.
35 typedef void (*cpu_setup_t
)(unsigned long offset
, struct cpu_spec
* spec
);
37 enum powerpc_oprofile_type
{
38 PPC_OPROFILE_INVALID
= 0,
39 PPC_OPROFILE_RS64
= 1,
40 PPC_OPROFILE_POWER4
= 2,
42 PPC_OPROFILE_BOOKE
= 4,
46 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
47 unsigned int pvr_mask
;
48 unsigned int pvr_value
;
51 unsigned long cpu_features
; /* Kernel features */
52 unsigned int cpu_user_features
; /* Userland features */
54 /* cache line sizes */
55 unsigned int icache_bsize
;
56 unsigned int dcache_bsize
;
58 /* number of performance monitor counters */
59 unsigned int num_pmcs
;
61 /* this is called to initialize various CPU bits like L1 cache,
62 * BHT, SPD, etc... from head.S before branching to identify_machine
64 cpu_setup_t cpu_setup
;
66 /* Used by oprofile userspace to select the right counters */
67 char *oprofile_cpu_type
;
69 /* Processor specific oprofile operations */
70 enum powerpc_oprofile_type oprofile_type
;
72 /* Name of processor class, for the ELF AT_PLATFORM entry */
76 extern struct cpu_spec
*cur_cpu_spec
;
78 extern void identify_cpu(unsigned long offset
, unsigned long cpu
);
79 extern void do_cpu_ftr_fixups(unsigned long offset
);
81 #endif /* __ASSEMBLY__ */
83 /* CPU kernel features */
85 /* Retain the 32b definitions all use bottom half of word */
86 #define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
87 #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
88 #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
89 #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
90 #define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
91 #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
92 #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
93 #define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
94 #define CPU_FTR_601 ASM_CONST(0x0000000000000100)
95 #define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
96 #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
97 #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
98 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
99 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
100 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
101 #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
102 #define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
103 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
104 #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
105 #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
106 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
109 /* Add the 64b processor unique features in the top half of the word */
110 #define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
111 #define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
112 #define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
113 #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
114 #define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
115 #define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
116 #define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
117 #define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
118 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
119 #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
120 #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
121 #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
122 #define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000)
123 #define CPU_FTR_PURR ASM_CONST(0x0000400000000000)
125 /* ensure on 32b processors the flags are available for compiling but
126 * don't do anything */
127 #define CPU_FTR_SLB ASM_CONST(0x0)
128 #define CPU_FTR_16M_PAGE ASM_CONST(0x0)
129 #define CPU_FTR_TLBIEL ASM_CONST(0x0)
130 #define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
131 #define CPU_FTR_IABR ASM_CONST(0x0)
132 #define CPU_FTR_MMCRA ASM_CONST(0x0)
133 #define CPU_FTR_CTRL ASM_CONST(0x0)
134 #define CPU_FTR_SMT ASM_CONST(0x0)
135 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
136 #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
137 #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
138 #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0)
139 #define CPU_FTR_PURR ASM_CONST(0x0)
144 #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
145 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
146 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
148 /* iSeries doesn't support large pages */
149 #ifdef CONFIG_PPC_ISERIES
150 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
152 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
153 #endif /* CONFIG_PPC_ISERIES */
155 /* We only set the altivec features if the kernel was compiled with altivec
158 #ifdef CONFIG_ALTIVEC
159 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
160 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
162 #define CPU_FTR_ALTIVEC_COMP 0
163 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
166 /* We need to mark all pages as being coherent if we're SMP or we
167 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
168 * it for PCI "streaming/prefetch" to work properly.
170 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
171 || defined(CONFIG_PPC_83xx)
172 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
174 #define CPU_FTR_COMMON 0
177 /* The powersave features NAP & DOZE seems to confuse BDI when
178 debugging. So if a BDI is used, disable theses
180 #ifndef CONFIG_BDI_SWITCH
181 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
182 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
184 #define CPU_FTR_MAYBE_CAN_DOZE 0
185 #define CPU_FTR_MAYBE_CAN_NAP 0
188 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
189 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
190 !defined(CONFIG_BOOKE))
192 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
193 #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
194 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
195 CPU_FTR_MAYBE_CAN_NAP)
196 #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
197 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE)
198 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
199 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
200 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP)
201 #define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
202 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
203 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP)
204 #define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
205 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
206 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP)
207 #define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
208 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
209 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
210 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
211 #define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
212 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
213 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
215 #define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
216 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
217 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
218 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS)
219 #define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
220 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
221 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
222 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS)
223 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
224 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
225 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
226 CPU_FTR_MAYBE_CAN_NAP)
227 #define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
228 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
229 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
230 CPU_FTR_MAYBE_CAN_NAP)
231 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
232 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
233 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
234 CPU_FTR_NEED_COHERENT)
235 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
237 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
238 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
239 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
240 CPU_FTR_NEED_COHERENT)
241 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
243 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
244 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
245 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT)
246 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
248 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
249 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
250 CPU_FTR_NEED_COHERENT)
251 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
253 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
254 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
255 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
256 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS)
257 #define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
259 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
260 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
261 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
262 CPU_FTR_NEED_COHERENT)
263 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
265 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
266 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
267 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
268 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC)
269 #define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
271 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
272 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
273 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
274 CPU_FTR_NEED_COHERENT)
275 #define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
277 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
278 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
279 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
280 CPU_FTR_NEED_COHERENT)
281 #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
282 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
283 #define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
284 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
285 #define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
286 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
288 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
289 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
290 #define CPU_FTRS_POWER3_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
291 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
292 #define CPU_FTRS_POWER4_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
293 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN)
294 #define CPU_FTRS_970_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
295 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP | \
296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
297 #define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
298 #define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
299 CPU_FTR_NODSISRALIGN)
300 #define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
301 CPU_FTR_NODSISRALIGN)
302 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
303 #define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
304 CPU_FTR_NODSISRALIGN)
305 #define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
306 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
307 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
309 #define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
310 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR)
311 #define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
312 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
313 CPU_FTR_MMCRA | CPU_FTR_CTRL)
314 #define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
315 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA)
316 #define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
317 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
318 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
319 #define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
320 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
321 CPU_FTR_MMCRA | CPU_FTR_SMT | \
322 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
323 CPU_FTR_MMCRA_SIHV | CPU_FTR_PURR)
324 #define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
325 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
326 CPU_FTR_MMCRA | CPU_FTR_SMT | \
327 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
328 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE)
329 #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
330 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
331 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
332 CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO)
333 #define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
334 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
338 #define CPU_FTRS_POSSIBLE \
339 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
340 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
341 CPU_FTRS_CELL | CPU_FTR_CI_LARGE_PAGE)
346 CPU_FTRS_PPC601
| CPU_FTRS_603
| CPU_FTRS_604
| CPU_FTRS_740_NOTAU
|
347 CPU_FTRS_740
| CPU_FTRS_750
| CPU_FTRS_750FX1
|
348 CPU_FTRS_750FX2
| CPU_FTRS_750FX
| CPU_FTRS_750GX
|
349 CPU_FTRS_7400_NOTAU
| CPU_FTRS_7400
| CPU_FTRS_7450_20
|
350 CPU_FTRS_7450_21
| CPU_FTRS_7450_23
| CPU_FTRS_7455_1
|
351 CPU_FTRS_7455_20
| CPU_FTRS_7455
| CPU_FTRS_7447_10
|
352 CPU_FTRS_7447
| CPU_FTRS_7447A
| CPU_FTRS_82XX
|
353 CPU_FTRS_G2_LE
| CPU_FTRS_E300
| CPU_FTRS_CLASSIC32
|
355 CPU_FTRS_GENERIC_32
|
357 #ifdef CONFIG_PPC64BRIDGE
361 CPU_FTRS_POWER4_32
| CPU_FTRS_970_32
|
376 CPU_FTRS_E500
| CPU_FTRS_E500_2
|
380 #endif /* __powerpc64__ */
383 #define CPU_FTRS_ALWAYS \
384 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
385 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
386 CPU_FTRS_CELL & CPU_FTRS_POSSIBLE)
391 CPU_FTRS_PPC601
& CPU_FTRS_603
& CPU_FTRS_604
& CPU_FTRS_740_NOTAU
&
392 CPU_FTRS_740
& CPU_FTRS_750
& CPU_FTRS_750FX1
&
393 CPU_FTRS_750FX2
& CPU_FTRS_750FX
& CPU_FTRS_750GX
&
394 CPU_FTRS_7400_NOTAU
& CPU_FTRS_7400
& CPU_FTRS_7450_20
&
395 CPU_FTRS_7450_21
& CPU_FTRS_7450_23
& CPU_FTRS_7455_1
&
396 CPU_FTRS_7455_20
& CPU_FTRS_7455
& CPU_FTRS_7447_10
&
397 CPU_FTRS_7447
& CPU_FTRS_7447A
& CPU_FTRS_82XX
&
398 CPU_FTRS_G2_LE
& CPU_FTRS_E300
& CPU_FTRS_CLASSIC32
&
400 CPU_FTRS_GENERIC_32
&
402 #ifdef CONFIG_PPC64BRIDGE
406 CPU_FTRS_POWER4_32
& CPU_FTRS_970_32
&
421 CPU_FTRS_E500
& CPU_FTRS_E500_2
&
425 #endif /* __powerpc64__ */
427 static inline int cpu_has_feature(unsigned long feature
)
429 return (CPU_FTRS_ALWAYS
& feature
) ||
431 & cur_cpu_spec
->cpu_features
435 #endif /* !__ASSEMBLY__ */
439 #define BEGIN_FTR_SECTION 98:
441 #ifndef __powerpc64__
442 #define END_FTR_SECTION(msk, val) \
444 .section __ftr_fixup,"a"; \
451 #else /* __powerpc64__ */
452 #define END_FTR_SECTION(msk, val) \
454 .section __ftr_fixup,"a"; \
461 #endif /* __powerpc64__ */
463 #define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
464 #define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
465 #endif /* __ASSEMBLY__ */
467 #endif /* __KERNEL__ */
468 #endif /* __ASM_POWERPC_CPUTABLE_H */