include/asm-powerpc/iseries/it_lp_queue.h

   1 /*
   2  * Copyright (C) 2001  Mike Corrigan IBM Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  17  */
  18 #ifndef _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H
  19 #define _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H
  20
  21 /*
  22  *      This control block defines the simple LP queue structure that is
  23  *      shared between the hypervisor (PLIC) and the OS in order to send
  24  *      events to an LP.
  25  */
  26
  27 #include <asm/types.h>
  28 #include <asm/ptrace.h>
  29
  30 struct HvLpEvent;
  31
  32 #define ITMaxLpQueues   8
  33
  34 #define NotUsed         0       // Queue will not be used by PLIC
  35 #define DedicatedIo     1       // Queue dedicated to IO processor specified
  36 #define DedicatedLp     2       // Queue dedicated to LP specified
  37 #define Shared          3       // Queue shared for both IO and LP
  38
  39 #define LpEventStackSize        4096
  40 #define LpEventMaxSize          256
  41 #define LpEventAlign            64
  42
  43 struct hvlpevent_queue {
  44 /*
  45  * The xSlicCurEventPtr is the pointer to the next event stack entry
  46  * that will become valid.  The OS must peek at this entry to determine
  47  * if it is valid.  PLIC will set the valid indicator as the very last
  48  * store into that entry.
  49  *
  50  * When the OS has completed processing of the event then it will mark
  51  * the event as invalid so that PLIC knows it can store into that event
  52  * location again.
  53  *
  54  * If the event stack fills and there are overflow events, then PLIC
  55  * will set the xPlicOverflowIntPending flag in which case the OS will
  56  * have to fetch the additional LP events once they have drained the
  57  * event stack.
  58  *
  59  * The first 16-bytes are known by both the OS and PLIC.  The remainder
  60  * of the cache line is for use by the OS.
  61  */
  62         u8      xPlicOverflowIntPending;// 0x00 Overflow events are pending
  63         u8      xPlicStatus;            // 0x01 DedicatedIo or DedicatedLp or NotUsed
  64         u16     xSlicLogicalProcIndex;  // 0x02 Logical Proc Index for correlation
  65         u8      xPlicRsvd[12];          // 0x04
  66         char    *xSlicCurEventPtr;      // 0x10
  67         char    *xSlicLastValidEventPtr; // 0x18
  68         char    *xSlicEventStackPtr;    // 0x20
  69         u8      xIndex;                 // 0x28 unique sequential index.
  70         u8      xSlicRsvd[3];           // 0x29-2b
  71         spinlock_t      lock;
  72 };
  73
  74 extern struct hvlpevent_queue hvlpevent_queue;
  75
  76 extern int hvlpevent_is_pending(void);
  77 extern void process_hvlpevents(struct pt_regs *);
  78 extern void setup_hvlpevent_queue(void);
  79
  80 #endif /* _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H */