[PATCH] uml: add -ffreestanding to CFLAGS
[linux/fpc-iii.git] / include / asm-powerpc / pci.h
blob5d2c9e6c4be2ba1483118e2de61b572ccbb2c2b1
1 #ifndef __ASM_POWERPC_PCI_H
2 #define __ASM_POWERPC_PCI_H
3 #ifdef __KERNEL__
5 /*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/types.h>
13 #include <linux/slab.h>
14 #include <linux/string.h>
15 #include <linux/dma-mapping.h>
17 #include <asm/machdep.h>
18 #include <asm/scatterlist.h>
19 #include <asm/io.h>
20 #include <asm/prom.h>
21 #include <asm/pci-bridge.h>
23 #include <asm-generic/pci-dma-compat.h>
25 #define PCIBIOS_MIN_IO 0x1000
26 #define PCIBIOS_MIN_MEM 0x10000000
28 struct pci_dev;
30 /* Values for the `which' argument to sys_pciconfig_iobase syscall. */
31 #define IOBASE_BRIDGE_NUMBER 0
32 #define IOBASE_MEMORY 1
33 #define IOBASE_IO 2
34 #define IOBASE_ISA_IO 3
35 #define IOBASE_ISA_MEM 4
38 * Set this to 1 if you want the kernel to re-assign all PCI
39 * bus numbers
41 extern int pci_assign_all_buses;
42 #define pcibios_assign_all_busses() (pci_assign_all_buses)
44 #define pcibios_scan_all_fns(a, b) 0
46 static inline void pcibios_set_master(struct pci_dev *dev)
48 /* No special bus mastering setup handling */
51 static inline void pcibios_penalize_isa_irq(int irq, int active)
53 /* We don't do dynamic PCI IRQ allocation */
56 #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
57 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
59 if (ppc_md.pci_get_legacy_ide_irq)
60 return ppc_md.pci_get_legacy_ide_irq(dev, channel);
61 return channel ? 15 : 14;
64 #ifdef CONFIG_PPC64
65 #define HAVE_ARCH_PCI_MWI 1
66 static inline int pcibios_prep_mwi(struct pci_dev *dev)
69 * We would like to avoid touching the cacheline size or MWI bit
70 * but we cant do that with the current pcibios_prep_mwi
71 * interface. pSeries firmware sets the cacheline size (which is not
72 * the cpu cacheline size in all cases) and hardware treats MWI
73 * the same as memory write. So we dont touch the cacheline size
74 * here and allow the generic code to set the MWI bit.
76 return 0;
79 extern struct dma_mapping_ops pci_dma_ops;
81 /* For DAC DMA, we currently don't support it by default, but
82 * we let 64-bit platforms override this.
84 static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask)
86 if (pci_dma_ops.dac_dma_supported)
87 return pci_dma_ops.dac_dma_supported(&hwdev->dev, mask);
88 return 0;
91 #ifdef CONFIG_PCI
92 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
93 enum pci_dma_burst_strategy *strat,
94 unsigned long *strategy_parameter)
96 unsigned long cacheline_size;
97 u8 byte;
99 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
100 if (byte == 0)
101 cacheline_size = 1024;
102 else
103 cacheline_size = (int) byte * 4;
105 *strat = PCI_DMA_BURST_MULTIPLE;
106 *strategy_parameter = cacheline_size;
108 #endif
110 extern int pci_domain_nr(struct pci_bus *bus);
112 /* Decide whether to display the domain number in /proc */
113 extern int pci_proc_domain(struct pci_bus *bus);
115 #else /* 32-bit */
117 #ifdef CONFIG_PCI
118 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
119 enum pci_dma_burst_strategy *strat,
120 unsigned long *strategy_parameter)
122 *strat = PCI_DMA_BURST_INFINITY;
123 *strategy_parameter = ~0UL;
125 #endif
128 * At present there are very few 32-bit PPC machines that can have
129 * memory above the 4GB point, and we don't support that.
131 #define pci_dac_dma_supported(pci_dev, mask) (0)
133 /* Return the index of the PCI controller for device PDEV. */
134 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
136 /* Set the name of the bus as it appears in /proc/bus/pci */
137 static inline int pci_proc_domain(struct pci_bus *bus)
139 return 0;
142 #endif /* CONFIG_PPC64 */
144 struct vm_area_struct;
145 /* Map a range of PCI memory or I/O space for a device into user space */
146 int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
147 enum pci_mmap_state mmap_state, int write_combine);
149 /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
150 #define HAVE_PCI_MMAP 1
152 #ifdef CONFIG_PPC64
153 /* pci_unmap_{single,page} is not a nop, thus... */
154 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
155 dma_addr_t ADDR_NAME;
156 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
157 __u32 LEN_NAME;
158 #define pci_unmap_addr(PTR, ADDR_NAME) \
159 ((PTR)->ADDR_NAME)
160 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
161 (((PTR)->ADDR_NAME) = (VAL))
162 #define pci_unmap_len(PTR, LEN_NAME) \
163 ((PTR)->LEN_NAME)
164 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
165 (((PTR)->LEN_NAME) = (VAL))
167 /* The PCI address space does not equal the physical memory address
168 * space (we have an IOMMU). The IDE and SCSI device layers use
169 * this boolean for bounce buffer decisions.
171 #define PCI_DMA_BUS_IS_PHYS (0)
173 #else /* 32-bit */
175 /* The PCI address space does equal the physical memory
176 * address space (no IOMMU). The IDE and SCSI device layers use
177 * this boolean for bounce buffer decisions.
179 #define PCI_DMA_BUS_IS_PHYS (1)
181 /* pci_unmap_{page,single} is a nop so... */
182 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
183 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
184 #define pci_unmap_addr(PTR, ADDR_NAME) (0)
185 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
186 #define pci_unmap_len(PTR, LEN_NAME) (0)
187 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
189 #endif /* CONFIG_PPC64 */
191 extern void pcibios_resource_to_bus(struct pci_dev *dev,
192 struct pci_bus_region *region,
193 struct resource *res);
195 extern void pcibios_bus_to_resource(struct pci_dev *dev,
196 struct resource *res,
197 struct pci_bus_region *region);
199 static inline struct resource *pcibios_select_root(struct pci_dev *pdev,
200 struct resource *res)
202 struct resource *root = NULL;
204 if (res->flags & IORESOURCE_IO)
205 root = &ioport_resource;
206 if (res->flags & IORESOURCE_MEM)
207 root = &iomem_resource;
209 return root;
212 extern int unmap_bus_range(struct pci_bus *bus);
214 extern int remap_bus_range(struct pci_bus *bus);
216 extern void pcibios_fixup_device_resources(struct pci_dev *dev,
217 struct pci_bus *bus);
219 extern void pcibios_claim_one_bus(struct pci_bus *b);
221 extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
223 extern struct pci_dev *of_create_pci_dev(struct device_node *node,
224 struct pci_bus *bus, int devfn);
226 extern void of_scan_pci_bridge(struct device_node *node,
227 struct pci_dev *dev);
229 extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
231 extern int pci_read_irq_line(struct pci_dev *dev);
233 extern void pcibios_add_platform_entries(struct pci_dev *dev);
235 struct file;
236 extern pgprot_t pci_phys_mem_access_prot(struct file *file,
237 unsigned long pfn,
238 unsigned long size,
239 pgprot_t prot);
241 #if defined(CONFIG_PPC_MULTIPLATFORM) || defined(CONFIG_PPC32)
242 #define HAVE_ARCH_PCI_RESOURCE_TO_USER
243 extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
244 const struct resource *rsrc,
245 u64 *start, u64 *end);
246 #endif /* CONFIG_PPC_MULTIPLATFORM || CONFIG_PPC32 */
248 #endif /* __KERNEL__ */
249 #endif /* __ASM_POWERPC_PCI_H */