drivers/pci/host/pci-keystone.c

   1 /*
   2  * PCIe host controller driver for Texas Instruments Keystone SoCs
   3  *
   4  * Copyright (C) 2013-2014 Texas Instruments., Ltd.
   5  *              http://www.ti.com
   6  *
   7  * Author: Murali Karicheri <m-karicheri2@ti.com>
   8  * Implementation based on pci-exynos.c and pcie-designware.c
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/irqchip/chained_irq.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/irqdomain.h>
  19 #include <linux/module.h>
  20 #include <linux/msi.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of.h>
  23 #include <linux/of_pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/phy/phy.h>
  26 #include <linux/resource.h>
  27 #include <linux/signal.h>
  28
  29 #include "pcie-designware.h"
  30 #include "pci-keystone.h"
  31
  32 #define DRIVER_NAME     "keystone-pcie"
  33
  34 /* driver specific constants */
  35 #define MAX_MSI_HOST_IRQS               8
  36 #define MAX_LEGACY_HOST_IRQS            4
  37
  38 /* DEV_STAT_CTRL */
  39 #define PCIE_CAP_BASE           0x70
  40
  41 /* PCIE controller device IDs */
  42 #define PCIE_RC_K2HK            0xb008
  43 #define PCIE_RC_K2E             0xb009
  44 #define PCIE_RC_K2L             0xb00a
  45
  46 #define to_keystone_pcie(x)     container_of(x, struct keystone_pcie, pp)
  47
  48 static void quirk_limit_mrrs(struct pci_dev *dev)
  49 {
  50         struct pci_bus *bus = dev->bus;
  51         struct pci_dev *bridge = bus->self;
  52         static const struct pci_device_id rc_pci_devids[] = {
  53                 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
  54                  .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
  55                 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),
  56                  .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
  57                 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
  58                  .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
  59                 { 0, },
  60         };
  61
  62         if (pci_is_root_bus(bus))
  63                 return;
  64
  65         /* look for the host bridge */
  66         while (!pci_is_root_bus(bus)) {
  67                 bridge = bus->self;
  68                 bus = bus->parent;
  69         }
  70
  71         if (bridge) {
  72                 /*
  73                  * Keystone PCI controller has a h/w limitation of
  74                  * 256 bytes maximum read request size.  It can't handle
  75                  * anything higher than this.  So force this limit on
  76                  * all downstream devices.
  77                  */
  78                 if (pci_match_id(rc_pci_devids, bridge)) {
  79                         if (pcie_get_readrq(dev) > 256) {
  80                                 dev_info(&dev->dev, "limiting MRRS to 256\n");
  81                                 pcie_set_readrq(dev, 256);
  82                         }
  83                 }
  84         }
  85 }
  86 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
  87
  88 static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
  89 {
  90         struct pcie_port *pp = &ks_pcie->pp;
  91         unsigned int retries;
  92
  93         dw_pcie_setup_rc(pp);
  94
  95         if (dw_pcie_link_up(pp)) {
  96                 dev_err(pp->dev, "Link already up\n");
  97                 return 0;
  98         }
  99
 100         ks_dw_pcie_initiate_link_train(ks_pcie);
 101         /* check if the link is up or not */
 102         for (retries = 0; retries < 200; retries++) {
 103                 if (dw_pcie_link_up(pp))
 104                         return 0;
 105                 usleep_range(100, 1000);
 106                 ks_dw_pcie_initiate_link_train(ks_pcie);
 107         }
 108
 109         dev_err(pp->dev, "phy link never came up\n");
 110         return -EINVAL;
 111 }
 112
 113 static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
 114 {
 115         unsigned int irq = irq_desc_get_irq(desc);
 116         struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
 117         u32 offset = irq - ks_pcie->msi_host_irqs[0];
 118         struct pcie_port *pp = &ks_pcie->pp;
 119         struct irq_chip *chip = irq_desc_get_chip(desc);
 120
 121         dev_dbg(pp->dev, "%s, irq %d\n", __func__, irq);
 122
 123         /*
 124          * The chained irq handler installation would have replaced normal
 125          * interrupt driver handler so we need to take care of mask/unmask and
 126          * ack operation.
 127          */
 128         chained_irq_enter(chip, desc);
 129         ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
 130         chained_irq_exit(chip, desc);
 131 }
 132
 133 /**
 134  * ks_pcie_legacy_irq_handler() - Handle legacy interrupt
 135  * @irq: IRQ line for legacy interrupts
 136  * @desc: Pointer to irq descriptor
 137  *
 138  * Traverse through pending legacy interrupts and invoke handler for each. Also
 139  * takes care of interrupt controller level mask/ack operation.
 140  */
 141 static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
 142 {
 143         unsigned int irq = irq_desc_get_irq(desc);
 144         struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
 145         struct pcie_port *pp = &ks_pcie->pp;
 146         u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
 147         struct irq_chip *chip = irq_desc_get_chip(desc);
 148
 149         dev_dbg(pp->dev, ": Handling legacy irq %d\n", irq);
 150
 151         /*
 152          * The chained irq handler installation would have replaced normal
 153          * interrupt driver handler so we need to take care of mask/unmask and
 154          * ack operation.
 155          */
 156         chained_irq_enter(chip, desc);
 157         ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
 158         chained_irq_exit(chip, desc);
 159 }
 160
 161 static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
 162                                            char *controller, int *num_irqs)
 163 {
 164         int temp, max_host_irqs, legacy = 1, *host_irqs, ret = -EINVAL;
 165         struct device *dev = ks_pcie->pp.dev;
 166         struct device_node *np_pcie = dev->of_node, **np_temp;
 167
 168         if (!strcmp(controller, "msi-interrupt-controller"))
 169                 legacy = 0;
 170
 171         if (legacy) {
 172                 np_temp = &ks_pcie->legacy_intc_np;
 173                 max_host_irqs = MAX_LEGACY_HOST_IRQS;
 174                 host_irqs = &ks_pcie->legacy_host_irqs[0];
 175         } else {
 176                 np_temp = &ks_pcie->msi_intc_np;
 177                 max_host_irqs = MAX_MSI_HOST_IRQS;
 178                 host_irqs =  &ks_pcie->msi_host_irqs[0];
 179         }
 180
 181         /* interrupt controller is in a child node */
 182         *np_temp = of_find_node_by_name(np_pcie, controller);
 183         if (!(*np_temp)) {
 184                 dev_err(dev, "Node for %s is absent\n", controller);
 185                 goto out;
 186         }
 187         temp = of_irq_count(*np_temp);
 188         if (!temp)
 189                 goto out;
 190         if (temp > max_host_irqs)
 191                 dev_warn(dev, "Too many %s interrupts defined %u\n",
 192                         (legacy ? "legacy" : "MSI"), temp);
 193
 194         /*
 195          * support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to
 196          * 7 (MSI)
 197          */
 198         for (temp = 0; temp < max_host_irqs; temp++) {
 199                 host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp);
 200                 if (!host_irqs[temp])
 201                         break;
 202         }
 203         if (temp) {
 204                 *num_irqs = temp;
 205                 ret = 0;
 206         }
 207 out:
 208         return ret;
 209 }
 210
 211 static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
 212 {
 213         int i;
 214
 215         /* Legacy IRQ */
 216         for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
 217                 irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i],
 218                                                  ks_pcie_legacy_irq_handler,
 219                                                  ks_pcie);
 220         }
 221         ks_dw_pcie_enable_legacy_irqs(ks_pcie);
 222
 223         /* MSI IRQ */
 224         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 225                 for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
 226                         irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i],
 227                                                          ks_pcie_msi_irq_handler,
 228                                                          ks_pcie);
 229                 }
 230         }
 231 }
 232
 233 /*
 234  * When a PCI device does not exist during config cycles, keystone host gets a
 235  * bus error instead of returning 0xffffffff. This handler always returns 0
 236  * for this kind of faults.
 237  */
 238 static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
 239                                 struct pt_regs *regs)
 240 {
 241         unsigned long instr = *(unsigned long *) instruction_pointer(regs);
 242
 243         if ((instr & 0x0e100090) == 0x00100090) {
 244                 int reg = (instr >> 12) & 15;
 245
 246                 regs->uregs[reg] = -1;
 247                 regs->ARM_pc += 4;
 248         }
 249
 250         return 0;
 251 }
 252
 253 static void __init ks_pcie_host_init(struct pcie_port *pp)
 254 {
 255         struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
 256         u32 val;
 257
 258         ks_pcie_establish_link(ks_pcie);
 259         ks_dw_pcie_setup_rc_app_regs(ks_pcie);
 260         ks_pcie_setup_interrupts(ks_pcie);
 261         writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
 262                         pp->dbi_base + PCI_IO_BASE);
 263
 264         /* update the Vendor ID */
 265         writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID);
 266
 267         /* update the DEV_STAT_CTRL to publish right mrrs */
 268         val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
 269         val &= ~PCI_EXP_DEVCTL_READRQ;
 270         /* set the mrrs to 256 bytes */
 271         val |= BIT(12);
 272         writel(val, pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
 273
 274         /*
 275          * PCIe access errors that result into OCP errors are caught by ARM as
 276          * "External aborts"
 277          */
 278         hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0,
 279                         "Asynchronous external abort");
 280 }
 281
 282 static struct pcie_host_ops keystone_pcie_host_ops = {
 283         .rd_other_conf = ks_dw_pcie_rd_other_conf,
 284         .wr_other_conf = ks_dw_pcie_wr_other_conf,
 285         .link_up = ks_dw_pcie_link_up,
 286         .host_init = ks_pcie_host_init,
 287         .msi_set_irq = ks_dw_pcie_msi_set_irq,
 288         .msi_clear_irq = ks_dw_pcie_msi_clear_irq,
 289         .get_msi_addr = ks_dw_pcie_get_msi_addr,
 290         .msi_host_init = ks_dw_pcie_msi_host_init,
 291         .scan_bus = ks_dw_pcie_v3_65_scan_bus,
 292 };
 293
 294 static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
 295                          struct platform_device *pdev)
 296 {
 297         struct pcie_port *pp = &ks_pcie->pp;
 298         int ret;
 299
 300         ret = ks_pcie_get_irq_controller_info(ks_pcie,
 301                                         "legacy-interrupt-controller",
 302                                         &ks_pcie->num_legacy_host_irqs);
 303         if (ret)
 304                 return ret;
 305
 306         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 307                 ret = ks_pcie_get_irq_controller_info(ks_pcie,
 308                                                 "msi-interrupt-controller",
 309                                                 &ks_pcie->num_msi_host_irqs);
 310                 if (ret)
 311                         return ret;
 312         }
 313
 314         pp->root_bus_nr = -1;
 315         pp->ops = &keystone_pcie_host_ops;
 316         ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
 317         if (ret) {
 318                 dev_err(&pdev->dev, "failed to initialize host\n");
 319                 return ret;
 320         }
 321
 322         return ret;
 323 }
 324
 325 static const struct of_device_id ks_pcie_of_match[] = {
 326         {
 327                 .type = "pci",
 328                 .compatible = "ti,keystone-pcie",
 329         },
 330         { },
 331 };
 332 MODULE_DEVICE_TABLE(of, ks_pcie_of_match);
 333
 334 static int __exit ks_pcie_remove(struct platform_device *pdev)
 335 {
 336         struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
 337
 338         clk_disable_unprepare(ks_pcie->clk);
 339
 340         return 0;
 341 }
 342
 343 static int __init ks_pcie_probe(struct platform_device *pdev)
 344 {
 345         struct device *dev = &pdev->dev;
 346         struct keystone_pcie *ks_pcie;
 347         struct pcie_port *pp;
 348         struct resource *res;
 349         void __iomem *reg_p;
 350         struct phy *phy;
 351         int ret = 0;
 352
 353         ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
 354                                 GFP_KERNEL);
 355         if (!ks_pcie)
 356                 return -ENOMEM;
 357
 358         pp = &ks_pcie->pp;
 359
 360         /* initialize SerDes Phy if present */
 361         phy = devm_phy_get(dev, "pcie-phy");
 362         if (!IS_ERR_OR_NULL(phy)) {
 363                 ret = phy_init(phy);
 364                 if (ret < 0)
 365                         return ret;
 366         }
 367
 368         /* index 2 is to read PCI DEVICE_ID */
 369         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 370         reg_p = devm_ioremap_resource(dev, res);
 371         if (IS_ERR(reg_p))
 372                 return PTR_ERR(reg_p);
 373         ks_pcie->device_id = readl(reg_p) >> 16;
 374         devm_iounmap(dev, reg_p);
 375         devm_release_mem_region(dev, res->start, resource_size(res));
 376
 377         pp->dev = dev;
 378         platform_set_drvdata(pdev, ks_pcie);
 379         ks_pcie->clk = devm_clk_get(dev, "pcie");
 380         if (IS_ERR(ks_pcie->clk)) {
 381                 dev_err(dev, "Failed to get pcie rc clock\n");
 382                 return PTR_ERR(ks_pcie->clk);
 383         }
 384         ret = clk_prepare_enable(ks_pcie->clk);
 385         if (ret)
 386                 return ret;
 387
 388         ret = ks_add_pcie_port(ks_pcie, pdev);
 389         if (ret < 0)
 390                 goto fail_clk;
 391
 392         return 0;
 393 fail_clk:
 394         clk_disable_unprepare(ks_pcie->clk);
 395
 396         return ret;
 397 }
 398
 399 static struct platform_driver ks_pcie_driver __refdata = {
 400         .probe  = ks_pcie_probe,
 401         .remove = __exit_p(ks_pcie_remove),
 402         .driver = {
 403                 .name   = "keystone-pcie",
 404                 .of_match_table = of_match_ptr(ks_pcie_of_match),
 405         },
 406 };
 407
 408 module_platform_driver(ks_pcie_driver);
 409
 410 MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
 411 MODULE_DESCRIPTION("Keystone PCIe host controller driver");
 412 MODULE_LICENSE("GPL v2");