drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <linux/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67 #include <linux/interval_tree.h>
  68 #include <linux/hashtable.h>
  69 #include <linux/fence.h>
  70
  71 #include <ttm/ttm_bo_api.h>
  72 #include <ttm/ttm_bo_driver.h>
  73 #include <ttm/ttm_placement.h>
  74 #include <ttm/ttm_module.h>
  75 #include <ttm/ttm_execbuf_util.h>
  76
  77 #include <drm/drm_gem.h>
  78
  79 #include "radeon_family.h"
  80 #include "radeon_mode.h"
  81 #include "radeon_reg.h"
  82
  83 /*
  84  * Modules parameters.
  85  */
  86 extern int radeon_no_wb;
  87 extern int radeon_modeset;
  88 extern int radeon_dynclks;
  89 extern int radeon_r4xx_atom;
  90 extern int radeon_agpmode;
  91 extern int radeon_vram_limit;
  92 extern int radeon_gart_size;
  93 extern int radeon_benchmarking;
  94 extern int radeon_testing;
  95 extern int radeon_connector_table;
  96 extern int radeon_tv;
  97 extern int radeon_audio;
  98 extern int radeon_disp_priority;
  99 extern int radeon_hw_i2c;
 100 extern int radeon_pcie_gen2;
 101 extern int radeon_msi;
 102 extern int radeon_lockup_timeout;
 103 extern int radeon_fastfb;
 104 extern int radeon_dpm;
 105 extern int radeon_aspm;
 106 extern int radeon_runtime_pm;
 107 extern int radeon_hard_reset;
 108 extern int radeon_vm_size;
 109 extern int radeon_vm_block_size;
 110 extern int radeon_deep_color;
 111 extern int radeon_use_pflipirq;
 112 extern int radeon_bapm;
 113 extern int radeon_backlight;
 114 extern int radeon_auxch;
 115 extern int radeon_mst;
 116 extern int radeon_uvd;
 117 extern int radeon_vce;
 118
 119 /*
 120  * Copy from radeon_drv.h so we don't have to include both and have conflicting
 121  * symbol;
 122  */
 123 #define RADEON_MAX_USEC_TIMEOUT                 100000  /* 100 ms */
 124 #define RADEON_FENCE_JIFFIES_TIMEOUT            (HZ / 2)
 125 #define RADEON_USEC_IB_TEST_TIMEOUT             1000000 /* 1s */
 126 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 127 #define RADEON_IB_POOL_SIZE                     16
 128 #define RADEON_DEBUGFS_MAX_COMPONENTS           32
 129 #define RADEONFB_CONN_LIMIT                     4
 130 #define RADEON_BIOS_NUM_SCRATCH                 8
 131
 132 /* internal ring indices */
 133 /* r1xx+ has gfx CP ring */
 134 #define RADEON_RING_TYPE_GFX_INDEX              0
 135
 136 /* cayman has 2 compute CP rings */
 137 #define CAYMAN_RING_TYPE_CP1_INDEX              1
 138 #define CAYMAN_RING_TYPE_CP2_INDEX              2
 139
 140 /* R600+ has an async dma ring */
 141 #define R600_RING_TYPE_DMA_INDEX                3
 142 /* cayman add a second async dma ring */
 143 #define CAYMAN_RING_TYPE_DMA1_INDEX             4
 144
 145 /* R600+ */
 146 #define R600_RING_TYPE_UVD_INDEX                5
 147
 148 /* TN+ */
 149 #define TN_RING_TYPE_VCE1_INDEX                 6
 150 #define TN_RING_TYPE_VCE2_INDEX                 7
 151
 152 /* max number of rings */
 153 #define RADEON_NUM_RINGS                        8
 154
 155 /* number of hw syncs before falling back on blocking */
 156 #define RADEON_NUM_SYNCS                        4
 157
 158 /* hardcode those limit for now */
 159 #define RADEON_VA_IB_OFFSET                     (1 << 20)
 160 #define RADEON_VA_RESERVED_SIZE                 (8 << 20)
 161 #define RADEON_IB_VM_MAX_SIZE                   (64 << 10)
 162
 163 /* hard reset data */
 164 #define RADEON_ASIC_RESET_DATA                  0x39d5e86b
 165
 166 /* reset flags */
 167 #define RADEON_RESET_GFX                        (1 << 0)
 168 #define RADEON_RESET_COMPUTE                    (1 << 1)
 169 #define RADEON_RESET_DMA                        (1 << 2)
 170 #define RADEON_RESET_CP                         (1 << 3)
 171 #define RADEON_RESET_GRBM                       (1 << 4)
 172 #define RADEON_RESET_DMA1                       (1 << 5)
 173 #define RADEON_RESET_RLC                        (1 << 6)
 174 #define RADEON_RESET_SEM                        (1 << 7)
 175 #define RADEON_RESET_IH                         (1 << 8)
 176 #define RADEON_RESET_VMC                        (1 << 9)
 177 #define RADEON_RESET_MC                         (1 << 10)
 178 #define RADEON_RESET_DISPLAY                    (1 << 11)
 179
 180 /* CG block flags */
 181 #define RADEON_CG_BLOCK_GFX                     (1 << 0)
 182 #define RADEON_CG_BLOCK_MC                      (1 << 1)
 183 #define RADEON_CG_BLOCK_SDMA                    (1 << 2)
 184 #define RADEON_CG_BLOCK_UVD                     (1 << 3)
 185 #define RADEON_CG_BLOCK_VCE                     (1 << 4)
 186 #define RADEON_CG_BLOCK_HDP                     (1 << 5)
 187 #define RADEON_CG_BLOCK_BIF                     (1 << 6)
 188
 189 /* CG flags */
 190 #define RADEON_CG_SUPPORT_GFX_MGCG              (1 << 0)
 191 #define RADEON_CG_SUPPORT_GFX_MGLS              (1 << 1)
 192 #define RADEON_CG_SUPPORT_GFX_CGCG              (1 << 2)
 193 #define RADEON_CG_SUPPORT_GFX_CGLS              (1 << 3)
 194 #define RADEON_CG_SUPPORT_GFX_CGTS              (1 << 4)
 195 #define RADEON_CG_SUPPORT_GFX_CGTS_LS           (1 << 5)
 196 #define RADEON_CG_SUPPORT_GFX_CP_LS             (1 << 6)
 197 #define RADEON_CG_SUPPORT_GFX_RLC_LS            (1 << 7)
 198 #define RADEON_CG_SUPPORT_MC_LS                 (1 << 8)
 199 #define RADEON_CG_SUPPORT_MC_MGCG               (1 << 9)
 200 #define RADEON_CG_SUPPORT_SDMA_LS               (1 << 10)
 201 #define RADEON_CG_SUPPORT_SDMA_MGCG             (1 << 11)
 202 #define RADEON_CG_SUPPORT_BIF_LS                (1 << 12)
 203 #define RADEON_CG_SUPPORT_UVD_MGCG              (1 << 13)
 204 #define RADEON_CG_SUPPORT_VCE_MGCG              (1 << 14)
 205 #define RADEON_CG_SUPPORT_HDP_LS                (1 << 15)
 206 #define RADEON_CG_SUPPORT_HDP_MGCG              (1 << 16)
 207
 208 /* PG flags */
 209 #define RADEON_PG_SUPPORT_GFX_PG                (1 << 0)
 210 #define RADEON_PG_SUPPORT_GFX_SMG               (1 << 1)
 211 #define RADEON_PG_SUPPORT_GFX_DMG               (1 << 2)
 212 #define RADEON_PG_SUPPORT_UVD                   (1 << 3)
 213 #define RADEON_PG_SUPPORT_VCE                   (1 << 4)
 214 #define RADEON_PG_SUPPORT_CP                    (1 << 5)
 215 #define RADEON_PG_SUPPORT_GDS                   (1 << 6)
 216 #define RADEON_PG_SUPPORT_RLC_SMU_HS            (1 << 7)
 217 #define RADEON_PG_SUPPORT_SDMA                  (1 << 8)
 218 #define RADEON_PG_SUPPORT_ACP                   (1 << 9)
 219 #define RADEON_PG_SUPPORT_SAMU                  (1 << 10)
 220
 221 /* max cursor sizes (in pixels) */
 222 #define CURSOR_WIDTH 64
 223 #define CURSOR_HEIGHT 64
 224
 225 #define CIK_CURSOR_WIDTH 128
 226 #define CIK_CURSOR_HEIGHT 128
 227
 228 /*
 229  * Errata workarounds.
 230  */
 231 enum radeon_pll_errata {
 232         CHIP_ERRATA_R300_CG             = 0x00000001,
 233         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 234         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 235 };
 236
 237
 238 struct radeon_device;
 239
 240
 241 /*
 242  * BIOS.
 243  */
 244 bool radeon_get_bios(struct radeon_device *rdev);
 245
 246 /*
 247  * Dummy page
 248  */
 249 struct radeon_dummy_page {
 250         uint64_t        entry;
 251         struct page     *page;
 252         dma_addr_t      addr;
 253 };
 254 int radeon_dummy_page_init(struct radeon_device *rdev);
 255 void radeon_dummy_page_fini(struct radeon_device *rdev);
 256
 257
 258 /*
 259  * Clocks
 260  */
 261 struct radeon_clock {
 262         struct radeon_pll p1pll;
 263         struct radeon_pll p2pll;
 264         struct radeon_pll dcpll;
 265         struct radeon_pll spll;
 266         struct radeon_pll mpll;
 267         /* 10 Khz units */
 268         uint32_t default_mclk;
 269         uint32_t default_sclk;
 270         uint32_t default_dispclk;
 271         uint32_t current_dispclk;
 272         uint32_t dp_extclk;
 273         uint32_t max_pixel_clock;
 274         uint32_t vco_freq;
 275 };
 276
 277 /*
 278  * Power management
 279  */
 280 int radeon_pm_init(struct radeon_device *rdev);
 281 int radeon_pm_late_init(struct radeon_device *rdev);
 282 void radeon_pm_fini(struct radeon_device *rdev);
 283 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 284 void radeon_pm_suspend(struct radeon_device *rdev);
 285 void radeon_pm_resume(struct radeon_device *rdev);
 286 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 287 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 288 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
 289                                    u8 clock_type,
 290                                    u32 clock,
 291                                    bool strobe_mode,
 292                                    struct atom_clock_dividers *dividers);
 293 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
 294                                         u32 clock,
 295                                         bool strobe_mode,
 296                                         struct atom_mpll_param *mpll_param);
 297 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
 298 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
 299                                           u16 voltage_level, u8 voltage_type,
 300                                           u32 *gpio_value, u32 *gpio_mask);
 301 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
 302                                          u32 eng_clock, u32 mem_clock);
 303 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
 304                                  u8 voltage_type, u16 *voltage_step);
 305 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
 306                              u16 voltage_id, u16 *voltage);
 307 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
 308                                                       u16 *voltage,
 309                                                       u16 leakage_idx);
 310 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
 311                                           u16 *leakage_id);
 312 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
 313                                                          u16 *vddc, u16 *vddci,
 314                                                          u16 virtual_voltage_id,
 315                                                          u16 vbios_voltage_id);
 316 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
 317                                 u16 virtual_voltage_id,
 318                                 u16 *voltage);
 319 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
 320                                       u8 voltage_type,
 321                                       u16 nominal_voltage,
 322                                       u16 *true_voltage);
 323 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
 324                                 u8 voltage_type, u16 *min_voltage);
 325 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
 326                                 u8 voltage_type, u16 *max_voltage);
 327 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
 328                                   u8 voltage_type, u8 voltage_mode,
 329                                   struct atom_voltage_table *voltage_table);
 330 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
 331                                  u8 voltage_type, u8 voltage_mode);
 332 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
 333                               u8 voltage_type,
 334                               u8 *svd_gpio_id, u8 *svc_gpio_id);
 335 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
 336                                    u32 mem_clock);
 337 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
 338                                u32 mem_clock);
 339 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
 340                                   u8 module_index,
 341                                   struct atom_mc_reg_table *reg_table);
 342 int radeon_atom_get_memory_info(struct radeon_device *rdev,
 343                                 u8 module_index, struct atom_memory_info *mem_info);
 344 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
 345                                      bool gddr5, u8 module_index,
 346                                      struct atom_memory_clock_range_table *mclk_range_table);
 347 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
 348                              u16 voltage_id, u16 *voltage);
 349 void rs690_pm_info(struct radeon_device *rdev);
 350 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
 351                                     unsigned *bankh, unsigned *mtaspect,
 352                                     unsigned *tile_split);
 353
 354 /*
 355  * Fences.
 356  */
 357 struct radeon_fence_driver {
 358         struct radeon_device            *rdev;
 359         uint32_t                        scratch_reg;
 360         uint64_t                        gpu_addr;
 361         volatile uint32_t               *cpu_addr;
 362         /* sync_seq is protected by ring emission lock */
 363         uint64_t                        sync_seq[RADEON_NUM_RINGS];
 364         atomic64_t                      last_seq;
 365         bool                            initialized, delayed_irq;
 366         struct delayed_work             lockup_work;
 367 };
 368
 369 struct radeon_fence {
 370         struct fence            base;
 371
 372         struct radeon_device    *rdev;
 373         uint64_t                seq;
 374         /* RB, DMA, etc. */
 375         unsigned                ring;
 376         bool                    is_vm_update;
 377
 378         wait_queue_t            fence_wake;
 379 };
 380
 381 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
 382 int radeon_fence_driver_init(struct radeon_device *rdev);
 383 void radeon_fence_driver_fini(struct radeon_device *rdev);
 384 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
 385 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
 386 void radeon_fence_process(struct radeon_device *rdev, int ring);
 387 bool radeon_fence_signaled(struct radeon_fence *fence);
 388 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
 389 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 390 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
 391 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
 392 int radeon_fence_wait_any(struct radeon_device *rdev,
 393                           struct radeon_fence **fences,
 394                           bool intr);
 395 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 396 void radeon_fence_unref(struct radeon_fence **fence);
 397 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
 398 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
 399 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
 400 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
 401                                                       struct radeon_fence *b)
 402 {
 403         if (!a) {
 404                 return b;
 405         }
 406
 407         if (!b) {
 408                 return a;
 409         }
 410
 411         BUG_ON(a->ring != b->ring);
 412
 413         if (a->seq > b->seq) {
 414                 return a;
 415         } else {
 416                 return b;
 417         }
 418 }
 419
 420 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
 421                                            struct radeon_fence *b)
 422 {
 423         if (!a) {
 424                 return false;
 425         }
 426
 427         if (!b) {
 428                 return true;
 429         }
 430
 431         BUG_ON(a->ring != b->ring);
 432
 433         return a->seq < b->seq;
 434 }
 435
 436 /*
 437  * Tiling registers
 438  */
 439 struct radeon_surface_reg {
 440         struct radeon_bo *bo;
 441 };
 442
 443 #define RADEON_GEM_MAX_SURFACES 8
 444
 445 /*
 446  * TTM.
 447  */
 448 struct radeon_mman {
 449         struct ttm_bo_global_ref        bo_global_ref;
 450         struct drm_global_reference     mem_global_ref;
 451         struct ttm_bo_device            bdev;
 452         bool                            mem_global_referenced;
 453         bool                            initialized;
 454
 455 #if defined(CONFIG_DEBUG_FS)
 456         struct dentry                   *vram;
 457         struct dentry                   *gtt;
 458 #endif
 459 };
 460
 461 struct radeon_bo_list {
 462         struct radeon_bo                *robj;
 463         struct ttm_validate_buffer      tv;
 464         uint64_t                        gpu_offset;
 465         unsigned                        prefered_domains;
 466         unsigned                        allowed_domains;
 467         uint32_t                        tiling_flags;
 468 };
 469
 470 /* bo virtual address in a specific vm */
 471 struct radeon_bo_va {
 472         /* protected by bo being reserved */
 473         struct list_head                bo_list;
 474         uint32_t                        flags;
 475         struct radeon_fence             *last_pt_update;
 476         unsigned                        ref_count;
 477
 478         /* protected by vm mutex */
 479         struct interval_tree_node       it;
 480         struct list_head                vm_status;
 481
 482         /* constant after initialization */
 483         struct radeon_vm                *vm;
 484         struct radeon_bo                *bo;
 485 };
 486
 487 struct radeon_bo {
 488         /* Protected by gem.mutex */
 489         struct list_head                list;
 490         /* Protected by tbo.reserved */
 491         u32                             initial_domain;
 492         struct ttm_place                placements[4];
 493         struct ttm_placement            placement;
 494         struct ttm_buffer_object        tbo;
 495         struct ttm_bo_kmap_obj          kmap;
 496         u32                             flags;
 497         unsigned                        pin_count;
 498         void                            *kptr;
 499         u32                             tiling_flags;
 500         u32                             pitch;
 501         int                             surface_reg;
 502         /* list of all virtual address to which this bo
 503          * is associated to
 504          */
 505         struct list_head                va;
 506         /* Constant after initialization */
 507         struct radeon_device            *rdev;
 508         struct drm_gem_object           gem_base;
 509
 510         struct ttm_bo_kmap_obj          dma_buf_vmap;
 511         pid_t                           pid;
 512
 513         struct radeon_mn                *mn;
 514         struct list_head                mn_list;
 515 };
 516 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 517
 518 int radeon_gem_debugfs_init(struct radeon_device *rdev);
 519
 520 /* sub-allocation manager, it has to be protected by another lock.
 521  * By conception this is an helper for other part of the driver
 522  * like the indirect buffer or semaphore, which both have their
 523  * locking.
 524  *
 525  * Principe is simple, we keep a list of sub allocation in offset
 526  * order (first entry has offset == 0, last entry has the highest
 527  * offset).
 528  *
 529  * When allocating new object we first check if there is room at
 530  * the end total_size - (last_object_offset + last_object_size) >=
 531  * alloc_size. If so we allocate new object there.
 532  *
 533  * When there is not enough room at the end, we start waiting for
 534  * each sub object until we reach object_offset+object_size >=
 535  * alloc_size, this object then become the sub object we return.
 536  *
 537  * Alignment can't be bigger than page size.
 538  *
 539  * Hole are not considered for allocation to keep things simple.
 540  * Assumption is that there won't be hole (all object on same
 541  * alignment).
 542  */
 543 struct radeon_sa_manager {
 544         wait_queue_head_t       wq;
 545         struct radeon_bo        *bo;
 546         struct list_head        *hole;
 547         struct list_head        flist[RADEON_NUM_RINGS];
 548         struct list_head        olist;
 549         unsigned                size;
 550         uint64_t                gpu_addr;
 551         void                    *cpu_ptr;
 552         uint32_t                domain;
 553         uint32_t                align;
 554 };
 555
 556 struct radeon_sa_bo;
 557
 558 /* sub-allocation buffer */
 559 struct radeon_sa_bo {
 560         struct list_head                olist;
 561         struct list_head                flist;
 562         struct radeon_sa_manager        *manager;
 563         unsigned                        soffset;
 564         unsigned                        eoffset;
 565         struct radeon_fence             *fence;
 566 };
 567
 568 /*
 569  * GEM objects.
 570  */
 571 struct radeon_gem {
 572         struct mutex            mutex;
 573         struct list_head        objects;
 574 };
 575
 576 int radeon_gem_init(struct radeon_device *rdev);
 577 void radeon_gem_fini(struct radeon_device *rdev);
 578 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
 579                                 int alignment, int initial_domain,
 580                                 u32 flags, bool kernel,
 581                                 struct drm_gem_object **obj);
 582
 583 int radeon_mode_dumb_create(struct drm_file *file_priv,
 584                             struct drm_device *dev,
 585                             struct drm_mode_create_dumb *args);
 586 int radeon_mode_dumb_mmap(struct drm_file *filp,
 587                           struct drm_device *dev,
 588                           uint32_t handle, uint64_t *offset_p);
 589
 590 /*
 591  * Semaphores.
 592  */
 593 struct radeon_semaphore {
 594         struct radeon_sa_bo     *sa_bo;
 595         signed                  waiters;
 596         uint64_t                gpu_addr;
 597 };
 598
 599 int radeon_semaphore_create(struct radeon_device *rdev,
 600                             struct radeon_semaphore **semaphore);
 601 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
 602                                   struct radeon_semaphore *semaphore);
 603 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
 604                                 struct radeon_semaphore *semaphore);
 605 void radeon_semaphore_free(struct radeon_device *rdev,
 606                            struct radeon_semaphore **semaphore,
 607                            struct radeon_fence *fence);
 608
 609 /*
 610  * Synchronization
 611  */
 612 struct radeon_sync {
 613         struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
 614         struct radeon_fence     *sync_to[RADEON_NUM_RINGS];
 615         struct radeon_fence     *last_vm_update;
 616 };
 617
 618 void radeon_sync_create(struct radeon_sync *sync);
 619 void radeon_sync_fence(struct radeon_sync *sync,
 620                        struct radeon_fence *fence);
 621 int radeon_sync_resv(struct radeon_device *rdev,
 622                      struct radeon_sync *sync,
 623                      struct reservation_object *resv,
 624                      bool shared);
 625 int radeon_sync_rings(struct radeon_device *rdev,
 626                       struct radeon_sync *sync,
 627                       int waiting_ring);
 628 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
 629                       struct radeon_fence *fence);
 630
 631 /*
 632  * GART structures, functions & helpers
 633  */
 634 struct radeon_mc;
 635
 636 #define RADEON_GPU_PAGE_SIZE 4096
 637 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 638 #define RADEON_GPU_PAGE_SHIFT 12
 639 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
 640
 641 #define RADEON_GART_PAGE_DUMMY  0
 642 #define RADEON_GART_PAGE_VALID  (1 << 0)
 643 #define RADEON_GART_PAGE_READ   (1 << 1)
 644 #define RADEON_GART_PAGE_WRITE  (1 << 2)
 645 #define RADEON_GART_PAGE_SNOOP  (1 << 3)
 646
 647 struct radeon_gart {
 648         dma_addr_t                      table_addr;
 649         struct radeon_bo                *robj;
 650         void                            *ptr;
 651         unsigned                        num_gpu_pages;
 652         unsigned                        num_cpu_pages;
 653         unsigned                        table_size;
 654         struct page                     **pages;
 655         uint64_t                        *pages_entry;
 656         bool                            ready;
 657 };
 658
 659 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 660 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 661 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 662 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 663 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
 664 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
 665 int radeon_gart_init(struct radeon_device *rdev);
 666 void radeon_gart_fini(struct radeon_device *rdev);
 667 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 668                         int pages);
 669 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 670                      int pages, struct page **pagelist,
 671                      dma_addr_t *dma_addr, uint32_t flags);
 672
 673
 674 /*
 675  * GPU MC structures, functions & helpers
 676  */
 677 struct radeon_mc {
 678         resource_size_t         aper_size;
 679         resource_size_t         aper_base;
 680         resource_size_t         agp_base;
 681         /* for some chips with <= 32MB we need to lie
 682          * about vram size near mc fb location */
 683         u64                     mc_vram_size;
 684         u64                     visible_vram_size;
 685         u64                     gtt_size;
 686         u64                     gtt_start;
 687         u64                     gtt_end;
 688         u64                     vram_start;
 689         u64                     vram_end;
 690         unsigned                vram_width;
 691         u64                     real_vram_size;
 692         int                     vram_mtrr;
 693         bool                    vram_is_ddr;
 694         bool                    igp_sideport_enabled;
 695         u64                     gtt_base_align;
 696         u64                     mc_mask;
 697 };
 698
 699 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 700 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 701
 702 /*
 703  * GPU scratch registers structures, functions & helpers
 704  */
 705 struct radeon_scratch {
 706         unsigned                num_reg;
 707         uint32_t                reg_base;
 708         bool                    free[32];
 709         uint32_t                reg[32];
 710 };
 711
 712 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 713 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 714
 715 /*
 716  * GPU doorbell structures, functions & helpers
 717  */
 718 #define RADEON_MAX_DOORBELLS 1024       /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
 719
 720 struct radeon_doorbell {
 721         /* doorbell mmio */
 722         resource_size_t         base;
 723         resource_size_t         size;
 724         u32 __iomem             *ptr;
 725         u32                     num_doorbells;  /* Number of doorbells actually reserved for radeon. */
 726         DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
 727 };
 728
 729 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
 730 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
 731 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
 732                                   phys_addr_t *aperture_base,
 733                                   size_t *aperture_size,
 734                                   size_t *start_offset);
 735
 736 /*
 737  * IRQS.
 738  */
 739
 740 struct radeon_flip_work {
 741         struct work_struct              flip_work;
 742         struct work_struct              unpin_work;
 743         struct radeon_device            *rdev;
 744         int                             crtc_id;
 745         uint64_t                        base;
 746         struct drm_pending_vblank_event *event;
 747         struct radeon_bo                *old_rbo;
 748         struct fence                    *fence;
 749         bool                            async;
 750 };
 751
 752 struct r500_irq_stat_regs {
 753         u32 disp_int;
 754         u32 hdmi0_status;
 755 };
 756
 757 struct r600_irq_stat_regs {
 758         u32 disp_int;
 759         u32 disp_int_cont;
 760         u32 disp_int_cont2;
 761         u32 d1grph_int;
 762         u32 d2grph_int;
 763         u32 hdmi0_status;
 764         u32 hdmi1_status;
 765 };
 766
 767 struct evergreen_irq_stat_regs {
 768         u32 disp_int;
 769         u32 disp_int_cont;
 770         u32 disp_int_cont2;
 771         u32 disp_int_cont3;
 772         u32 disp_int_cont4;
 773         u32 disp_int_cont5;
 774         u32 d1grph_int;
 775         u32 d2grph_int;
 776         u32 d3grph_int;
 777         u32 d4grph_int;
 778         u32 d5grph_int;
 779         u32 d6grph_int;
 780         u32 afmt_status1;
 781         u32 afmt_status2;
 782         u32 afmt_status3;
 783         u32 afmt_status4;
 784         u32 afmt_status5;
 785         u32 afmt_status6;
 786 };
 787
 788 struct cik_irq_stat_regs {
 789         u32 disp_int;
 790         u32 disp_int_cont;
 791         u32 disp_int_cont2;
 792         u32 disp_int_cont3;
 793         u32 disp_int_cont4;
 794         u32 disp_int_cont5;
 795         u32 disp_int_cont6;
 796         u32 d1grph_int;
 797         u32 d2grph_int;
 798         u32 d3grph_int;
 799         u32 d4grph_int;
 800         u32 d5grph_int;
 801         u32 d6grph_int;
 802 };
 803
 804 union radeon_irq_stat_regs {
 805         struct r500_irq_stat_regs r500;
 806         struct r600_irq_stat_regs r600;
 807         struct evergreen_irq_stat_regs evergreen;
 808         struct cik_irq_stat_regs cik;
 809 };
 810
 811 struct radeon_irq {
 812         bool                            installed;
 813         spinlock_t                      lock;
 814         atomic_t                        ring_int[RADEON_NUM_RINGS];
 815         bool                            crtc_vblank_int[RADEON_MAX_CRTCS];
 816         atomic_t                        pflip[RADEON_MAX_CRTCS];
 817         wait_queue_head_t               vblank_queue;
 818         bool                            hpd[RADEON_MAX_HPD_PINS];
 819         bool                            afmt[RADEON_MAX_AFMT_BLOCKS];
 820         union radeon_irq_stat_regs      stat_regs;
 821         bool                            dpm_thermal;
 822 };
 823
 824 int radeon_irq_kms_init(struct radeon_device *rdev);
 825 void radeon_irq_kms_fini(struct radeon_device *rdev);
 826 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
 827 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
 828 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
 829 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
 830 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
 831 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
 832 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
 833 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
 834 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
 835
 836 /*
 837  * CP & rings.
 838  */
 839
 840 struct radeon_ib {
 841         struct radeon_sa_bo             *sa_bo;
 842         uint32_t                        length_dw;
 843         uint64_t                        gpu_addr;
 844         uint32_t                        *ptr;
 845         int                             ring;
 846         struct radeon_fence             *fence;
 847         struct radeon_vm                *vm;
 848         bool                            is_const_ib;
 849         struct radeon_sync              sync;
 850 };
 851
 852 struct radeon_ring {
 853         struct radeon_bo        *ring_obj;
 854         volatile uint32_t       *ring;
 855         unsigned                rptr_offs;
 856         unsigned                rptr_save_reg;
 857         u64                     next_rptr_gpu_addr;
 858         volatile u32            *next_rptr_cpu_addr;
 859         unsigned                wptr;
 860         unsigned                wptr_old;
 861         unsigned                ring_size;
 862         unsigned                ring_free_dw;
 863         int                     count_dw;
 864         atomic_t                last_rptr;
 865         atomic64_t              last_activity;
 866         uint64_t                gpu_addr;
 867         uint32_t                align_mask;
 868         uint32_t                ptr_mask;
 869         bool                    ready;
 870         u32                     nop;
 871         u32                     idx;
 872         u64                     last_semaphore_signal_addr;
 873         u64                     last_semaphore_wait_addr;
 874         /* for CIK queues */
 875         u32 me;
 876         u32 pipe;
 877         u32 queue;
 878         struct radeon_bo        *mqd_obj;
 879         u32 doorbell_index;
 880         unsigned                wptr_offs;
 881 };
 882
 883 struct radeon_mec {
 884         struct radeon_bo        *hpd_eop_obj;
 885         u64                     hpd_eop_gpu_addr;
 886         u32 num_pipe;
 887         u32 num_mec;
 888         u32 num_queue;
 889 };
 890
 891 /*
 892  * VM
 893  */
 894
 895 /* maximum number of VMIDs */
 896 #define RADEON_NUM_VM   16
 897
 898 /* number of entries in page table */
 899 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
 900
 901 /* PTBs (Page Table Blocks) need to be aligned to 32K */
 902 #define RADEON_VM_PTB_ALIGN_SIZE   32768
 903 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
 904 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
 905
 906 #define R600_PTE_VALID          (1 << 0)
 907 #define R600_PTE_SYSTEM         (1 << 1)
 908 #define R600_PTE_SNOOPED        (1 << 2)
 909 #define R600_PTE_READABLE       (1 << 5)
 910 #define R600_PTE_WRITEABLE      (1 << 6)
 911
 912 /* PTE (Page Table Entry) fragment field for different page sizes */
 913 #define R600_PTE_FRAG_4KB       (0 << 7)
 914 #define R600_PTE_FRAG_64KB      (4 << 7)
 915 #define R600_PTE_FRAG_256KB     (6 << 7)
 916
 917 /* flags needed to be set so we can copy directly from the GART table */
 918 #define R600_PTE_GART_MASK      ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
 919                                   R600_PTE_SYSTEM | R600_PTE_VALID )
 920
 921 struct radeon_vm_pt {
 922         struct radeon_bo                *bo;
 923         uint64_t                        addr;
 924 };
 925
 926 struct radeon_vm_id {
 927         unsigned                id;
 928         uint64_t                pd_gpu_addr;
 929         /* last flushed PD/PT update */
 930         struct radeon_fence     *flushed_updates;
 931         /* last use of vmid */
 932         struct radeon_fence     *last_id_use;
 933 };
 934
 935 struct radeon_vm {
 936         struct mutex            mutex;
 937
 938         struct rb_root          va;
 939
 940         /* protecting invalidated and freed */
 941         spinlock_t              status_lock;
 942
 943         /* BOs moved, but not yet updated in the PT */
 944         struct list_head        invalidated;
 945
 946         /* BOs freed, but not yet updated in the PT */
 947         struct list_head        freed;
 948
 949         /* BOs cleared in the PT */
 950         struct list_head        cleared;
 951
 952         /* contains the page directory */
 953         struct radeon_bo        *page_directory;
 954         unsigned                max_pde_used;
 955
 956         /* array of page tables, one for each page directory entry */
 957         struct radeon_vm_pt     *page_tables;
 958
 959         struct radeon_bo_va     *ib_bo_va;
 960
 961         /* for id and flush management per ring */
 962         struct radeon_vm_id     ids[RADEON_NUM_RINGS];
 963 };
 964
 965 struct radeon_vm_manager {
 966         struct radeon_fence             *active[RADEON_NUM_VM];
 967         uint32_t                        max_pfn;
 968         /* number of VMIDs */
 969         unsigned                        nvm;
 970         /* vram base address for page table entry  */
 971         u64                             vram_base_offset;
 972         /* is vm enabled? */
 973         bool                            enabled;
 974         /* for hw to save the PD addr on suspend/resume */
 975         uint32_t                        saved_table_addr[RADEON_NUM_VM];
 976 };
 977
 978 /*
 979  * file private structure
 980  */
 981 struct radeon_fpriv {
 982         struct radeon_vm                vm;
 983 };
 984
 985 /*
 986  * R6xx+ IH ring
 987  */
 988 struct r600_ih {
 989         struct radeon_bo        *ring_obj;
 990         volatile uint32_t       *ring;
 991         unsigned                rptr;
 992         unsigned                ring_size;
 993         uint64_t                gpu_addr;
 994         uint32_t                ptr_mask;
 995         atomic_t                lock;
 996         bool                    enabled;
 997 };
 998
 999 /*
1000  * RLC stuff
1001  */
1002 #include "clearstate_defs.h"
1003
1004 struct radeon_rlc {
1005         /* for power gating */
1006         struct radeon_bo        *save_restore_obj;
1007         uint64_t                save_restore_gpu_addr;
1008         volatile uint32_t       *sr_ptr;
1009         const u32               *reg_list;
1010         u32                     reg_list_size;
1011         /* for clear state */
1012         struct radeon_bo        *clear_state_obj;
1013         uint64_t                clear_state_gpu_addr;
1014         volatile uint32_t       *cs_ptr;
1015         const struct cs_section_def   *cs_data;
1016         u32                     clear_state_size;
1017         /* for cp tables */
1018         struct radeon_bo        *cp_table_obj;
1019         uint64_t                cp_table_gpu_addr;
1020         volatile uint32_t       *cp_table_ptr;
1021         u32                     cp_table_size;
1022 };
1023
1024 int radeon_ib_get(struct radeon_device *rdev, int ring,
1025                   struct radeon_ib *ib, struct radeon_vm *vm,
1026                   unsigned size);
1027 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1028 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1029                        struct radeon_ib *const_ib, bool hdp_flush);
1030 int radeon_ib_pool_init(struct radeon_device *rdev);
1031 void radeon_ib_pool_fini(struct radeon_device *rdev);
1032 int radeon_ib_ring_tests(struct radeon_device *rdev);
1033 /* Ring access between begin & end cannot sleep */
1034 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1035                                       struct radeon_ring *ring);
1036 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1037 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1038 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1039 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1040                         bool hdp_flush);
1041 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1042                                bool hdp_flush);
1043 void radeon_ring_undo(struct radeon_ring *ring);
1044 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1045 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1046 void radeon_ring_lockup_update(struct radeon_device *rdev,
1047                                struct radeon_ring *ring);
1048 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1049 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1050                             uint32_t **data);
1051 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1052                         unsigned size, uint32_t *data);
1053 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1054                      unsigned rptr_offs, u32 nop);
1055 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1056
1057
1058 /* r600 async dma */
1059 void r600_dma_stop(struct radeon_device *rdev);
1060 int r600_dma_resume(struct radeon_device *rdev);
1061 void r600_dma_fini(struct radeon_device *rdev);
1062
1063 void cayman_dma_stop(struct radeon_device *rdev);
1064 int cayman_dma_resume(struct radeon_device *rdev);
1065 void cayman_dma_fini(struct radeon_device *rdev);
1066
1067 /*
1068  * CS.
1069  */
1070 struct radeon_cs_chunk {
1071         uint32_t                length_dw;
1072         uint32_t                *kdata;
1073         void __user             *user_ptr;
1074 };
1075
1076 struct radeon_cs_parser {
1077         struct device           *dev;
1078         struct radeon_device    *rdev;
1079         struct drm_file         *filp;
1080         /* chunks */
1081         unsigned                nchunks;
1082         struct radeon_cs_chunk  *chunks;
1083         uint64_t                *chunks_array;
1084         /* IB */
1085         unsigned                idx;
1086         /* relocations */
1087         unsigned                nrelocs;
1088         struct radeon_bo_list   *relocs;
1089         struct radeon_bo_list   *vm_bos;
1090         struct list_head        validated;
1091         unsigned                dma_reloc_idx;
1092         /* indices of various chunks */
1093         struct radeon_cs_chunk  *chunk_ib;
1094         struct radeon_cs_chunk  *chunk_relocs;
1095         struct radeon_cs_chunk  *chunk_flags;
1096         struct radeon_cs_chunk  *chunk_const_ib;
1097         struct radeon_ib        ib;
1098         struct radeon_ib        const_ib;
1099         void                    *track;
1100         unsigned                family;
1101         int                     parser_error;
1102         u32                     cs_flags;
1103         u32                     ring;
1104         s32                     priority;
1105         struct ww_acquire_ctx   ticket;
1106 };
1107
1108 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1109 {
1110         struct radeon_cs_chunk *ibc = p->chunk_ib;
1111
1112         if (ibc->kdata)
1113                 return ibc->kdata[idx];
1114         return p->ib.ptr[idx];
1115 }
1116
1117
1118 struct radeon_cs_packet {
1119         unsigned        idx;
1120         unsigned        type;
1121         unsigned        reg;
1122         unsigned        opcode;
1123         int             count;
1124         unsigned        one_reg_wr;
1125 };
1126
1127 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1128                                       struct radeon_cs_packet *pkt,
1129                                       unsigned idx, unsigned reg);
1130 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1131                                       struct radeon_cs_packet *pkt);
1132
1133
1134 /*
1135  * AGP
1136  */
1137 int radeon_agp_init(struct radeon_device *rdev);
1138 void radeon_agp_resume(struct radeon_device *rdev);
1139 void radeon_agp_suspend(struct radeon_device *rdev);
1140 void radeon_agp_fini(struct radeon_device *rdev);
1141
1142
1143 /*
1144  * Writeback
1145  */
1146 struct radeon_wb {
1147         struct radeon_bo        *wb_obj;
1148         volatile uint32_t       *wb;
1149         uint64_t                gpu_addr;
1150         bool                    enabled;
1151         bool                    use_event;
1152 };
1153
1154 #define RADEON_WB_SCRATCH_OFFSET 0
1155 #define RADEON_WB_RING0_NEXT_RPTR 256
1156 #define RADEON_WB_CP_RPTR_OFFSET 1024
1157 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1158 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1159 #define R600_WB_DMA_RPTR_OFFSET   1792
1160 #define R600_WB_IH_WPTR_OFFSET   2048
1161 #define CAYMAN_WB_DMA1_RPTR_OFFSET   2304
1162 #define R600_WB_EVENT_OFFSET     3072
1163 #define CIK_WB_CP1_WPTR_OFFSET     3328
1164 #define CIK_WB_CP2_WPTR_OFFSET     3584
1165 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1166 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1167
1168 /**
1169  * struct radeon_pm - power management datas
1170  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
1171  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1172  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
1173  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
1174  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
1175  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
1176  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1177  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
1178  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
1179  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
1180  * @needed_bandwidth:   current bandwidth needs
1181  *
1182  * It keeps track of various data needed to take powermanagement decision.
1183  * Bandwidth need is used to determine minimun clock of the GPU and memory.
1184  * Equation between gpu/memory clock and available bandwidth is hw dependent
1185  * (type of memory, bus size, efficiency, ...)
1186  */
1187
1188 enum radeon_pm_method {
1189         PM_METHOD_PROFILE,
1190         PM_METHOD_DYNPM,
1191         PM_METHOD_DPM,
1192 };
1193
1194 enum radeon_dynpm_state {
1195         DYNPM_STATE_DISABLED,
1196         DYNPM_STATE_MINIMUM,
1197         DYNPM_STATE_PAUSED,
1198         DYNPM_STATE_ACTIVE,
1199         DYNPM_STATE_SUSPENDED,
1200 };
1201 enum radeon_dynpm_action {
1202         DYNPM_ACTION_NONE,
1203         DYNPM_ACTION_MINIMUM,
1204         DYNPM_ACTION_DOWNCLOCK,
1205         DYNPM_ACTION_UPCLOCK,
1206         DYNPM_ACTION_DEFAULT
1207 };
1208
1209 enum radeon_voltage_type {
1210         VOLTAGE_NONE = 0,
1211         VOLTAGE_GPIO,
1212         VOLTAGE_VDDC,
1213         VOLTAGE_SW
1214 };
1215
1216 enum radeon_pm_state_type {
1217         /* not used for dpm */
1218         POWER_STATE_TYPE_DEFAULT,
1219         POWER_STATE_TYPE_POWERSAVE,
1220         /* user selectable states */
1221         POWER_STATE_TYPE_BATTERY,
1222         POWER_STATE_TYPE_BALANCED,
1223         POWER_STATE_TYPE_PERFORMANCE,
1224         /* internal states */
1225         POWER_STATE_TYPE_INTERNAL_UVD,
1226         POWER_STATE_TYPE_INTERNAL_UVD_SD,
1227         POWER_STATE_TYPE_INTERNAL_UVD_HD,
1228         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1229         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1230         POWER_STATE_TYPE_INTERNAL_BOOT,
1231         POWER_STATE_TYPE_INTERNAL_THERMAL,
1232         POWER_STATE_TYPE_INTERNAL_ACPI,
1233         POWER_STATE_TYPE_INTERNAL_ULV,
1234         POWER_STATE_TYPE_INTERNAL_3DPERF,
1235 };
1236
1237 enum radeon_pm_profile_type {
1238         PM_PROFILE_DEFAULT,
1239         PM_PROFILE_AUTO,
1240         PM_PROFILE_LOW,
1241         PM_PROFILE_MID,
1242         PM_PROFILE_HIGH,
1243 };
1244
1245 #define PM_PROFILE_DEFAULT_IDX 0
1246 #define PM_PROFILE_LOW_SH_IDX  1
1247 #define PM_PROFILE_MID_SH_IDX  2
1248 #define PM_PROFILE_HIGH_SH_IDX 3
1249 #define PM_PROFILE_LOW_MH_IDX  4
1250 #define PM_PROFILE_MID_MH_IDX  5
1251 #define PM_PROFILE_HIGH_MH_IDX 6
1252 #define PM_PROFILE_MAX         7
1253
1254 struct radeon_pm_profile {
1255         int dpms_off_ps_idx;
1256         int dpms_on_ps_idx;
1257         int dpms_off_cm_idx;
1258         int dpms_on_cm_idx;
1259 };
1260
1261 enum radeon_int_thermal_type {
1262         THERMAL_TYPE_NONE,
1263         THERMAL_TYPE_EXTERNAL,
1264         THERMAL_TYPE_EXTERNAL_GPIO,
1265         THERMAL_TYPE_RV6XX,
1266         THERMAL_TYPE_RV770,
1267         THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1268         THERMAL_TYPE_EVERGREEN,
1269         THERMAL_TYPE_SUMO,
1270         THERMAL_TYPE_NI,
1271         THERMAL_TYPE_SI,
1272         THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1273         THERMAL_TYPE_CI,
1274         THERMAL_TYPE_KV,
1275 };
1276
1277 struct radeon_voltage {
1278         enum radeon_voltage_type type;
1279         /* gpio voltage */
1280         struct radeon_gpio_rec gpio;
1281         u32 delay; /* delay in usec from voltage drop to sclk change */
1282         bool active_high; /* voltage drop is active when bit is high */
1283         /* VDDC voltage */
1284         u8 vddc_id; /* index into vddc voltage table */
1285         u8 vddci_id; /* index into vddci voltage table */
1286         bool vddci_enabled;
1287         /* r6xx+ sw */
1288         u16 voltage;
1289         /* evergreen+ vddci */
1290         u16 vddci;
1291 };
1292
1293 /* clock mode flags */
1294 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
1295
1296 struct radeon_pm_clock_info {
1297         /* memory clock */
1298         u32 mclk;
1299         /* engine clock */
1300         u32 sclk;
1301         /* voltage info */
1302         struct radeon_voltage voltage;
1303         /* standardized clock flags */
1304         u32 flags;
1305 };
1306
1307 /* state flags */
1308 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1309
1310 struct radeon_power_state {
1311         enum radeon_pm_state_type type;
1312         struct radeon_pm_clock_info *clock_info;
1313         /* number of valid clock modes in this power state */
1314         int num_clock_modes;
1315         struct radeon_pm_clock_info *default_clock_mode;
1316         /* standardized state flags */
1317         u32 flags;
1318         u32 misc; /* vbios specific flags */
1319         u32 misc2; /* vbios specific flags */
1320         int pcie_lanes; /* pcie lanes */
1321 };
1322
1323 /*
1324  * Some modes are overclocked by very low value, accept them
1325  */
1326 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1327
1328 enum radeon_dpm_auto_throttle_src {
1329         RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1330         RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1331 };
1332
1333 enum radeon_dpm_event_src {
1334         RADEON_DPM_EVENT_SRC_ANALOG = 0,
1335         RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1336         RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1337         RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1338         RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1339 };
1340
1341 #define RADEON_MAX_VCE_LEVELS 6
1342
1343 enum radeon_vce_level {
1344         RADEON_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
1345         RADEON_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
1346         RADEON_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
1347         RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1348         RADEON_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
1349         RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1350 };
1351
1352 struct radeon_ps {
1353         u32 caps; /* vbios flags */
1354         u32 class; /* vbios flags */
1355         u32 class2; /* vbios flags */
1356         /* UVD clocks */
1357         u32 vclk;
1358         u32 dclk;
1359         /* VCE clocks */
1360         u32 evclk;
1361         u32 ecclk;
1362         bool vce_active;
1363         enum radeon_vce_level vce_level;
1364         /* asic priv */
1365         void *ps_priv;
1366 };
1367
1368 struct radeon_dpm_thermal {
1369         /* thermal interrupt work */
1370         struct work_struct work;
1371         /* low temperature threshold */
1372         int                min_temp;
1373         /* high temperature threshold */
1374         int                max_temp;
1375         /* was interrupt low to high or high to low */
1376         bool               high_to_low;
1377 };
1378
1379 enum radeon_clk_action
1380 {
1381         RADEON_SCLK_UP = 1,
1382         RADEON_SCLK_DOWN
1383 };
1384
1385 struct radeon_blacklist_clocks
1386 {
1387         u32 sclk;
1388         u32 mclk;
1389         enum radeon_clk_action action;
1390 };
1391
1392 struct radeon_clock_and_voltage_limits {
1393         u32 sclk;
1394         u32 mclk;
1395         u16 vddc;
1396         u16 vddci;
1397 };
1398
1399 struct radeon_clock_array {
1400         u32 count;
1401         u32 *values;
1402 };
1403
1404 struct radeon_clock_voltage_dependency_entry {
1405         u32 clk;
1406         u16 v;
1407 };
1408
1409 struct radeon_clock_voltage_dependency_table {
1410         u32 count;
1411         struct radeon_clock_voltage_dependency_entry *entries;
1412 };
1413
1414 union radeon_cac_leakage_entry {
1415         struct {
1416                 u16 vddc;
1417                 u32 leakage;
1418         };
1419         struct {
1420                 u16 vddc1;
1421                 u16 vddc2;
1422                 u16 vddc3;
1423         };
1424 };
1425
1426 struct radeon_cac_leakage_table {
1427         u32 count;
1428         union radeon_cac_leakage_entry *entries;
1429 };
1430
1431 struct radeon_phase_shedding_limits_entry {
1432         u16 voltage;
1433         u32 sclk;
1434         u32 mclk;
1435 };
1436
1437 struct radeon_phase_shedding_limits_table {
1438         u32 count;
1439         struct radeon_phase_shedding_limits_entry *entries;
1440 };
1441
1442 struct radeon_uvd_clock_voltage_dependency_entry {
1443         u32 vclk;
1444         u32 dclk;
1445         u16 v;
1446 };
1447
1448 struct radeon_uvd_clock_voltage_dependency_table {
1449         u8 count;
1450         struct radeon_uvd_clock_voltage_dependency_entry *entries;
1451 };
1452
1453 struct radeon_vce_clock_voltage_dependency_entry {
1454         u32 ecclk;
1455         u32 evclk;
1456         u16 v;
1457 };
1458
1459 struct radeon_vce_clock_voltage_dependency_table {
1460         u8 count;
1461         struct radeon_vce_clock_voltage_dependency_entry *entries;
1462 };
1463
1464 struct radeon_ppm_table {
1465         u8 ppm_design;
1466         u16 cpu_core_number;
1467         u32 platform_tdp;
1468         u32 small_ac_platform_tdp;
1469         u32 platform_tdc;
1470         u32 small_ac_platform_tdc;
1471         u32 apu_tdp;
1472         u32 dgpu_tdp;
1473         u32 dgpu_ulv_power;
1474         u32 tj_max;
1475 };
1476
1477 struct radeon_cac_tdp_table {
1478         u16 tdp;
1479         u16 configurable_tdp;
1480         u16 tdc;
1481         u16 battery_power_limit;
1482         u16 small_power_limit;
1483         u16 low_cac_leakage;
1484         u16 high_cac_leakage;
1485         u16 maximum_power_delivery_limit;
1486 };
1487
1488 struct radeon_dpm_dynamic_state {
1489         struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1490         struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1491         struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1492         struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1493         struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1494         struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1495         struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1496         struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1497         struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1498         struct radeon_clock_array valid_sclk_values;
1499         struct radeon_clock_array valid_mclk_values;
1500         struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1501         struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1502         u32 mclk_sclk_ratio;
1503         u32 sclk_mclk_delta;
1504         u16 vddc_vddci_delta;
1505         u16 min_vddc_for_pcie_gen2;
1506         struct radeon_cac_leakage_table cac_leakage_table;
1507         struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1508         struct radeon_ppm_table *ppm_table;
1509         struct radeon_cac_tdp_table *cac_tdp_table;
1510 };
1511
1512 struct radeon_dpm_fan {
1513         u16 t_min;
1514         u16 t_med;
1515         u16 t_high;
1516         u16 pwm_min;
1517         u16 pwm_med;
1518         u16 pwm_high;
1519         u8 t_hyst;
1520         u32 cycle_delay;
1521         u16 t_max;
1522         u8 control_mode;
1523         u16 default_max_fan_pwm;
1524         u16 default_fan_output_sensitivity;
1525         u16 fan_output_sensitivity;
1526         bool ucode_fan_control;
1527 };
1528
1529 enum radeon_pcie_gen {
1530         RADEON_PCIE_GEN1 = 0,
1531         RADEON_PCIE_GEN2 = 1,
1532         RADEON_PCIE_GEN3 = 2,
1533         RADEON_PCIE_GEN_INVALID = 0xffff
1534 };
1535
1536 enum radeon_dpm_forced_level {
1537         RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1538         RADEON_DPM_FORCED_LEVEL_LOW = 1,
1539         RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1540 };
1541
1542 struct radeon_vce_state {
1543         /* vce clocks */
1544         u32 evclk;
1545         u32 ecclk;
1546         /* gpu clocks */
1547         u32 sclk;
1548         u32 mclk;
1549         u8 clk_idx;
1550         u8 pstate;
1551 };
1552
1553 struct radeon_dpm {
1554         struct radeon_ps        *ps;
1555         /* number of valid power states */
1556         int                     num_ps;
1557         /* current power state that is active */
1558         struct radeon_ps        *current_ps;
1559         /* requested power state */
1560         struct radeon_ps        *requested_ps;
1561         /* boot up power state */
1562         struct radeon_ps        *boot_ps;
1563         /* default uvd power state */
1564         struct radeon_ps        *uvd_ps;
1565         /* vce requirements */
1566         struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1567         enum radeon_vce_level vce_level;
1568         enum radeon_pm_state_type state;
1569         enum radeon_pm_state_type user_state;
1570         u32                     platform_caps;
1571         u32                     voltage_response_time;
1572         u32                     backbias_response_time;
1573         void                    *priv;
1574         u32                     new_active_crtcs;
1575         int                     new_active_crtc_count;
1576         u32                     current_active_crtcs;
1577         int                     current_active_crtc_count;
1578         bool single_display;
1579         struct radeon_dpm_dynamic_state dyn_state;
1580         struct radeon_dpm_fan fan;
1581         u32 tdp_limit;
1582         u32 near_tdp_limit;
1583         u32 near_tdp_limit_adjusted;
1584         u32 sq_ramping_threshold;
1585         u32 cac_leakage;
1586         u16 tdp_od_limit;
1587         u32 tdp_adjustment;
1588         u16 load_line_slope;
1589         bool power_control;
1590         bool ac_power;
1591         /* special states active */
1592         bool                    thermal_active;
1593         bool                    uvd_active;
1594         bool                    vce_active;
1595         /* thermal handling */
1596         struct radeon_dpm_thermal thermal;
1597         /* forced levels */
1598         enum radeon_dpm_forced_level forced_level;
1599         /* track UVD streams */
1600         unsigned sd;
1601         unsigned hd;
1602 };
1603
1604 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1605 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1606
1607 struct radeon_pm {
1608         struct mutex            mutex;
1609         /* write locked while reprogramming mclk */
1610         struct rw_semaphore     mclk_lock;
1611         u32                     active_crtcs;
1612         int                     active_crtc_count;
1613         int                     req_vblank;
1614         bool                    vblank_sync;
1615         fixed20_12              max_bandwidth;
1616         fixed20_12              igp_sideport_mclk;
1617         fixed20_12              igp_system_mclk;
1618         fixed20_12              igp_ht_link_clk;
1619         fixed20_12              igp_ht_link_width;
1620         fixed20_12              k8_bandwidth;
1621         fixed20_12              sideport_bandwidth;
1622         fixed20_12              ht_bandwidth;
1623         fixed20_12              core_bandwidth;
1624         fixed20_12              sclk;
1625         fixed20_12              mclk;
1626         fixed20_12              needed_bandwidth;
1627         struct radeon_power_state *power_state;
1628         /* number of valid power states */
1629         int                     num_power_states;
1630         int                     current_power_state_index;
1631         int                     current_clock_mode_index;
1632         int                     requested_power_state_index;
1633         int                     requested_clock_mode_index;
1634         int                     default_power_state_index;
1635         u32                     current_sclk;
1636         u32                     current_mclk;
1637         u16                     current_vddc;
1638         u16                     current_vddci;
1639         u32                     default_sclk;
1640         u32                     default_mclk;
1641         u16                     default_vddc;
1642         u16                     default_vddci;
1643         struct radeon_i2c_chan *i2c_bus;
1644         /* selected pm method */
1645         enum radeon_pm_method     pm_method;
1646         /* dynpm power management */
1647         struct delayed_work     dynpm_idle_work;
1648         enum radeon_dynpm_state dynpm_state;
1649         enum radeon_dynpm_action        dynpm_planned_action;
1650         unsigned long           dynpm_action_timeout;
1651         bool                    dynpm_can_upclock;
1652         bool                    dynpm_can_downclock;
1653         /* profile-based power management */
1654         enum radeon_pm_profile_type profile;
1655         int                     profile_index;
1656         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1657         /* internal thermal controller on rv6xx+ */
1658         enum radeon_int_thermal_type int_thermal_type;
1659         struct device           *int_hwmon_dev;
1660         /* fan control parameters */
1661         bool                    no_fan;
1662         u8                      fan_pulses_per_revolution;
1663         u8                      fan_min_rpm;
1664         u8                      fan_max_rpm;
1665         /* dpm */
1666         bool                    dpm_enabled;
1667         bool                    sysfs_initialized;
1668         struct radeon_dpm       dpm;
1669 };
1670
1671 int radeon_pm_get_type_index(struct radeon_device *rdev,
1672                              enum radeon_pm_state_type ps_type,
1673                              int instance);
1674 /*
1675  * UVD
1676  */
1677 #define RADEON_DEFAULT_UVD_HANDLES      10
1678 #define RADEON_MAX_UVD_HANDLES          30
1679 #define RADEON_UVD_STACK_SIZE           (200*1024)
1680 #define RADEON_UVD_HEAP_SIZE            (256*1024)
1681 #define RADEON_UVD_SESSION_SIZE         (50*1024)
1682
1683 struct radeon_uvd {
1684         bool                    fw_header_present;
1685         struct radeon_bo        *vcpu_bo;
1686         void                    *cpu_addr;
1687         uint64_t                gpu_addr;
1688         unsigned                max_handles;
1689         atomic_t                handles[RADEON_MAX_UVD_HANDLES];
1690         struct drm_file         *filp[RADEON_MAX_UVD_HANDLES];
1691         unsigned                img_size[RADEON_MAX_UVD_HANDLES];
1692         struct delayed_work     idle_work;
1693 };
1694
1695 int radeon_uvd_init(struct radeon_device *rdev);
1696 void radeon_uvd_fini(struct radeon_device *rdev);
1697 int radeon_uvd_suspend(struct radeon_device *rdev);
1698 int radeon_uvd_resume(struct radeon_device *rdev);
1699 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1700                               uint32_t handle, struct radeon_fence **fence);
1701 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1702                                uint32_t handle, struct radeon_fence **fence);
1703 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1704                                        uint32_t allowed_domains);
1705 void radeon_uvd_free_handles(struct radeon_device *rdev,
1706                              struct drm_file *filp);
1707 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1708 void radeon_uvd_note_usage(struct radeon_device *rdev);
1709 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1710                                   unsigned vclk, unsigned dclk,
1711                                   unsigned vco_min, unsigned vco_max,
1712                                   unsigned fb_factor, unsigned fb_mask,
1713                                   unsigned pd_min, unsigned pd_max,
1714                                   unsigned pd_even,
1715                                   unsigned *optimal_fb_div,
1716                                   unsigned *optimal_vclk_div,
1717                                   unsigned *optimal_dclk_div);
1718 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1719                                 unsigned cg_upll_func_cntl);
1720
1721 /*
1722  * VCE
1723  */
1724 #define RADEON_MAX_VCE_HANDLES  16
1725
1726 struct radeon_vce {
1727         struct radeon_bo        *vcpu_bo;
1728         uint64_t                gpu_addr;
1729         unsigned                fw_version;
1730         unsigned                fb_version;
1731         atomic_t                handles[RADEON_MAX_VCE_HANDLES];
1732         struct drm_file         *filp[RADEON_MAX_VCE_HANDLES];
1733         unsigned                img_size[RADEON_MAX_VCE_HANDLES];
1734         struct delayed_work     idle_work;
1735         uint32_t                keyselect;
1736 };
1737
1738 int radeon_vce_init(struct radeon_device *rdev);
1739 void radeon_vce_fini(struct radeon_device *rdev);
1740 int radeon_vce_suspend(struct radeon_device *rdev);
1741 int radeon_vce_resume(struct radeon_device *rdev);
1742 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1743                               uint32_t handle, struct radeon_fence **fence);
1744 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1745                                uint32_t handle, struct radeon_fence **fence);
1746 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1747 void radeon_vce_note_usage(struct radeon_device *rdev);
1748 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1749 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1750 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1751                                struct radeon_ring *ring,
1752                                struct radeon_semaphore *semaphore,
1753                                bool emit_wait);
1754 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1755 void radeon_vce_fence_emit(struct radeon_device *rdev,
1756                            struct radeon_fence *fence);
1757 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1758 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1759
1760 struct r600_audio_pin {
1761         int                     channels;
1762         int                     rate;
1763         int                     bits_per_sample;
1764         u8                      status_bits;
1765         u8                      category_code;
1766         u32                     offset;
1767         bool                    connected;
1768         u32                     id;
1769 };
1770
1771 struct r600_audio {
1772         bool enabled;
1773         struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1774         int num_pins;
1775         struct radeon_audio_funcs *hdmi_funcs;
1776         struct radeon_audio_funcs *dp_funcs;
1777         struct radeon_audio_basic_funcs *funcs;
1778 };
1779
1780 /*
1781  * Benchmarking
1782  */
1783 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1784
1785
1786 /*
1787  * Testing
1788  */
1789 void radeon_test_moves(struct radeon_device *rdev);
1790 void radeon_test_ring_sync(struct radeon_device *rdev,
1791                            struct radeon_ring *cpA,
1792                            struct radeon_ring *cpB);
1793 void radeon_test_syncing(struct radeon_device *rdev);
1794
1795 /*
1796  * MMU Notifier
1797  */
1798 #if defined(CONFIG_MMU_NOTIFIER)
1799 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1800 void radeon_mn_unregister(struct radeon_bo *bo);
1801 #else
1802 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1803 {
1804         return -ENODEV;
1805 }
1806 static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1807 #endif
1808
1809 /*
1810  * Debugfs
1811  */
1812 struct radeon_debugfs {
1813         struct drm_info_list    *files;
1814         unsigned                num_files;
1815 };
1816
1817 int radeon_debugfs_add_files(struct radeon_device *rdev,
1818                              struct drm_info_list *files,
1819                              unsigned nfiles);
1820 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1821
1822 /*
1823  * ASIC ring specific functions.
1824  */
1825 struct radeon_asic_ring {
1826         /* ring read/write ptr handling */
1827         u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1828         u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1829         void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1830
1831         /* validating and patching of IBs */
1832         int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1833         int (*cs_parse)(struct radeon_cs_parser *p);
1834
1835         /* command emmit functions */
1836         void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1837         void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1838         void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1839         bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1840                                struct radeon_semaphore *semaphore, bool emit_wait);
1841         void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1842                          unsigned vm_id, uint64_t pd_addr);
1843
1844         /* testing functions */
1845         int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1846         int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1847         bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1848
1849         /* deprecated */
1850         void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1851 };
1852
1853 /*
1854  * ASIC specific functions.
1855  */
1856 struct radeon_asic {
1857         int (*init)(struct radeon_device *rdev);
1858         void (*fini)(struct radeon_device *rdev);
1859         int (*resume)(struct radeon_device *rdev);
1860         int (*suspend)(struct radeon_device *rdev);
1861         void (*vga_set_state)(struct radeon_device *rdev, bool state);
1862         int (*asic_reset)(struct radeon_device *rdev, bool hard);
1863         /* Flush the HDP cache via MMIO */
1864         void (*mmio_hdp_flush)(struct radeon_device *rdev);
1865         /* check if 3D engine is idle */
1866         bool (*gui_idle)(struct radeon_device *rdev);
1867         /* wait for mc_idle */
1868         int (*mc_wait_for_idle)(struct radeon_device *rdev);
1869         /* get the reference clock */
1870         u32 (*get_xclk)(struct radeon_device *rdev);
1871         /* get the gpu clock counter */
1872         uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1873         /* get register for info ioctl */
1874         int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1875         /* gart */
1876         struct {
1877                 void (*tlb_flush)(struct radeon_device *rdev);
1878                 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1879                 void (*set_page)(struct radeon_device *rdev, unsigned i,
1880                                  uint64_t entry);
1881         } gart;
1882         struct {
1883                 int (*init)(struct radeon_device *rdev);
1884                 void (*fini)(struct radeon_device *rdev);
1885                 void (*copy_pages)(struct radeon_device *rdev,
1886                                    struct radeon_ib *ib,
1887                                    uint64_t pe, uint64_t src,
1888                                    unsigned count);
1889                 void (*write_pages)(struct radeon_device *rdev,
1890                                     struct radeon_ib *ib,
1891                                     uint64_t pe,
1892                                     uint64_t addr, unsigned count,
1893                                     uint32_t incr, uint32_t flags);
1894                 void (*set_pages)(struct radeon_device *rdev,
1895                                   struct radeon_ib *ib,
1896                                   uint64_t pe,
1897                                   uint64_t addr, unsigned count,
1898                                   uint32_t incr, uint32_t flags);
1899                 void (*pad_ib)(struct radeon_ib *ib);
1900         } vm;
1901         /* ring specific callbacks */
1902         const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1903         /* irqs */
1904         struct {
1905                 int (*set)(struct radeon_device *rdev);
1906                 int (*process)(struct radeon_device *rdev);
1907         } irq;
1908         /* displays */
1909         struct {
1910                 /* display watermarks */
1911                 void (*bandwidth_update)(struct radeon_device *rdev);
1912                 /* get frame count */
1913                 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1914                 /* wait for vblank */
1915                 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1916                 /* set backlight level */
1917                 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1918                 /* get backlight level */
1919                 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1920                 /* audio callbacks */
1921                 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1922                 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1923         } display;
1924         /* copy functions for bo handling */
1925         struct {
1926                 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1927                                              uint64_t src_offset,
1928                                              uint64_t dst_offset,
1929                                              unsigned num_gpu_pages,
1930                                              struct reservation_object *resv);
1931                 u32 blit_ring_index;
1932                 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1933                                             uint64_t src_offset,
1934                                             uint64_t dst_offset,
1935                                             unsigned num_gpu_pages,
1936                                             struct reservation_object *resv);
1937                 u32 dma_ring_index;
1938                 /* method used for bo copy */
1939                 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1940                                              uint64_t src_offset,
1941                                              uint64_t dst_offset,
1942                                              unsigned num_gpu_pages,
1943                                              struct reservation_object *resv);
1944                 /* ring used for bo copies */
1945                 u32 copy_ring_index;
1946         } copy;
1947         /* surfaces */
1948         struct {
1949                 int (*set_reg)(struct radeon_device *rdev, int reg,
1950                                        uint32_t tiling_flags, uint32_t pitch,
1951                                        uint32_t offset, uint32_t obj_size);
1952                 void (*clear_reg)(struct radeon_device *rdev, int reg);
1953         } surface;
1954         /* hotplug detect */
1955         struct {
1956                 void (*init)(struct radeon_device *rdev);
1957                 void (*fini)(struct radeon_device *rdev);
1958                 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1959                 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1960         } hpd;
1961         /* static power management */
1962         struct {
1963                 void (*misc)(struct radeon_device *rdev);
1964                 void (*prepare)(struct radeon_device *rdev);
1965                 void (*finish)(struct radeon_device *rdev);
1966                 void (*init_profile)(struct radeon_device *rdev);
1967                 void (*get_dynpm_state)(struct radeon_device *rdev);
1968                 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1969                 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1970                 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1971                 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1972                 int (*get_pcie_lanes)(struct radeon_device *rdev);
1973                 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1974                 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1975                 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1976                 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1977                 int (*get_temperature)(struct radeon_device *rdev);
1978         } pm;
1979         /* dynamic power management */
1980         struct {
1981                 int (*init)(struct radeon_device *rdev);
1982                 void (*setup_asic)(struct radeon_device *rdev);
1983                 int (*enable)(struct radeon_device *rdev);
1984                 int (*late_enable)(struct radeon_device *rdev);
1985                 void (*disable)(struct radeon_device *rdev);
1986                 int (*pre_set_power_state)(struct radeon_device *rdev);
1987                 int (*set_power_state)(struct radeon_device *rdev);
1988                 void (*post_set_power_state)(struct radeon_device *rdev);
1989                 void (*display_configuration_changed)(struct radeon_device *rdev);
1990                 void (*fini)(struct radeon_device *rdev);
1991                 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1992                 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1993                 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1994                 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1995                 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1996                 bool (*vblank_too_short)(struct radeon_device *rdev);
1997                 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1998                 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1999                 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
2000                 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
2001                 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
2002                 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
2003                 u32 (*get_current_sclk)(struct radeon_device *rdev);
2004                 u32 (*get_current_mclk)(struct radeon_device *rdev);
2005         } dpm;
2006         /* pageflipping */
2007         struct {
2008                 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
2009                 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
2010         } pflip;
2011 };
2012
2013 /*
2014  * Asic structures
2015  */
2016 struct r100_asic {
2017         const unsigned          *reg_safe_bm;
2018         unsigned                reg_safe_bm_size;
2019         u32                     hdp_cntl;
2020 };
2021
2022 struct r300_asic {
2023         const unsigned          *reg_safe_bm;
2024         unsigned                reg_safe_bm_size;
2025         u32                     resync_scratch;
2026         u32                     hdp_cntl;
2027 };
2028
2029 struct r600_asic {
2030         unsigned                max_pipes;
2031         unsigned                max_tile_pipes;
2032         unsigned                max_simds;
2033         unsigned                max_backends;
2034         unsigned                max_gprs;
2035         unsigned                max_threads;
2036         unsigned                max_stack_entries;
2037         unsigned                max_hw_contexts;
2038         unsigned                max_gs_threads;
2039         unsigned                sx_max_export_size;
2040         unsigned                sx_max_export_pos_size;
2041         unsigned                sx_max_export_smx_size;
2042         unsigned                sq_num_cf_insts;
2043         unsigned                tiling_nbanks;
2044         unsigned                tiling_npipes;
2045         unsigned                tiling_group_size;
2046         unsigned                tile_config;
2047         unsigned                backend_map;
2048         unsigned                active_simds;
2049 };
2050
2051 struct rv770_asic {
2052         unsigned                max_pipes;
2053         unsigned                max_tile_pipes;
2054         unsigned                max_simds;
2055         unsigned                max_backends;
2056         unsigned                max_gprs;
2057         unsigned                max_threads;
2058         unsigned                max_stack_entries;
2059         unsigned                max_hw_contexts;
2060         unsigned                max_gs_threads;
2061         unsigned                sx_max_export_size;
2062         unsigned                sx_max_export_pos_size;
2063         unsigned                sx_max_export_smx_size;
2064         unsigned                sq_num_cf_insts;
2065         unsigned                sx_num_of_sets;
2066         unsigned                sc_prim_fifo_size;
2067         unsigned                sc_hiz_tile_fifo_size;
2068         unsigned                sc_earlyz_tile_fifo_fize;
2069         unsigned                tiling_nbanks;
2070         unsigned                tiling_npipes;
2071         unsigned                tiling_group_size;
2072         unsigned                tile_config;
2073         unsigned                backend_map;
2074         unsigned                active_simds;
2075 };
2076
2077 struct evergreen_asic {
2078         unsigned num_ses;
2079         unsigned max_pipes;
2080         unsigned max_tile_pipes;
2081         unsigned max_simds;
2082         unsigned max_backends;
2083         unsigned max_gprs;
2084         unsigned max_threads;
2085         unsigned max_stack_entries;
2086         unsigned max_hw_contexts;
2087         unsigned max_gs_threads;
2088         unsigned sx_max_export_size;
2089         unsigned sx_max_export_pos_size;
2090         unsigned sx_max_export_smx_size;
2091         unsigned sq_num_cf_insts;
2092         unsigned sx_num_of_sets;
2093         unsigned sc_prim_fifo_size;
2094         unsigned sc_hiz_tile_fifo_size;
2095         unsigned sc_earlyz_tile_fifo_size;
2096         unsigned tiling_nbanks;
2097         unsigned tiling_npipes;
2098         unsigned tiling_group_size;
2099         unsigned tile_config;
2100         unsigned backend_map;
2101         unsigned active_simds;
2102 };
2103
2104 struct cayman_asic {
2105         unsigned max_shader_engines;
2106         unsigned max_pipes_per_simd;
2107         unsigned max_tile_pipes;
2108         unsigned max_simds_per_se;
2109         unsigned max_backends_per_se;
2110         unsigned max_texture_channel_caches;
2111         unsigned max_gprs;
2112         unsigned max_threads;
2113         unsigned max_gs_threads;
2114         unsigned max_stack_entries;
2115         unsigned sx_num_of_sets;
2116         unsigned sx_max_export_size;
2117         unsigned sx_max_export_pos_size;
2118         unsigned sx_max_export_smx_size;
2119         unsigned max_hw_contexts;
2120         unsigned sq_num_cf_insts;
2121         unsigned sc_prim_fifo_size;
2122         unsigned sc_hiz_tile_fifo_size;
2123         unsigned sc_earlyz_tile_fifo_size;
2124
2125         unsigned num_shader_engines;
2126         unsigned num_shader_pipes_per_simd;
2127         unsigned num_tile_pipes;
2128         unsigned num_simds_per_se;
2129         unsigned num_backends_per_se;
2130         unsigned backend_disable_mask_per_asic;
2131         unsigned backend_map;
2132         unsigned num_texture_channel_caches;
2133         unsigned mem_max_burst_length_bytes;
2134         unsigned mem_row_size_in_kb;
2135         unsigned shader_engine_tile_size;
2136         unsigned num_gpus;
2137         unsigned multi_gpu_tile_size;
2138
2139         unsigned tile_config;
2140         unsigned active_simds;
2141 };
2142
2143 struct si_asic {
2144         unsigned max_shader_engines;
2145         unsigned max_tile_pipes;
2146         unsigned max_cu_per_sh;
2147         unsigned max_sh_per_se;
2148         unsigned max_backends_per_se;
2149         unsigned max_texture_channel_caches;
2150         unsigned max_gprs;
2151         unsigned max_gs_threads;
2152         unsigned max_hw_contexts;
2153         unsigned sc_prim_fifo_size_frontend;
2154         unsigned sc_prim_fifo_size_backend;
2155         unsigned sc_hiz_tile_fifo_size;
2156         unsigned sc_earlyz_tile_fifo_size;
2157
2158         unsigned num_tile_pipes;
2159         unsigned backend_enable_mask;
2160         unsigned backend_disable_mask_per_asic;
2161         unsigned backend_map;
2162         unsigned num_texture_channel_caches;
2163         unsigned mem_max_burst_length_bytes;
2164         unsigned mem_row_size_in_kb;
2165         unsigned shader_engine_tile_size;
2166         unsigned num_gpus;
2167         unsigned multi_gpu_tile_size;
2168
2169         unsigned tile_config;
2170         uint32_t tile_mode_array[32];
2171         uint32_t active_cus;
2172 };
2173
2174 struct cik_asic {
2175         unsigned max_shader_engines;
2176         unsigned max_tile_pipes;
2177         unsigned max_cu_per_sh;
2178         unsigned max_sh_per_se;
2179         unsigned max_backends_per_se;
2180         unsigned max_texture_channel_caches;
2181         unsigned max_gprs;
2182         unsigned max_gs_threads;
2183         unsigned max_hw_contexts;
2184         unsigned sc_prim_fifo_size_frontend;
2185         unsigned sc_prim_fifo_size_backend;
2186         unsigned sc_hiz_tile_fifo_size;
2187         unsigned sc_earlyz_tile_fifo_size;
2188
2189         unsigned num_tile_pipes;
2190         unsigned backend_enable_mask;
2191         unsigned backend_disable_mask_per_asic;
2192         unsigned backend_map;
2193         unsigned num_texture_channel_caches;
2194         unsigned mem_max_burst_length_bytes;
2195         unsigned mem_row_size_in_kb;
2196         unsigned shader_engine_tile_size;
2197         unsigned num_gpus;
2198         unsigned multi_gpu_tile_size;
2199
2200         unsigned tile_config;
2201         uint32_t tile_mode_array[32];
2202         uint32_t macrotile_mode_array[16];
2203         uint32_t active_cus;
2204 };
2205
2206 union radeon_asic_config {
2207         struct r300_asic        r300;
2208         struct r100_asic        r100;
2209         struct r600_asic        r600;
2210         struct rv770_asic       rv770;
2211         struct evergreen_asic   evergreen;
2212         struct cayman_asic      cayman;
2213         struct si_asic          si;
2214         struct cik_asic         cik;
2215 };
2216
2217 /*
2218  * asic initizalization from radeon_asic.c
2219  */
2220 void radeon_agp_disable(struct radeon_device *rdev);
2221 int radeon_asic_init(struct radeon_device *rdev);
2222
2223
2224 /*
2225  * IOCTL.
2226  */
2227 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2228                           struct drm_file *filp);
2229 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2230                             struct drm_file *filp);
2231 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2232                              struct drm_file *filp);
2233 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2234                          struct drm_file *file_priv);
2235 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2236                            struct drm_file *file_priv);
2237 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2238                             struct drm_file *file_priv);
2239 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2240                            struct drm_file *file_priv);
2241 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2242                                 struct drm_file *filp);
2243 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2244                           struct drm_file *filp);
2245 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2246                           struct drm_file *filp);
2247 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2248                               struct drm_file *filp);
2249 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2250                           struct drm_file *filp);
2251 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2252                         struct drm_file *filp);
2253 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2254 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2255                                 struct drm_file *filp);
2256 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2257                                 struct drm_file *filp);
2258
2259 /* VRAM scratch page for HDP bug, default vram page */
2260 struct r600_vram_scratch {
2261         struct radeon_bo                *robj;
2262         volatile uint32_t               *ptr;
2263         u64                             gpu_addr;
2264 };
2265
2266 /*
2267  * ACPI
2268  */
2269 struct radeon_atif_notification_cfg {
2270         bool enabled;
2271         int command_code;
2272 };
2273
2274 struct radeon_atif_notifications {
2275         bool display_switch;
2276         bool expansion_mode_change;
2277         bool thermal_state;
2278         bool forced_power_state;
2279         bool system_power_state;
2280         bool display_conf_change;
2281         bool px_gfx_switch;
2282         bool brightness_change;
2283         bool dgpu_display_event;
2284 };
2285
2286 struct radeon_atif_functions {
2287         bool system_params;
2288         bool sbios_requests;
2289         bool select_active_disp;
2290         bool lid_state;
2291         bool get_tv_standard;
2292         bool set_tv_standard;
2293         bool get_panel_expansion_mode;
2294         bool set_panel_expansion_mode;
2295         bool temperature_change;
2296         bool graphics_device_types;
2297 };
2298
2299 struct radeon_atif {
2300         struct radeon_atif_notifications notifications;
2301         struct radeon_atif_functions functions;
2302         struct radeon_atif_notification_cfg notification_cfg;
2303         struct radeon_encoder *encoder_for_bl;
2304 };
2305
2306 struct radeon_atcs_functions {
2307         bool get_ext_state;
2308         bool pcie_perf_req;
2309         bool pcie_dev_rdy;
2310         bool pcie_bus_width;
2311 };
2312
2313 struct radeon_atcs {
2314         struct radeon_atcs_functions functions;
2315 };
2316
2317 /*
2318  * Core structure, functions and helpers.
2319  */
2320 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2321 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2322
2323 struct radeon_device {
2324         struct device                   *dev;
2325         struct drm_device               *ddev;
2326         struct pci_dev                  *pdev;
2327         struct rw_semaphore             exclusive_lock;
2328         /* ASIC */
2329         union radeon_asic_config        config;
2330         enum radeon_family              family;
2331         unsigned long                   flags;
2332         int                             usec_timeout;
2333         enum radeon_pll_errata          pll_errata;
2334         int                             num_gb_pipes;
2335         int                             num_z_pipes;
2336         int                             disp_priority;
2337         /* BIOS */
2338         uint8_t                         *bios;
2339         bool                            is_atom_bios;
2340         uint16_t                        bios_header_start;
2341         struct radeon_bo                *stollen_vga_memory;
2342         /* Register mmio */
2343         resource_size_t                 rmmio_base;
2344         resource_size_t                 rmmio_size;
2345         /* protects concurrent MM_INDEX/DATA based register access */
2346         spinlock_t mmio_idx_lock;
2347         /* protects concurrent SMC based register access */
2348         spinlock_t smc_idx_lock;
2349         /* protects concurrent PLL register access */
2350         spinlock_t pll_idx_lock;
2351         /* protects concurrent MC register access */
2352         spinlock_t mc_idx_lock;
2353         /* protects concurrent PCIE register access */
2354         spinlock_t pcie_idx_lock;
2355         /* protects concurrent PCIE_PORT register access */
2356         spinlock_t pciep_idx_lock;
2357         /* protects concurrent PIF register access */
2358         spinlock_t pif_idx_lock;
2359         /* protects concurrent CG register access */
2360         spinlock_t cg_idx_lock;
2361         /* protects concurrent UVD register access */
2362         spinlock_t uvd_idx_lock;
2363         /* protects concurrent RCU register access */
2364         spinlock_t rcu_idx_lock;
2365         /* protects concurrent DIDT register access */
2366         spinlock_t didt_idx_lock;
2367         /* protects concurrent ENDPOINT (audio) register access */
2368         spinlock_t end_idx_lock;
2369         void __iomem                    *rmmio;
2370         radeon_rreg_t                   mc_rreg;
2371         radeon_wreg_t                   mc_wreg;
2372         radeon_rreg_t                   pll_rreg;
2373         radeon_wreg_t                   pll_wreg;
2374         uint32_t                        pcie_reg_mask;
2375         radeon_rreg_t                   pciep_rreg;
2376         radeon_wreg_t                   pciep_wreg;
2377         /* io port */
2378         void __iomem                    *rio_mem;
2379         resource_size_t                 rio_mem_size;
2380         struct radeon_clock             clock;
2381         struct radeon_mc                mc;
2382         struct radeon_gart              gart;
2383         struct radeon_mode_info         mode_info;
2384         struct radeon_scratch           scratch;
2385         struct radeon_doorbell          doorbell;
2386         struct radeon_mman              mman;
2387         struct radeon_fence_driver      fence_drv[RADEON_NUM_RINGS];
2388         wait_queue_head_t               fence_queue;
2389         u64                             fence_context;
2390         struct mutex                    ring_lock;
2391         struct radeon_ring              ring[RADEON_NUM_RINGS];
2392         bool                            ib_pool_ready;
2393         struct radeon_sa_manager        ring_tmp_bo;
2394         struct radeon_irq               irq;
2395         struct radeon_asic              *asic;
2396         struct radeon_gem               gem;
2397         struct radeon_pm                pm;
2398         struct radeon_uvd               uvd;
2399         struct radeon_vce               vce;
2400         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2401         struct radeon_wb                wb;
2402         struct radeon_dummy_page        dummy_page;
2403         bool                            shutdown;
2404         bool                            need_dma32;
2405         bool                            accel_working;
2406         bool                            fastfb_working; /* IGP feature*/
2407         bool                            needs_reset, in_reset;
2408         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2409         const struct firmware *me_fw;   /* all family ME firmware */
2410         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
2411         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
2412         const struct firmware *mc_fw;   /* NI MC firmware */
2413         const struct firmware *ce_fw;   /* SI CE firmware */
2414         const struct firmware *mec_fw;  /* CIK MEC firmware */
2415         const struct firmware *mec2_fw; /* KV MEC2 firmware */
2416         const struct firmware *sdma_fw; /* CIK SDMA firmware */
2417         const struct firmware *smc_fw;  /* SMC firmware */
2418         const struct firmware *uvd_fw;  /* UVD firmware */
2419         const struct firmware *vce_fw;  /* VCE firmware */
2420         bool new_fw;
2421         struct r600_vram_scratch vram_scratch;
2422         int msi_enabled; /* msi enabled */
2423         struct r600_ih ih; /* r6/700 interrupt ring */
2424         struct radeon_rlc rlc;
2425         struct radeon_mec mec;
2426         struct delayed_work hotplug_work;
2427         struct work_struct dp_work;
2428         struct work_struct audio_work;
2429         int num_crtc; /* number of crtcs */
2430         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2431         bool has_uvd;
2432         bool has_vce;
2433         struct r600_audio audio; /* audio stuff */
2434         struct notifier_block acpi_nb;
2435         /* only one userspace can use Hyperz features or CMASK at a time */
2436         struct drm_file *hyperz_filp;
2437         struct drm_file *cmask_filp;
2438         /* i2c buses */
2439         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2440         /* debugfs */
2441         struct radeon_debugfs   debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2442         unsigned                debugfs_count;
2443         /* virtual memory */
2444         struct radeon_vm_manager        vm_manager;
2445         struct mutex                    gpu_clock_mutex;
2446         /* memory stats */
2447         atomic64_t                      vram_usage;
2448         atomic64_t                      gtt_usage;
2449         atomic64_t                      num_bytes_moved;
2450         atomic_t                        gpu_reset_counter;
2451         /* ACPI interface */
2452         struct radeon_atif              atif;
2453         struct radeon_atcs              atcs;
2454         /* srbm instance registers */
2455         struct mutex                    srbm_mutex;
2456         /* GRBM index mutex. Protects concurrents access to GRBM index */
2457         struct mutex                    grbm_idx_mutex;
2458         /* clock, powergating flags */
2459         u32 cg_flags;
2460         u32 pg_flags;
2461
2462         struct dev_pm_domain vga_pm_domain;
2463         bool have_disp_power_ref;
2464         u32 px_quirk_flags;
2465
2466         /* tracking pinned memory */
2467         u64 vram_pin_size;
2468         u64 gart_pin_size;
2469
2470         /* amdkfd interface */
2471         struct kfd_dev          *kfd;
2472
2473         struct mutex    mn_lock;
2474         DECLARE_HASHTABLE(mn_hash, 7);
2475 };
2476
2477 bool radeon_is_px(struct drm_device *dev);
2478 int radeon_device_init(struct radeon_device *rdev,
2479                        struct drm_device *ddev,
2480                        struct pci_dev *pdev,
2481                        uint32_t flags);
2482 void radeon_device_fini(struct radeon_device *rdev);
2483 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2484
2485 #define RADEON_MIN_MMIO_SIZE 0x10000
2486
2487 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2488 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2489 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2490                                     bool always_indirect)
2491 {
2492         /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2493         if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2494                 return readl(((void __iomem *)rdev->rmmio) + reg);
2495         else
2496                 return r100_mm_rreg_slow(rdev, reg);
2497 }
2498 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2499                                 bool always_indirect)
2500 {
2501         if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2502                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2503         else
2504                 r100_mm_wreg_slow(rdev, reg, v);
2505 }
2506
2507 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2508 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2509
2510 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2511 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2512
2513 /*
2514  * Cast helper
2515  */
2516 extern const struct fence_ops radeon_fence_ops;
2517
2518 static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2519 {
2520         struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2521
2522         if (__f->base.ops == &radeon_fence_ops)
2523                 return __f;
2524
2525         return NULL;
2526 }
2527
2528 /*
2529  * Registers read & write functions.
2530  */
2531 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2532 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2533 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2534 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2535 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2536 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2537 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2538 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2539 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2540 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2541 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2542 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2543 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2544 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2545 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2546 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2547 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2548 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2549 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2550 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2551 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2552 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2553 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2554 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2555 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2556 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2557 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2558 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2559 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2560 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2561 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2562 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2563 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2564 #define WREG32_P(reg, val, mask)                                \
2565         do {                                                    \
2566                 uint32_t tmp_ = RREG32(reg);                    \
2567                 tmp_ &= (mask);                                 \
2568                 tmp_ |= ((val) & ~(mask));                      \
2569                 WREG32(reg, tmp_);                              \
2570         } while (0)
2571 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2572 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2573 #define WREG32_PLL_P(reg, val, mask)                            \
2574         do {                                                    \
2575                 uint32_t tmp_ = RREG32_PLL(reg);                \
2576                 tmp_ &= (mask);                                 \
2577                 tmp_ |= ((val) & ~(mask));                      \
2578                 WREG32_PLL(reg, tmp_);                          \
2579         } while (0)
2580 #define WREG32_SMC_P(reg, val, mask)                            \
2581         do {                                                    \
2582                 uint32_t tmp_ = RREG32_SMC(reg);                \
2583                 tmp_ &= (mask);                                 \
2584                 tmp_ |= ((val) & ~(mask));                      \
2585                 WREG32_SMC(reg, tmp_);                          \
2586         } while (0)
2587 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2588 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2589 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2590
2591 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2592 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2593
2594 /*
2595  * Indirect registers accessors.
2596  * They used to be inlined, but this increases code size by ~65 kbytes.
2597  * Since each performs a pair of MMIO ops
2598  * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2599  * the cost of call+ret is almost negligible. MMIO and locking
2600  * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2601  */
2602 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2603 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2604 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2605 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2606 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2607 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2608 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2609 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2610 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2611 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2612 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2613 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2614 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2615 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2616 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2617 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2618
2619 void r100_pll_errata_after_index(struct radeon_device *rdev);
2620
2621
2622 /*
2623  * ASICs helpers.
2624  */
2625 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2626                             (rdev->pdev->device == 0x5969))
2627 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2628                 (rdev->family == CHIP_RV200) || \
2629                 (rdev->family == CHIP_RS100) || \
2630                 (rdev->family == CHIP_RS200) || \
2631                 (rdev->family == CHIP_RV250) || \
2632                 (rdev->family == CHIP_RV280) || \
2633                 (rdev->family == CHIP_RS300))
2634 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
2635                 (rdev->family == CHIP_RV350) ||                 \
2636                 (rdev->family == CHIP_R350)  ||                 \
2637                 (rdev->family == CHIP_RV380) ||                 \
2638                 (rdev->family == CHIP_R420)  ||                 \
2639                 (rdev->family == CHIP_R423)  ||                 \
2640                 (rdev->family == CHIP_RV410) ||                 \
2641                 (rdev->family == CHIP_RS400) ||                 \
2642                 (rdev->family == CHIP_RS480))
2643 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2644                 (rdev->ddev->pdev->device == 0x9443) || \
2645                 (rdev->ddev->pdev->device == 0x944B) || \
2646                 (rdev->ddev->pdev->device == 0x9506) || \
2647                 (rdev->ddev->pdev->device == 0x9509) || \
2648                 (rdev->ddev->pdev->device == 0x950F) || \
2649                 (rdev->ddev->pdev->device == 0x689C) || \
2650                 (rdev->ddev->pdev->device == 0x689D))
2651 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2652 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
2653                             (rdev->family == CHIP_RS690)  ||    \
2654                             (rdev->family == CHIP_RS740)  ||    \
2655                             (rdev->family >= CHIP_R600))
2656 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2657 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2658 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2659 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2660                              (rdev->flags & RADEON_IS_IGP))
2661 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2662 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2663 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2664                              (rdev->flags & RADEON_IS_IGP))
2665 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2666 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2667 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2668 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2669 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2670 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2671                              (rdev->family == CHIP_MULLINS))
2672
2673 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2674                               (rdev->ddev->pdev->device == 0x6850) || \
2675                               (rdev->ddev->pdev->device == 0x6858) || \
2676                               (rdev->ddev->pdev->device == 0x6859) || \
2677                               (rdev->ddev->pdev->device == 0x6840) || \
2678                               (rdev->ddev->pdev->device == 0x6841) || \
2679                               (rdev->ddev->pdev->device == 0x6842) || \
2680                               (rdev->ddev->pdev->device == 0x6843))
2681
2682 /*
2683  * BIOS helpers.
2684  */
2685 #define RBIOS8(i) (rdev->bios[i])
2686 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2687 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2688
2689 int radeon_combios_init(struct radeon_device *rdev);
2690 void radeon_combios_fini(struct radeon_device *rdev);
2691 int radeon_atombios_init(struct radeon_device *rdev);
2692 void radeon_atombios_fini(struct radeon_device *rdev);
2693
2694
2695 /*
2696  * RING helpers.
2697  */
2698
2699 /**
2700  * radeon_ring_write - write a value to the ring
2701  *
2702  * @ring: radeon_ring structure holding ring information
2703  * @v: dword (dw) value to write
2704  *
2705  * Write a value to the requested ring buffer (all asics).
2706  */
2707 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2708 {
2709         if (ring->count_dw <= 0)
2710                 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2711
2712         ring->ring[ring->wptr++] = v;
2713         ring->wptr &= ring->ptr_mask;
2714         ring->count_dw--;
2715         ring->ring_free_dw--;
2716 }
2717
2718 /*
2719  * ASICs macro.
2720  */
2721 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2722 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2723 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2724 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2725 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2726 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2727 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2728 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2729 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2730 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2731 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2732 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2733 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2734 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2735 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2736 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2737 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2738 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2739 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2740 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2741 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2742 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2743 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2744 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2745 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2746 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2747 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2748 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2749 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2750 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2751 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2752 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2753 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2754 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2755 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2756 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2757 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2758 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2759 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2760 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2761 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2762 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2763 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2764 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2765 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2766 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2767 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2768 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2769 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2770 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2771 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2772 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2773 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2774 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2775 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2776 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2777 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2778 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2779 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2780 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2781 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2782 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2783 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2784 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2785 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2786 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2787 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2788 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2789 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2790 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2791 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2792 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2793 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2794 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2795 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2796 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2797 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2798 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2799 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2800 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2801 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2802 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2803 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2804 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2805 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2806 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2807 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2808 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2809 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2810 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2811 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2812
2813 /* Common functions */
2814 /* AGP */
2815 extern int radeon_gpu_reset(struct radeon_device *rdev);
2816 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2817 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2818 extern void radeon_agp_disable(struct radeon_device *rdev);
2819 extern int radeon_modeset_init(struct radeon_device *rdev);
2820 extern void radeon_modeset_fini(struct radeon_device *rdev);
2821 extern bool radeon_card_posted(struct radeon_device *rdev);
2822 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2823 extern void radeon_update_display_priority(struct radeon_device *rdev);
2824 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2825 extern void radeon_scratch_init(struct radeon_device *rdev);
2826 extern void radeon_wb_fini(struct radeon_device *rdev);
2827 extern int radeon_wb_init(struct radeon_device *rdev);
2828 extern void radeon_wb_disable(struct radeon_device *rdev);
2829 extern void radeon_surface_init(struct radeon_device *rdev);
2830 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2831 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2832 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2833 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2834 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2835 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2836                                      uint32_t flags);
2837 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2838 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2839 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2840 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2841 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2842 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2843                               bool fbcon, bool freeze);
2844 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2845 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2846                                              const u32 *registers,
2847                                              const u32 array_size);
2848
2849 /*
2850  * vm
2851  */
2852 int radeon_vm_manager_init(struct radeon_device *rdev);
2853 void radeon_vm_manager_fini(struct radeon_device *rdev);
2854 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2855 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2856 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2857                                           struct radeon_vm *vm,
2858                                           struct list_head *head);
2859 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2860                                        struct radeon_vm *vm, int ring);
2861 void radeon_vm_flush(struct radeon_device *rdev,
2862                      struct radeon_vm *vm,
2863                      int ring, struct radeon_fence *fence);
2864 void radeon_vm_fence(struct radeon_device *rdev,
2865                      struct radeon_vm *vm,
2866                      struct radeon_fence *fence);
2867 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2868 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2869                                     struct radeon_vm *vm);
2870 int radeon_vm_clear_freed(struct radeon_device *rdev,
2871                           struct radeon_vm *vm);
2872 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2873                              struct radeon_vm *vm);
2874 int radeon_vm_bo_update(struct radeon_device *rdev,
2875                         struct radeon_bo_va *bo_va,
2876                         struct ttm_mem_reg *mem);
2877 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2878                              struct radeon_bo *bo);
2879 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2880                                        struct radeon_bo *bo);
2881 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2882                                       struct radeon_vm *vm,
2883                                       struct radeon_bo *bo);
2884 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2885                           struct radeon_bo_va *bo_va,
2886                           uint64_t offset,
2887                           uint32_t flags);
2888 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2889                       struct radeon_bo_va *bo_va);
2890
2891 /* audio */
2892 void r600_audio_update_hdmi(struct work_struct *work);
2893 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2894 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2895 void r600_audio_enable(struct radeon_device *rdev,
2896                        struct r600_audio_pin *pin,
2897                        u8 enable_mask);
2898 void dce6_audio_enable(struct radeon_device *rdev,
2899                        struct r600_audio_pin *pin,
2900                        u8 enable_mask);
2901
2902 /*
2903  * R600 vram scratch functions
2904  */
2905 int r600_vram_scratch_init(struct radeon_device *rdev);
2906 void r600_vram_scratch_fini(struct radeon_device *rdev);
2907
2908 /*
2909  * r600 cs checking helper
2910  */
2911 unsigned r600_mip_minify(unsigned size, unsigned level);
2912 bool r600_fmt_is_valid_color(u32 format);
2913 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2914 int r600_fmt_get_blocksize(u32 format);
2915 int r600_fmt_get_nblocksx(u32 format, u32 w);
2916 int r600_fmt_get_nblocksy(u32 format, u32 h);
2917
2918 /*
2919  * r600 functions used by radeon_encoder.c
2920  */
2921 struct radeon_hdmi_acr {
2922         u32 clock;
2923
2924         int n_32khz;
2925         int cts_32khz;
2926
2927         int n_44_1khz;
2928         int cts_44_1khz;
2929
2930         int n_48khz;
2931         int cts_48khz;
2932
2933 };
2934
2935 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2936
2937 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2938                                      u32 tiling_pipe_num,
2939                                      u32 max_rb_num,
2940                                      u32 total_max_rb_num,
2941                                      u32 enabled_rb_mask);
2942
2943 /*
2944  * evergreen functions used by radeon_encoder.c
2945  */
2946
2947 extern int ni_init_microcode(struct radeon_device *rdev);
2948 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2949
2950 /* radeon_acpi.c */
2951 #if defined(CONFIG_ACPI)
2952 extern int radeon_acpi_init(struct radeon_device *rdev);
2953 extern void radeon_acpi_fini(struct radeon_device *rdev);
2954 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2955 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2956                                                 u8 perf_req, bool advertise);
2957 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2958 #else
2959 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2960 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2961 #endif
2962
2963 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2964                            struct radeon_cs_packet *pkt,
2965                            unsigned idx);
2966 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2967 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2968                            struct radeon_cs_packet *pkt);
2969 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2970                                 struct radeon_bo_list **cs_reloc,
2971                                 int nomm);
2972 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2973                                uint32_t *vline_start_end,
2974                                uint32_t *vline_status);
2975
2976 #include "radeon_object.h"
2977
2978 #endif