include/asm-x86_64/cpufeature.h

   1 /*
   2  * cpufeature.h
   3  *
   4  * Defines x86 CPU feature bits
   5  */
   6
   7 #ifndef __ASM_X8664_CPUFEATURE_H
   8 #define __ASM_X8664_CPUFEATURE_H
   9
  10 #define NCAPINTS        7       /* N 32-bit words worth of info */
  11
  12 /* Intel-defined CPU features, CPUID level 0x00000001, word 0 */
  13 #define X86_FEATURE_FPU         (0*32+ 0) /* Onboard FPU */
  14 #define X86_FEATURE_VME         (0*32+ 1) /* Virtual Mode Extensions */
  15 #define X86_FEATURE_DE          (0*32+ 2) /* Debugging Extensions */
  16 #define X86_FEATURE_PSE         (0*32+ 3) /* Page Size Extensions */
  17 #define X86_FEATURE_TSC         (0*32+ 4) /* Time Stamp Counter */
  18 #define X86_FEATURE_MSR         (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
  19 #define X86_FEATURE_PAE         (0*32+ 6) /* Physical Address Extensions */
  20 #define X86_FEATURE_MCE         (0*32+ 7) /* Machine Check Architecture */
  21 #define X86_FEATURE_CX8         (0*32+ 8) /* CMPXCHG8 instruction */
  22 #define X86_FEATURE_APIC        (0*32+ 9) /* Onboard APIC */
  23 #define X86_FEATURE_SEP         (0*32+11) /* SYSENTER/SYSEXIT */
  24 #define X86_FEATURE_MTRR        (0*32+12) /* Memory Type Range Registers */
  25 #define X86_FEATURE_PGE         (0*32+13) /* Page Global Enable */
  26 #define X86_FEATURE_MCA         (0*32+14) /* Machine Check Architecture */
  27 #define X86_FEATURE_CMOV        (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
  28 #define X86_FEATURE_PAT         (0*32+16) /* Page Attribute Table */
  29 #define X86_FEATURE_PSE36       (0*32+17) /* 36-bit PSEs */
  30 #define X86_FEATURE_PN          (0*32+18) /* Processor serial number */
  31 #define X86_FEATURE_CLFLSH      (0*32+19) /* Supports the CLFLUSH instruction */
  32 #define X86_FEATURE_DTES        (0*32+21) /* Debug Trace Store */
  33 #define X86_FEATURE_ACPI        (0*32+22) /* ACPI via MSR */
  34 #define X86_FEATURE_MMX         (0*32+23) /* Multimedia Extensions */
  35 #define X86_FEATURE_FXSR        (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
  36                                           /* of FPU context), and CR4.OSFXSR available */
  37 #define X86_FEATURE_XMM         (0*32+25) /* Streaming SIMD Extensions */
  38 #define X86_FEATURE_XMM2        (0*32+26) /* Streaming SIMD Extensions-2 */
  39 #define X86_FEATURE_SELFSNOOP   (0*32+27) /* CPU self snoop */
  40 #define X86_FEATURE_HT          (0*32+28) /* Hyper-Threading */
  41 #define X86_FEATURE_ACC         (0*32+29) /* Automatic clock control */
  42 #define X86_FEATURE_IA64        (0*32+30) /* IA-64 processor */
  43
  44 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
  45 /* Don't duplicate feature flags which are redundant with Intel! */
  46 #define X86_FEATURE_SYSCALL     (1*32+11) /* SYSCALL/SYSRET */
  47 #define X86_FEATURE_MMXEXT      (1*32+22) /* AMD MMX extensions */
  48 #define X86_FEATURE_FXSR_OPT    (1*32+25) /* FXSR optimizations */
  49 #define X86_FEATURE_LM          (1*32+29) /* Long Mode (x86-64) */
  50 #define X86_FEATURE_3DNOWEXT    (1*32+30) /* AMD 3DNow! extensions */
  51 #define X86_FEATURE_3DNOW       (1*32+31) /* 3DNow! */
  52
  53 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
  54 #define X86_FEATURE_RECOVERY    (2*32+ 0) /* CPU in recovery mode */
  55 #define X86_FEATURE_LONGRUN     (2*32+ 1) /* Longrun power control */
  56 #define X86_FEATURE_LRTI        (2*32+ 3) /* LongRun table interface */
  57
  58 /* Other features, Linux-defined mapping, word 3 */
  59 /* This range is used for feature bits which conflict or are synthesized */
  60 #define X86_FEATURE_CXMMX       (3*32+ 0) /* Cyrix MMX extensions */
  61 #define X86_FEATURE_K6_MTRR     (3*32+ 1) /* AMD K6 nonstandard MTRRs */
  62 #define X86_FEATURE_CYRIX_ARR   (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
  63 #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
  64 #define X86_FEATURE_K8_C        (3*32+ 4) /* C stepping K8 */
  65 #define X86_FEATURE_CONSTANT_TSC (3*32+5) /* TSC runs at constant rate */
  66
  67 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
  68 #define X86_FEATURE_XMM3        (4*32+ 0) /* Streaming SIMD Extensions-3 */
  69 #define X86_FEATURE_MWAIT       (4*32+ 3) /* Monitor/Mwait support */
  70 #define X86_FEATURE_DSCPL       (4*32+ 4) /* CPL Qualified Debug Store */
  71 #define X86_FEATURE_EST         (4*32+ 7) /* Enhanced SpeedStep */
  72 #define X86_FEATURE_TM2         (4*32+ 8) /* Thermal Monitor 2 */
  73 #define X86_FEATURE_CID         (4*32+10) /* Context ID */
  74 #define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
  75 #define X86_FEATURE_XTPR        (4*32+14) /* Send Task Priority Messages */
  76
  77 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
  78 #define X86_FEATURE_XSTORE      (5*32+ 2) /* on-CPU RNG present (xstore insn) */
  79 #define X86_FEATURE_XSTORE_EN   (5*32+ 3) /* on-CPU RNG enabled */
  80 #define X86_FEATURE_XCRYPT      (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
  81 #define X86_FEATURE_XCRYPT_EN   (5*32+ 7) /* on-CPU crypto enabled */
  82
  83 /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
  84 #define X86_FEATURE_LAHF_LM     (6*32+ 0) /* LAHF/SAHF in long mode */
  85 #define X86_FEATURE_CMP_LEGACY  (6*32+ 1) /* If yes HyperThreading not valid */
  86
  87 #define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)
  88 #define boot_cpu_has(bit)      test_bit(bit, boot_cpu_data.x86_capability)
  89
  90 #define cpu_has_fpu            1
  91 #define cpu_has_vme            0
  92 #define cpu_has_de             1
  93 #define cpu_has_pse            1
  94 #define cpu_has_tsc            1
  95 #define cpu_has_pae            ___BUG___
  96 #define cpu_has_pge            1
  97 #define cpu_has_apic           boot_cpu_has(X86_FEATURE_APIC)
  98 #define cpu_has_mtrr           1
  99 #define cpu_has_mmx            1
 100 #define cpu_has_fxsr           1
 101 #define cpu_has_xmm            1
 102 #define cpu_has_xmm2           1
 103 #define cpu_has_xmm3           boot_cpu_has(X86_FEATURE_XMM3)
 104 #define cpu_has_ht             boot_cpu_has(X86_FEATURE_HT)
 105 #define cpu_has_mp             1 /* XXX */
 106 #define cpu_has_k6_mtrr        0
 107 #define cpu_has_cyrix_arr      0
 108 #define cpu_has_centaur_mcr    0
 109 #define cpu_has_clflush        boot_cpu_has(X86_FEATURE_CLFLSH)
 110
 111 #endif /* __ASM_X8664_CPUFEATURE_H */