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rtlwifi: rtl8192{c,u}: Remove CamelCase variables
[linux/fpc-iii.git] / drivers / net / wireless / realtek / rtlwifi / rtl8192ce / hw.c
blob5cf5a85d1376815e3fdba0bcd6b8acb384a57c27
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "reg.h"
12 #include "def.h"
13 #include "phy.h"
14 #include "../rtl8192c/dm_common.h"
15 #include "../rtl8192c/fw_common.h"
16 #include "../rtl8192c/phy_common.h"
17 #include "dm.h"
18 #include "led.h"
19 #include "hw.h"
20
21 #define LLT_CONFIG 5
22
23 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
24 u8 set_bits, u8 clear_bits)
25 {
26 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
27 struct rtl_priv *rtlpriv = rtl_priv(hw);
28
29 rtlpci->reg_bcn_ctrl_val |= set_bits;
30 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
31
32 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
33 }
34
35 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
36 {
37 struct rtl_priv *rtlpriv = rtl_priv(hw);
38 u8 tmp1byte;
39
40 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
41 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
43 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
44 tmp1byte &= ~(BIT(0));
45 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
46 }
47
48 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
49 {
50 struct rtl_priv *rtlpriv = rtl_priv(hw);
51 u8 tmp1byte;
52
53 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
54 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
56 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
57 tmp1byte |= BIT(0);
58 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
59 }
60
61 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
62 {
63 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
64 }
65
66 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
67 {
68 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
69 }
70
71 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
72 {
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
75 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
76
77 switch (variable) {
78 case HW_VAR_RCR:
79 *((u32 *) (val)) = rtlpci->receive_config;
80 break;
81 case HW_VAR_RF_STATE:
82 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
83 break;
84 case HW_VAR_FWLPS_RF_ON:{
85 enum rf_pwrstate rfstate;
86 u32 val_rcr;
87
88 rtlpriv->cfg->ops->get_hw_reg(hw,
89 HW_VAR_RF_STATE,
90 (u8 *)(&rfstate));
91 if (rfstate == ERFOFF) {
92 *((bool *) (val)) = true;
93 } else {
94 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
95 val_rcr &= 0x00070000;
96 if (val_rcr)
97 *((bool *) (val)) = false;
98 else
99 *((bool *) (val)) = true;
100 }
101 break;
102 }
103 case HW_VAR_FW_PSMODE_STATUS:
104 *((bool *) (val)) = ppsc->fw_current_inpsmode;
105 break;
106 case HW_VAR_CORRECT_TSF:{
107 u64 tsf;
108 u32 *ptsf_low = (u32 *)&tsf;
109 u32 *ptsf_high = ((u32 *)&tsf) + 1;
110
111 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
112 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
113
114 *((u64 *) (val)) = tsf;
115
116 break;
117 }
118 case HAL_DEF_WOWLAN:
119 break;
120 default:
121 pr_err("switch case %#x not processed\n", variable);
122 break;
123 }
124 }
125
126 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
127 {
128 struct rtl_priv *rtlpriv = rtl_priv(hw);
129 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
130 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
131 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
132 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
133 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
134 u8 idx;
135
136 switch (variable) {
137 case HW_VAR_ETHER_ADDR:{
138 for (idx = 0; idx < ETH_ALEN; idx++) {
139 rtl_write_byte(rtlpriv, (REG_MACID + idx),
140 val[idx]);
141 }
142 break;
143 }
144 case HW_VAR_BASIC_RATE:{
145 u16 rate_cfg = ((u16 *) val)[0];
146 u8 rate_index = 0;
147 rate_cfg &= 0x15f;
148 rate_cfg |= 0x01;
149 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
150 rtl_write_byte(rtlpriv, REG_RRSR + 1,
151 (rate_cfg >> 8) & 0xff);
152 while (rate_cfg > 0x1) {
153 rate_cfg = (rate_cfg >> 1);
154 rate_index++;
155 }
156 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
157 rate_index);
158 break;
159 }
160 case HW_VAR_BSSID:{
161 for (idx = 0; idx < ETH_ALEN; idx++) {
162 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
163 val[idx]);
164 }
165 break;
166 }
167 case HW_VAR_SIFS:{
168 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
169 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
170
171 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
172 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
173
174 if (!mac->ht_enable)
175 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
176 0x0e0e);
177 else
178 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
179 *((u16 *) val));
180 break;
181 }
182 case HW_VAR_SLOT_TIME:{
183 u8 e_aci;
184
185 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
186 "HW_VAR_SLOT_TIME %x\n", val[0]);
187
188 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
189
190 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
191 rtlpriv->cfg->ops->set_hw_reg(hw,
192 HW_VAR_AC_PARAM,
193 &e_aci);
194 }
195 break;
196 }
197 case HW_VAR_ACK_PREAMBLE:{
198 u8 reg_tmp;
199 u8 short_preamble = (bool)*val;
200 reg_tmp = (mac->cur_40_prime_sc) << 5;
201 if (short_preamble)
202 reg_tmp |= 0x80;
203
204 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
205 break;
206 }
207 case HW_VAR_AMPDU_MIN_SPACE:{
208 u8 min_spacing_to_set;
209 u8 sec_min_space;
210
211 min_spacing_to_set = *val;
212 if (min_spacing_to_set <= 7) {
213 sec_min_space = 0;
214
215 if (min_spacing_to_set < sec_min_space)
216 min_spacing_to_set = sec_min_space;
217
218 mac->min_space_cfg = ((mac->min_space_cfg &
219 0xf8) |
220 min_spacing_to_set);
221
222 *val = min_spacing_to_set;
223
224 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
225 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
226 mac->min_space_cfg);
227
228 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
229 mac->min_space_cfg);
230 }
231 break;
232 }
233 case HW_VAR_SHORTGI_DENSITY:{
234 u8 density_to_set;
235
236 density_to_set = *val;
237 mac->min_space_cfg |= (density_to_set << 3);
238
239 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
240 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
241 mac->min_space_cfg);
242
243 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
244 mac->min_space_cfg);
245
246 break;
247 }
248 case HW_VAR_AMPDU_FACTOR:{
249 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
250 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
251
252 u8 factor_toset;
253 u8 *p_regtoset = NULL;
254 u8 index = 0;
255
256 if ((rtlpriv->btcoexist.bt_coexistence) &&
257 (rtlpriv->btcoexist.bt_coexist_type ==
258 BT_CSR_BC4))
259 p_regtoset = regtoset_bt;
260 else
261 p_regtoset = regtoset_normal;
262
263 factor_toset = *(val);
264 if (factor_toset <= 3) {
265 factor_toset = (1 << (factor_toset + 2));
266 if (factor_toset > 0xf)
267 factor_toset = 0xf;
268
269 for (index = 0; index < 4; index++) {
270 if ((p_regtoset[index] & 0xf0) >
271 (factor_toset << 4))
272 p_regtoset[index] =
273 (p_regtoset[index] & 0x0f) |
274 (factor_toset << 4);
275
276 if ((p_regtoset[index] & 0x0f) >
277 factor_toset)
278 p_regtoset[index] =
279 (p_regtoset[index] & 0xf0) |
280 (factor_toset);
281
282 rtl_write_byte(rtlpriv,
283 (REG_AGGLEN_LMT + index),
284 p_regtoset[index]);
285
286 }
287
288 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
289 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
290 factor_toset);
291 }
292 break;
293 }
294 case HW_VAR_AC_PARAM:{
295 u8 e_aci = *(val);
296 rtl92c_dm_init_edca_turbo(hw);
297
298 if (rtlpci->acm_method != EACMWAY2_SW)
299 rtlpriv->cfg->ops->set_hw_reg(hw,
300 HW_VAR_ACM_CTRL,
301 (&e_aci));
302 break;
303 }
304 case HW_VAR_ACM_CTRL:{
305 u8 e_aci = *(val);
306 union aci_aifsn *p_aci_aifsn =
307 (union aci_aifsn *)(&(mac->ac[0].aifs));
308 u8 acm = p_aci_aifsn->f.acm;
309 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
310
311 acm_ctrl =
312 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
313
314 if (acm) {
315 switch (e_aci) {
316 case AC0_BE:
317 acm_ctrl |= ACMHW_BEQEN;
318 break;
319 case AC2_VI:
320 acm_ctrl |= ACMHW_VIQEN;
321 break;
322 case AC3_VO:
323 acm_ctrl |= ACMHW_VOQEN;
324 break;
325 default:
326 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
327 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
328 acm);
329 break;
330 }
331 } else {
332 switch (e_aci) {
333 case AC0_BE:
334 acm_ctrl &= (~ACMHW_BEQEN);
335 break;
336 case AC2_VI:
337 acm_ctrl &= (~ACMHW_VIQEN);
338 break;
339 case AC3_VO:
340 acm_ctrl &= (~ACMHW_VOQEN);
341 break;
342 default:
343 pr_err("switch case %#x not processed\n",
344 e_aci);
345 break;
346 }
347 }
348
349 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
350 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
351 acm_ctrl);
352 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
353 break;
354 }
355 case HW_VAR_RCR:{
356 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
357 rtlpci->receive_config = ((u32 *) (val))[0];
358 break;
359 }
360 case HW_VAR_RETRY_LIMIT:{
361 u8 retry_limit = val[0];
362
363 rtl_write_word(rtlpriv, REG_RL,
364 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
365 retry_limit << RETRY_LIMIT_LONG_SHIFT);
366 break;
367 }
368 case HW_VAR_DUAL_TSF_RST:
369 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
370 break;
371 case HW_VAR_EFUSE_BYTES:
372 rtlefuse->efuse_usedbytes = *((u16 *) val);
373 break;
374 case HW_VAR_EFUSE_USAGE:
375 rtlefuse->efuse_usedpercentage = *val;
376 break;
377 case HW_VAR_IO_CMD:
378 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
379 break;
380 case HW_VAR_WPA_CONFIG:
381 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
382 break;
383 case HW_VAR_SET_RPWM:{
384 u8 rpwm_val;
385
386 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
387 udelay(1);
388
389 if (rpwm_val & BIT(7)) {
390 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
391 } else {
392 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
393 *val | BIT(7));
394 }
395
396 break;
397 }
398 case HW_VAR_H2C_FW_PWRMODE:{
399 u8 psmode = *val;
400
401 if ((psmode != FW_PS_ACTIVE_MODE) &&
402 (!IS_92C_SERIAL(rtlhal->version))) {
403 rtl92c_dm_rf_saving(hw, true);
404 }
405
406 rtl92c_set_fw_pwrmode_cmd(hw, *val);
407 break;
408 }
409 case HW_VAR_FW_PSMODE_STATUS:
410 ppsc->fw_current_inpsmode = *((bool *) val);
411 break;
412 case HW_VAR_H2C_FW_JOINBSSRPT:{
413 u8 mstatus = *val;
414 u8 tmp_regcr, tmp_reg422;
415 bool recover = false;
416
417 if (mstatus == RT_MEDIA_CONNECT) {
418 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
419 NULL);
420
421 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
422 rtl_write_byte(rtlpriv, REG_CR + 1,
423 (tmp_regcr | BIT(0)));
424
425 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
426 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
427
428 tmp_reg422 =
429 rtl_read_byte(rtlpriv,
430 REG_FWHW_TXQ_CTRL + 2);
431 if (tmp_reg422 & BIT(6))
432 recover = true;
433 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
434 tmp_reg422 & (~BIT(6)));
435
436 rtl92c_set_fw_rsvdpagepkt(hw, NULL);
437
438 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
439 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
440
441 if (recover) {
442 rtl_write_byte(rtlpriv,
443 REG_FWHW_TXQ_CTRL + 2,
444 tmp_reg422);
445 }
446
447 rtl_write_byte(rtlpriv, REG_CR + 1,
448 (tmp_regcr & ~(BIT(0))));
449 }
450 rtl92c_set_fw_joinbss_report_cmd(hw, *val);
451
452 break;
453 }
454 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
455 rtl92c_set_p2p_ps_offload_cmd(hw, *val);
456 break;
457 case HW_VAR_AID:{
458 u16 u2btmp;
459 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
460 u2btmp &= 0xC000;
461 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
462 mac->assoc_id));
463
464 break;
465 }
466 case HW_VAR_CORRECT_TSF:{
467 u8 btype_ibss = val[0];
468
469 if (btype_ibss)
470 _rtl92ce_stop_tx_beacon(hw);
471
472 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
473
474 rtl_write_dword(rtlpriv, REG_TSFTR,
475 (u32) (mac->tsf & 0xffffffff));
476 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
477 (u32) ((mac->tsf >> 32) & 0xffffffff));
478
479 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
480
481 if (btype_ibss)
482 _rtl92ce_resume_tx_beacon(hw);
483
484 break;
485
486 }
487 case HW_VAR_FW_LPS_ACTION: {
488 bool enter_fwlps = *((bool *)val);
489 u8 rpwm_val, fw_pwrmode;
490 bool fw_current_inps;
491
492 if (enter_fwlps) {
493 rpwm_val = 0x02; /* RF off */
494 fw_current_inps = true;
495 rtlpriv->cfg->ops->set_hw_reg(hw,
496 HW_VAR_FW_PSMODE_STATUS,
497 (u8 *)(&fw_current_inps));
498 rtlpriv->cfg->ops->set_hw_reg(hw,
499 HW_VAR_H2C_FW_PWRMODE,
500 &ppsc->fwctrl_psmode);
501
502 rtlpriv->cfg->ops->set_hw_reg(hw,
503 HW_VAR_SET_RPWM,
504 &rpwm_val);
505 } else {
506 rpwm_val = 0x0C; /* RF on */
507 fw_pwrmode = FW_PS_ACTIVE_MODE;
508 fw_current_inps = false;
509 rtlpriv->cfg->ops->set_hw_reg(hw,
510 HW_VAR_SET_RPWM,
511 &rpwm_val);
512 rtlpriv->cfg->ops->set_hw_reg(hw,
513 HW_VAR_H2C_FW_PWRMODE,
514 &fw_pwrmode);
515
516 rtlpriv->cfg->ops->set_hw_reg(hw,
517 HW_VAR_FW_PSMODE_STATUS,
518 (u8 *)(&fw_current_inps));
519 }
520 break; }
521 case HW_VAR_KEEP_ALIVE: {
522 u8 array[2];
523
524 array[0] = 0xff;
525 array[1] = *((u8 *)val);
526 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, array);
527 break; }
528 default:
529 pr_err("switch case %d not processed\n", variable);
530 break;
531 }
532 }
533
534 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
535 {
536 struct rtl_priv *rtlpriv = rtl_priv(hw);
537 bool status = true;
538 long count = 0;
539 u32 value = _LLT_INIT_ADDR(address) |
540 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
541
542 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
543
544 do {
545 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
546 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
547 break;
548
549 if (count > POLLING_LLT_THRESHOLD) {
550 pr_err("Failed to polling write LLT done at address %d!\n",
551 address);
552 status = false;
553 break;
554 }
555 } while (++count);
556
557 return status;
558 }
559
560 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
561 {
562 struct rtl_priv *rtlpriv = rtl_priv(hw);
563 unsigned short i;
564 u8 txpktbuf_bndy;
565 u8 maxpage;
566 bool status;
567
568 #if LLT_CONFIG == 1
569 maxpage = 255;
570 txpktbuf_bndy = 252;
571 #elif LLT_CONFIG == 2
572 maxpage = 127;
573 txpktbuf_bndy = 124;
574 #elif LLT_CONFIG == 3
575 maxpage = 255;
576 txpktbuf_bndy = 174;
577 #elif LLT_CONFIG == 4
578 maxpage = 255;
579 txpktbuf_bndy = 246;
580 #elif LLT_CONFIG == 5
581 maxpage = 255;
582 txpktbuf_bndy = 246;
583 #endif
584
585 #if LLT_CONFIG == 1
586 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
587 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
588 #elif LLT_CONFIG == 2
589 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
590 #elif LLT_CONFIG == 3
591 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
592 #elif LLT_CONFIG == 4
593 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
594 #elif LLT_CONFIG == 5
595 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
596
597 rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
598 #endif
599
600 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
601 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
602
603 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
604 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
605
606 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
607 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
608 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
609
610 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
611 status = _rtl92ce_llt_write(hw, i, i + 1);
612 if (true != status)
613 return status;
614 }
615
616 status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
617 if (true != status)
618 return status;
619
620 for (i = txpktbuf_bndy; i < maxpage; i++) {
621 status = _rtl92ce_llt_write(hw, i, (i + 1));
622 if (true != status)
623 return status;
624 }
625
626 status = _rtl92ce_llt_write(hw, maxpage, txpktbuf_bndy);
627 if (true != status)
628 return status;
629
630 return true;
631 }
632
633 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
634 {
635 struct rtl_priv *rtlpriv = rtl_priv(hw);
636 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
637 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
638 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
639
640 if (rtlpci->up_first_time)
641 return;
642
643 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
644 rtl92ce_sw_led_on(hw, pled0);
645 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
646 rtl92ce_sw_led_on(hw, pled0);
647 else
648 rtl92ce_sw_led_off(hw, pled0);
649 }
650
651 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
652 {
653 struct rtl_priv *rtlpriv = rtl_priv(hw);
654 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
655 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
656
657 unsigned char bytetmp;
658 unsigned short wordtmp;
659 u16 retry;
660
661 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
662 if (rtlpriv->btcoexist.bt_coexistence) {
663 u32 value32;
664 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
665 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
666 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
667 }
668 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
669 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
670
671 if (rtlpriv->btcoexist.bt_coexistence) {
672 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
673
674 u4b_tmp &= (~0x00024800);
675 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
676 }
677
678 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
679 udelay(2);
680
681 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
682 udelay(2);
683
684 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
685 udelay(2);
686
687 retry = 0;
688 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
689 rtl_read_dword(rtlpriv, 0xEC), bytetmp);
690
691 while ((bytetmp & BIT(0)) && retry < 1000) {
692 retry++;
693 udelay(50);
694 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
695 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
696 rtl_read_dword(rtlpriv, 0xEC), bytetmp);
697 udelay(50);
698 }
699
700 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
701
702 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
703 udelay(2);
704
705 if (rtlpriv->btcoexist.bt_coexistence) {
706 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
707 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
708 }
709
710 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
711
712 if (!_rtl92ce_llt_table_init(hw))
713 return false;
714
715 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
716 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
717
718 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
719
720 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
721 wordtmp &= 0xf;
722 wordtmp |= 0xF771;
723 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
724
725 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
726 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
727 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
728
729 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
730
731 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
732 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
733 DMA_BIT_MASK(32));
734 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
735 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
736 DMA_BIT_MASK(32));
737 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
738 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
739 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
740 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
741 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
742 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
743 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
744 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
745 rtl_write_dword(rtlpriv, REG_HQ_DESA,
746 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
747 DMA_BIT_MASK(32));
748 rtl_write_dword(rtlpriv, REG_RX_DESA,
749 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
750 DMA_BIT_MASK(32));
751
752 if (IS_92C_SERIAL(rtlhal->version))
753 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
754 else
755 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
756
757 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
758
759 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
760 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
761 do {
762 retry++;
763 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
764 } while ((retry < 200) && (bytetmp & BIT(7)));
765
766 _rtl92ce_gen_refresh_led_state(hw);
767
768 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
769
770 return true;
771 }
772
773 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
774 {
775 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
776 struct rtl_priv *rtlpriv = rtl_priv(hw);
777 u8 reg_bw_opmode;
778 u32 reg_prsr;
779
780 reg_bw_opmode = BW_OPMODE_20MHZ;
781 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
782
783 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
784
785 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
786
787 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
788
789 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
790
791 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
792
793 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
794
795 rtl_write_word(rtlpriv, REG_RL, 0x0707);
796
797 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
798
799 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
800
801 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
802 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
803 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
804 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
805
806 if ((rtlpriv->btcoexist.bt_coexistence) &&
807 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
808 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
809 else
810 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
811
812 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
813
814 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
815
816 rtlpci->reg_bcn_ctrl_val = 0x1f;
817 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
818
819 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
820
821 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
822
823 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
824 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
825
826 if ((rtlpriv->btcoexist.bt_coexistence) &&
827 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) {
828 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
829 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
830 } else {
831 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
832 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
833 }
834
835 if ((rtlpriv->btcoexist.bt_coexistence) &&
836 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
837 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
838 else
839 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
840
841 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
842
843 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
844 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
845
846 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
847
848 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
849
850 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
851 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
852
853 }
854
855 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
856 {
857 struct rtl_priv *rtlpriv = rtl_priv(hw);
858 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
859
860 rtl_write_byte(rtlpriv, 0x34b, 0x93);
861 rtl_write_word(rtlpriv, 0x350, 0x870c);
862 rtl_write_byte(rtlpriv, 0x352, 0x1);
863
864 if (ppsc->support_backdoor)
865 rtl_write_byte(rtlpriv, 0x349, 0x1b);
866 else
867 rtl_write_byte(rtlpriv, 0x349, 0x03);
868
869 rtl_write_word(rtlpriv, 0x350, 0x2718);
870 rtl_write_byte(rtlpriv, 0x352, 0x1);
871 }
872
873 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
874 {
875 struct rtl_priv *rtlpriv = rtl_priv(hw);
876 u8 sec_reg_value;
877
878 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
879 "PairwiseENcAlgorithm = %d GroupEncAlgorithm = %d\n",
880 rtlpriv->sec.pairwise_enc_algorithm,
881 rtlpriv->sec.group_enc_algorithm);
882
883 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
884 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
885 "not open hw encryption\n");
886 return;
887 }
888
889 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
890
891 if (rtlpriv->sec.use_defaultkey) {
892 sec_reg_value |= SCR_TXUSEDK;
893 sec_reg_value |= SCR_RXUSEDK;
894 }
895
896 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
897
898 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
899
900 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
901 "The SECR-value %x\n", sec_reg_value);
902
903 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
904
905 }
906
907 int rtl92ce_hw_init(struct ieee80211_hw *hw)
908 {
909 struct rtl_priv *rtlpriv = rtl_priv(hw);
910 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
911 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
912 struct rtl_phy *rtlphy = &(rtlpriv->phy);
913 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
914 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
915 bool rtstatus = true;
916 bool is92c;
917 int err;
918 u8 tmp_u1b;
919 unsigned long flags;
920
921 rtlpci->being_init_adapter = true;
922
923 /* Since this function can take a very long time (up to 350 ms)
924 * and can be called with irqs disabled, reenable the irqs
925 * to let the other devices continue being serviced.
926 *
927 * It is safe doing so since our own interrupts will only be enabled
928 * in a subsequent step.
929 */
930 local_save_flags(flags);
931 local_irq_enable();
932
933 rtlhal->fw_ready = false;
934 rtlpriv->intf_ops->disable_aspm(hw);
935 rtstatus = _rtl92ce_init_mac(hw);
936 if (!rtstatus) {
937 pr_err("Init MAC failed\n");
938 err = 1;
939 goto exit;
940 }
941
942 err = rtl92c_download_fw(hw);
943 if (err) {
944 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
945 "Failed to download FW. Init HW without FW now..\n");
946 err = 1;
947 goto exit;
948 }
949
950 rtlhal->fw_ready = true;
951 rtlhal->last_hmeboxnum = 0;
952 rtl92c_phy_mac_config(hw);
953 /* because last function modify RCR, so we update
954 * rcr var here, or TP will unstable for receive_config
955 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
956 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
957 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
958 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
959 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
960 rtl92c_phy_bb_config(hw);
961 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
962 rtl92c_phy_rf_config(hw);
963 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
964 !IS_92C_SERIAL(rtlhal->version)) {
965 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
966 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
967 } else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
968 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
969 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
970 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
971 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
972 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
973 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
974 }
975 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
976 RF_CHNLBW, RFREG_OFFSET_MASK);
977 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
978 RF_CHNLBW, RFREG_OFFSET_MASK);
979 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
980 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
981 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
982 _rtl92ce_hw_configure(hw);
983 rtl_cam_reset_all_entry(hw);
984 rtl92ce_enable_hw_security_config(hw);
985
986 ppsc->rfpwr_state = ERFON;
987
988 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
989 _rtl92ce_enable_aspm_back_door(hw);
990 rtlpriv->intf_ops->enable_aspm(hw);
991
992 rtl8192ce_bt_hw_init(hw);
993
994 if (ppsc->rfpwr_state == ERFON) {
995 rtl92c_phy_set_rfpath_switch(hw, 1);
996 if (rtlphy->iqk_initialized) {
997 rtl92c_phy_iq_calibrate(hw, true);
998 } else {
999 rtl92c_phy_iq_calibrate(hw, false);
1000 rtlphy->iqk_initialized = true;
1001 }
1002
1003 rtl92c_dm_check_txpower_tracking(hw);
1004 rtl92c_phy_lc_calibrate(hw);
1005 }
1006
1007 is92c = IS_92C_SERIAL(rtlhal->version);
1008 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1009 if (!(tmp_u1b & BIT(0))) {
1010 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1011 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1012 }
1013
1014 if (!(tmp_u1b & BIT(1)) && is92c) {
1015 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1016 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n");
1017 }
1018
1019 if (!(tmp_u1b & BIT(4))) {
1020 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1021 tmp_u1b &= 0x0F;
1022 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1023 udelay(10);
1024 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1025 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1026 }
1027 rtl92c_dm_init(hw);
1028 exit:
1029 local_irq_restore(flags);
1030 rtlpci->being_init_adapter = false;
1031 return err;
1032 }
1033
1034 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
1035 {
1036 struct rtl_priv *rtlpriv = rtl_priv(hw);
1037 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1038 enum version_8192c version = VERSION_UNKNOWN;
1039 u32 value32;
1040 const char *versionid;
1041
1042 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1043 if (value32 & TRP_VAUX_EN) {
1044 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1045 VERSION_A_CHIP_88C;
1046 } else {
1047 version = (enum version_8192c) (CHIP_VER_B |
1048 ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) |
1049 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1050 if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 &
1051 CHIP_VER_RTL_MASK)) {
1052 version = (enum version_8192c)(version |
1053 ((((value32 & CHIP_VER_RTL_MASK) == BIT(12))
1054 ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) |
1055 CHIP_VENDOR_UMC));
1056 }
1057 if (IS_92C_SERIAL(version)) {
1058 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
1059 version = (enum version_8192c)(version |
1060 ((CHIP_BONDING_IDENTIFIER(value32)
1061 == CHIP_BONDING_92C_1T2R) ?
1062 RF_TYPE_1T2R : 0));
1063 }
1064 }
1065
1066 switch (version) {
1067 case VERSION_B_CHIP_92C:
1068 versionid = "B_CHIP_92C";
1069 break;
1070 case VERSION_B_CHIP_88C:
1071 versionid = "B_CHIP_88C";
1072 break;
1073 case VERSION_A_CHIP_92C:
1074 versionid = "A_CHIP_92C";
1075 break;
1076 case VERSION_A_CHIP_88C:
1077 versionid = "A_CHIP_88C";
1078 break;
1079 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
1080 versionid = "A_CUT_92C_1T2R";
1081 break;
1082 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
1083 versionid = "A_CUT_92C";
1084 break;
1085 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
1086 versionid = "A_CUT_88C";
1087 break;
1088 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
1089 versionid = "B_CUT_92C_1T2R";
1090 break;
1091 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
1092 versionid = "B_CUT_92C";
1093 break;
1094 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
1095 versionid = "B_CUT_88C";
1096 break;
1097 default:
1098 versionid = "Unknown. Bug?";
1099 break;
1100 }
1101
1102 pr_info("Chip Version ID: %s\n", versionid);
1103
1104 switch (version & 0x3) {
1105 case CHIP_88C:
1106 rtlphy->rf_type = RF_1T1R;
1107 break;
1108 case CHIP_92C:
1109 rtlphy->rf_type = RF_2T2R;
1110 break;
1111 case CHIP_92C_1T2R:
1112 rtlphy->rf_type = RF_1T2R;
1113 break;
1114 default:
1115 rtlphy->rf_type = RF_1T1R;
1116 pr_err("ERROR RF_Type is set!!\n");
1117 break;
1118 }
1119
1120 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1121 rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
1122
1123 return version;
1124 }
1125
1126 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1127 enum nl80211_iftype type)
1128 {
1129 struct rtl_priv *rtlpriv = rtl_priv(hw);
1130 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1131 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1132 u8 mode = MSR_NOLINK;
1133
1134 bt_msr &= 0xfc;
1135
1136 switch (type) {
1137 case NL80211_IFTYPE_UNSPECIFIED:
1138 mode = MSR_NOLINK;
1139 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1140 "Set Network type to NO LINK!\n");
1141 break;
1142 case NL80211_IFTYPE_ADHOC:
1143 mode = MSR_ADHOC;
1144 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1145 "Set Network type to Ad Hoc!\n");
1146 break;
1147 case NL80211_IFTYPE_STATION:
1148 mode = MSR_INFRA;
1149 ledaction = LED_CTL_LINK;
1150 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1151 "Set Network type to STA!\n");
1152 break;
1153 case NL80211_IFTYPE_AP:
1154 mode = MSR_AP;
1155 ledaction = LED_CTL_LINK;
1156 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1157 "Set Network type to AP!\n");
1158 break;
1159 case NL80211_IFTYPE_MESH_POINT:
1160 mode = MSR_ADHOC;
1161 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1162 "Set Network type to Mesh Point!\n");
1163 break;
1164 default:
1165 pr_err("Network type %d not supported!\n", type);
1166 return 1;
1167
1168 }
1169
1170 /* MSR_INFRA == Link in infrastructure network;
1171 * MSR_ADHOC == Link in ad hoc network;
1172 * Therefore, check link state is necessary.
1173 *
1174 * MSR_AP == AP mode; link state does not matter here.
1175 */
1176 if (mode != MSR_AP &&
1177 rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1178 mode = MSR_NOLINK;
1179 ledaction = LED_CTL_NO_LINK;
1180 }
1181 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1182 _rtl92ce_stop_tx_beacon(hw);
1183 _rtl92ce_enable_bcn_sub_func(hw);
1184 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1185 _rtl92ce_resume_tx_beacon(hw);
1186 _rtl92ce_disable_bcn_sub_func(hw);
1187 } else {
1188 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1189 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1190 mode);
1191 }
1192 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1193
1194 rtlpriv->cfg->ops->led_control(hw, ledaction);
1195 if (mode == MSR_AP)
1196 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1197 else
1198 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1199 return 0;
1200 }
1201
1202 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1203 {
1204 struct rtl_priv *rtlpriv = rtl_priv(hw);
1205 u32 reg_rcr;
1206
1207 if (rtlpriv->psc.rfpwr_state != ERFON)
1208 return;
1209
1210 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1211
1212 if (check_bssid) {
1213 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1214 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1215 (u8 *) (&reg_rcr));
1216 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1217 } else if (!check_bssid) {
1218 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1219 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1220 rtlpriv->cfg->ops->set_hw_reg(hw,
1221 HW_VAR_RCR, (u8 *) (&reg_rcr));
1222 }
1223
1224 }
1225
1226 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1227 {
1228 struct rtl_priv *rtlpriv = rtl_priv(hw);
1229
1230 if (_rtl92ce_set_media_status(hw, type))
1231 return -EOPNOTSUPP;
1232
1233 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1234 if (type != NL80211_IFTYPE_AP &&
1235 type != NL80211_IFTYPE_MESH_POINT)
1236 rtl92ce_set_check_bssid(hw, true);
1237 } else {
1238 rtl92ce_set_check_bssid(hw, false);
1239 }
1240
1241 return 0;
1242 }
1243
1244 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1245 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1246 {
1247 struct rtl_priv *rtlpriv = rtl_priv(hw);
1248 rtl92c_dm_init_edca_turbo(hw);
1249 switch (aci) {
1250 case AC1_BK:
1251 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1252 break;
1253 case AC0_BE:
1254 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1255 break;
1256 case AC2_VI:
1257 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1258 break;
1259 case AC3_VO:
1260 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1261 break;
1262 default:
1263 WARN_ONCE(true, "rtl8192ce: invalid aci: %d !\n", aci);
1264 break;
1265 }
1266 }
1267
1268 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1269 {
1270 struct rtl_priv *rtlpriv = rtl_priv(hw);
1271 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1272
1273 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1274 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1275 rtlpci->irq_enabled = true;
1276 }
1277
1278 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1279 {
1280 struct rtl_priv *rtlpriv = rtl_priv(hw);
1281 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1282
1283 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1284 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1285 rtlpci->irq_enabled = false;
1286 }
1287
1288 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1289 {
1290 struct rtl_priv *rtlpriv = rtl_priv(hw);
1291 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1292 u8 u1b_tmp;
1293 u32 u4b_tmp;
1294
1295 rtlpriv->intf_ops->enable_aspm(hw);
1296 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1297 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1298 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1299 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1300 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1301 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1302 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7))
1303 rtl92c_firmware_selfreset(hw);
1304 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1305 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1306 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1307 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1308 if ((rtlpriv->btcoexist.bt_coexistence) &&
1309 ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
1310 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8))) {
1311 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1312 (u1b_tmp << 8));
1313 } else {
1314 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1315 (u1b_tmp << 8));
1316 }
1317 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1318 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1319 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1320 if (!IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version))
1321 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1322 if (rtlpriv->btcoexist.bt_coexistence) {
1323 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1324 u4b_tmp |= 0x03824800;
1325 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1326 } else {
1327 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1328 }
1329
1330 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1331 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1332 }
1333
1334 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1335 {
1336 struct rtl_priv *rtlpriv = rtl_priv(hw);
1337 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1338 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1339 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1340 enum nl80211_iftype opmode;
1341
1342 mac->link_state = MAC80211_NOLINK;
1343 opmode = NL80211_IFTYPE_UNSPECIFIED;
1344 _rtl92ce_set_media_status(hw, opmode);
1345 if (rtlpci->driver_is_goingto_unload ||
1346 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1347 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1348 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1349 _rtl92ce_poweroff_adapter(hw);
1350
1351 /* after power off we should do iqk again */
1352 rtlpriv->phy.iqk_initialized = false;
1353 }
1354
1355 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1356 struct rtl_int *intvec)
1357 {
1358 struct rtl_priv *rtlpriv = rtl_priv(hw);
1359 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1360
1361 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1362 rtl_write_dword(rtlpriv, ISR, intvec->inta);
1363 }
1364
1365 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1366 {
1367
1368 struct rtl_priv *rtlpriv = rtl_priv(hw);
1369 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1370 u16 bcn_interval, atim_window;
1371
1372 bcn_interval = mac->beacon_interval;
1373 atim_window = 2; /*FIX MERGE */
1374 rtl92ce_disable_interrupt(hw);
1375 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1376 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1377 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1378 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1379 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1380 rtl_write_byte(rtlpriv, 0x606, 0x30);
1381 rtl92ce_enable_interrupt(hw);
1382 }
1383
1384 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1385 {
1386 struct rtl_priv *rtlpriv = rtl_priv(hw);
1387 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1388 u16 bcn_interval = mac->beacon_interval;
1389
1390 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1391 "beacon_interval:%d\n", bcn_interval);
1392 rtl92ce_disable_interrupt(hw);
1393 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1394 rtl92ce_enable_interrupt(hw);
1395 }
1396
1397 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1398 u32 add_msr, u32 rm_msr)
1399 {
1400 struct rtl_priv *rtlpriv = rtl_priv(hw);
1401 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1402
1403 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1404 add_msr, rm_msr);
1405
1406 if (add_msr)
1407 rtlpci->irq_mask[0] |= add_msr;
1408 if (rm_msr)
1409 rtlpci->irq_mask[0] &= (~rm_msr);
1410 rtl92ce_disable_interrupt(hw);
1411 rtl92ce_enable_interrupt(hw);
1412 }
1413
1414 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1415 bool autoload_fail,
1416 u8 *hwinfo)
1417 {
1418 struct rtl_priv *rtlpriv = rtl_priv(hw);
1419 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1420 u8 rf_path, index, tempval;
1421 u16 i;
1422
1423 for (rf_path = 0; rf_path < 2; rf_path++) {
1424 for (i = 0; i < 3; i++) {
1425 if (!autoload_fail) {
1426 rtlefuse->
1427 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1428 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1429 rtlefuse->
1430 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1431 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1432 i];
1433 } else {
1434 rtlefuse->
1435 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1436 EEPROM_DEFAULT_TXPOWERLEVEL;
1437 rtlefuse->
1438 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1439 EEPROM_DEFAULT_TXPOWERLEVEL;
1440 }
1441 }
1442 }
1443
1444 for (i = 0; i < 3; i++) {
1445 if (!autoload_fail)
1446 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1447 else
1448 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1449 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1450 (tempval & 0xf);
1451 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1452 ((tempval & 0xf0) >> 4);
1453 }
1454
1455 for (rf_path = 0; rf_path < 2; rf_path++)
1456 for (i = 0; i < 3; i++)
1457 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1458 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1459 rf_path, i,
1460 rtlefuse->
1461 eeprom_chnlarea_txpwr_cck[rf_path][i]);
1462 for (rf_path = 0; rf_path < 2; rf_path++)
1463 for (i = 0; i < 3; i++)
1464 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1465 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1466 rf_path, i,
1467 rtlefuse->
1468 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
1469 for (rf_path = 0; rf_path < 2; rf_path++)
1470 for (i = 0; i < 3; i++)
1471 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1472 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1473 rf_path, i,
1474 rtlefuse->
1475 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
1476
1477 for (rf_path = 0; rf_path < 2; rf_path++) {
1478 for (i = 0; i < 14; i++) {
1479 index = rtl92c_get_chnl_group((u8)i);
1480
1481 rtlefuse->txpwrlevel_cck[rf_path][i] =
1482 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1483 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1484 rtlefuse->
1485 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1486
1487 if ((rtlefuse->
1488 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1489 rtlefuse->
1490 eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
1491 > 0) {
1492 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1493 rtlefuse->
1494 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1495 [index] -
1496 rtlefuse->
1497 eprom_chnl_txpwr_ht40_2sdf[rf_path]
1498 [index];
1499 } else {
1500 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1501 }
1502 }
1503
1504 for (i = 0; i < 14; i++) {
1505 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1506 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1507 rf_path, i,
1508 rtlefuse->txpwrlevel_cck[rf_path][i],
1509 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1510 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1511 }
1512 }
1513
1514 for (i = 0; i < 3; i++) {
1515 if (!autoload_fail) {
1516 rtlefuse->eeprom_pwrlimit_ht40[i] =
1517 hwinfo[EEPROM_TXPWR_GROUP + i];
1518 rtlefuse->eeprom_pwrlimit_ht20[i] =
1519 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1520 } else {
1521 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1522 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1523 }
1524 }
1525
1526 for (rf_path = 0; rf_path < 2; rf_path++) {
1527 for (i = 0; i < 14; i++) {
1528 index = rtl92c_get_chnl_group((u8)i);
1529
1530 if (rf_path == RF90_PATH_A) {
1531 rtlefuse->pwrgroup_ht20[rf_path][i] =
1532 (rtlefuse->eeprom_pwrlimit_ht20[index]
1533 & 0xf);
1534 rtlefuse->pwrgroup_ht40[rf_path][i] =
1535 (rtlefuse->eeprom_pwrlimit_ht40[index]
1536 & 0xf);
1537 } else if (rf_path == RF90_PATH_B) {
1538 rtlefuse->pwrgroup_ht20[rf_path][i] =
1539 ((rtlefuse->eeprom_pwrlimit_ht20[index]
1540 & 0xf0) >> 4);
1541 rtlefuse->pwrgroup_ht40[rf_path][i] =
1542 ((rtlefuse->eeprom_pwrlimit_ht40[index]
1543 & 0xf0) >> 4);
1544 }
1545
1546 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1547 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1548 rf_path, i,
1549 rtlefuse->pwrgroup_ht20[rf_path][i]);
1550 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1551 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1552 rf_path, i,
1553 rtlefuse->pwrgroup_ht40[rf_path][i]);
1554 }
1555 }
1556
1557 for (i = 0; i < 14; i++) {
1558 index = rtl92c_get_chnl_group((u8)i);
1559
1560 if (!autoload_fail)
1561 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1562 else
1563 tempval = EEPROM_DEFAULT_HT20_DIFF;
1564
1565 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1566 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1567 ((tempval >> 4) & 0xF);
1568
1569 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1570 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1571
1572 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1573 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1574
1575 index = rtl92c_get_chnl_group((u8)i);
1576
1577 if (!autoload_fail)
1578 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1579 else
1580 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1581
1582 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1583 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1584 ((tempval >> 4) & 0xF);
1585 }
1586
1587 rtlefuse->legacy_ht_txpowerdiff =
1588 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1589
1590 for (i = 0; i < 14; i++)
1591 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1592 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1593 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1594 for (i = 0; i < 14; i++)
1595 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1596 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1597 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1598 for (i = 0; i < 14; i++)
1599 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1600 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1601 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1602 for (i = 0; i < 14; i++)
1603 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1604 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1605 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1606
1607 if (!autoload_fail)
1608 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1609 else
1610 rtlefuse->eeprom_regulatory = 0;
1611 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1612 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1613
1614 if (!autoload_fail) {
1615 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1616 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1617 } else {
1618 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1619 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1620 }
1621 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1622 rtlefuse->eeprom_tssi[RF90_PATH_A],
1623 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1624
1625 if (!autoload_fail)
1626 tempval = hwinfo[EEPROM_THERMAL_METER];
1627 else
1628 tempval = EEPROM_DEFAULT_THERMALMETER;
1629 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1630
1631 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1632 rtlefuse->apk_thermalmeterignore = true;
1633
1634 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1635 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1636 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1637 }
1638
1639 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1640 {
1641 struct rtl_priv *rtlpriv = rtl_priv(hw);
1642 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1643 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1644 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1645 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1646 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1647 COUNTRY_CODE_WORLD_WIDE_13};
1648 u8 *hwinfo;
1649
1650 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1651 if (!hwinfo)
1652 return;
1653
1654 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1655 goto exit;
1656
1657 _rtl92ce_read_txpower_info_from_hwpg(hw,
1658 rtlefuse->autoload_failflag,
1659 hwinfo);
1660
1661 rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1662 rtlefuse->autoload_failflag,
1663 hwinfo);
1664 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1665 switch (rtlefuse->eeprom_oemid) {
1666 case EEPROM_CID_DEFAULT:
1667 if (rtlefuse->eeprom_did == 0x8176) {
1668 if ((rtlefuse->eeprom_svid == 0x103C &&
1669 rtlefuse->eeprom_smid == 0x1629))
1670 rtlhal->oem_id = RT_CID_819X_HP;
1671 else
1672 rtlhal->oem_id = RT_CID_DEFAULT;
1673 } else {
1674 rtlhal->oem_id = RT_CID_DEFAULT;
1675 }
1676 break;
1677 case EEPROM_CID_TOSHIBA:
1678 rtlhal->oem_id = RT_CID_TOSHIBA;
1679 break;
1680 case EEPROM_CID_QMI:
1681 rtlhal->oem_id = RT_CID_819X_QMI;
1682 break;
1683 case EEPROM_CID_WHQL:
1684 default:
1685 rtlhal->oem_id = RT_CID_DEFAULT;
1686 break;
1687 }
1688 }
1689 exit:
1690 kfree(hwinfo);
1691 }
1692
1693 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1694 {
1695 struct rtl_priv *rtlpriv = rtl_priv(hw);
1696 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1697
1698 switch (rtlhal->oem_id) {
1699 case RT_CID_819X_HP:
1700 rtlpriv->ledctl.led_opendrain = true;
1701 break;
1702 case RT_CID_819X_LENOVO:
1703 case RT_CID_DEFAULT:
1704 case RT_CID_TOSHIBA:
1705 case RT_CID_CCX:
1706 case RT_CID_819X_ACER:
1707 case RT_CID_WHQL:
1708 default:
1709 break;
1710 }
1711 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1712 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1713 }
1714
1715 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1716 {
1717 struct rtl_priv *rtlpriv = rtl_priv(hw);
1718 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1719 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1720 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1721 u8 tmp_u1b;
1722
1723 rtlhal->version = _rtl92ce_read_chip_version(hw);
1724 if (get_rf_type(rtlphy) == RF_1T1R)
1725 rtlpriv->dm.rfpath_rxenable[0] = true;
1726 else
1727 rtlpriv->dm.rfpath_rxenable[0] =
1728 rtlpriv->dm.rfpath_rxenable[1] = true;
1729 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1730 rtlhal->version);
1731 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1732 if (tmp_u1b & BIT(4)) {
1733 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1734 rtlefuse->epromtype = EEPROM_93C46;
1735 } else {
1736 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1737 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1738 }
1739 if (tmp_u1b & BIT(5)) {
1740 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1741 rtlefuse->autoload_failflag = false;
1742 _rtl92ce_read_adapter_info(hw);
1743 } else {
1744 pr_err("Autoload ERR!!\n");
1745 }
1746 _rtl92ce_hal_customized_behavior(hw);
1747 }
1748
1749 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1750 struct ieee80211_sta *sta)
1751 {
1752 struct rtl_priv *rtlpriv = rtl_priv(hw);
1753 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1754 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1755 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1756 u32 ratr_value;
1757 u8 ratr_index = 0;
1758 u8 nmode = mac->ht_enable;
1759 u16 shortgi_rate;
1760 u32 tmp_ratr_value;
1761 u8 curtxbw_40mhz = mac->bw_40;
1762 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1763 1 : 0;
1764 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1765 1 : 0;
1766 enum wireless_mode wirelessmode = mac->mode;
1767 u32 ratr_mask;
1768
1769 if (rtlhal->current_bandtype == BAND_ON_5G)
1770 ratr_value = sta->supp_rates[1] << 4;
1771 else
1772 ratr_value = sta->supp_rates[0];
1773 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1774 ratr_value = 0xfff;
1775
1776 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1777 sta->ht_cap.mcs.rx_mask[0] << 12);
1778 switch (wirelessmode) {
1779 case WIRELESS_MODE_B:
1780 if (ratr_value & 0x0000000c)
1781 ratr_value &= 0x0000000d;
1782 else
1783 ratr_value &= 0x0000000f;
1784 break;
1785 case WIRELESS_MODE_G:
1786 ratr_value &= 0x00000FF5;
1787 break;
1788 case WIRELESS_MODE_N_24G:
1789 case WIRELESS_MODE_N_5G:
1790 nmode = 1;
1791 if (get_rf_type(rtlphy) == RF_1T2R ||
1792 get_rf_type(rtlphy) == RF_1T1R)
1793 ratr_mask = 0x000ff005;
1794 else
1795 ratr_mask = 0x0f0ff005;
1796
1797 ratr_value &= ratr_mask;
1798 break;
1799 default:
1800 if (rtlphy->rf_type == RF_1T2R)
1801 ratr_value &= 0x000ff0ff;
1802 else
1803 ratr_value &= 0x0f0ff0ff;
1804
1805 break;
1806 }
1807
1808 if ((rtlpriv->btcoexist.bt_coexistence) &&
1809 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
1810 (rtlpriv->btcoexist.bt_cur_state) &&
1811 (rtlpriv->btcoexist.bt_ant_isolation) &&
1812 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
1813 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
1814 ratr_value &= 0x0fffcfc0;
1815 else
1816 ratr_value &= 0x0FFFFFFF;
1817
1818 if (nmode && ((curtxbw_40mhz &&
1819 curshortgi_40mhz) || (!curtxbw_40mhz &&
1820 curshortgi_20mhz))) {
1821
1822 ratr_value |= 0x10000000;
1823 tmp_ratr_value = (ratr_value >> 12);
1824
1825 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1826 if ((1 << shortgi_rate) & tmp_ratr_value)
1827 break;
1828 }
1829
1830 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1831 (shortgi_rate << 4) | (shortgi_rate);
1832 }
1833
1834 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1835
1836 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1837 rtl_read_dword(rtlpriv, REG_ARFR0));
1838 }
1839
1840 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1841 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
1842 {
1843 struct rtl_priv *rtlpriv = rtl_priv(hw);
1844 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1845 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1846 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1847 struct rtl_sta_info *sta_entry = NULL;
1848 u32 ratr_bitmap;
1849 u8 ratr_index;
1850 u8 curtxbw_40mhz = (sta->ht_cap.cap &
1851 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
1852 u8 curshortgi_40mhz = (sta->ht_cap.cap &
1853 IEEE80211_HT_CAP_SGI_40) ? 1 : 0;
1854 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1855 1 : 0;
1856 enum wireless_mode wirelessmode = 0;
1857 bool shortgi = false;
1858 u8 rate_mask[5];
1859 u8 macid = 0;
1860
1861 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1862 wirelessmode = sta_entry->wireless_mode;
1863 if (mac->opmode == NL80211_IFTYPE_STATION ||
1864 mac->opmode == NL80211_IFTYPE_MESH_POINT)
1865 curtxbw_40mhz = mac->bw_40;
1866 else if (mac->opmode == NL80211_IFTYPE_AP ||
1867 mac->opmode == NL80211_IFTYPE_ADHOC)
1868 macid = sta->aid + 1;
1869
1870 if (rtlhal->current_bandtype == BAND_ON_5G)
1871 ratr_bitmap = sta->supp_rates[1] << 4;
1872 else
1873 ratr_bitmap = sta->supp_rates[0];
1874 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1875 ratr_bitmap = 0xfff;
1876 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1877 sta->ht_cap.mcs.rx_mask[0] << 12);
1878 switch (wirelessmode) {
1879 case WIRELESS_MODE_B:
1880 ratr_index = RATR_INX_WIRELESS_B;
1881 if (ratr_bitmap & 0x0000000c)
1882 ratr_bitmap &= 0x0000000d;
1883 else
1884 ratr_bitmap &= 0x0000000f;
1885 break;
1886 case WIRELESS_MODE_G:
1887 ratr_index = RATR_INX_WIRELESS_GB;
1888
1889 if (rssi_level == 1)
1890 ratr_bitmap &= 0x00000f00;
1891 else if (rssi_level == 2)
1892 ratr_bitmap &= 0x00000ff0;
1893 else
1894 ratr_bitmap &= 0x00000ff5;
1895 break;
1896 case WIRELESS_MODE_A:
1897 ratr_index = RATR_INX_WIRELESS_A;
1898 ratr_bitmap &= 0x00000ff0;
1899 break;
1900 case WIRELESS_MODE_N_24G:
1901 case WIRELESS_MODE_N_5G:
1902 ratr_index = RATR_INX_WIRELESS_NGB;
1903
1904 if (rtlphy->rf_type == RF_1T2R ||
1905 rtlphy->rf_type == RF_1T1R) {
1906 if (curtxbw_40mhz) {
1907 if (rssi_level == 1)
1908 ratr_bitmap &= 0x000f0000;
1909 else if (rssi_level == 2)
1910 ratr_bitmap &= 0x000ff000;
1911 else
1912 ratr_bitmap &= 0x000ff015;
1913 } else {
1914 if (rssi_level == 1)
1915 ratr_bitmap &= 0x000f0000;
1916 else if (rssi_level == 2)
1917 ratr_bitmap &= 0x000ff000;
1918 else
1919 ratr_bitmap &= 0x000ff005;
1920 }
1921 } else {
1922 if (curtxbw_40mhz) {
1923 if (rssi_level == 1)
1924 ratr_bitmap &= 0x0f0f0000;
1925 else if (rssi_level == 2)
1926 ratr_bitmap &= 0x0f0ff000;
1927 else
1928 ratr_bitmap &= 0x0f0ff015;
1929 } else {
1930 if (rssi_level == 1)
1931 ratr_bitmap &= 0x0f0f0000;
1932 else if (rssi_level == 2)
1933 ratr_bitmap &= 0x0f0ff000;
1934 else
1935 ratr_bitmap &= 0x0f0ff005;
1936 }
1937 }
1938
1939 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1940 (!curtxbw_40mhz && curshortgi_20mhz)) {
1941
1942 if (macid == 0)
1943 shortgi = true;
1944 else if (macid == 1)
1945 shortgi = false;
1946 }
1947 break;
1948 default:
1949 ratr_index = RATR_INX_WIRELESS_NGB;
1950
1951 if (rtlphy->rf_type == RF_1T2R)
1952 ratr_bitmap &= 0x000ff0ff;
1953 else
1954 ratr_bitmap &= 0x0f0ff0ff;
1955 break;
1956 }
1957 sta_entry->ratr_index = ratr_index;
1958
1959 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1960 "ratr_bitmap :%x\n", ratr_bitmap);
1961 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
1962 (ratr_index << 28);
1963 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1964 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1965 "Rate_index:%x, ratr_val:%x, %5phC\n",
1966 ratr_index, ratr_bitmap, rate_mask);
1967 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1968 }
1969
1970 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
1971 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
1972 {
1973 struct rtl_priv *rtlpriv = rtl_priv(hw);
1974
1975 if (rtlpriv->dm.useramask)
1976 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
1977 else
1978 rtl92ce_update_hal_rate_table(hw, sta);
1979 }
1980
1981 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1982 {
1983 struct rtl_priv *rtlpriv = rtl_priv(hw);
1984 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1985 u16 sifs_timer;
1986
1987 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1988 &mac->slot_time);
1989 if (!mac->ht_enable)
1990 sifs_timer = 0x0a0a;
1991 else
1992 sifs_timer = 0x1010;
1993 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
1994 }
1995
1996 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
1997 {
1998 struct rtl_priv *rtlpriv = rtl_priv(hw);
1999 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2000 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2001 enum rf_pwrstate e_rfpowerstate_toset;
2002 u8 u1tmp;
2003 bool actuallyset = false;
2004 unsigned long flag;
2005
2006 if (rtlpci->being_init_adapter)
2007 return false;
2008
2009 if (ppsc->swrf_processing)
2010 return false;
2011
2012 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2013 if (ppsc->rfchange_inprogress) {
2014 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2015 return false;
2016 } else {
2017 ppsc->rfchange_inprogress = true;
2018 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2019 }
2020
2021 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2022 REG_MAC_PINMUX_CFG)&~(BIT(3)));
2023
2024 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2025 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2026
2027 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2028 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2029 "GPIOChangeRF - HW Radio ON, RF ON\n");
2030
2031 e_rfpowerstate_toset = ERFON;
2032 ppsc->hwradiooff = false;
2033 actuallyset = true;
2034 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2035 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2036 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2037
2038 e_rfpowerstate_toset = ERFOFF;
2039 ppsc->hwradiooff = true;
2040 actuallyset = true;
2041 }
2042
2043 if (actuallyset) {
2044 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2045 ppsc->rfchange_inprogress = false;
2046 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2047 } else {
2048 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2049 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2050
2051 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2052 ppsc->rfchange_inprogress = false;
2053 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2054 }
2055
2056 *valid = 1;
2057 return !ppsc->hwradiooff;
2058
2059 }
2060
2061 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2062 u8 *p_macaddr, bool is_group, u8 enc_algo,
2063 bool is_wepkey, bool clear_all)
2064 {
2065 struct rtl_priv *rtlpriv = rtl_priv(hw);
2066 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2067 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2068 u8 *macaddr = p_macaddr;
2069 u32 entry_id = 0;
2070 bool is_pairwise = false;
2071
2072 static u8 cam_const_addr[4][6] = {
2073 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2074 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2075 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2076 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2077 };
2078 static u8 cam_const_broad[] = {
2079 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2080 };
2081
2082 if (clear_all) {
2083 u8 idx = 0;
2084 u8 cam_offset = 0;
2085 u8 clear_number = 5;
2086
2087 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2088
2089 for (idx = 0; idx < clear_number; idx++) {
2090 rtl_cam_mark_invalid(hw, cam_offset + idx);
2091 rtl_cam_empty_entry(hw, cam_offset + idx);
2092
2093 if (idx < 5) {
2094 memset(rtlpriv->sec.key_buf[idx], 0,
2095 MAX_KEY_LEN);
2096 rtlpriv->sec.key_len[idx] = 0;
2097 }
2098 }
2099
2100 } else {
2101 switch (enc_algo) {
2102 case WEP40_ENCRYPTION:
2103 enc_algo = CAM_WEP40;
2104 break;
2105 case WEP104_ENCRYPTION:
2106 enc_algo = CAM_WEP104;
2107 break;
2108 case TKIP_ENCRYPTION:
2109 enc_algo = CAM_TKIP;
2110 break;
2111 case AESCCMP_ENCRYPTION:
2112 enc_algo = CAM_AES;
2113 break;
2114 default:
2115 pr_err("switch case %#x not processed\n",
2116 enc_algo);
2117 enc_algo = CAM_TKIP;
2118 break;
2119 }
2120
2121 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2122 macaddr = cam_const_addr[key_index];
2123 entry_id = key_index;
2124 } else {
2125 if (is_group) {
2126 macaddr = cam_const_broad;
2127 entry_id = key_index;
2128 } else {
2129 if (mac->opmode == NL80211_IFTYPE_AP ||
2130 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2131 entry_id = rtl_cam_get_free_entry(hw,
2132 p_macaddr);
2133 if (entry_id >= TOTAL_CAM_ENTRY) {
2134 pr_err("Can not find free hw security cam entry\n");
2135 return;
2136 }
2137 } else {
2138 entry_id = CAM_PAIRWISE_KEY_POSITION;
2139 }
2140
2141 key_index = PAIRWISE_KEYIDX;
2142 is_pairwise = true;
2143 }
2144 }
2145
2146 if (rtlpriv->sec.key_len[key_index] == 0) {
2147 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2148 "delete one entry, entry_id is %d\n",
2149 entry_id);
2150 if (mac->opmode == NL80211_IFTYPE_AP ||
2151 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2152 rtl_cam_del_entry(hw, p_macaddr);
2153 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2154 } else {
2155 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2156 "The insert KEY length is %d\n",
2157 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2158 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2159 "The insert KEY is %x %x\n",
2160 rtlpriv->sec.key_buf[0][0],
2161 rtlpriv->sec.key_buf[0][1]);
2162
2163 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2164 "add one entry\n");
2165 if (is_pairwise) {
2166 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2167 "Pairwise Key content",
2168 rtlpriv->sec.pairwise_key,
2169 rtlpriv->sec.
2170 key_len[PAIRWISE_KEYIDX]);
2171
2172 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2173 "set Pairwise key\n");
2174
2175 rtl_cam_add_one_entry(hw, macaddr, key_index,
2176 entry_id, enc_algo,
2177 CAM_CONFIG_NO_USEDK,
2178 rtlpriv->sec.
2179 key_buf[key_index]);
2180 } else {
2181 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2182 "set group key\n");
2183
2184 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2185 rtl_cam_add_one_entry(hw,
2186 rtlefuse->dev_addr,
2187 PAIRWISE_KEYIDX,
2188 CAM_PAIRWISE_KEY_POSITION,
2189 enc_algo,
2190 CAM_CONFIG_NO_USEDK,
2191 rtlpriv->sec.key_buf
2192 [entry_id]);
2193 }
2194
2195 rtl_cam_add_one_entry(hw, macaddr, key_index,
2196 entry_id, enc_algo,
2197 CAM_CONFIG_NO_USEDK,
2198 rtlpriv->sec.key_buf[entry_id]);
2199 }
2200
2201 }
2202 }
2203 }
2204
2205 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2206 {
2207 struct rtl_priv *rtlpriv = rtl_priv(hw);
2208
2209 rtlpriv->btcoexist.bt_coexistence =
2210 rtlpriv->btcoexist.eeprom_bt_coexist;
2211 rtlpriv->btcoexist.bt_ant_num =
2212 rtlpriv->btcoexist.eeprom_bt_ant_num;
2213 rtlpriv->btcoexist.bt_coexist_type =
2214 rtlpriv->btcoexist.eeprom_bt_type;
2215
2216 if (rtlpriv->btcoexist.reg_bt_iso == 2)
2217 rtlpriv->btcoexist.bt_ant_isolation =
2218 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2219 else
2220 rtlpriv->btcoexist.bt_ant_isolation =
2221 rtlpriv->btcoexist.reg_bt_iso;
2222
2223 rtlpriv->btcoexist.bt_radio_shared_type =
2224 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2225
2226 if (rtlpriv->btcoexist.bt_coexistence) {
2227 if (rtlpriv->btcoexist.reg_bt_sco == 1)
2228 rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2229 else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2230 rtlpriv->btcoexist.bt_service = BT_SCO;
2231 else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2232 rtlpriv->btcoexist.bt_service = BT_BUSY;
2233 else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2234 rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2235 else
2236 rtlpriv->btcoexist.bt_service = BT_IDLE;
2237
2238 rtlpriv->btcoexist.bt_edca_ul = 0;
2239 rtlpriv->btcoexist.bt_edca_dl = 0;
2240 rtlpriv->btcoexist.bt_rssi_state = 0xff;
2241 }
2242 }
2243
2244 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2245 bool auto_load_fail, u8 *hwinfo)
2246 {
2247 struct rtl_priv *rtlpriv = rtl_priv(hw);
2248 u8 val;
2249
2250 if (!auto_load_fail) {
2251 rtlpriv->btcoexist.eeprom_bt_coexist =
2252 ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2253 val = hwinfo[RF_OPTION4];
2254 rtlpriv->btcoexist.eeprom_bt_type = ((val & 0xe) >> 1);
2255 rtlpriv->btcoexist.eeprom_bt_ant_num = (val & 0x1);
2256 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4);
2257 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2258 ((val & 0x20) >> 5);
2259 } else {
2260 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2261 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2262 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2263 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2264 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2265 }
2266
2267 rtl8192ce_bt_var_init(hw);
2268 }
2269
2270 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2271 {
2272 struct rtl_priv *rtlpriv = rtl_priv(hw);
2273
2274 /* 0:Low, 1:High, 2:From Efuse. */
2275 rtlpriv->btcoexist.reg_bt_iso = 2;
2276 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2277 rtlpriv->btcoexist.reg_bt_sco = 3;
2278 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2279 rtlpriv->btcoexist.reg_bt_sco = 0;
2280 }
2281
2282
2283 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2284 {
2285 struct rtl_priv *rtlpriv = rtl_priv(hw);
2286 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2287
2288 u8 u1_tmp;
2289
2290 if (rtlpriv->btcoexist.bt_coexistence &&
2291 ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2292 rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2293
2294 if (rtlpriv->btcoexist.bt_ant_isolation)
2295 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2296
2297 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2298 BIT_OFFSET_LEN_MASK_32(0, 1);
2299 u1_tmp = u1_tmp |
2300 ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2301 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2302 ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2303 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2304 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2305
2306 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2307 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2308 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2309
2310 /* Config to 1T1R. */
2311 if (rtlphy->rf_type == RF_1T1R) {
2312 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2313 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2314 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2315
2316 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2317 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2318 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2319 }
2320 }
2321 }
2322
2323 void rtl92ce_suspend(struct ieee80211_hw *hw)
2324 {
2325 }
2326
2327 void rtl92ce_resume(struct ieee80211_hw *hw)
2328 {
2329 }
Linux with added FPC-III support