lib/MCA/Context.cpp

   1 //===---------------------------- Context.cpp -------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 ///
  10 /// This file defines a class for holding ownership of various simulated
  11 /// hardware units.  A Context also provides a utility routine for constructing
  12 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
  13 /// stages.
  14 ///
  15 //===----------------------------------------------------------------------===//
  16
  17 #include "llvm/MCA/Context.h"
  18 #include "llvm/MCA/HardwareUnits/RegisterFile.h"
  19 #include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
  20 #include "llvm/MCA/HardwareUnits/Scheduler.h"
  21 #include "llvm/MCA/Stages/DispatchStage.h"
  22 #include "llvm/MCA/Stages/EntryStage.h"
  23 #include "llvm/MCA/Stages/ExecuteStage.h"
  24 #include "llvm/MCA/Stages/MicroOpQueueStage.h"
  25 #include "llvm/MCA/Stages/RetireStage.h"
  26
  27 namespace llvm {
  28 namespace mca {
  29
  30 std::unique_ptr<Pipeline>
  31 Context::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) {
  32   const MCSchedModel &SM = STI.getSchedModel();
  33
  34   // Create the hardware units defining the backend.
  35   auto RCU = std::make_unique<RetireControlUnit>(SM);
  36   auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
  37   auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
  38                                        Opts.StoreQueueSize, Opts.AssumeNoAlias);
  39   auto HWS = std::make_unique<Scheduler>(SM, *LSU);
  40
  41   // Create the pipeline stages.
  42   auto Fetch = std::make_unique<EntryStage>(SrcMgr);
  43   auto Dispatch = std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth,
  44                                                    *RCU, *PRF);
  45   auto Execute =
  46       std::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis);
  47   auto Retire = std::make_unique<RetireStage>(*RCU, *PRF);
  48
  49   // Pass the ownership of all the hardware units to this Context.
  50   addHardwareUnit(std::move(RCU));
  51   addHardwareUnit(std::move(PRF));
  52   addHardwareUnit(std::move(LSU));
  53   addHardwareUnit(std::move(HWS));
  54
  55   // Build the pipeline.
  56   auto StagePipeline = std::make_unique<Pipeline>();
  57   StagePipeline->appendStage(std::move(Fetch));
  58   if (Opts.MicroOpQueueSize)
  59     StagePipeline->appendStage(std::make_unique<MicroOpQueueStage>(
  60         Opts.MicroOpQueueSize, Opts.DecodersThroughput));
  61   StagePipeline->appendStage(std::move(Dispatch));
  62   StagePipeline->appendStage(std::move(Execute));
  63   StagePipeline->appendStage(std::move(Retire));
  64   return StagePipeline;
  65 }
  66
  67 } // namespace mca
  68 } // namespace llvm