lib/Target/AArch64/AArch64CallingConvention.cpp

   1 //=== AArch64CallingConvention.cpp - AArch64 CC impl ------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the table-generated and custom routines for the AArch64
  10 // Calling Convention.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "AArch64CallingConvention.h"
  15 #include "AArch64.h"
  16 #include "AArch64InstrInfo.h"
  17 #include "AArch64Subtarget.h"
  18 #include "llvm/CodeGen/CallingConvLower.h"
  19 #include "llvm/CodeGen/TargetInstrInfo.h"
  20 #include "llvm/IR/CallingConv.h"
  21 using namespace llvm;
  22
  23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
  24                                      AArch64::X3, AArch64::X4, AArch64::X5,
  25                                      AArch64::X6, AArch64::X7};
  26 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
  27                                      AArch64::H3, AArch64::H4, AArch64::H5,
  28                                      AArch64::H6, AArch64::H7};
  29 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
  30                                      AArch64::S3, AArch64::S4, AArch64::S5,
  31                                      AArch64::S6, AArch64::S7};
  32 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
  33                                      AArch64::D3, AArch64::D4, AArch64::D5,
  34                                      AArch64::D6, AArch64::D7};
  35 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
  36                                      AArch64::Q3, AArch64::Q4, AArch64::Q5,
  37                                      AArch64::Q6, AArch64::Q7};
  38
  39 static bool finishStackBlock(SmallVectorImpl<CCValAssign> &PendingMembers,
  40                              MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
  41                              CCState &State, unsigned SlotAlign) {
  42   unsigned Size = LocVT.getSizeInBits() / 8;
  43   unsigned StackAlign =
  44       State.getMachineFunction().getDataLayout().getStackAlignment();
  45   unsigned Align = std::min(ArgFlags.getOrigAlign(), StackAlign);
  46
  47   for (auto &It : PendingMembers) {
  48     It.convertToMem(State.AllocateStack(Size, std::max(Align, SlotAlign)));
  49     State.addLoc(It);
  50     SlotAlign = 1;
  51   }
  52
  53   // All pending members have now been allocated
  54   PendingMembers.clear();
  55   return true;
  56 }
  57
  58 /// The Darwin variadic PCS places anonymous arguments in 8-byte stack slots. An
  59 /// [N x Ty] type must still be contiguous in memory though.
  60 static bool CC_AArch64_Custom_Stack_Block(
  61       unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo,
  62       ISD::ArgFlagsTy &ArgFlags, CCState &State) {
  63   SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
  64
  65   // Add the argument to the list to be allocated once we know the size of the
  66   // block.
  67   PendingMembers.push_back(
  68       CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
  69
  70   if (!ArgFlags.isInConsecutiveRegsLast())
  71     return true;
  72
  73   return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, 8);
  74 }
  75
  76 /// Given an [N x Ty] block, it should be passed in a consecutive sequence of
  77 /// registers. If no such sequence is available, mark the rest of the registers
  78 /// of that type as used and place the argument on the stack.
  79 static bool CC_AArch64_Custom_Block(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
  80                                     CCValAssign::LocInfo &LocInfo,
  81                                     ISD::ArgFlagsTy &ArgFlags, CCState &State) {
  82   // Try to allocate a contiguous block of registers, each of the correct
  83   // size to hold one member.
  84   ArrayRef<MCPhysReg> RegList;
  85   if (LocVT.SimpleTy == MVT::i64)
  86     RegList = XRegList;
  87   else if (LocVT.SimpleTy == MVT::f16)
  88     RegList = HRegList;
  89   else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector())
  90     RegList = SRegList;
  91   else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector())
  92     RegList = DRegList;
  93   else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector())
  94     RegList = QRegList;
  95   else {
  96     // Not an array we want to split up after all.
  97     return false;
  98   }
  99
 100   SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
 101
 102   // Add the argument to the list to be allocated once we know the size of the
 103   // block.
 104   PendingMembers.push_back(
 105       CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
 106
 107   if (!ArgFlags.isInConsecutiveRegsLast())
 108     return true;
 109
 110   unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
 111   if (RegResult) {
 112     for (auto &It : PendingMembers) {
 113       It.convertToReg(RegResult);
 114       State.addLoc(It);
 115       ++RegResult;
 116     }
 117     PendingMembers.clear();
 118     return true;
 119   }
 120
 121   // Mark all regs in the class as unavailable
 122   for (auto Reg : RegList)
 123     State.AllocateReg(Reg);
 124
 125   const AArch64Subtarget &Subtarget = static_cast<const AArch64Subtarget &>(
 126       State.getMachineFunction().getSubtarget());
 127   unsigned SlotAlign = Subtarget.isTargetDarwin() ? 1 : 8;
 128
 129   return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, SlotAlign);
 130 }
 131
 132 // TableGen provides definitions of the calling convention analysis entry
 133 // points.
 134 #include "AArch64GenCallingConv.inc"